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https://opencores.org/ocsvn/ethmac/ethmac/trunk
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Rev 19 → Rev 20
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,16
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
50,57 → 60,57
// |
|
|
`define FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements |
// Should be cleared for the ASIC implementation |
`define ETH_FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements |
// Should be cleared for the ASIC implementation |
|
|
// Address is {`ETHERNET_SPACE, REG_SPACE, 12'hx} |
`define ETHERNET_SPACE 16'hf000 // Ethernet space is allocated from 0xF0000000 to 0xF000FFFF |
`define REG_SPACE 4'h0 // Register space is allocated to 0xF0000000 |
`define BD_SPACE 4'h1 // Buffer descriptor space is allocated to 0xF0001000 |
`define TX_DATA 4'h2 // Tx data is written to address 0xF0002000. Since DMA is used, TX_DATA is not used in equations. |
`define RX_DATA 4'h3 // Rx data is read from address 0xF0003000. Since DMA is used, RX_DATA is not used in equations. |
`define ETH_ETHERNET_SPACE 16'hf000 // Ethernet space is allocated from 0xF0000000 to 0xF000FFFF |
`define ETH_REG_SPACE 4'h0 // Register space is allocated to 0xF0000000 |
`define ETH_BD_SPACE 4'h1 // Buffer descriptor space is allocated to 0xF0001000 |
`define ETH_TX_DATA 4'h2 // Tx data is written to address 0xF0002000. Since DMA is used, TX_DATA is not used in equations. |
`define ETH_RX_DATA 4'h3 // Rx data is read from address 0xF0003000. Since DMA is used, RX_DATA is not used in equations. |
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`define PACKET_SEND_ADR 32'h20 // Packet for TX are written to the address 0x20 |
`define ETH_PACKET_SEND_ADR 32'h20 // Packet for TX are written to the address 0x20 |
|
`define MODER_ADR 6'h0 |
`define INT_SOURCE_ADR 6'h1 |
`define INT_MASK_ADR 6'h2 |
`define IPGT_ADR 6'h3 |
`define IPGR1_ADR 6'h4 |
`define IPGR2_ADR 6'h5 |
`define PACKETLEN_ADR 6'h6 |
`define COLLCONF_ADR 6'h7 |
`define RX_BD_ADR_ADR 6'h8 |
`define CTRLMODER_ADR 6'hA |
`define MIIMODER_ADR 6'hB |
`define MIICOMMAND_ADR 6'hC |
`define MIIADDRESS_ADR 6'hD |
`define MIITX_DATA_ADR 6'hE |
`define MIIRX_DATA_ADR 6'hF |
`define MIISTATUS_ADR 6'h10 |
`define MAC_ADDR0_ADR 6'h11 |
`define MAC_ADDR1_ADR 6'h12 |
`define ETH_MODER_ADR 6'h0 |
`define ETH_INT_SOURCE_ADR 6'h1 |
`define ETH_INT_MASK_ADR 6'h2 |
`define ETH_IPGT_ADR 6'h3 |
`define ETH_IPGR1_ADR 6'h4 |
`define ETH_IPGR2_ADR 6'h5 |
`define ETH_PACKETLEN_ADR 6'h6 |
`define ETH_COLLCONF_ADR 6'h7 |
`define ETH_RX_BD_ADR_ADR 6'h8 |
`define ETH_CTRLMODER_ADR 6'hA |
`define ETH_MIIMODER_ADR 6'hB |
`define ETH_MIICOMMAND_ADR 6'hC |
`define ETH_MIIADDRESS_ADR 6'hD |
`define ETH_MIITX_DATA_ADR 6'hE |
`define ETH_MIIRX_DATA_ADR 6'hF |
`define ETH_MIISTATUS_ADR 6'h10 |
`define ETH_MAC_ADDR0_ADR 6'h11 |
`define ETH_MAC_ADDR1_ADR 6'h12 |
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`define MODER_DEF 32'h0000A000 |
`define INT_SOURCE_DEF 32'h00000000 |
`define INT_MASK_DEF 32'h00000000 |
`define IPGT_DEF 32'h00000012 |
`define IPGR1_DEF 32'h0000000C |
`define IPGR2_DEF 32'h00000012 |
`define PACKETLEN_DEF 32'h003C0600 |
`define COLLCONF_DEF 32'h000F0040 |
`define CTRLMODER_DEF 32'h00000000 |
`define MIIMODER_DEF 32'h00000064 |
`define MIICOMMAND_DEF 32'h00000000 |
`define MIIADDRESS_DEF 32'h00000000 |
`define MIITX_DATA_DEF 32'h00000000 |
`define MIIRX_DATA_DEF 32'h00000000 |
`define MIISTATUS_DEF 32'h00000000 |
`define MAC_ADDR0_DEF 32'h00000000 |
`define MAC_ADDR1_DEF 32'h00000000 |
`define ETH_MODER_DEF 32'h0000A000 |
`define ETH_INT_SOURCE_DEF 32'h00000000 |
`define ETH_INT_MASK_DEF 32'h00000000 |
`define ETH_IPGT_DEF 32'h00000012 |
`define ETH_IPGR1_DEF 32'h0000000C |
`define ETH_IPGR2_DEF 32'h00000012 |
`define ETH_PACKETLEN_DEF 32'h003C0600 |
`define ETH_COLLCONF_DEF 32'h000F0040 |
`define ETH_CTRLMODER_DEF 32'h00000000 |
`define ETH_MIIMODER_DEF 32'h00000064 |
`define ETH_MIICOMMAND_DEF 32'h00000000 |
`define ETH_MIIADDRESS_DEF 32'h00000000 |
`define ETH_MIITX_DATA_DEF 32'h00000000 |
`define ETH_MIIRX_DATA_DEF 32'h00000000 |
`define ETH_MIISTATUS_DEF 32'h00000000 |
`define ETH_MAC_ADDR0_DEF 32'h00000000 |
`define ETH_MAC_ADDR1_DEF 32'h00000000 |
|
`define RX_BD_ADR_DEF 8'h0 |
`define ETH_RX_BD_ADR_DEF 8'h0 |
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/08 08:28:21 mohor |
// "else" was missing within the always block in file eth_wishbonedma.v. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
222,7 → 225,9
|
reg GotDataSync1; |
reg GotDataSync2; |
reg GotDataSync3; |
wire TPauseRqSync2; |
//reg GotDataSync3; |
wire GotDataSync3; |
reg GotData; |
reg SyncGetNewTxData_wb1; |
reg SyncGetNewTxData_wb2; |
229,13 → 234,16
reg SyncGetNewTxData_wb3; |
reg TxDoneSync1; |
reg TxDoneSync2; |
reg TxDoneSync3; |
//reg TxDoneSync3; |
wire TxDoneSync3; |
reg TxRetrySync1; |
reg TxRetrySync2; |
reg TxRetrySync3; |
//reg TxRetrySync3; |
wire TxRetrySync3; |
reg TxAbortSync1; |
reg TxAbortSync2; |
reg TxAbortSync3; |
//reg TxAbortSync3; |
wire TxAbortSync3; |
|
reg TxAbort_q; |
reg TxDone_q; |
253,15 → 261,18
reg Shifting_wb_Sync1; |
reg Shifting_wb_Sync2; |
reg LatchNow_wb; |
//wire LatchNow_wb; |
|
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEnded; |
//reg ShiftEnded; |
wire ShiftEnded; |
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reg RxStartFrmSync1; |
reg RxStartFrmSync2; |
reg RxStartFrmSync3; |
//reg RxStartFrmSync3; |
wire RxStartFrmSync3; |
|
reg DMACycleFinishedTx_q; |
reg DataNotAvaliable; |
272,6 → 283,7
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reg TxCtrlEndFrm_wbSync1; |
reg TxCtrlEndFrm_wbSync2; |
wire TxCtrlEndFrm_wbSync3; |
reg TxCtrlEndFrm_wb; |
|
wire [15:0] TxPauseTV; |
329,8 → 341,6
wire ResetTxAbortSync; |
wire SetSyncGetNewTxData_wb; |
|
wire SetTxDoneSync; |
wire SetTxRetrySync; |
wire SetTxAbortSync; |
wire ResetShiftEnded; |
wire ResetRxStartFrmSync1; |
348,28 → 358,40
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assign AccessToBD = WB_ADR_I[15:12] == `BD_SPACE; |
assign AccessToBD = WB_ADR_I[15:12] == `ETH_BD_SPACE; |
|
assign DWord = &WB_SEL_I; |
assign BDWe = DWord & WB_CYC_I & WB_STB_I & WB_WE_I & AccessToBD; |
assign BDRead = DWord & WB_CYC_I & WB_STB_I & ~WB_WE_I & AccessToBD; |
assign WB_ACK_O = BDWe | BDRead & BDRead_q; // ACK is delayed one clock because of BLOCKRAM properties when performing read |
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`ifdef FPGA |
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reg EnableRAM; |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
EnableRAM <=#Tp 1'b0; |
else |
if(BDWe) |
EnableRAM <=#Tp 1'b1; |
else |
EnableRAM <=#Tp EnableRAM; |
end |
|
`ifdef ETH_FPGA |
// Xilinx BlockRAM for storing Tx and Rx buffer descriptors |
|
RAMB4_S16_S16 RAM1 ( .DIA(WB_DAT_I[15:0]), .DOA(WB_BDDataOut[15:0]), .ADDRA(WB_ADR_I[9:2]), |
.WEA(BDWe), .CLKA(WB_CLK_I), .ENA(1'b1), |
.RSTA(WB_RST_I), .DIB(BDDataIn[15:0]), .DOB(BDDataOut[15:0]), |
.ADDRB(BDAddress[7:0]), .WEB(BDStatusWrite), .CLKB(~WB_CLK_I), |
.ENB(1'b1), .RSTB(WB_RST_I) ); |
.ADDRB(BDAddress[7:0]), .WEB(BDStatusWrite), .CLKB(WB_CLK_I), |
.ENB(EnableRAM), .RSTB(WB_RST_I) ); |
RAMB4_S16_S16 RAM2 ( .DIA(WB_DAT_I[31:16]), .DOA(WB_BDDataOut[31:16]), .ADDRA(WB_ADR_I[9:2]), |
.WEA(BDWe), .CLKA(WB_CLK_I), .ENA(1'b1), |
.RSTA(WB_RST_I), .DIB(BDDataIn[31:16]), .DOB(BDDataOut[31:16]), |
.ADDRB(BDAddress[7:0]), .WEB(BDStatusWrite), .CLKB(~WB_CLK_I), |
.ENB(1'b1), .RSTB(WB_RST_I) ); |
.ADDRB(BDAddress[7:0]), .WEB(BDStatusWrite), .CLKB(WB_CLK_I), |
.ENB(EnableRAM), .RSTB(WB_RST_I) ); |
`else |
// Artisan RAM (ASIC implementation) for storing Tx and Rx buffer descriptors |
// Size will be reduced before implementation to 256 x 32 |
380,7 → 402,7
.cena(1'b0), .wena(~BDWe), |
.aa({5'h0, WB_ADR_I[9:2]}), .da({32'h0, WB_DAT_I[31:0]}), |
.oena(1'b0), |
.qb({qb_dummy[63:32], BDDataOut[31:0]}), .clkb(~WB_CLK_I), |
.qb({qb_dummy[63:32], BDDataOut[31:0]}), .clkb(WB_CLK_I), |
.cenb(1'b0), .wenb(~BDStatusWrite), |
.ab({5'h0, BDAddress[7:0]}), .db({32'h0, BDDataIn[31:0]}), |
.oenb(1'b0) |
418,7 → 440,7
|
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// Latching READY status of the Tx buffer descriptor |
always @ (negedge WB_CLK_I or posedge WB_RST_I) |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxBDReady <=#Tp 1'b0; |
432,7 → 454,7
|
|
// Latching READY status of the Tx buffer descriptor |
always @ (negedge WB_CLK_I or posedge WB_RST_I) |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
begin |
557,7 → 579,7
if(WB_RST_I) |
TxStatus <=#Tp 16'h0; |
else |
if(TxBDRead & ~TxEn) |
if(TxBDRead & TxEn) |
TxStatus <=#Tp BDDataOut[15:0]; |
end |
|
568,7 → 590,7
if(WB_RST_I) |
TxLength <=#Tp 16'h0; |
else |
if(TxBDRead & ~TxEn) |
if(TxBDRead & TxEn) |
TxLength <=#Tp BDDataOut[31:16]; |
else |
if(GetNewTxData_wb & ~WillSendControlFrame) |
588,7 → 610,7
if(WB_RST_I) |
RxStatus <=#Tp 16'h0; |
else |
if(RxBDRead & ~RxEn) |
if(RxBDRead & RxEn) |
RxStatus <=#Tp BDDataOut[15:0]; |
end |
|
869,41 → 891,14
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// Latching and synchronizing the Tx pause request signal |
eth_sync_clk1_clk2 syn1 (.clk1(MTxClk), .clk2(WB_CLK_I), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(TxPauseRq), .sync_out(TPauseRqSync2) |
); |
|
wire ResetTPauseRq; |
wire SetTPauseRq; |
reg TPauseRqSync1; |
reg TPauseRqSync2; |
|
assign ResetTPauseRq = TPauseRqSync2 | WB_RST_I; |
assign SetTPauseRq = TxPauseRq; |
|
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// Sync stage 1 |
always @ (posedge SetTPauseRq or posedge ResetTPauseRq) |
begin |
if(ResetTPauseRq) |
TPauseRqSync1 <=#Tp 1'b0; |
else |
TPauseRqSync1 <=#Tp 1'b1; |
end |
|
// Sync stage 2 |
always @ (posedge MTxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TPauseRqSync2 <=#Tp 1'b0; |
else |
if(TPauseRqSync1 & ~TPauseRq) |
TPauseRqSync2 <=#Tp 1'b1; |
else |
TPauseRqSync2 <=#Tp 1'b0; |
end |
|
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always @ (posedge MTxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TPauseRq <=#Tp 1'b0; |
else |
if(TPauseRq ) |
938,46 → 933,11
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// Sinchronizing and evaluating tx data |
assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I; |
assign ResetGotData = GotDataSync3 & ~TxStartFrm_wb | WB_RST_I; |
|
eth_sync_clk1_clk2 syn2 (.clk1(MTxClk), .clk2(WB_CLK_I), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(SetGotData), .sync_out(GotDataSync3)); |
|
// Sync stage 1 |
always @ (posedge SetGotData or posedge ResetGotData) |
begin |
if(ResetGotData) |
GotDataSync1 <=#Tp 1'b0; |
else |
GotDataSync1 <=#Tp 1'b1; |
end |
|
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// Sync stage 2 |
always @ (posedge MTxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
GotDataSync2 <=#Tp 1'b0; |
else |
if(GotDataSync1 & ~GotData) |
GotDataSync2 <=#Tp 1'b1; |
else |
GotDataSync2 <=#Tp 1'b0; |
end |
|
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// Sync stage 3 |
always @ (posedge MTxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
GotDataSync3 <=#Tp 1'b0; |
else |
if(GotDataSync2 & ~GotData) |
GotDataSync3 <=#Tp 1'b1; |
else |
GotDataSync3 <=#Tp 1'b0; |
end |
|
|
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// Evaluating data. If abort or retry occured meanwhile than data is ignored. |
assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrmRequest | TxStartFrm)); |
|
1159,6 → 1119,11
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// Synchronizing request for a new tx data |
|
//ne eth_sync_clk1_clk2 syn3 (.clk1(MTxClk), .clk2(WB_CLK_I), .reset1(WB_RST_I), .reset2(WB_RST_I), |
// .set2(SetGotData), .sync_out(GotDataSync3)); |
|
// This section still needs to be changed due to ASIC demands |
assign ResetSyncGetNewTxData_wb = SyncGetNewTxData_wb3 | TxAbort_wb | TxRetry_wb | WB_RST_I; |
assign SetSyncGetNewTxData_wb = GetNewTxData; |
|
1214,46 → 1179,12
|
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// Synchronizine transmit done signal |
assign ResetTxDoneSync = TxDoneSync3 | WB_RST_I; |
assign SetTxDoneSync = TxDone; |
// Sinchronizing and evaluating tx data |
eth_sync_clk1_clk2 syn4 (.clk1(WB_CLK_I), .clk2(MTxClk), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(TxDone), .sync_out(TxDoneSync3) |
); |
|
|
// Sync stage 1 |
always @ (posedge SetTxDoneSync or posedge ResetTxDoneSync ) |
begin |
if(ResetTxDoneSync) |
TxDoneSync1 <=#Tp 1'b0; |
else |
TxDoneSync1 <=#Tp 1'b1; |
end |
|
|
// Sync stage 2 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxDoneSync2 <=#Tp 1'b0; |
else |
if(TxDoneSync1 & ~TxDone_wb) |
TxDoneSync2 <=#Tp 1'b1; |
else |
TxDoneSync2 <=#Tp 1'b0; |
end |
|
|
// Sync stage 3 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxDoneSync3 <=#Tp 1'b0; |
else |
if(TxDoneSync2 & ~TxDone_wb) |
TxDoneSync3 <=#Tp 1'b1; |
else |
TxDoneSync3 <=#Tp 1'b0; |
end |
|
|
// Syncronized signal TxDone_wb (sync. to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
1268,7 → 1199,6
end |
|
|
// Synchronizing transmit control end frame signal |
assign ResetTxCtrlEndFrm_wb = TxCtrlEndFrm_wb | WB_RST_I; |
assign SetTxCtrlEndFrm_wb = TxCtrlEndFrm; |
|
1311,46 → 1241,10
|
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// Synchronizing TxRetry signal |
assign ResetTxRetrySync = TxRetrySync3 | WB_RST_I; |
assign SetTxRetrySync = TxRetryLatched; |
eth_sync_clk1_clk2 syn6 (.clk1(WB_CLK_I), .clk2(MTxClk), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(TxRetryLatched), .sync_out(TxRetrySync3)); |
|
|
// Sync. stage 1 |
always @ (posedge SetTxRetrySync or posedge ResetTxRetrySync) |
begin |
if(ResetTxRetrySync) |
TxRetrySync1 <=#Tp 1'b0; |
else |
TxRetrySync1 <=#Tp 1'b1; |
end |
|
|
// Sync. stage 2 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxRetrySync2 <=#Tp 1'b0; |
else |
if(TxRetrySync1 & ~TxRetry_wb) |
TxRetrySync2 <=#Tp 1'b1; |
else |
TxRetrySync2 <=#Tp 1'b0; |
end |
|
|
// Sync. stage 3 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxRetrySync3 <=#Tp 1'b0; |
else |
if(TxRetrySync2 & ~TxRetry_wb) |
TxRetrySync3 <=#Tp 1'b1; |
else |
TxRetrySync3 <=#Tp 1'b0; |
end |
|
|
// Synchronized signal TxRetry_wb (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
1366,46 → 1260,10
|
|
// Synchronizing TxAbort signal |
assign ResetTxAbortSync = TxAbortSync3 | WB_RST_I; |
assign SetTxAbortSync = TxAbort; |
eth_sync_clk1_clk2 syn7 (.clk1(WB_CLK_I), .clk2(MTxClk), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(TxAbort), .sync_out(TxAbortSync3)); |
|
|
// Sync. stage 1 |
always @ (posedge SetTxAbortSync or posedge ResetTxAbortSync) |
begin |
if(ResetTxAbortSync) |
TxAbortSync1 <=#Tp 1'b0; |
else |
TxAbortSync1 <=#Tp 1'b1; |
end |
|
|
// Sync. stage 2 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxAbortSync2 <=#Tp 1'b0; |
else |
if(TxAbortSync1 & ~TxAbort_wb) |
TxAbortSync2 <=#Tp 1'b1; |
else |
TxAbortSync2 <=#Tp 1'b0; |
end |
|
|
// Sync. stage 3 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
TxAbortSync3 <=#Tp 1'b0; |
else |
if(TxAbortSync2 & ~TxAbort_wb) |
TxAbortSync3 <=#Tp 1'b1; |
else |
TxAbortSync3 <=#Tp 1'b0; |
end |
|
|
// Synchronized TxAbort_wb signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
1492,60 → 1350,11
|
|
// Generation of the synchronized signal ShiftEnded that indicates end of reception |
assign ResetShiftEnded = ShiftEndedSync3 | WB_RST_I; |
assign StartShiftEnded = RxEndFrm_wb; |
eth_sync_clk1_clk2 syn8 (.clk1(MRxClk), .clk2(WB_CLK_I), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(RxEndFrm_wb), .sync_out(ShiftEnded) |
); |
|
|
// Sync. stage 1 |
always @ (posedge StartShiftEnded or posedge ResetShiftEnded) |
begin |
if(ResetShiftEnded) |
ShiftEndedSync1 <=#Tp 1'b0; |
else |
ShiftEndedSync1 <=#Tp 1'b1; |
end |
|
|
// Sync. stage 2 |
always @ (posedge MRxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
ShiftEndedSync2 <=#Tp 1'b0; |
else |
if(ShiftEndedSync1 & ~ShiftEnded) |
ShiftEndedSync2 <=#Tp 1'b1; |
else |
ShiftEndedSync2 <=#Tp 1'b0; |
end |
|
|
// Sync. stage 3 |
always @ (posedge MRxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
ShiftEndedSync3 <=#Tp 1'b0; |
else |
if(ShiftEndedSync2 & ~ShiftEnded) |
ShiftEndedSync3 <=#Tp 1'b1; |
else |
ShiftEndedSync3 <=#Tp 1'b0; |
end |
|
|
|
// Synchronized signal ShiftEnded |
always @ (posedge MRxClk or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
ShiftEnded <=#Tp 1'b0; |
else |
if(ShiftEndedSync3 & ~ShiftEnded) |
ShiftEnded <=#Tp 1'b1; |
else |
ShiftEnded <=#Tp 1'b0; |
end |
|
|
// Indicating that last byte is being reveived |
always @ (posedge MRxClk or posedge WB_RST_I) |
begin |
1645,46 → 1454,13
|
|
// Synchronizing Rx start frame to the WISHBONE clock |
assign ResetRxStartFrmSync1 = RxStartFrmSync3 | WB_RST_I; |
assign StartRxStartFrmSync1 = RxStartFrm & RxBDReady; |
|
eth_sync_clk1_clk2 syn9 (.clk1(WB_CLK_I), .clk2(MRxClk), .reset1(WB_RST_I), .reset2(WB_RST_I), |
.set2(SetGotData), .sync_out(RxStartFrmSync3) |
); |
|
// Sync. stage 1 |
always @ (posedge StartRxStartFrmSync1 or posedge ResetRxStartFrmSync1) |
begin |
if(ResetRxStartFrmSync1) |
RxStartFrmSync1 <=#Tp 1'b0; |
else |
RxStartFrmSync1 <=#Tp 1'b1; |
end |
|
|
// Sync. stage 2 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
RxStartFrmSync2 <=#Tp 1'b0; |
else |
if(RxStartFrmSync1 & ~RxStartFrm_wb) |
RxStartFrmSync2 <=#Tp 1'b1; |
else |
RxStartFrmSync2 <=#Tp 1'b0; |
end |
|
|
// Sync. stage 3 |
always @ (posedge WB_CLK_I or posedge WB_RST_I) |
begin |
if(WB_RST_I) |
RxStartFrmSync3 <=#Tp 1'b0; |
else |
if(RxStartFrmSync2 & ~RxStartFrm_wb) |
RxStartFrmSync3 <=#Tp 1'b1; |
else |
RxStartFrmSync3 <=#Tp 1'b0; |
end |
|
|
// Generating synchronized Rx start frame |
always @ ( posedge WB_CLK_I or posedge WB_RST_I) |
begin |
1699,6 → 1475,11
|
|
//Synchronizing signal for latching data that will be written to the WISHBONE |
//eth_sync_clk1_clk2 syn10 (.clk1(WB_CLK_I), .clk2(MRxClk), .reset1(WB_RST_I), .reset2(WB_RST_I), |
// .set2(StartShifting), .sync_out(LatchNow_wb) |
// ); |
|
// This section still needs to be changed due to ASIC demands |
assign ResetShifting_wb = LatchNow_wb | WB_RST_I; |
assign StartShifting_wb = StartShifting; |
|
1825,3 → 1606,4
end |
|
endmodule |
|
/trunk/rtl/verilog/eth_sync_clk1_clk2.v
0,0 → 1,142
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_sync_clk1_clk2.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/cores/ethmac/ //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
// |
// |
// |
|
`include "eth_timescale.v" |
|
// FF in clock domain 1 is being set by a signal from the clock domain 2 |
module eth_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out); |
|
parameter Tp = 1; |
|
input clk1; |
input clk2; |
input reset1; |
input reset2; |
input set2; |
|
output sync_out; |
|
reg set2_q; |
reg set2_q2; |
reg set1_q; |
reg set1_q2; |
reg clear2_q; |
reg clear2_q2; |
reg sync_out; |
|
wire z; |
|
assign z = set2 | set2_q & ~clear2_q2; |
|
|
// Latching and synchronizing "set" to clk2 |
always @ (posedge clk2 or posedge reset2) |
begin |
if(reset2) |
set2_q <=#Tp 1'b0; |
else |
set2_q <=#Tp z; |
end |
|
|
always @ (posedge clk2 or posedge reset2) |
begin |
if(reset2) |
set2_q2 <=#Tp 1'b0; |
else |
set2_q2 <=#Tp set2_q; |
end |
|
|
// Synchronizing "set" to clk1 |
always @ (posedge clk1 or posedge reset1) |
begin |
if(reset1) |
set1_q <=#Tp 1'b0; |
else |
set1_q <=#Tp set2_q2; |
end |
|
|
always @ (posedge clk1 or posedge reset1) |
begin |
if(reset1) |
set1_q2 <=#Tp 1'b0; |
else |
set1_q2 <=#Tp set1_q; |
end |
|
|
// Synchronizing "clear" to clk2 |
always @ (posedge clk2 or posedge reset2) |
begin |
if(reset2) |
clear2_q <=#Tp 1'b0; |
else |
clear2_q <=#Tp set1_q2; |
end |
|
|
always @ (posedge clk2 or posedge reset2) |
begin |
if(reset2) |
clear2_q2 <=#Tp 1'b0; |
else |
clear2_q2 <=#Tp clear2_q; |
end |
|
|
always @ (posedge clk1 or posedge reset1) |
begin |
if(reset1) |
sync_out <=#Tp 1'b0; |
else |
sync_out <=#Tp set1_q2; |
end |
|
endmodule |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 14:03:59 mohor |
// Signal names changed on the top level for easier pad insertion (ASIC). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
59,11 → 62,9
// |
// |
// |
// |
// |
// |
|
|
|
`include "eth_defines.v" |
`include "eth_timescale.v" |
|
78,13 → 79,13
wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o, |
|
//TX |
mtxclk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
|
//RX |
mrxclk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
|
// MIIM |
mdc_pad_o, md_pad_i, md_pad_o, md_pad_oe |
mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o |
|
|
); |
115,13 → 116,13
output wb_rd_o; // DMA restart descriptor output |
|
// Tx |
input mtxclk_pad_i; // Transmit clock (from PHY) |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) |
output mtxen_pad_o; // Transmit enable (to PHY) |
output mtxerr_pad_o; // Transmit error (to PHY) |
|
// Rx |
input mrxclk_pad_i; // Receive clock (from PHY) |
input mrx_clk_pad_i; // Receive clock (from PHY) |
input [3:0] mrxd_pad_i; // Receive nibble (from PHY) |
input mrxdv_pad_i; // Receive data valid (from PHY) |
input mrxerr_pad_i; // Receive data error (from PHY) |
134,7 → 135,7
input md_pad_i; // MII data input (from I/O cell) |
output mdc_pad_o; // MII Management data clock (to PHY) |
output md_pad_o; // MII data output (to I/O cell) |
output md_pad_oe; // MII data output enable (to I/O cell) |
output md_padoen_o; // MII data output enable (to I/O cell) |
|
|
wire [7:0] r_ClkDiv; |
173,7 → 174,7
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD), |
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat), |
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o), |
.MdoEn(md_pad_oe), .Mdc(mdc_pad_o), .Busy(Busy_stat), |
.MdoEn(md_padoen_o), .Mdc(mdc_pad_o), .Busy(Busy_stat), |
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat), |
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) |
); |
227,13 → 228,13
|
|
|
assign EthAddMatch = wb_adr_i[31:16] == `ETHERNET_SPACE; |
assign EthAddMatch = wb_adr_i[31:16] == `ETH_ETHERNET_SPACE; |
assign WB_STB_I_eth = wb_stb_i & EthAddMatch; |
assign WB_CYC_I_eth = wb_stb_i & EthAddMatch; |
|
assign wb_err_o = wb_stb_i & wb_cyc_i & EthAddMatch & ~DWord; |
assign DWord = &wb_sel_i; |
assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `REG_SPACE); |
assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `ETH_REG_SPACE); |
assign RegAck = RegCs; |
assign wb_ack_o = RegAck | BDAck; |
|
289,11 → 290,11
// Connecting MACControl |
eth_maccontrol maccontrol1 |
( |
.MTxClk(mtxclk_pad_i), .TPauseRq(TPauseRq), |
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq), |
.TxPauseTV(TxPauseTV), .TxDataIn(TxData), |
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm), |
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn), |
.TxAbortIn(TxAbortIn), .MRxClk(mrxclk_pad_i), |
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i), |
.RxData(RxData), .RxValid(RxValid), |
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), |
342,7 → 343,7
// Connecting TxEthMAC |
eth_txethmac txethmac1 |
( |
.MTxClk(mtxclk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense), |
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense), |
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut), |
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut), |
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD), |
374,7 → 375,7
// Connecting RxEthMAC |
eth_rxethmac rxethmac1 |
( |
.MRxClk(mrxclk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb), |
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb), |
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), |
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst), |
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm), |
387,7 → 388,7
|
|
// MII Carrier Sense Synchronization |
always @ (posedge mtxclk_pad_i or posedge r_Rst) |
always @ (posedge mtx_clk_pad_i or posedge r_Rst) |
begin |
if(r_Rst) |
begin |
405,7 → 406,7
|
|
// MII Collision Synchronization |
always @ (posedge mtxclk_pad_i or posedge r_Rst) |
always @ (posedge mtx_clk_pad_i or posedge r_Rst) |
begin |
if(r_Rst) |
begin |
430,7 → 431,7
|
|
// Carrier sense is synchronized to receive clock. |
always @ (posedge mrxclk_pad_i or posedge r_Rst) |
always @ (posedge mrx_clk_pad_i or posedge r_Rst) |
begin |
if(r_Rst) |
begin |
446,7 → 447,7
|
|
// Delayed WillTransmit |
always @ (posedge mrxclk_pad_i) |
always @ (posedge mrx_clk_pad_i) |
begin |
WillTransmit_q <= #Tp WillTransmit; |
WillTransmit_q2 <= #Tp WillTransmit_q; |
458,7 → 459,7
|
|
// Synchronized Receive Enable |
always @ (posedge mrxclk_pad_i or posedge r_Rst) |
always @ (posedge mrx_clk_pad_i or posedge r_Rst) |
begin |
if(r_Rst) |
RxEnSync <= #Tp 1'b0; |
483,7 → 484,7
.WB_RD_O(wb_rd_o), |
|
//TX |
.MTxClk(mtxclk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), |
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), |
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0), |
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun), |
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV), |
495,7 → 496,7
.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), |
|
//RX |
.MRxClk(mrxclk_pad_i), .RxData(RxData), .RxValid(RxValid), |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), |
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm) |
); |
|
504,7 → 505,7
// Connecting MacStatus module |
eth_macstatus macstatus1 |
( |
.MRxClk(mrxclk_pad_i), .Reset(r_Rst), .TransmitEnd(), |
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), |
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb), |
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble), |
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,16
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.2 2001/08/02 09:25:31 mohor |
// Unconnected signals are now connected. |
// |
165,25 → 175,25
wire Write = Cs & Rw; |
wire Read = Cs & ~Rw; |
|
wire MODER_Wr = (Address == `MODER_ADR) & Write; |
wire INT_SOURCE_Wr = (Address == `INT_SOURCE_ADR) & Write; |
wire INT_MASK_Wr = (Address == `INT_MASK_ADR) & Write; |
wire IPGT_Wr = (Address == `IPGT_ADR) & Write; |
wire IPGR1_Wr = (Address == `IPGR1_ADR) & Write; |
wire IPGR2_Wr = (Address == `IPGR2_ADR) & Write; |
wire PACKETLEN_Wr = (Address == `PACKETLEN_ADR) & Write; |
wire COLLCONF_Wr = (Address == `COLLCONF_ADR) & Write; |
wire MODER_Wr = (Address == `ETH_MODER_ADR) & Write; |
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR) & Write; |
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR) & Write; |
wire IPGT_Wr = (Address == `ETH_IPGT_ADR) & Write; |
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR) & Write; |
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR) & Write; |
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR) & Write; |
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR) & Write; |
|
wire CTRLMODER_Wr = (Address == `CTRLMODER_ADR) & Write; |
wire MIIMODER_Wr = (Address == `MIIMODER_ADR) & Write; |
wire MIICOMMAND_Wr = (Address == `MIICOMMAND_ADR) & Write; |
wire MIIADDRESS_Wr = (Address == `MIIADDRESS_ADR) & Write; |
wire MIITX_DATA_Wr = (Address == `MIITX_DATA_ADR) & Write; |
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR) & Write; |
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR) & Write; |
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR) & Write; |
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR) & Write; |
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR) & Write; |
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; |
wire MIISTATUS_Wr = (Address == `MIISTATUS_ADR) & Write; |
wire MAC_ADDR0_Wr = (Address == `MAC_ADDR0_ADR) & Write; |
wire MAC_ADDR1_Wr = (Address == `MAC_ADDR1_ADR) & Write; |
assign RX_BD_ADR_Wr = (Address == `RX_BD_ADR_ADR) & Write; |
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR) & Write; |
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR) & Write; |
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR) & Write; |
assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR) & Write; |
|
|
|
206,17 → 216,17
wire [31:0] MAC_ADDR1Out; |
wire [31:0] RX_BD_ADROut; |
|
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF)); |
eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`INT_SOURCE_DEF)); |
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`INT_MASK_DEF)); |
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGT_DEF)); |
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGR1_DEF)); |
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGR2_DEF)); |
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`PACKETLEN_DEF)); |
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`COLLCONF_DEF)); |
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF)); |
eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_SOURCE_DEF)); |
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF)); |
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF)); |
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF)); |
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF)); |
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF)); |
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF)); |
|
// CTRLMODER registers |
wire [31:0] DefaultCtrlModer = `CTRLMODER_DEF; |
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF; |
assign CTRLMODEROut[31:3] = 29'h0; |
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0])); |
// End: CTRLMODER registers |
225,7 → 235,7
|
|
|
eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIMODER_DEF)); |
eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF)); |
|
assign MIICOMMANDOut[31:3] = 29'h0; |
eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0)); |
232,19 → 242,19
eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0)); |
eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0)); |
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eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIADDRESS_DEF)); |
eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIITX_DATA_DEF)); |
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIRX_DATA_DEF)); |
//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIISTATUS_DEF)); |
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`MAC_ADDR0_DEF)); |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`MAC_ADDR1_DEF)); |
eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF)); |
eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF)); |
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF)); |
//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF)); |
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF)); |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF)); |
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assign RX_BD_ADROut[31:8] = 24'h0; |
eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`RX_BD_ADR_DEF)); |
eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_ADR_DEF)); |
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reg LinkFailRegister; |
wire ResetLinkFailRegister = Address == `MIISTATUS_ADR & Read; |
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read; |
reg ResetLinkFailRegister_q1; |
reg ResetLinkFailRegister_q2; |
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277,24 → 287,24
if(Read) // read |
begin |
case(Address) |
`MODER_ADR : DataOut<=MODEROut; |
`INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; |
`INT_MASK_ADR : DataOut<=INT_MASKOut; |
`IPGT_ADR : DataOut<=IPGTOut; |
`IPGR1_ADR : DataOut<=IPGR1Out; |
`IPGR2_ADR : DataOut<=IPGR2Out; |
`PACKETLEN_ADR : DataOut<=PACKETLENOut; |
`COLLCONF_ADR : DataOut<=COLLCONFOut; |
`CTRLMODER_ADR : DataOut<=CTRLMODEROut; |
`MIIMODER_ADR : DataOut<=MIIMODEROut; |
`MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; |
`MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; |
`MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; |
`MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; |
`MIISTATUS_ADR : DataOut<=MIISTATUSOut; |
`MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
`MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
`RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut; |
`ETH_MODER_ADR : DataOut<=MODEROut; |
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; |
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut; |
`ETH_IPGT_ADR : DataOut<=IPGTOut; |
`ETH_IPGR1_ADR : DataOut<=IPGR1Out; |
`ETH_IPGR2_ADR : DataOut<=IPGR2Out; |
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut; |
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut; |
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut; |
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut; |
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; |
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; |
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; |
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; |
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; |
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
`ETH_RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut; |
default: DataOut<=32'h0; |
endcase |
end |