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/modular_oscilloscope/trunk/hdl/adq/adq.vhd
0,0 → 1,193
----------------------------------------------------------------------------------------------------
--| Modular Oscilloscope
--| UNSL - Argentina
--|
--| File: adq.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--| Adquisition control module.
--| It drives the ADC chips.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | apr-2008 | First testing
--| 0.10 | apr-2009 | First release
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
--| Wishbone Rev. B.3 compatible
----------------------------------------------------------------------------------------------------
 
 
 
 
 
 
 
-- ADR+1 datos canal 1
-- ADR+2 datos canal 2
-- ADR+3 sin usar
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.NUMERIC_STD.ALL;
--use work.adq_pgk.all;
 
entity adq is
generic (
DEFALT_CONFIG : std_logic_vector := "0000100000000000"
-- bits 8 a 0 clk_pre_scaler
-- bits 9 clk_pre_scaler_ena
-- bit 10 adc_sleep
-- bit 11 adc_chip_sel
-- bits 12 a 15 sin usar
-- si clk_pre_scaler_ena = 1
-- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2)
-- sino frecuencia_adc = frecuencia_wbn
);
port(
-- Externo
adc_data: in std_logic_vector (9 downto 0);
adc_sel: out std_logic;
adc_clk: out std_logic;
adc_sleep: out std_logic;
adc_chip_sel: out std_logic;
 
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (15 downto 0);
ADR_I: in std_logic_vector (1 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
DAT_O: out std_logic_vector (15 downto 0);
ACK_O: out std_logic
);
end adq;
architecture beh1 of adq is
-- Tipos
type data_array is array(0 to 2) of std_logic_vector(15 downto 0);
-- type arr is array(0 to 3) of std_logic_vector(15 downto 0);
--
-- signal arr_a : arr;
-- signal vec_0, vec_1, vec_2, vec_3 : std_logic vector(15 downto 0);
-- ....
-- arr_a(0) <= vec_0;
-- arr_a(1) <= vec_1;
-- ....
 
signal config: std_logic_vector (15 downto 0);
signal selector: data_array;
-- Registros
signal count: std_logic_vector (9 downto 0);
 
signal s_adc_clk, s_adc_sleep, s_adc_chip_sel: std_logic;
 
 
signal clk_pre_scaler: std_logic_vector (8 downto 0);
signal clk_pre_scaler_ena: std_logic;
--signal clk_enable: std_logic_vector (9 downto 0);
 
begin
--------------------------------------------------------------------------------------------------
-- Asignaciones
 
selector(0) <= config;
selector(1) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
selector(2) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
--selector(3) <= (others => '0' ); -- Sin usar
 
clk_pre_scaler <= config(8 downto 0);
clk_pre_scaler_ena <= config(9);
s_adc_sleep <= config(10);
s_adc_chip_sel <= config(11);
-- sin asignar <= config(13); para usar en otras implementaciones
-- sin asignar <= config(14);
-- sin asignar <= config(15);
 
adc_sleep <= s_adc_sleep;
adc_chip_sel <= s_adc_chip_sel;
--------------------------------------------------------------------------------------------------
 
process (CLK_I, clk_pre_scaler,RST_I,count, clk_pre_scaler_ena)
begin
if RST_I = '1' then
count <= (others => '0');
s_adc_clk <= '0';
elsif clk_pre_scaler_ena = '1' then
if CLK_I'event and CLK_I = '1' then
count <= count + 1;
if count = clk_pre_scaler then
s_adc_clk <= not(s_adc_clk);
count <= (others => '0');
end if;
end if;
else
count <= (others => '0');
s_adc_clk <= CLK_I;
end if;
end process;
adc_clk <= s_adc_clk;
--------------------------------------------------------------------------------------------------
 
ACK_O <= CYC_I and STB_I and (data_ack_ready or conf_ack_ready);
data_ack_ready <= '1' when (unsigned(count) = 0 and WE_I = '0' and unsigned(ADR_I) /= 0 and s_adc_clk = '1')
or (clk_pre_scaler_ena /= '1')
else
'0';
 
conf_ack_ready <= '1' when unsigned(ADR_I) = 0 else
'0';
--------------------------------------------------------------------------------------------------
 
adc_sel <= '1' when unsigned(ADR_I) = 2 else -- selecciona canal Q
'0'; -- selecciona canal I
--------------------------------------------------------------------------------------------------
-- Lectura y escritura de datos
 
DAT_O <= selector(conv_integer(ADR_I));
 
process (CLK_I, ADR_I, RST_I, DAT_I)
begin
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
config <= DEFALT_CONFIG;
elsif WE_I = '1' and CYC_I = '1' and STB_I = '1' then
if unsigned(ADR_I) = 0 then
config <= DAT_I;
end if;
end if;
end if;
 
end process;
 
 
end architecture beh1;
/modular_oscilloscope/trunk/hdl/adq/adq_pkg.vhd
0,0 → 1,69
----------------------------------------------------------------------------------------------------
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: adq_pkg.vhd
--| Version: 0.01
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--| Adquisition control module.
--| Package for instantiate all adq modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | apr-2009 | First release
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package adq_pkg is
--------------------------------------------------------------------------------------------------
-- Componentes
component adq is
generic (
DEFALT_CONFIG : std_logic_vector
-- bits 8 a 0 clk_pre_scaler
-- bits 9 clk_pre_scaler_ena
-- bit 10 adc_sleep
-- bit 11 adc_chip_sel
-- bits 12 a 15 sin usar
-- si clk_pre_scaler_ena = 1
-- frecuencia_adc = frecuencia_wbn / (clk_pre_scaler + 2)
-- sino frecuencia_adc = frecuencia_wbn
);
port(
-- Externo
adc_data: in std_logic_vector (9 downto 0);
adc_sel: out std_logic;
adc_clk: out std_logic;
adc_sleep: out std_logic;
adc_chip_sel: out std_logic;
 
-- Interno
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (15 downto 0);
ADR_I: in std_logic_vector (1 downto 0);
CYC_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
DAT_O: out std_logic_vector (15 downto 0);
ACK_O: out std_logic
);
end component adq;
 
end package adq_pkg;
modular_oscilloscope/trunk/hdl/adq/adq_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: modular_oscilloscope/trunk/hdl/adq/adq_tbench_text.vhd =================================================================== --- modular_oscilloscope/trunk/hdl/adq/adq_tbench_text.vhd (nonexistent) +++ modular_oscilloscope/trunk/hdl/adq/adq_tbench_text.vhd (revision 20) @@ -0,0 +1,322 @@ +-------------------------------------------------------------------------------------------------100 +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: adq_tbench_text.vhd +--| Version: 0.01 +--| Tested in: Actel A3PE1500 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| Adquisition control module. +--| This file is only for test purposes. Testing adq. Test bench. +--| It may not work for other than Actel Libero software. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | apr-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright ® 2009, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + +-- NOTE: It may not work for other than Actel Libero software. +-- You can download Libero for free from Actel website. + + + + +-- Clock Domains: + +-- Unclocked +-- --------- +-- Signals: +-- adc_data +-- RST_I +-- DAT_I +-- ADR_I +-- CYC_I +-- STB_I +-- WE_I +-- RST_I + +-- Clocked +-- --------- +-- CLK_I +library ieee, std; +use ieee.std_logic_1164.all; +library syncad_vhdl_lib; +use syncad_vhdl_lib.TBDefinitions.all; +-- Additional libraries used by Model Under Test. +library IEEE; +use work.adq_pkg.all; +-- End Additional libraries used by Model Under Test. + +entity stimulus is + port ( + adc_data: inout std_logic_vector (9 downto 0); + RST_I: inout std_logic; + CLK_I: inout std_logic; + DAT_I: inout std_logic_vector (15 downto 0); + ADR_I: inout std_logic_vector (1 downto 0); + CYC_I: inout std_logic; + STB_I: inout std_logic; + WE_I: inout std_logic); + +end stimulus; + +architecture STIMULATOR of stimulus is + + -- Control Signal Declarations + signal tb_status : TStatus; + signal tb_ParameterInitFlag : boolean := false; + + -- Parm Declarations + signal clk_MinHL : time := 0 ns; + signal clk_MaxHL : time := 0 ns; + signal clk_MinLH : time := 0 ns; + signal clk_MaxLH : time := 0 ns; + signal clk_JFall : time := 0 ns; + signal clk_JRise : time := 0 ns; + signal clk_Duty : real := 0.0; + signal clk_Period : time := 0 ns; + signal clk_Offset : time := 0 ns; + + -- Status Control block. + +begin + + process + variable good : boolean; + begin + wait until tb_ParameterInitFlag; + tb_status <= TB_ONCE; + wait for 20000 ns; + tb_status <= TB_DONE; + wait; + end process; + + -- Parm Assignment Block + AssignParms : process + variable clk_MinHL_real : real; + variable clk_MaxHL_real : real; + variable clk_MinLH_real : real; + variable clk_MaxLH_real : real; + variable clk_JFall_real : real; + variable clk_JRise_real : real; + variable clk_Duty_real : real; + variable clk_Period_real : real; + variable clk_Offset_real : real; + begin + clk_MinHL_real := 0.0; + clk_MinHL <= clk_MinHL_real * 1 ns; + clk_MaxHL_real := 0.0; + clk_MaxHL <= clk_MaxHL_real * 1 ns; + clk_MinLH_real := 0.0; + clk_MinLH <= clk_MinLH_real * 1 ns; + clk_MaxLH_real := 0.0; + clk_MaxLH <= clk_MaxLH_real * 1 ns; + clk_JFall_real := 0.0; + clk_JFall <= clk_JFall_real * 1 ns; + clk_JRise_real := 0.0; + clk_JRise <= clk_JRise_real * 1 ns; + clk_Duty_real := 50.0; + clk_Duty <= clk_Duty_real; + clk_Period_real := 100.0; --<--<--<--<-- + clk_Period <= clk_Period_real * 1 ns; + clk_Offset_real := 0.0; + clk_Offset <= clk_Offset_real * 1 ns; + tb_ParameterInitFlag <= true; + wait; + end process; + + -- Clocks + + -- Clock Instantiation + tb_clk : entity syncad_vhdl_lib.tb_clock_minmax + generic map (name => "tb_clk", + initialize => true, + state1 => '1', + state2 => '0') + port map (tb_status, + CLK_I, + clk_MinLH, + clk_MaxLH, + clk_MinHL, + clk_MaxHL, + clk_Offset, + clk_Period, + clk_Duty, + clk_JRise, + clk_JFall); + + -- Clocked Sequences + + -- Sequence: Unclocked + Unclocked : process + begin + -- Valores iniciales + ADR_I <= "00"; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + DAT_I <= "0000000000000000"; + adc_data <= "1010101010"; + + -- Reset inicial + wait for 0 ns; + RST_I <= '1'; + wait for 310 ns; + RST_I <= '0'; + + + + -- Prueba escritura a puertos + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000000000000000"; + + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000010000000000"; + + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000100000000000"; + wait for 100 ns; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000110000000000"; + + + + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000100000000000"; + wait for 100 ns; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + + -- Prueba valores preescala + ---- clk_pre_scaler_ena = 1, clk_pre_scaler = 0 (frec/4) + wait for 100 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000101000000000"; + wait for 100 ns; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + + ---- clk_pre_scaler_ena = 1, clk_pre_scaler = 3 (frec/8) + wait for 1000 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000101000000011"; + wait for 100 ns; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + + ---- clk_pre_scaler_ena = 1, clk_pre_scaler = 10 (frec/24) + wait for 1800 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000101000001010"; + wait for 100 ns; + CYC_I <= '0'; STB_I <= '0'; WE_I <= '0'; + + + -- Prueba de lectura de ADC + ---- Canal 1 + wait for 3000 ns; + ADR_I <= "01"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '0'; + + ---- Canal 1 + wait for 3000 ns; + ADR_I <= "10"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '0'; + + ---- Cambio de parámetros y lectura canal 1 + wait for 3000 ns; + ADR_I <= "00"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '1'; + DAT_I <= "0000100111111111"; + wait for 100 ns; + ADR_I <= "01"; + CYC_I <= '1'; STB_I <= '1'; WE_I <= '0'; + + wait; + + end process; +end STIMULATOR; + +-- Test Bench wrapper for stimulus and Model Under Test +library ieee, std; +use ieee.std_logic_1164.all; +library syncad_vhdl_lib; +use syncad_vhdl_lib.TBDefinitions.all; +-- Additional libraries used by Model Under Test. +library IEEE; +use work.adq_pkg.all; +-- End Additional libraries used by Model Under Test. + +entity testbench is +end testbench; +architecture tbGeneratedCode of testbench is + -- Externo + signal adc_data: std_logic_vector (9 downto 0); + signal adc_sel: std_logic; + signal adc_clk: std_logic; + signal adc_sleep: std_logic; + signal adc_chip_sel: std_logic; + + -- Interno + signal RST_I: std_logic; + signal CLK_I: std_logic; + signal DAT_I: std_logic_vector (15 downto 0); + signal ADR_I: std_logic_vector (1 downto 0); + signal CYC_I: std_logic; + signal STB_I: std_logic; + signal WE_I: std_logic; + signal DAT_O: std_logic_vector (15 downto 0); + signal ACK_O: std_logic ; + +begin + + stimulus_0 : entity work.stimulus + port map ( + adc_data => adc_data, + RST_I => RST_I, + CLK_I => CLK_I, + DAT_I => DAT_I, + ADR_I => ADR_I, + CYC_I => CYC_I, + STB_I => STB_I, + WE_I => WE_I + ); + + -- Instantiation of Model Under Test. + adq_0 : entity work.adq + port map ( + -- Interno + CLK_I => CLK_I, + RST_I => RST_I, + DAT_I => DAT_I, + DAT_O => DAT_O, + ADR_I => ADR_I, + CYC_I => CYC_I, + STB_I => STB_I, + WE_I => WE_I, + ACK_O => ACK_O, + + -- Externo + adc_clk => adc_clk, + adc_data => adc_data, + adc_sel => adc_sel, + adc_sleep => adc_sleep, + adc_chip_sel => adc_chip_sel + ); +end tbGeneratedCode;
modular_oscilloscope/trunk/hdl/adq/adq_tbench_text.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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