URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
Subversion Repositories xucpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/xucpu/trunk/src/components/BRAM/RAM.vhdl
32,7 → 32,7
GENERIC ( |
filename : STRING := ""; |
w_data : NATURAL RANGE 1 TO 32 := 16; |
w_addr : NATURAL RANGE 8 TO 14 := 10); |
w_addr : NATURAL RANGE 8 TO 15 := 10); |
PORT ( |
clk : IN STD_LOGIC; |
we : IN STD_LOGIC; |
/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
20,7 → 20,7
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
USE work.ram_parts.ALL; |
USE work.RAM.ALL; |
|
-- Test bench for instatiating a memory and initialising |
-- it from a file. |
30,7 → 30,7
|
ARCHITECTURE Structural OF tb_generic_ram IS |
|
CONSTANT w_addr : INTEGER := 12; |
CONSTANT w_addr : INTEGER := 15; |
|
SIGNAL clock : STD_LOGIC := '0'; |
SIGNAL we : STD_LOGIC := '0'; |
44,10 → 44,10
|
BEGIN -- ARCHITECTURE Structural |
|
RAM1 : RAM_GENERIC |
RAM1 : memory |
GENERIC MAP ( |
filename => "test_data.txt", |
w_addr => 12) |
w_addr => w_addr) |
PORT MAP ( |
clk => clock, |
we => we, |
60,7 → 60,7
CTR1 : PROCESS (clock) IS |
BEGIN -- PROCESS CTR1 |
IF rising_edge(clock) THEN -- rising clock edge |
IF ctr_a = 4095 THEN |
IF ctr_a = (2**w_addr) - 1 THEN |
ctr_a <= 0; |
ELSE |
ctr_a <= ctr_a + 1; |