OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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    from Rev 191 to Rev 192
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Rev 191 → Rev 192

/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
144,9 → 144,9
reg reset_n;
wire puc_rst;
reg nmi;
reg [13:0] irq;
wire [13:0] irq_acc;
wire [13:0] irq_in;
reg [`IRQ_NR-3:0] irq;
wire [`IRQ_NR-3:0] irq_acc;
wire [`IRQ_NR-3:0] irq_in;
reg cpu_en;
reg [13:0] wkup;
wire [13:0] wkup_in;
237,10 → 237,10
dco_local_enable = 1'b0;
forever
begin
#25; // 20 MHz
dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
if (dco_local_enable)
dco_clk = ~dco_clk;
#25; // 20 MHz
dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
if (dco_local_enable)
dco_clk = ~dco_clk;
end
end
 
250,10 → 250,10
lfxt_local_enable = 1'b0;
forever
begin
#763; // 655 kHz
lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
if (lfxt_local_enable)
lfxt_clk = ~lfxt_clk;
#763; // 655 kHz
lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
if (lfxt_local_enable)
lfxt_clk = ~lfxt_clk;
end
end
 
270,7 → 270,7
begin
error = 0;
stimulus_done = 1;
irq = 14'h0000;
irq = {`IRQ_NR-2{1'b0}};
nmi = 1'b0;
wkup = 14'h0000;
cpu_en = 1'b1;
444,7 → 444,7
.p6_dout_en (p6_dout_en), // Port 6 data output enable
.p6_sel (p6_sel), // Port 6 function select
.per_dout (per_dout_dio), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.p1_din (p1_din), // Port 1 data input
481,7 → 481,7
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (inclk), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
.irq_ta0_acc (irq_acc[`IRQ_NR-7]),// Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
578,35 → 578,35
// Map peripheral interrupts & wakeups
//----------------------------------------
 
assign irq_in = irq | {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
irq_uart_rx, // Vector 7 (0xFFEE)
irq_uart_tx, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
irq_port2, // Vector 3 (0xFFE6)
irq_port1, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
1'b0}; // Vector 0 (0xFFE0)
assign irq_in = irq | {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
irq_uart_rx, // Vector 7 (0xFFEE)
irq_uart_tx, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
irq_port2, // Vector 3 (0xFFE6)
irq_port1, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
{`IRQ_NR-15{1'b0}}}; // Vector 0 (0xFFE0)
 
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
1'b0, // Vector 9 (0xFFF2)
1'b0, // Vector 8 (0xFFF0)
1'b0, // Vector 7 (0xFFEE)
1'b0, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
1'b0, // Vector 3 (0xFFE6)
1'b0, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
1'b0}; // Vector 0 (0xFFE0)
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
1'b0, // Vector 9 (0xFFF2)
1'b0, // Vector 8 (0xFFF0)
1'b0, // Vector 7 (0xFFEE)
1'b0, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
1'b0, // Vector 3 (0xFFE6)
1'b0, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
1'b0}; // Vector 0 (0xFFE0)
 
 
//
626,7 → 626,7
.data_out_en (1'b0), // Output enable
.data_out (1'b0) // Output
);
io_cell sda_slave_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_slave_in), // Input
642,7 → 642,7
.data_out_en (!dbg_scl_master), // Output enable
.data_out (1'b0) // Output
);
io_cell sda_master_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_master_in), // Input
726,17 → 726,17
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
750,8 → 750,8
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
 
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
48,101 → 48,101
module omsp_frontend (
 
// OUTPUTs
dbg_halt_st, // Halt/Run status from CPU
decode_noirq, // Frontend decode instruction
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: Reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_mov, // Decoded Inst: mov instruction
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
irq_acc, // Interrupt request accepted (one-hot signal)
mab, // Frontend Memory address bus
mb_en, // Frontend Memory bus enable
mclk_enable, // Main System Clock enable
mclk_wkup, // Main System Clock wake-up (asynchronous)
nmi_acc, // Non-Maskable interrupt request accepted
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
dbg_halt_st, // Halt/Run status from CPU
decode_noirq, // Frontend decode instruction
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: Reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_mov, // Decoded Inst: mov instruction
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
irq_acc, // Interrupt request accepted (one-hot signal)
mab, // Frontend Memory address bus
mb_en, // Frontend Memory bus enable
mclk_enable, // Main System Clock enable
mclk_wkup, // Main System Clock wake-up (asynchronous)
nmi_acc, // Non-Maskable interrupt request accepted
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
 
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
mdb_in, // Frontend Memory data bus input
nmi_pnd, // Non-maskable interrupt pending
nmi_wkup, // NMI Wakeup
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
puc_rst, // Main system reset
scan_enable, // Scan enable (active during scan shifting)
wdt_irq, // Watchdog-timer interrupt
wdt_wkup, // Watchdog Wakeup
wkup // System Wake-up (asynchronous)
cpu_en_s, // Enable CPU code execution (synchronous)
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
mdb_in, // Frontend Memory data bus input
nmi_pnd, // Non-maskable interrupt pending
nmi_wkup, // NMI Wakeup
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
puc_rst, // Main system reset
scan_enable, // Scan enable (active during scan shifting)
wdt_irq, // Watchdog-timer interrupt
wdt_wkup, // Watchdog Wakeup
wkup // System Wake-up (asynchronous)
);
 
// OUTPUTs
//=========
output dbg_halt_st; // Halt/Run status from CPU
output decode_noirq; // Frontend decode instruction
output [3:0] e_state; // Execution state
output exec_done; // Execution completed
output [7:0] inst_ad; // Decoded Inst: destination addressing mode
output [7:0] inst_as; // Decoded Inst: source addressing mode
output [11:0] inst_alu; // ALU control signals
output inst_bw; // Decoded Inst: byte width
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
output inst_irq_rst; // Decoded Inst: Reset interrupt
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
output inst_mov; // Decoded Inst: mov instruction
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
output [15:0] inst_src; // Decoded Inst: source (one hot)
output [2:0] inst_type; // Decoded Instruction type
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [15:0] mab; // Frontend Memory address bus
output mb_en; // Frontend Memory bus enable
output mclk_enable; // Main System Clock enable
output mclk_wkup; // Main System Clock wake-up (asynchronous)
output nmi_acc; // Non-Maskable interrupt request accepted
output [15:0] pc; // Program counter
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
output dbg_halt_st; // Halt/Run status from CPU
output decode_noirq; // Frontend decode instruction
output [3:0] e_state; // Execution state
output exec_done; // Execution completed
output [7:0] inst_ad; // Decoded Inst: destination addressing mode
output [7:0] inst_as; // Decoded Inst: source addressing mode
output [11:0] inst_alu; // ALU control signals
output inst_bw; // Decoded Inst: byte width
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
output inst_irq_rst; // Decoded Inst: Reset interrupt
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
output inst_mov; // Decoded Inst: mov instruction
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
output [15:0] inst_src; // Decoded Inst: source (one hot)
output [2:0] inst_type; // Decoded Instruction type
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [15:0] mab; // Frontend Memory address bus
output mb_en; // Frontend Memory bus enable
output mclk_enable; // Main System Clock enable
output mclk_wkup; // Main System Clock wake-up (asynchronous)
output nmi_acc; // Non-Maskable interrupt request accepted
output [15:0] pc; // Program counter
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
 
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [13:0] irq; // Maskable interrupts
input mclk; // Main system clock
input [15:0] mdb_in; // Frontend Memory data bus input
input nmi_pnd; // Non-maskable interrupt pending
input nmi_wkup; // NMI Wakeup
input [15:0] pc_sw; // Program counter software value
input pc_sw_wr; // Program counter software write
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
input wdt_irq; // Watchdog-timer interrupt
input wdt_wkup; // Watchdog Wakeup
input wkup; // System Wake-up (asynchronous)
input cpu_en_s; // Enable CPU code execution (synchronous)
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [`IRQ_NR-3:0] irq; // Maskable interrupts
input mclk; // Main system clock
input [15:0] mdb_in; // Frontend Memory data bus input
input nmi_pnd; // Non-maskable interrupt pending
input nmi_wkup; // NMI Wakeup
input [15:0] pc_sw; // Program counter software value
input pc_sw_wr; // Program counter software write
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
input wdt_irq; // Watchdog-timer interrupt
input wdt_wkup; // Watchdog Wakeup
input wkup; // System Wake-up (asynchronous)
 
 
//=============================================================================
149,6 → 149,15
// 1) UTILITY FUNCTIONS
//=============================================================================
 
// 64 bits one-hot decoder
function [63:0] one_hot64;
input [5:0] binary;
begin
one_hot64 = 64'h0000_0000_0000_0000;
one_hot64[binary] = 1'b1;
end
endfunction
 
// 16 bits one-hot decoder
function [15:0] one_hot16;
input [3:0] binary;
157,7 → 166,7
one_hot16[binary] = 1'b1;
end
endfunction
 
// 8 bits one-hot decoder
function [7:0] one_hot8;
input [2:0] binary;
166,6 → 175,17
one_hot8[binary] = 1'b1;
end
endfunction
 
// Get IRQ number
function [5:0] get_irq_num;
input [62:0] irq_all;
integer ii;
begin
get_irq_num = 6'h3f;
for (ii = 62; ii >= 0; ii = ii - 1)
if (&get_irq_num & irq_all[ii]) get_irq_num = ii[5:0];
end
endfunction
 
//=============================================================================
286,36 → 306,38
wire mclk_irq_num = mclk;
`endif
 
// Select interrupt vector
reg [3:0] irq_num;
// Combine all IRQs
`ifdef IRQ_16
wire [62:0] irq_all = {nmi_pnd, irq, 48'h0000_0000_0000} |
`else
`ifdef IRQ_32
wire [62:0] irq_all = {nmi_pnd, irq, 32'h0000} |
`else
`ifdef IRQ_64
wire [62:0] irq_all = {nmi_pnd, irq} |
`endif
`endif
`endif
{1'b0, 3'h0, wdt_irq, {58{1'b0}}};
 
// Select highest priority IRQ
reg [5:0] irq_num;
always @(posedge mclk_irq_num or posedge puc_rst)
if (puc_rst) irq_num <= 4'hf;
if (puc_rst) irq_num <= 6'h3f;
`ifdef CLOCK_GATING
else irq_num <= nmi_pnd ? 4'he :
else
`else
else if (irq_detect) irq_num <= nmi_pnd ? 4'he :
else if (irq_detect)
`endif
irq[13] ? 4'hd :
irq[12] ? 4'hc :
irq[11] ? 4'hb :
(irq[10] | wdt_irq) ? 4'ha :
irq[9] ? 4'h9 :
irq[8] ? 4'h8 :
irq[7] ? 4'h7 :
irq[6] ? 4'h6 :
irq[5] ? 4'h5 :
irq[4] ? 4'h4 :
irq[3] ? 4'h3 :
irq[2] ? 4'h2 :
irq[1] ? 4'h1 :
irq[0] ? 4'h0 : 4'hf;
irq_num <= get_irq_num(irq_all);
 
wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
// Generate selected IRQ vector address
wire [15:0] irq_addr = {9'h1ff, irq_num, 1'b0};
 
// Interrupt request accepted
wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
wire [13:0] irq_acc = irq_acc_all[13:0];
wire nmi_acc = irq_acc_all[14];
wire [63:0] irq_acc_all = one_hot64(irq_num) & {64{(i_state==I_IRQ_FETCH)}};
wire [`IRQ_NR-3:0] irq_acc = irq_acc_all[61:64-`IRQ_NR];
wire nmi_acc = irq_acc_all[62];
 
//
// 4.2) SYSTEM WAKEUP
/openmsp430/trunk/core/rtl/verilog/omsp_alu.v
97,7 → 97,7
 
reg [4:0] Z_;
begin
Z_ = {1'b0,X}+{1'b0,Y}+{4'b0,C_};
Z_ = {1'b0,X}+{1'b0,Y}+{4'b0000,C_};
if (Z_<5'd10) bcd_add = Z_;
else bcd_add = Z_+5'd6;
end
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
139,6 → 139,17
 
 
//-------------------------------------------------------
// Number of available IRQs
//-------------------------------------------------------
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
//-------------------------------------------------------
//`define IRQ_16
//`define IRQ_32
`define IRQ_64
 
 
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
630,6 → 641,19
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
 
// Number of available IRQs
`ifdef IRQ_16
`define IRQ_NR 16
`endif
`ifdef IRQ_32
`define IRQ_NR 32
`define IRQ_NR_GE_32
`endif
`ifdef IRQ_64
`define IRQ_NR 64
`define IRQ_NR_GE_32
`endif
 
//
// STATES, REGISTER FIELDS, ...
//======================================
851,6 → 875,20
//======================================
// CONFIGURATION CHECKS
//======================================
 
`ifdef IRQ_16
`ifdef IRQ_32
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef IRQ_32
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
114,7 → 114,7
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
output mclk; // Main system clock
142,7 → 142,7
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [13:0] irq; // Maskable interrupts
input [`IRQ_NR-3:0] irq; // Maskable interrupts (14, 30 or 62)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
input [15:0] per_dout; // Peripheral data output
261,7 → 261,7
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.cpuoff (cpuoff), // Turns off the CPU
317,7 → 317,7
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpuoff (cpuoff), // Turns off the CPU
411,7 → 411,7
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
// INPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
446,7 → 446,7
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
// INPUTs
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
471,32 → 471,32
omsp_watchdog watchdog_0 (
 
// OUTPUTs
.per_dout (per_dout_wdog), // Peripheral data output
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_reset (wdt_reset), // Watchdog-timer reset
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
.per_dout (per_dout_wdog), // Peripheral data output
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_reset (wdt_reset), // Watchdog-timer reset
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
// INPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_irq_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_irq_clr (irq_acc[`IRQ_NR-6]), // Clear Watchdog-timer interrupt flag
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
);
`else
assign per_dout_wdog = 16'h0000;
516,7 → 516,7
 
// OUTPUTs
.per_dout (per_dout_mpy), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
559,7 → 559,7
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_id (cpu_id), // CPU ID
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
166,6 → 166,17
`undef NMI
`endif
 
// Number of available IRQs
`ifdef IRQ_16
`undef IRQ_16
`endif
`ifdef IRQ_32
`undef IRQ_32
`endif
`ifdef IRQ_64
`undef IRQ_64
`endif
 
// Input synchronizers
`ifdef SYNC_NMI
`undef SYNC_NMI
382,6 → 393,14
`undef PER_MSB
`endif
 
// Number of available IRQs
`ifdef IRQ_NR
`undef IRQ_NR
`endif
`ifdef IRQ_NR_GE_32
`undef IRQ_NR_GE_32
`endif
 
// Instructions type
`ifdef INST_SO
`undef INST_SO
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
58,6 → 58,8
# Interrupts & NMI
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log
../bin/msp430sim nmi | tee ./log/nmi.log
../bin/msp430sim irq32 | tee ./log/irq32.log
../bin/msp430sim irq64 | tee ./log/irq64.log
 
# ROM Data Read access
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log
/openmsp430/trunk/core/sim/rtl_sim/src/irq32.v
0,0 → 1,345
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* IRQ 1 to 16 FOR SYSTEM WITH 32 IRQs */
/*---------------------------------------------------------------------------*/
/* Test the some IRQs for RTL configuration with more than 16 IRQs: */
/* */
/* - for 16 IRQ configuration: test is skipped. */
/* - for 32 IRQ configuration: will test IRQ 1 to 16. */
/* - for 64 IRQ configuration: will test IRQ 32 to 48. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
 
integer i;
reg [15:0] temp_val;
 
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef IRQ_NR_GE_32
 
repeat(5) @(posedge mclk);
stimulus_done = 0;
 
// RETI Instruction test
//--------------------------
@(r15==16'h1000);
if (r3 !==16'h0000) tb_error("====== RESET Vector: R3 value =====");
if (r4 !==16'h0000) tb_error("====== RESET Vector: R4 value =====");
if (r5 !==16'h0000) tb_error("====== RESET Vector: R5 value =====");
if (r6 !==16'h0000) tb_error("====== RESET Vector: R6 value =====");
if (r7 !==16'h0000) tb_error("====== RESET Vector: R7 value =====");
if (r8 !==16'h0000) tb_error("====== RESET Vector: R8 value =====");
if (r9 !==16'h0000) tb_error("====== RESET Vector: R9 value =====");
if (r10 !==16'h0000) tb_error("====== RESET Vector: R10 value =====");
if (r11 !==16'h0000) tb_error("====== RESET Vector: R11 value =====");
if (r12 !==16'h0000) tb_error("====== RESET Vector: R12 value =====");
if (r13 !==16'h0000) tb_error("====== RESET Vector: R13 value =====");
if (r14 !==16'h0000) tb_error("====== RESET Vector: R14 value =====");
 
 
// RETI Instruction test
//--------------------------
@(r15==16'h2000);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== RETI: SP value =====");
if (r2 !==16'h010f) tb_error("====== RETI: SR value =====");
if (r5 !==16'h1234) tb_error("====== RETI: R5 value =====");
 
 
// Test interruption 0
//--------------------------
@(r15==16'h3000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-32:0] = {`IRQ_NR-32+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-32:0] = {`IRQ_NR-32+1{1'b0}};
 
@(r15==16'h3001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 0: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 0: GIE value =====");
if (r6 !==16'h5678) tb_error("====== IRQ 0: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 0: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 0: R8 value =====");
 
 
// Test interruption 1
//--------------------------
@(r15==16'h4000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-31:0] = {`IRQ_NR-31+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-31:0] = {`IRQ_NR-31+1{1'b0}};
 
@(r15==16'h4001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 1: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 1: GIE value =====");
if (r6 !==16'h9abc) tb_error("====== IRQ 1: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 1: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 1: R8 value =====");
 
 
// Test interruption 2
//--------------------------
@(r15==16'h5000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-30:0] = {`IRQ_NR-30+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-30:0] = {`IRQ_NR-30+1{1'b0}};
 
@(r15==16'h5001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 2: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 2: GIE value =====");
if (r6 !==16'hdef1) tb_error("====== IRQ 2: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 2: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 2: R8 value =====");
 
 
// Test interruption 3
//--------------------------
@(r15==16'h6000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-29:0] = {`IRQ_NR-29+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-29:0] = {`IRQ_NR-29+1{1'b0}};
 
@(r15==16'h6001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 3: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 3: GIE value =====");
if (r6 !==16'h2345) tb_error("====== IRQ 3: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 3: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 3: R8 value =====");
 
 
// Test interruption 4
//--------------------------
@(r15==16'h7000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-28:0] = {`IRQ_NR-28+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-28:0] = {`IRQ_NR-28+1{1'b0}};
 
@(r15==16'h7001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 4: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 4: GIE value =====");
if (r6 !==16'h6789) tb_error("====== IRQ 4: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 4: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 4: R8 value =====");
 
 
// Test interruption 5
//--------------------------
@(r15==16'h8000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-27:0] = {`IRQ_NR-27+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-27:0] = {`IRQ_NR-27+1{1'b0}};
 
@(r15==16'h8001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 5: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 5: GIE value =====");
if (r6 !==16'habcd) tb_error("====== IRQ 5: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 5: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 5: R8 value =====");
 
 
// Test interruption 6
//--------------------------
@(r15==16'h9000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-26:0] = {`IRQ_NR-26+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-26:0] = {`IRQ_NR-26+1{1'b0}};
 
@(r15==16'h9001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 6: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 6: GIE value =====");
if (r6 !==16'hef12) tb_error("====== IRQ 6: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 6: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 6: R8 value =====");
 
 
// Test interruption 7
//--------------------------
@(r15==16'ha000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-25:0] = {`IRQ_NR-25+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-25:0] = {`IRQ_NR-25+1{1'b0}};
 
@(r15==16'ha001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 7: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 7: GIE value =====");
if (r6 !==16'h3456) tb_error("====== IRQ 7: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 7: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 7: R8 value =====");
 
 
// Test interruption 8
//--------------------------
@(r15==16'hb000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-24:0] = {`IRQ_NR-24+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-24:0] = {`IRQ_NR-24+1{1'b0}};
 
@(r15==16'hb001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 8: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 8: GIE value =====");
if (r6 !==16'h789a) tb_error("====== IRQ 8: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 8: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 8: R8 value =====");
 
 
// Test interruption 9
//--------------------------
@(r15==16'hc000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-23:0] = {`IRQ_NR-23+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-23:0] = {`IRQ_NR-23+1{1'b0}};
 
@(r15==16'hc001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 9: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 9: GIE value =====");
if (r6 !==16'hbcde) tb_error("====== IRQ 9: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 9: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 9: R8 value =====");
 
 
// Test interruption 10
//--------------------------
@(r15==16'hd000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-22:0] = {`IRQ_NR-22+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-22:0] = {`IRQ_NR-22+1{1'b0}};
 
@(r15==16'hd001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 10: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 10: GIE value =====");
if (r6 !==16'hf123) tb_error("====== IRQ 10: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 10: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 10: R8 value =====");
 
 
// Test interruption 11
//--------------------------
@(r15==16'he000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-21:0] = {`IRQ_NR-21+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-21:0] = {`IRQ_NR-21+1{1'b0}};
 
@(r15==16'he001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 11: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 11: GIE value =====");
if (r6 !==16'h4567) tb_error("====== IRQ 11: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 11: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 11: R8 value =====");
 
 
// Test interruption 12
//--------------------------
@(r15==16'hf000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-20:0] = {`IRQ_NR-20+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-20:0] = {`IRQ_NR-20+1{1'b0}};
 
@(r15==16'hf001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 12: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 12: GIE value =====");
if (r6 !==16'h89ab) tb_error("====== IRQ 12: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 12: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 12: R8 value =====");
 
 
// Test interruption 13
//--------------------------
@(r15==16'hf100);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-19:0] = {`IRQ_NR-19+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-19:0] = {`IRQ_NR-19+1{1'b0}};
 
@(r15==16'hf101);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 13: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 13: GIE value =====");
if (r6 !==16'hcdef) tb_error("====== IRQ 13: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 13: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 13: R8 value =====");
 
 
// Test interruption 14
//--------------------------
@(r15==16'hf200);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-18:0] = {`IRQ_NR-18+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-18:0] = {`IRQ_NR-18+1{1'b0}};
 
@(r15==16'hf201);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 14: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 14: GIE value =====");
if (r6 !==16'hfedc) tb_error("====== IRQ 14: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 14: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 14: R8 value =====");
 
 
// Test interruption 15
//--------------------------
@(r15==16'hf300);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-17:0] = {`IRQ_NR-17+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-17:0] = {`IRQ_NR-17+1{1'b0}};
 
@(r15==16'hf301);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 15: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 15: GIE value =====");
if (r6 !==16'hba98) tb_error("====== IRQ 15: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 15: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 15: R8 value =====");
 
 
stimulus_done = 1;
`else
 
$display(" ===============================================");
$display("| SIMULATION SKIPPED |");
$display("| (RTL configured to support 16 IRQs only) |");
$display(" ===============================================");
$finish;
`endif
end
 
/openmsp430/trunk/core/sim/rtl_sim/src/irq64.s43
0,0 → 1,877
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* IRQ 1 to 32 FOR SYSTEM WITH 64 IRQs */
/*---------------------------------------------------------------------------*/
/* Test the some IRQs for RTL configuration with more than 16 IRQs: */
/* */
/* - for 16 IRQ configuration: test is skipped. */
/* - for 32 IRQ configuration: test is skipped. */
/* - for 64 IRQ configuration: will test IRQ 1 to 32. */
/* */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
mov #0x1234, r3
mov #0x1234, r4
mov #0x1234, r5
mov #0x1234, r6
mov #0x1234, r7
mov #0x1234, r8
mov #0x1234, r9
mov #0x1234, r10
mov #0x1234, r11
mov #0x1234, r12
mov #0x1234, r13
mov #0x1234, r14
main:
# Test RESET vector
#------------------------
mov #0x1000, r15
 
 
# Test RETI instruction
#------------------------
 
# Pre-initialize stack
mov #DMEM_252, r1
push #RETI_ROUTINE
push #0x010f
mov #0x0000, &0x0200
 
# Run RETI test
mov #0x0000, r2
mov #0x0000, r5
reti
end_of_reti_test:
 
mov #0x2000, r15
 
 
# Test IRQ 0
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x3000, r15
 
wait_irq00:
cmp #0x5678, r6
jne wait_irq00
 
mov #0x3001, r15
 
 
# Test IRQ 1
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x4000, r15
 
wait_irq01:
cmp #0x9abc, r6
jne wait_irq01
 
mov #0x4001, r15
 
 
# Test IRQ 2
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x5000, r15
 
wait_irq02:
cmp #0xdef1, r6
jne wait_irq02
 
mov #0x5001, r15
 
 
# Test IRQ 3
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x6000, r15
 
wait_irq03:
cmp #0x2345, r6
jne wait_irq03
 
mov #0x6001, r15
 
 
# Test IRQ 4
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x7000, r15
 
wait_irq04:
cmp #0x6789, r6
jne wait_irq04
 
mov #0x7001, r15
 
 
# Test IRQ 5
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x8000, r15
 
wait_irq05:
cmp #0xabcd, r6
jne wait_irq05
 
mov #0x8001, r15
 
 
# Test IRQ 6
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x9000, r15
 
wait_irq06:
cmp #0xef12, r6
jne wait_irq06
 
mov #0x9001, r15
 
 
# Test IRQ 7
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xa000, r15
 
wait_irq07:
cmp #0x3456, r6
jne wait_irq07
 
mov #0xa001, r15
 
 
# Test IRQ 8
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xb000, r15
 
wait_irq08:
cmp #0x789a, r6
jne wait_irq08
 
mov #0xb001, r15
 
 
# Test IRQ 9
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xc000, r15
 
wait_irq09:
cmp #0xbcde, r6
jne wait_irq09
 
mov #0xc001, r15
 
 
# Test IRQ 10
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xd000, r15
 
wait_irq10:
cmp #0xf123, r6
jne wait_irq10
 
mov #0xd001, r15
 
 
# Test IRQ 11
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xe000, r15
 
wait_irq11:
cmp #0x4567, r6
jne wait_irq11
 
mov #0xe001, r15
 
 
# Test IRQ 12
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf000, r15
 
wait_irq12:
cmp #0x89ab, r6
jne wait_irq12
 
mov #0xf001, r15
 
 
# Test IRQ 13
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf100, r15
 
wait_irq13:
cmp #0xcdef, r6
jne wait_irq13
 
mov #0xf101, r15
 
 
# Test IRQ 14
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf200, r15
 
wait_irq14:
cmp #0xfedc, r6
jne wait_irq14
 
mov #0xf201, r15
 
 
# Test IRQ 15
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf300, r15
 
wait_irq15:
cmp #0xba98, r6
jne wait_irq15
 
mov #0xf301, r15
 
 
# Test IRQ 16
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf400, r15
 
wait_irq16:
cmp #0x7654, r6
jne wait_irq16
 
mov #0xf401, r15
 
 
# Test IRQ 17
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf500, r15
 
wait_irq17:
cmp #0x3210, r6
jne wait_irq17
 
mov #0xf501, r15
 
 
# Test IRQ 18
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf600, r15
 
wait_irq18:
cmp #0x0246, r6
jne wait_irq18
 
mov #0xf601, r15
 
 
# Test IRQ 19
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf700, r15
 
wait_irq19:
cmp #0x1357, r6
jne wait_irq19
 
mov #0xf701, r15
 
 
# Test IRQ 20
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf800, r15
 
wait_irq20:
cmp #0x8ace, r6
jne wait_irq20
 
mov #0xf801, r15
 
 
# Test IRQ 21
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf900, r15
 
wait_irq21:
cmp #0x9bdf, r6
jne wait_irq21
 
mov #0xf901, r15
 
 
# Test IRQ 22
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xfa00, r15
 
wait_irq22:
cmp #0xfdb9, r6
jne wait_irq22
 
mov #0xfa01, r15
 
 
# Test IRQ 23
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xfb00, r15
 
wait_irq23:
cmp #0xeca8, r6
jne wait_irq23
 
mov #0xfb01, r15
 
 
# Test IRQ 24
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xfc00, r15
 
wait_irq24:
cmp #0x7531, r6
jne wait_irq24
 
mov #0xfc01, r15
 
 
# Test IRQ 25
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xfd00, r15
 
wait_irq25:
cmp #0x6420, r6
jne wait_irq25
 
mov #0xfd01, r15
 
 
# Test IRQ 26
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xfe00, r15
 
wait_irq26:
cmp #0x0134, r6
jne wait_irq26
 
mov #0xfe01, r15
 
 
# Test IRQ 27
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xff00, r15
 
wait_irq27:
cmp #0x1245, r6
jne wait_irq27
 
mov #0xff01, r15
 
 
# Test IRQ 28
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xff10, r15
 
wait_irq28:
cmp #0x2356, r6
jne wait_irq28
 
mov #0xff11, r15
 
 
# Test IRQ 29
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xff20, r15
 
wait_irq29:
cmp #0x3467, r6
jne wait_irq29
 
mov #0xff21, r15
 
 
# Test IRQ 30
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xff30, r15
 
wait_irq30:
cmp #0x4578, r6
jne wait_irq30
 
mov #0xff31, r15
 
 
# Test IRQ 31
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xff40, r15
 
wait_irq31:
cmp #0x5689, r6
jne wait_irq31
 
mov #0xff41, r15
 
 
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
 
 
 
/* ---------------------- FUNCTIONS --------------- */
 
RETI_ROUTINE:
mov #0x1234, r5
jmp end_of_reti_test
 
 
IRQ00_ROUTINE:
mov #0x5678, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ01_ROUTINE:
mov #0x9abc, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ02_ROUTINE:
mov #0xdef1, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ03_ROUTINE:
mov #0x2345, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ04_ROUTINE:
mov #0x6789, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ05_ROUTINE:
mov #0xabcd, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ06_ROUTINE:
mov #0xef12, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ07_ROUTINE:
mov #0x3456, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ08_ROUTINE:
mov #0x789a, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ09_ROUTINE:
mov #0xbcde, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ10_ROUTINE:
mov #0xf123, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ11_ROUTINE:
mov #0x4567, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ12_ROUTINE:
mov #0x89ab, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ13_ROUTINE:
mov #0xcdef, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ14_ROUTINE:
mov #0xfedc, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ15_ROUTINE:
mov #0xba98, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ16_ROUTINE:
mov #0x7654, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ17_ROUTINE:
mov #0x3210, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ18_ROUTINE:
mov #0x0246, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ19_ROUTINE:
mov #0x1357, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ20_ROUTINE:
mov #0x8ace, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ21_ROUTINE:
mov #0x9bdf, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ22_ROUTINE:
mov #0xfdb9, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ23_ROUTINE:
mov #0xeca8, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ24_ROUTINE:
mov #0x7531, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ25_ROUTINE:
mov #0x6420, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ26_ROUTINE:
mov #0x0134, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ27_ROUTINE:
mov #0x1245, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ28_ROUTINE:
mov #0x2356, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ29_ROUTINE:
mov #0x3467, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ30_ROUTINE:
mov #0x4578, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ31_ROUTINE:
mov #0x5689, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
nop
nop
nop
nop
nop
 
 
 
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors64, "a"
.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority) <unused>
.word IRQ01_ROUTINE ; Interrupt 1 <unused>
.word IRQ02_ROUTINE ; Interrupt 2 <unused>
.word IRQ03_ROUTINE ; Interrupt 3 <unused>
.word IRQ04_ROUTINE ; Interrupt 4 <unused>
.word IRQ05_ROUTINE ; Interrupt 5 <unused>
.word IRQ06_ROUTINE ; Interrupt 6 <unused>
.word IRQ07_ROUTINE ; Interrupt 7 <unused>
.word IRQ08_ROUTINE ; Interrupt 8 <unused>
.word IRQ09_ROUTINE ; Interrupt 9 <unused>
.word IRQ10_ROUTINE ; Interrupt 10 <unused>
.word IRQ11_ROUTINE ; Interrupt 11 <unused>
.word IRQ12_ROUTINE ; Interrupt 12 <unused>
.word IRQ13_ROUTINE ; Interrupt 13 <unused>
.word IRQ14_ROUTINE ; Interrupt 14 <unused>
.word IRQ15_ROUTINE ; Interrupt 15 <unused>
.word IRQ16_ROUTINE ; Interrupt 16 <unused>
.word IRQ17_ROUTINE ; Interrupt 17 <unused>
.word IRQ18_ROUTINE ; Interrupt 18 <unused>
.word IRQ19_ROUTINE ; Interrupt 19 <unused>
.word IRQ20_ROUTINE ; Interrupt 20 <unused>
.word IRQ21_ROUTINE ; Interrupt 21 <unused>
.word IRQ22_ROUTINE ; Interrupt 22 <unused>
.word IRQ23_ROUTINE ; Interrupt 23 <unused>
.word IRQ24_ROUTINE ; Interrupt 24 <unused>
.word IRQ25_ROUTINE ; Interrupt 25 <unused>
.word IRQ26_ROUTINE ; Interrupt 26 <unused>
.word IRQ27_ROUTINE ; Interrupt 27 <unused>
.word IRQ28_ROUTINE ; Interrupt 28 <unused>
.word IRQ29_ROUTINE ; Interrupt 29 <unused>
.word IRQ30_ROUTINE ; Interrupt 30 <unused>
.word IRQ31_ROUTINE ; Interrupt 31 <unused>
 
.section .vectors32, "a"
.word end_of_test ; Interrupt 32 <unused>
.word end_of_test ; Interrupt 33 <unused>
.word end_of_test ; Interrupt 34 <unused>
.word end_of_test ; Interrupt 35 <unused>
.word end_of_test ; Interrupt 36 <unused>
.word end_of_test ; Interrupt 37 <unused>
.word end_of_test ; Interrupt 38 <unused>
.word end_of_test ; Interrupt 39 <unused>
.word end_of_test ; Interrupt 40 <unused>
.word end_of_test ; Interrupt 41 <unused>
.word end_of_test ; Interrupt 42 <unused>
.word end_of_test ; Interrupt 43 <unused>
.word end_of_test ; Interrupt 44 <unused>
.word end_of_test ; Interrupt 45 <unused>
.word end_of_test ; Interrupt 46 <unused>
.word end_of_test ; Interrupt 47 <unused>
 
.section .vectors, "a"
.word end_of_test ; Interrupt 48 <unused>
.word end_of_test ; Interrupt 49 <unused>
.word end_of_test ; Interrupt 50 <unused>
.word end_of_test ; Interrupt 51 <unused>
.word end_of_test ; Interrupt 52 <unused>
.word end_of_test ; Interrupt 53 <unused>
.word end_of_test ; Interrupt 54 <unused>
.word end_of_test ; Interrupt 55 <unused>
.word end_of_test ; Interrupt 56 <unused>
.word end_of_test ; Interrupt 57 <unused>
.word end_of_test ; Interrupt 58 Watchdog timer
.word end_of_test ; Interrupt 59 <unused>
.word end_of_test ; Interrupt 60 <unused>
.word end_of_test ; Interrupt 61 <unused>
.word end_of_test ; Interrupt 62 NMI
.word main ; Interrupt 63 (highest priority) RESET
/openmsp430/trunk/core/sim/rtl_sim/src/irq32.s43
0,0 → 1,491
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* IRQ 1 to 16 FOR SYSTEM WITH 32 IRQs */
/*---------------------------------------------------------------------------*/
/* Test the some IRQs for RTL configuration with more than 16 IRQs: */
/* */
/* - for 16 IRQ configuration: test is skipped. */
/* - for 32 IRQ configuration: will test IRQ 1 to 16. */
/* - for 64 IRQ configuration: will test IRQ 32 to 48. */
/* */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
mov #0x1234, r3
mov #0x1234, r4
mov #0x1234, r5
mov #0x1234, r6
mov #0x1234, r7
mov #0x1234, r8
mov #0x1234, r9
mov #0x1234, r10
mov #0x1234, r11
mov #0x1234, r12
mov #0x1234, r13
mov #0x1234, r14
main:
# Test RESET vector
#------------------------
mov #0x1000, r15
 
 
# Test RETI instruction
#------------------------
 
# Pre-initialize stack
mov #DMEM_252, r1
push #RETI_ROUTINE
push #0x010f
mov #0x0000, &0x0200
 
# Run RETI test
mov #0x0000, r2
mov #0x0000, r5
reti
end_of_reti_test:
 
mov #0x2000, r15
 
 
# Test IRQ 0
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x3000, r15
 
wait_irq00:
cmp #0x5678, r6
jne wait_irq00
 
mov #0x3001, r15
 
 
# Test IRQ 1
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x4000, r15
 
wait_irq01:
cmp #0x9abc, r6
jne wait_irq01
 
mov #0x4001, r15
 
 
# Test IRQ 2
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x5000, r15
 
wait_irq02:
cmp #0xdef1, r6
jne wait_irq02
 
mov #0x5001, r15
 
 
# Test IRQ 3
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x6000, r15
 
wait_irq03:
cmp #0x2345, r6
jne wait_irq03
 
mov #0x6001, r15
 
 
# Test IRQ 4
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x7000, r15
 
wait_irq04:
cmp #0x6789, r6
jne wait_irq04
 
mov #0x7001, r15
 
 
# Test IRQ 5
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x8000, r15
 
wait_irq05:
cmp #0xabcd, r6
jne wait_irq05
 
mov #0x8001, r15
 
 
# Test IRQ 6
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0x9000, r15
 
wait_irq06:
cmp #0xef12, r6
jne wait_irq06
 
mov #0x9001, r15
 
 
# Test IRQ 7
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xa000, r15
 
wait_irq07:
cmp #0x3456, r6
jne wait_irq07
 
mov #0xa001, r15
 
 
# Test IRQ 8
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xb000, r15
 
wait_irq08:
cmp #0x789a, r6
jne wait_irq08
 
mov #0xb001, r15
 
 
# Test IRQ 9
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xc000, r15
 
wait_irq09:
cmp #0xbcde, r6
jne wait_irq09
 
mov #0xc001, r15
 
 
# Test IRQ 10
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xd000, r15
 
wait_irq10:
cmp #0xf123, r6
jne wait_irq10
 
mov #0xd001, r15
 
 
# Test IRQ 11
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xe000, r15
 
wait_irq11:
cmp #0x4567, r6
jne wait_irq11
 
mov #0xe001, r15
 
 
# Test IRQ 12
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf000, r15
 
wait_irq12:
cmp #0x89ab, r6
jne wait_irq12
 
mov #0xf001, r15
 
 
# Test IRQ 13
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf100, r15
 
wait_irq13:
cmp #0xcdef, r6
jne wait_irq13
 
mov #0xf101, r15
 
 
# Test IRQ 14
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf200, r15
 
wait_irq14:
cmp #0xfedc, r6
jne wait_irq14
 
mov #0xf201, r15
 
 
# Test IRQ 15
#-------------------------
 
mov #0x0008, r2 ; Enable interrupts
mov #0x0000, r6
mov #0xaaaa, r7
mov #0x5555, r8
mov #0xf300, r15
 
wait_irq15:
cmp #0xba98, r6
jne wait_irq15
 
mov #0xf301, r15
 
 
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
 
 
 
/* ---------------------- FUNCTIONS --------------- */
 
RETI_ROUTINE:
mov #0x1234, r5
jmp end_of_reti_test
 
 
IRQ00_ROUTINE:
mov #0x5678, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ01_ROUTINE:
mov #0x9abc, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ02_ROUTINE:
mov #0xdef1, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ03_ROUTINE:
mov #0x2345, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ04_ROUTINE:
mov #0x6789, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ05_ROUTINE:
mov #0xabcd, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ06_ROUTINE:
mov #0xef12, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ07_ROUTINE:
mov #0x3456, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ08_ROUTINE:
mov #0x789a, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ09_ROUTINE:
mov #0xbcde, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ10_ROUTINE:
mov #0xf123, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ11_ROUTINE:
mov #0x4567, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ12_ROUTINE:
mov #0x89ab, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ13_ROUTINE:
mov #0xcdef, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ14_ROUTINE:
mov #0xfedc, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
IRQ15_ROUTINE:
mov #0xba98, r6
mov r2, r7 ; Save Status register
mov r1, r8 ; Save Stack register
reti
 
nop
nop
nop
nop
nop
 
 
 
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors32, "a"
.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority) <unused>
.word IRQ01_ROUTINE ; Interrupt 1 <unused>
.word IRQ02_ROUTINE ; Interrupt 2 <unused>
.word IRQ03_ROUTINE ; Interrupt 3 <unused>
.word IRQ04_ROUTINE ; Interrupt 4 <unused>
.word IRQ05_ROUTINE ; Interrupt 5 <unused>
.word IRQ06_ROUTINE ; Interrupt 6 <unused>
.word IRQ07_ROUTINE ; Interrupt 7 <unused>
.word IRQ08_ROUTINE ; Interrupt 8 <unused>
.word IRQ09_ROUTINE ; Interrupt 9 <unused>
.word IRQ10_ROUTINE ; Interrupt 10 <unused>
.word IRQ11_ROUTINE ; Interrupt 11 <unused>
.word IRQ12_ROUTINE ; Interrupt 12 <unused>
.word IRQ13_ROUTINE ; Interrupt 13 <unused>
.word IRQ14_ROUTINE ; Interrupt 14 <unused>
.word IRQ15_ROUTINE ; Interrupt 15 <unused>
 
.section .vectors, "a"
.word end_of_test ; Interrupt 16 <unused>
.word end_of_test ; Interrupt 17 <unused>
.word end_of_test ; Interrupt 18 <unused>
.word end_of_test ; Interrupt 19 <unused>
.word end_of_test ; Interrupt 20 <unused>
.word end_of_test ; Interrupt 21 <unused>
.word end_of_test ; Interrupt 22 <unused>
.word end_of_test ; Interrupt 23 <unused>
.word end_of_test ; Interrupt 24 <unused>
.word end_of_test ; Interrupt 25 <unused>
.word end_of_test ; Interrupt 26 Watchdog timer
.word end_of_test ; Interrupt 27 <unused>
.word end_of_test ; Interrupt 28 <unused>
.word end_of_test ; Interrupt 29 <unused>
.word end_of_test ; Interrupt 30 NMI
.word main ; Interrupt 31 (highest priority) RESET
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v
225,13 → 225,13
dbg_uart_wr(CPU_CTL, 16'h0002);
 
// Generate an IRQ
wkup[0] = 1'b1;
wkup[0] = 1'b1;
@(negedge mclk);
irq[0] = 1'b1;
@(negedge irq_acc[0])
irq[`IRQ_NR-16] = 1'b1;
@(negedge irq_acc[`IRQ_NR-16])
@(negedge mclk);
wkup[0] = 1'b0;
irq[0] = 1'b0;
wkup[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b0;
repeat(10) @(posedge mclk);
 
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
200,9 → 200,9
test_nr = 8;
 
// Generate IRQ to terminate the test pattern
irq[1] = 1'b1;
irq[`IRQ_NR-15] = 1'b1;
@(r13);
irq[1] = 1'b0;
irq[`IRQ_NR-15] = 1'b0;
stimulus_done = 1;
 
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.v
65,12 → 65,12
#(6000);
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
 
wkup[0] = 1'b1;
wkup[0] = 1'b1;
@(negedge mclk)
irq[0] = 1'b1;
@(negedge irq_acc[0])
wkup[0] = 1'b0;
irq[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b1;
@(negedge irq_acc[`IRQ_NR-16])
wkup[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b0;
@(r15==16'h1002);
nmi = 1'b0;
182,12 → 182,12
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI nested: CPU is not sleeping =====");
#(2000);
wkup[0] = 1'b1;
irq[0] = 1'b1;
@(negedge irq_acc[0])
wkup[0] = 1'b0;
irq[0] = 1'b0;
nmi = 1'b1;
wkup[0] = 1'b1;
irq[`IRQ_NR-16] = 1'b1;
@(negedge irq_acc[`IRQ_NR-16])
wkup[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b0;
nmi = 1'b1;
 
@(r15==16'h4002);
if (r6 !==16'h0001) tb_error("====== NMI nested: NMI irq was not taken =====");
/openmsp430/trunk/core/sim/rtl_sim/src/irq64.v
0,0 → 1,601
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* IRQ 1 to 32 FOR SYSTEM WITH 64 IRQs */
/*---------------------------------------------------------------------------*/
/* Test the some IRQs for RTL configuration with more than 16 IRQs: */
/* */
/* - for 16 IRQ configuration: test is skipped. */
/* - for 32 IRQ configuration: test is skipped. */
/* - for 64 IRQ configuration: will test IRQ 1 to 32. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
 
integer i;
reg [15:0] temp_val;
 
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef IRQ_64
 
repeat(5) @(posedge mclk);
stimulus_done = 0;
 
// RETI Instruction test
//--------------------------
@(r15==16'h1000);
if (r3 !==16'h0000) tb_error("====== RESET Vector: R3 value =====");
if (r4 !==16'h0000) tb_error("====== RESET Vector: R4 value =====");
if (r5 !==16'h0000) tb_error("====== RESET Vector: R5 value =====");
if (r6 !==16'h0000) tb_error("====== RESET Vector: R6 value =====");
if (r7 !==16'h0000) tb_error("====== RESET Vector: R7 value =====");
if (r8 !==16'h0000) tb_error("====== RESET Vector: R8 value =====");
if (r9 !==16'h0000) tb_error("====== RESET Vector: R9 value =====");
if (r10 !==16'h0000) tb_error("====== RESET Vector: R10 value =====");
if (r11 !==16'h0000) tb_error("====== RESET Vector: R11 value =====");
if (r12 !==16'h0000) tb_error("====== RESET Vector: R12 value =====");
if (r13 !==16'h0000) tb_error("====== RESET Vector: R13 value =====");
if (r14 !==16'h0000) tb_error("====== RESET Vector: R14 value =====");
 
 
// RETI Instruction test
//--------------------------
@(r15==16'h2000);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== RETI: SP value =====");
if (r2 !==16'h010f) tb_error("====== RETI: SR value =====");
if (r5 !==16'h1234) tb_error("====== RETI: R5 value =====");
 
 
// Test interruption 0
//--------------------------
@(r15==16'h3000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-64:0] = {`IRQ_NR-64+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-64:0] = {`IRQ_NR-64+1{1'b0}};
 
@(r15==16'h3001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 0: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 0: GIE value =====");
if (r6 !==16'h5678) tb_error("====== IRQ 0: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 0: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 0: R8 value =====");
 
 
// Test interruption 1
//--------------------------
@(r15==16'h4000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-63:0] = {`IRQ_NR-63+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-63:0] = {`IRQ_NR-63+1{1'b0}};
 
@(r15==16'h4001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 1: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 1: GIE value =====");
if (r6 !==16'h9abc) tb_error("====== IRQ 1: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 1: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 1: R8 value =====");
 
 
// Test interruption 2
//--------------------------
@(r15==16'h5000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-62:0] = {`IRQ_NR-62+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-62:0] = {`IRQ_NR-62+1{1'b0}};
 
@(r15==16'h5001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 2: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 2: GIE value =====");
if (r6 !==16'hdef1) tb_error("====== IRQ 2: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 2: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 2: R8 value =====");
 
 
// Test interruption 3
//--------------------------
@(r15==16'h6000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-61:0] = {`IRQ_NR-61+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-61:0] = {`IRQ_NR-61+1{1'b0}};
 
@(r15==16'h6001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 3: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 3: GIE value =====");
if (r6 !==16'h2345) tb_error("====== IRQ 3: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 3: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 3: R8 value =====");
 
 
// Test interruption 4
//--------------------------
@(r15==16'h7000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-60:0] = {`IRQ_NR-60+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-60:0] = {`IRQ_NR-60+1{1'b0}};
 
@(r15==16'h7001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 4: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 4: GIE value =====");
if (r6 !==16'h6789) tb_error("====== IRQ 4: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 4: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 4: R8 value =====");
 
 
// Test interruption 5
//--------------------------
@(r15==16'h8000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-59:0] = {`IRQ_NR-59+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-59:0] = {`IRQ_NR-59+1{1'b0}};
 
@(r15==16'h8001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 5: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 5: GIE value =====");
if (r6 !==16'habcd) tb_error("====== IRQ 5: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 5: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 5: R8 value =====");
 
 
// Test interruption 6
//--------------------------
@(r15==16'h9000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-58:0] = {`IRQ_NR-58+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-58:0] = {`IRQ_NR-58+1{1'b0}};
 
@(r15==16'h9001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 6: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 6: GIE value =====");
if (r6 !==16'hef12) tb_error("====== IRQ 6: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 6: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 6: R8 value =====");
 
 
// Test interruption 7
//--------------------------
@(r15==16'ha000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-57:0] = {`IRQ_NR-57+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-57:0] = {`IRQ_NR-57+1{1'b0}};
 
@(r15==16'ha001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 7: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 7: GIE value =====");
if (r6 !==16'h3456) tb_error("====== IRQ 7: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 7: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 7: R8 value =====");
 
 
// Test interruption 8
//--------------------------
@(r15==16'hb000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-56:0] = {`IRQ_NR-56+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-56:0] = {`IRQ_NR-56+1{1'b0}};
 
@(r15==16'hb001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 8: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 8: GIE value =====");
if (r6 !==16'h789a) tb_error("====== IRQ 8: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 8: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 8: R8 value =====");
 
 
// Test interruption 9
//--------------------------
@(r15==16'hc000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-55:0] = {`IRQ_NR-55+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-55:0] = {`IRQ_NR-55+1{1'b0}};
 
@(r15==16'hc001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 9: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 9: GIE value =====");
if (r6 !==16'hbcde) tb_error("====== IRQ 9: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 9: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 9: R8 value =====");
 
 
// Test interruption 10
//--------------------------
@(r15==16'hd000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-54:0] = {`IRQ_NR-54+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-54:0] = {`IRQ_NR-54+1{1'b0}};
 
@(r15==16'hd001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 10: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 10: GIE value =====");
if (r6 !==16'hf123) tb_error("====== IRQ 10: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 10: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 10: R8 value =====");
 
 
// Test interruption 11
//--------------------------
@(r15==16'he000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-53:0] = {`IRQ_NR-53+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-53:0] = {`IRQ_NR-53+1{1'b0}};
 
@(r15==16'he001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 11: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 11: GIE value =====");
if (r6 !==16'h4567) tb_error("====== IRQ 11: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 11: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 11: R8 value =====");
 
 
// Test interruption 12
//--------------------------
@(r15==16'hf000);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-52:0] = {`IRQ_NR-52+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-52:0] = {`IRQ_NR-52+1{1'b0}};
 
@(r15==16'hf001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 12: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 12: GIE value =====");
if (r6 !==16'h89ab) tb_error("====== IRQ 12: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 12: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 12: R8 value =====");
 
 
// Test interruption 13
//--------------------------
@(r15==16'hf100);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-51:0] = {`IRQ_NR-51+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-51:0] = {`IRQ_NR-51+1{1'b0}};
 
@(r15==16'hf101);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 13: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 13: GIE value =====");
if (r6 !==16'hcdef) tb_error("====== IRQ 13: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 13: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 13: R8 value =====");
 
 
// Test interruption 14
//--------------------------
@(r15==16'hf200);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-50:0] = {`IRQ_NR-50+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-50:0] = {`IRQ_NR-50+1{1'b0}};
 
@(r15==16'hf201);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 14: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 14: GIE value =====");
if (r6 !==16'hfedc) tb_error("====== IRQ 14: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 14: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 14: R8 value =====");
 
 
// Test interruption 15
//--------------------------
@(r15==16'hf300);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-49:0] = {`IRQ_NR-49+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-49:0] = {`IRQ_NR-49+1{1'b0}};
 
@(r15==16'hf301);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 15: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 15: GIE value =====");
if (r6 !==16'hba98) tb_error("====== IRQ 15: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 15: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 15: R8 value =====");
 
 
// Test interruption 16
//--------------------------
@(r15==16'hf400);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-48:0] = {`IRQ_NR-48+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-48:0] = {`IRQ_NR-48+1{1'b0}};
 
@(r15==16'hf401);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 16: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 16: GIE value =====");
if (r6 !==16'h7654) tb_error("====== IRQ 16: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 16: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 16: R8 value =====");
 
 
// Test interruption 17
//--------------------------
@(r15==16'hf500);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-47:0] = {`IRQ_NR-47+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-47:0] = {`IRQ_NR-47+1{1'b0}};
 
@(r15==16'hf501);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 17: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 17: GIE value =====");
if (r6 !==16'h3210) tb_error("====== IRQ 17: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 17: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 17: R8 value =====");
 
 
// Test interruption 18
//--------------------------
@(r15==16'hf600);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-46:0] = {`IRQ_NR-46+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-46:0] = {`IRQ_NR-46+1{1'b0}};
 
@(r15==16'hf601);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 18: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 18: GIE value =====");
if (r6 !==16'h0246) tb_error("====== IRQ 18: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 18: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 18: R8 value =====");
 
 
// Test interruption 19
//--------------------------
@(r15==16'hf700);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-45:0] = {`IRQ_NR-45+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-45:0] = {`IRQ_NR-45+1{1'b0}};
 
@(r15==16'hf701);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 19: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 19: GIE value =====");
if (r6 !==16'h1357) tb_error("====== IRQ 19: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 19: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 19: R8 value =====");
 
 
// Test interruption 20
//--------------------------
@(r15==16'hf800);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-44:0] = {`IRQ_NR-44+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-44:0] = {`IRQ_NR-44+1{1'b0}};
 
@(r15==16'hf801);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 20: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 20: GIE value =====");
if (r6 !==16'h8ace) tb_error("====== IRQ 20: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 20: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 20: R8 value =====");
 
 
// Test interruption 21
//--------------------------
@(r15==16'hf900);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-43:0] = {`IRQ_NR-43+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-43:0] = {`IRQ_NR-43+1{1'b0}};
 
@(r15==16'hf901);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 21: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 21: GIE value =====");
if (r6 !==16'h9bdf) tb_error("====== IRQ 21: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 21: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 21: R8 value =====");
 
 
// Test interruption 22
//--------------------------
@(r15==16'hfa00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-42:0] = {`IRQ_NR-42+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-42:0] = {`IRQ_NR-42+1{1'b0}};
 
@(r15==16'hfa01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 22: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 22: GIE value =====");
if (r6 !==16'hfdb9) tb_error("====== IRQ 22: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 22: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 22: R8 value =====");
 
 
// Test interruption 23
//--------------------------
@(r15==16'hfb00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-41:0] = {`IRQ_NR-41+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-41:0] = {`IRQ_NR-41+1{1'b0}};
 
@(r15==16'hfb01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 23: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 23: GIE value =====");
if (r6 !==16'heca8) tb_error("====== IRQ 23: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 23: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 23: R8 value =====");
 
 
// Test interruption 24
//--------------------------
@(r15==16'hfc00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-40:0] = {`IRQ_NR-40+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-40:0] = {`IRQ_NR-40+1{1'b0}};
 
@(r15==16'hfc01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 24: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 24: GIE value =====");
if (r6 !==16'h7531) tb_error("====== IRQ 24: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 24: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 24: R8 value =====");
 
 
// Test interruption 25
//--------------------------
@(r15==16'hfd00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-39:0] = {`IRQ_NR-39+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-39:0] = {`IRQ_NR-39+1{1'b0}};
 
@(r15==16'hfd01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 25: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 25: GIE value =====");
if (r6 !==16'h6420) tb_error("====== IRQ 25: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 25: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 25: R8 value =====");
 
 
// Test interruption 26
//--------------------------
@(r15==16'hfe00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-38:0] = {`IRQ_NR-38+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-38:0] = {`IRQ_NR-38+1{1'b0}};
 
@(r15==16'hfe01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 26: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 26: GIE value =====");
if (r6 !==16'h0134) tb_error("====== IRQ 26: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 26: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 26: R8 value =====");
 
 
// Test interruption 27
//--------------------------
@(r15==16'hff00);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-37:0] = {`IRQ_NR-37+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-37:0] = {`IRQ_NR-37+1{1'b0}};
 
@(r15==16'hff01);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 27: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 27: GIE value =====");
if (r6 !==16'h1245) tb_error("====== IRQ 27: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 27: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 27: R8 value =====");
 
 
// Test interruption 28
//--------------------------
@(r15==16'hff10);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-36:0] = {`IRQ_NR-36+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-36:0] = {`IRQ_NR-36+1{1'b0}};
 
@(r15==16'hff11);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 28: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 28: GIE value =====");
if (r6 !==16'h2356) tb_error("====== IRQ 28: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 28: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 28: R8 value =====");
 
 
// Test interruption 29
//--------------------------
@(r15==16'hff20);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-35:0] = {`IRQ_NR-35+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-35:0] = {`IRQ_NR-35+1{1'b0}};
 
@(r15==16'hff21);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 29: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 29: GIE value =====");
if (r6 !==16'h3467) tb_error("====== IRQ 29: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 29: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 29: R8 value =====");
 
 
// Test interruption 30
//--------------------------
@(r15==16'hff30);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-34:0] = {`IRQ_NR-34+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-34:0] = {`IRQ_NR-34+1{1'b0}};
 
@(r15==16'hff31);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 30: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 30: GIE value =====");
if (r6 !==16'h4578) tb_error("====== IRQ 30: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 30: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 30: R8 value =====");
 
 
// Test interruption 31
//--------------------------
@(r15==16'hff40);
repeat(2) @(posedge mclk);
irq[`IRQ_NR-33:0] = {`IRQ_NR-33+1{1'b1}};
repeat(15) @(posedge mclk);
irq[`IRQ_NR-33:0] = {`IRQ_NR-33+1{1'b0}};
 
@(r15==16'hff41);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 31: SP value =====");
if (r2[3] !==1'b1) tb_error("====== IRQ 31: GIE value =====");
if (r6 !==16'h5689) tb_error("====== IRQ 31: R6 value =====");
if (r7 !==16'h0000) tb_error("====== IRQ 31: R7 value =====");
if (r8 !==(`PER_SIZE+16'h004e)) tb_error("====== IRQ 31: R8 value =====");
 
 
stimulus_done = 1;
`else
 
$display(" ===============================================");
$display("| SIMULATION SKIPPED |");
$display("| (RTL configured to support 16 or 32 IRQs) |");
$display(" ===============================================");
$finish;
`endif
end
 
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
74,9 → 74,9
//--------------------------
@(r15==16'h3000);
repeat(2) @(posedge mclk);
irq[0] = 1'b1;
irq[`IRQ_NR-16:0] = {`IRQ_NR-16+1{1'b1}};
repeat(15) @(posedge mclk);
irq[0] = 1'b0;
irq[`IRQ_NR-16:0] = {`IRQ_NR-16+1{1'b0}};
 
@(r15==16'h3001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 0: SP value =====");
90,9 → 90,9
//--------------------------
@(r15==16'h4000);
repeat(2) @(posedge mclk);
irq[1:0] = {2{1'b1}};
irq[`IRQ_NR-15:0] = {`IRQ_NR-15+1{1'b1}};
repeat(15) @(posedge mclk);
irq[1:0] = 1'b0;
irq[`IRQ_NR-15:0] = {`IRQ_NR-15+1{1'b0}};
 
@(r15==16'h4001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 1: SP value =====");
106,9 → 106,9
//--------------------------
@(r15==16'h5000);
repeat(2) @(posedge mclk);
irq[2:0] = {3{1'b1}};
irq[`IRQ_NR-14:0] = {`IRQ_NR-14+1{1'b1}};
repeat(15) @(posedge mclk);
irq[2:0] = 1'b0;
irq[`IRQ_NR-14:0] = {`IRQ_NR-14+1{1'b0}};
 
@(r15==16'h5001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 2: SP value =====");
122,9 → 122,9
//--------------------------
@(r15==16'h6000);
repeat(2) @(posedge mclk);
irq[3:0] = {4{1'b1}};
irq[`IRQ_NR-13:0] = {`IRQ_NR-13+1{1'b1}};
repeat(15) @(posedge mclk);
irq[3:0] = 1'b0;
irq[`IRQ_NR-13:0] = {`IRQ_NR-13+1{1'b0}};
 
@(r15==16'h6001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 3: SP value =====");
138,9 → 138,9
//--------------------------
@(r15==16'h7000);
repeat(2) @(posedge mclk);
irq[4:0] = {5{1'b1}};
irq[`IRQ_NR-12:0] = {`IRQ_NR-12+1{1'b1}};
repeat(15) @(posedge mclk);
irq[4:0] = 1'b0;
irq[`IRQ_NR-12:0] = {`IRQ_NR-12+1{1'b0}};
 
@(r15==16'h7001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 4: SP value =====");
154,9 → 154,9
//--------------------------
@(r15==16'h8000);
repeat(2) @(posedge mclk);
irq[5:0] = {6{1'b1}};
irq[`IRQ_NR-11:0] = {`IRQ_NR-11+1{1'b1}};
repeat(15) @(posedge mclk);
irq[5:0] = 1'b0;
irq[`IRQ_NR-11:0] = {`IRQ_NR-11+1{1'b0}};
 
@(r15==16'h8001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 5: SP value =====");
170,9 → 170,9
//--------------------------
@(r15==16'h9000);
repeat(2) @(posedge mclk);
irq[6:0] = {7{1'b1}};
irq[`IRQ_NR-10:0] = {`IRQ_NR-10+1{1'b1}};
repeat(15) @(posedge mclk);
irq[6:0] = 1'b0;
irq[`IRQ_NR-10:0] = {`IRQ_NR-10+1{1'b0}};
 
@(r15==16'h9001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 6: SP value =====");
186,9 → 186,9
//--------------------------
@(r15==16'ha000);
repeat(2) @(posedge mclk);
irq[7:0] = {8{1'b1}};
irq[`IRQ_NR-9:0] = {`IRQ_NR-9+1{1'b1}};
repeat(15) @(posedge mclk);
irq[7:0] = 1'b0;
irq[`IRQ_NR-9:0] = {`IRQ_NR-9+1{1'b0}};
 
@(r15==16'ha001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 7: SP value =====");
202,9 → 202,9
//--------------------------
@(r15==16'hb000);
repeat(2) @(posedge mclk);
irq[8:0] = {9{1'b1}};
irq[`IRQ_NR-8:0] = {`IRQ_NR-8+1{1'b1}};
repeat(15) @(posedge mclk);
irq[8:0] = 1'b0;
irq[`IRQ_NR-8:0] = {`IRQ_NR-8+1{1'b0}};
 
@(r15==16'hb001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 8: SP value =====");
218,9 → 218,9
//--------------------------
@(r15==16'hc000);
repeat(2) @(posedge mclk);
irq[9:0] = {10{1'b1}};
irq[`IRQ_NR-7:0] = {`IRQ_NR-7+1{1'b1}};
repeat(15) @(posedge mclk);
irq[9:0] = 1'b0;
irq[`IRQ_NR-7:0] = {`IRQ_NR-7+1{1'b0}};
 
@(r15==16'hc001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 9: SP value =====");
234,9 → 234,9
//--------------------------
@(r15==16'hd000);
repeat(2) @(posedge mclk);
irq[10:0] = {11{1'b1}};
irq[`IRQ_NR-6:0] = {`IRQ_NR-6+1{1'b1}};
repeat(15) @(posedge mclk);
irq[10:0] = 1'b0;
irq[`IRQ_NR-6:0] = {`IRQ_NR-6+1{1'b0}};
 
@(r15==16'hd001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 10: SP value =====");
250,9 → 250,9
//--------------------------
@(r15==16'he000);
repeat(2) @(posedge mclk);
irq[11:0] = {12{1'b1}};
irq[`IRQ_NR-5:0] = {`IRQ_NR-5+1{1'b1}};
repeat(15) @(posedge mclk);
irq[11:0] = 1'b0;
irq[`IRQ_NR-5:0] = {`IRQ_NR-5+1{1'b0}};
 
@(r15==16'he001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 11: SP value =====");
266,9 → 266,9
//--------------------------
@(r15==16'hf000);
repeat(2) @(posedge mclk);
irq[12:0] = {13{1'b1}};
irq[`IRQ_NR-4:0] = {`IRQ_NR-4+1{1'b1}};
repeat(15) @(posedge mclk);
irq[12:0] = 1'b0;
irq[`IRQ_NR-4:0] = {`IRQ_NR-4+1{1'b0}};
 
@(r15==16'hf001);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 12: SP value =====");
282,9 → 282,9
//--------------------------
@(r15==16'hf100);
repeat(2) @(posedge mclk);
irq[13:0] = {14{1'b1}};
irq[`IRQ_NR-3:0] = {`IRQ_NR-3+1{1'b1}};
repeat(15) @(posedge mclk);
irq[13:0] = 1'b0;
irq[`IRQ_NR-3:0] = {`IRQ_NR-3+1{1'b0}};
 
@(r15==16'hf101);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== IRQ 13: SP value =====");
301,11 → 301,11
repeat(2) @(negedge mclk);
nmi = 1'b1;
@(posedge nmi_detect);
irq[13:0] = {14{1'b1}};
irq[`IRQ_NR-3:0] = {`IRQ_NR-3+1{1'b1}};
repeat(8) @(posedge mclk);
nmi = 1'b0;
repeat(2) @(posedge mclk);
irq[13:0] = 1'b0;
irq[`IRQ_NR-3:0] = {`IRQ_NR-3+1{1'b0}};
 
@(r15==16'hf201);
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== NMI: SP value =====");
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
125,10 → 125,11
# Make local copy of the openMSP403 configuration file
# and prepare it for MSPGCC preprocessing
cp $incfile ./pmem.h
sed -i 's/`ifdef/#ifdef/g' ./pmem.h
sed -i 's/`else/#else/g' ./pmem.h
sed -i 's/`endif/#endif/g' ./pmem.h
sed -i 's/`define/#define/g' ./pmem.h
sed -i 's/`ifdef/#ifdef/g' ./pmem.h
sed -i 's/`else/#else/g' ./pmem.h
sed -i 's/`endif/#endif/g' ./pmem.h
sed -i 's/`define/#define/g' ./pmem.h
sed -i 's/`include/\/\/#include/g' ./pmem.h
sed -i 's/`//g' ./pmem.h
sed -i "s/'//g" ./pmem.h
 
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
106,10 → 106,11
# Make local copy of the openMSP403 configuration file
# and prepare it for MSPGCC preprocessing
cp $incfile ./pmem.h
sed -i 's/`ifdef/#ifdef/g' ./pmem.h
sed -i 's/`else/#else/g' ./pmem.h
sed -i 's/`endif/#endif/g' ./pmem.h
sed -i 's/`define/#define/g' ./pmem.h
sed -i 's/`ifdef/#ifdef/g' ./pmem.h
sed -i 's/`else/#else/g' ./pmem.h
sed -i 's/`endif/#endif/g' ./pmem.h
sed -i 's/`define/#define/g' ./pmem.h
sed -i 's/`include/\/\/#include/g' ./pmem.h
sed -i 's/`//g' ./pmem.h
sed -i "s/'//g" ./pmem.h
 
/openmsp430/trunk/core/sim/rtl_sim/bin/template.x
3,9 → 3,11
OUTPUT_ARCH("msp430")
MEMORY
{
text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE
data (rwx) : ORIGIN = PER_SIZE, LENGTH = DMEM_SIZE
vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20
text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE
data (rwx) : ORIGIN = PER_SIZE, LENGTH = DMEM_SIZE
vectors64 (rw) : ORIGIN = 0xff80, LENGTH = 0x40
vectors32 (rw) : ORIGIN = 0xffc0, LENGTH = 0x20
vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20
}
SECTIONS
{
131,6 → 133,18
PROVIDE (__noinit_end = .) ;
_end = . ;
} > data
.vectors32 :
{
PROVIDE (__vectors32_start = .) ;
*(.vectors32*)
_vectors32_end = . ;
} > vectors32
.vectors64 :
{
PROVIDE (__vectors64_start = .) ;
*(.vectors64*)
_vectors64_end = . ;
} > vectors64
.vectors :
{
PROVIDE (__vectors_start = .) ;

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