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Rev 195 → Rev 196

/trunk/or1ksim/cpu/or1k/spr_defs.h
43,6 → 43,13
/* System control and status group */
#define SPR_VR (SPRGROUP_SYS + 0)
#define SPR_UPR (SPRGROUP_SYS + 1)
#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
#define SPR_DCCFGR (SPRGROUP_SYS + 5)
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
#define SPR_PC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
147,6 → 154,86
#define SPR_UPR_CUST 0xff000000 /* Custom units */
 
/*
* Bit definitions for the CPU Configuration register
*
*/
#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
#define SPR_CPUCFGR_HGF 0x00000010 /* Half GPR File */
#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 Supported */
#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 Supported */
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 Supported */
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFP64P Supported */
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 Supported */
 
/*
* Bit definitions for the DMMU Configuration register
*
*/
#define SPR_DMMUCFGR_NTW 0x00000003 /* Number of TLB Ways */
#define SPR_DMMUCFGR_NTS 0x0000001c /* Number of TLB Sets (entries per way) */
#define SPR_DMMUCFGR_NAE 0x000000e0 /* Number of ATB Entries */
#define SPR_DMMUCFGR_CRI 0x00000100 /* Control Register Implemented */
#define SPR_DMMUCFGR_PRI 0x00000200 /* Protection Register Implemented */
#define SPR_DMMUCFGR_TEIRI 0x00000400 /* TLB Entry Invalidate Register Implemented */
#define SPR_DMMUCFGR_HTR 0x00000800 /* Hardware TLB Reload */
 
/*
* Bit definitions for the IMMU Configuration register
*
*/
#define SPR_IMMUCFGR_NTW 0x00000003 /* Number of TLB Ways */
#define SPR_IMMUCFGR_NTS 0x0000001c /* Number of TLB Sets (entries per way) */
#define SPR_IMMUCFGR_NAE 0x000000e0 /* Number of ATB Entries */
#define SPR_IMMUCFGR_CRI 0x00000100 /* Control Register Implemented */
#define SPR_IMMUCFGR_PRI 0x00000200 /* Protection Register Implemented */
#define SPR_IMMUCFGR_TEIRI 0x00000400 /* TLB Entry Invalidate Register Implemented */
#define SPR_IMMUCFGR_HTR 0x00000800 /* Hardware TLB Reload */
 
/*
* Bit definitions for the DC Configuration register
*
*/
#define SPR_DCCFGR_NCW 0x00000007 /* Number of Cache Ways */
#define SPR_DCCFGR_NCS 0x00000078 /* Number of Cache Sets (cache blocks per way) */
#define SPR_DCCFGR_CBS 0x00000080 /* Cache Block Size */
#define SPR_DCCFGR_CWS 0x00000100 /* Cache Write Strategy */
#define SPR_DCCFGR_CCRI 0x00000200 /* Cache Control Register Implemented */
#define SPR_DCCFGR_CBIRI 0x00000400 /* Cache Block Invalidate Register Implemented */
#define SPR_DCCFGR_CBPRI 0x00000800 /* Cache Block Prefetch Register Implemented */
#define SPR_DCCFGR_CBLRI 0x00001000 /*Cache Block Lock Register Implemented */
#define SPR_DCCFGR_CBFRI 0x00002000 /* Cache Block Flush Register Implemented */
#define SPR_DCCFGR_CBWBRI 0x00004000 /* Cache Block Write-Back Register Implemented */
 
/*
* Bit definitions for the IC Configuration register
*
*/
#define SPR_ICCFGR_NCW 0x00000007 /* Number of Cache Ways */
#define SPR_ICCFGR_NCS 0x00000078 /* Number of Cache Sets (cache blocks per way) */
#define SPR_ICCFGR_CBS 0x00000080 /* Cache Block Size */
#define SPR_ICCFGR_CWS 0x00000100 /* Cache Write Strategy */
#define SPR_ICCFGR_CCRI 0x00000200 /* Cache Control Register Implemented */
#define SPR_ICCFGR_CBIRI 0x00000400 /* Cache Block Invalidate Register Implemented */
#define SPR_ICCFGR_CBPRI 0x00000800 /* Cache Block Prefetch Register Implemented */
#define SPR_ICCFGR_CBLRI 0x00001000 /*Cache Block Lock Register Implemented */
#define SPR_ICCFGR_CBFRI 0x00002000 /* Cache Block Flush Register Implemented */
#define SPR_ICCFGR_CBWBRI 0x00004000 /* Cache Block Write-Back Register Implemented */
 
/*
* Bit definitions for the Debug Configuration register
*
*/
#define SPR_DCFGR_NDP 0x00000007 /* Number of Debug Pairs */
#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint Counters Implemented */
 
/*
* Bit definitions for the Performance Counters Configuration register
*
*/
#define SPR_PCCFGR_NDP 0x00000007 /* Number of Performance Counters */
 
 
/*
* Bit definitions for the Supervision Register
*
*/
355,11 → 442,11
* Bit definitions for the Power management register
*
*/
#define SPR_PMR_SDF 0x00000001 /* Slow down factor */
#define SPR_PMR_DME 0x00000002 /* Doze mode enable */
#define SPR_PMR_SME 0x00000004 /* Sleep mode enable */
#define SPR_PMR_DCGE 0x00000008 /* Dynamic clock gating enable */
#define SPR_PMR_SUME 0x00000010 /* Suspend mode enable */
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
 
/*
* Bit definitions for PICMR
/trunk/or1ksim/sim-config.c
53,6 → 53,13
config.profile = 0;
 
mtspr(SPR_VR, SPR_VR_VER & 0x1200);
mtspr(SPR_CPUCFGR, SPR_CPUCFGR_OB32S);
mtspr(SPR_DMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
mtspr(SPR_IMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
mtspr(SPR_DCCFGR, (0 << 5) | (7 << 2) | (1 << 0));
mtspr(SPR_ICCFGR, (0 << 5) | (7 << 2) | (1 << 0));
mtspr(SPR_DCFGR, SPR_DCFGR_WPCI);
mtspr(SPR_PCCFGR, 1);
 
val = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |

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