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    from Rev 198 to Rev 199
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Rev 198 → Rev 199

/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
37,12 → 37,12
-- "1_1111_1110" (0x0FE) Reserved
-- "1_1111_1111" (0x1FF) RX Length / Status***
--
-- * Address 0xFE reports the SDLC bit clock status and updates on changes.
-- * Address 0xFE reports the SDLC bit clock status and updates on changes.
-- 1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
-- 0x00. Otherwise, it will report 0xFF if the bitclock is present.
-- 2) Writing any value to the register will cause the controller to
-- silently reset the clock status without causing an interrupt.
--
--
-- ** This location serves as the control/status register for transmit
-- 1) Writing a value between 1 and 253 will trigger the transmit engine,
-- using the write value as the packet length.
49,7 → 49,7
-- 2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
-- 3) This value will change from the user written value to 0xFF once the
-- packet is transmitted to indicate the transmission is complete.
--
--
-- *** This location serves as the status register for the receive
-- 1) This value is only updated on reception of a full frame, indicated
-- by a start followed by a stop flag. Incomplete frames are ignored.
72,6 → 72,8
 
entity o8_sdlc_if is
generic(
Monitor_Enable : boolean := true;
Attach_Monitor_to_CPU_Side : boolean := false;
Poly_Init : std_logic_vector(15 downto 0) := x"0000";
Set_As_Master : boolean := true;
Clock_Offset : integer := 6;
205,6 → 207,31
q_b => DP_Rd_Data
);
 
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
 
U_MON: entity work.sdlc_monitor
port map(
clock => Clock,
address => RAM_Lower_Addr,
data => Wr_Data,
wren => RAM_Wr_En,
q => open
);
end generate;
 
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
 
U_MON: entity work.sdlc_monitor
port map(
clock => Clock,
address => DP_Addr,
data => DP_Wr_Data,
wren => DP_Wr_En,
q => open
);
 
end generate;
 
U_BCLK : entity work.sdlc_serial_clk
generic map(
Set_As_Master => Set_As_Master,
/open8_urisc/trunk/VHDL/sdlc_monitor.vhd
0,0 → 1,156
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: sdlc_monitor.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY sdlc_monitor IS
PORT
(
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END sdlc_monitor;
 
 
ARCHITECTURE SYN OF sdlc_monitor IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SDLC",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 9,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "SDLC"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SDLC"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_monitor.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_monitor.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_monitor.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_monitor.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_monitor_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/open8_urisc/trunk/VHDL/sdlc_serial_ctrl.vhd
84,9 → 84,9
signal RAM_Updated : std_logic;
 
-- RAM Arbitration logic
type DP_ARB_STATES is (IDLE,
PORT0_AD, PORT0_WR, PORT0_RD0, PORT0_RD1, PORT0_RD2,
PORT1_AD, PORT1_WR, PORT1_RD0, PORT1_RD1, PORT1_RD2 );
type DP_ARB_STATES is (PAUSE, IDLE,
PORT0_AD, PORT0_WR, PORT0_RD0, PORT0_RD1,
PORT1_AD, PORT1_WR, PORT1_RD0, PORT1_RD1 );
signal DP_Arb_State : DP_ARB_STATES := IDLE;
signal DP_Last_Port : std_logic := '0';
 
135,8 → 135,8
 
type RX_FSM_STATES is ( WAIT_FOR_CLOCK, WAIT_FOR_FLAG,
RX_MESG_DATA, RX_WR_DATA,
RX_CRC_LB_RD, RX_CRC_UB_RD, CHK_CRC,
RX_WR_COUNT, RX_TERM );
RX_CRC_LB_RD, RX_CRC_UB_RD,
RX_WR_CRC, RX_WR_COUNT );
 
signal RX_State : RX_FSM_STATES := WAIT_FOR_CLOCK;
 
169,6 → 169,7
elsif( rising_edge(Clock) )then
DP_Port0_Ack <= '0';
DP_Port1_Ack <= '0';
DP_Wr_En <= '0';
 
case( DP_Arb_State )is
when IDLE =>
197,12 → 198,9
DP_Arb_State <= PORT0_RD1;
 
when PORT0_RD1 =>
DP_Arb_State <= PORT0_RD2;
 
when PORT0_RD2 =>
DP_Port0_Ack <= '1';
DP_Port0_RdData <= DP_Rd_Data;
DP_Arb_State <= IDLE;
DP_Arb_State <= PAUSE;
 
when PORT1_AD =>
DP_Last_Port <= '1';
223,11 → 221,11
DP_Arb_State <= PORT1_RD1;
 
when PORT1_RD1 =>
DP_Arb_State <= PORT1_RD2;
 
when PORT1_RD2 =>
DP_Port1_Ack <= '1';
DP_Port1_RdData <= DP_Rd_Data;
DP_Arb_State <= PAUSE;
 
when PAUSE =>
DP_Arb_State <= IDLE;
 
when others => null;
307,7 → 305,7
end if;
 
when RD_TX_REGISTER =>
DP_Port0_Addr <= CR_REGISTER;
DP_Port0_Addr <= TX_REGISTER;
DP_Port0_Req <= '1';
if( DP_Port0_Ack = '1' )then
DP_Port0_Req <= '0';
390,7 → 388,7
end if;
 
when TX_DONE =>
DP_Port0_Addr <= CR_REGISTER;
DP_Port0_Addr <= TX_REGISTER;
DP_Port0_Req <= '1';
DP_Port0_WrData <= FLAG_DONE;
DP_Port0_RWn <= '0';
507,6 → 505,7
 
when RX_MESG_DATA =>
if( RX_Frame_Stop = '1' )then
RX_Length <= RX_Length - 1;
RX_State <= RX_CRC_UB_RD;
elsif( RX_Frame_Valid = '1' )then
RX_State <= RX_WR_DATA;
539,23 → 538,29
end if;
 
when RX_CRC_LB_RD =>
RX_Length <= RX_Length - DP_Port1_Ack;
DP_Port1_Addr <= RX_Length;
DP_Port1_Req <= '1';
if( DP_Port1_Ack = '1' )then
DP_Port1_Req <= '0';
RX_CRC_Rcvd_LB <= DP_Port1_RdData;
RX_State <= RX_WR_COUNT;
RX_State <= RX_WR_CRC;
end if;
 
when CHK_CRC =>
RX_State <= RX_WR_COUNT;
when RX_WR_CRC =>
DP_Port1_Addr <= CS_REGISTER;
DP_Port1_WrData <= x"FF";
if( RX_CRC_Rcvd /= RX_CRC_Calc )then
RX_Length <= ERR_CHECKSUM;
DP_Port1_WrData <= x"00";
end if;
DP_Port1_RWn <= '0';
DP_Port1_Req <= '1';
if( DP_Port1_Ack = '1' )then
DP_Port1_Req <= '0';
RX_State <= RX_WR_COUNT;
end if;
 
when RX_WR_COUNT =>
DP_Port1_Addr <= CR_REGISTER;
DP_Port1_Addr <= RX_REGISTER;
DP_Port1_WrData <= RX_Length;
DP_Port1_RWn <= '0';
DP_Port1_Req <= '1';
/open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd
36,7 → 36,9
 
-- Internal definitions
constant CK_REGISTER : DATA_IN_TYPE := x"FE";
constant CR_REGISTER : DATA_IN_TYPE := x"FF";
constant TX_REGISTER : DATA_IN_TYPE := x"FF";
constant CS_REGISTER : DATA_IN_TYPE := x"FE";
constant RX_REGISTER : DATA_IN_TYPE := x"FF";
 
constant TX_RESERVED_LOW : integer := 0;
constant TX_RESERVED_HIGH : integer := 254;
44,7 → 46,6
constant FLAG_DONE : DATA_IN_TYPE := x"FF";
 
constant ERR_LENGTH : DATA_IN_TYPE := x"00";
constant ERR_CHECKSUM : DATA_IN_TYPE := x"FF";
 
end package;
 

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