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URL https://opencores.org/ocsvn/axi_vga/axi_vga/trunk

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/axi_vga/trunk/model/axi_hp_slave.v
0,0 → 1,636
 
`define read_ready_time 10
`define read_ready_timeX 5
`define write_ready_time 3
//Author: Hugoliu Date:20160904
//The test model for AXI3 slave port
 
module HP_slave(
S_AXI_ARESETN,
S_AXI_ACLK,
//Slave port
S_AXI_HP_araddr,
S_AXI_HP_arburst,
S_AXI_HP_arcache,
S_AXI_HP_arid,
S_AXI_HP_arlen,
S_AXI_HP_arlock,
S_AXI_HP_arprot,
S_AXI_HP_arqos,
S_AXI_HP_arready,
S_AXI_HP_arsize,
S_AXI_HP_arvalid,
S_AXI_HP_awaddr,
S_AXI_HP_awburst,
S_AXI_HP_awcache,
S_AXI_HP_awid,
S_AXI_HP_awlen,
S_AXI_HP_awlock,
S_AXI_HP_awprot,
S_AXI_HP_awqos,
S_AXI_HP_awready,
S_AXI_HP_awsize,
S_AXI_HP_awvalid,
S_AXI_HP_bid,
S_AXI_HP_bready,
S_AXI_HP_bresp,
S_AXI_HP_bvalid,
S_AXI_HP_rdata,
S_AXI_HP_rid,
S_AXI_HP_rlast,
S_AXI_HP_rready,
S_AXI_HP_rresp,
S_AXI_HP_rvalid,
S_AXI_HP_wdata,
S_AXI_HP_wid,
S_AXI_HP_wlast,
S_AXI_HP_wready,
S_AXI_HP_wstrb,
S_AXI_HP_wvalid,
//Slave port
S_AXI_HP1_araddr,
S_AXI_HP1_arburst,
S_AXI_HP1_arcache,
S_AXI_HP1_arid,
S_AXI_HP1_arlen,
S_AXI_HP1_arlock,
S_AXI_HP1_arprot,
S_AXI_HP1_arqos,
S_AXI_HP1_arready,
S_AXI_HP1_arsize,
S_AXI_HP1_arvalid,
S_AXI_HP1_awaddr,
S_AXI_HP1_awburst,
S_AXI_HP1_awcache,
S_AXI_HP1_awid,
S_AXI_HP1_awlen,
S_AXI_HP1_awlock,
S_AXI_HP1_awprot,
S_AXI_HP1_awqos,
S_AXI_HP1_awready,
S_AXI_HP1_awsize,
S_AXI_HP1_awvalid,
S_AXI_HP1_bid,
S_AXI_HP1_bready,
S_AXI_HP1_bresp,
S_AXI_HP1_bvalid,
S_AXI_HP1_rdata,
S_AXI_HP1_rid,
S_AXI_HP1_rlast,
S_AXI_HP1_rready,
S_AXI_HP1_rresp,
S_AXI_HP1_rvalid,
S_AXI_HP1_wdata,
S_AXI_HP1_wid,
S_AXI_HP1_wlast,
S_AXI_HP1_wready,
S_AXI_HP1_wstrb,
S_AXI_HP1_wvalid
);
//system signal
input S_AXI_ARESETN,
S_AXI_ACLK;
 
 
// Slave Interface Write Address channel Ports
//HP slave port
//write address phase
input [31:0] S_AXI_HP_awaddr;
input [1:0] S_AXI_HP_awburst;
input [3:0] S_AXI_HP_awcache;
input [5:0] S_AXI_HP_awid;
input [3:0] S_AXI_HP_awlen;
input [1:0] S_AXI_HP_awlock;
input [2:0] S_AXI_HP_awprot;
input [3:0] S_AXI_HP_awqos;
output S_AXI_HP_awready;
input [2:0] S_AXI_HP_awsize;
input S_AXI_HP_awvalid;
//write response phase
output [5:0] S_AXI_HP_bid;
input S_AXI_HP_bready;
output [1:0] S_AXI_HP_bresp;
output S_AXI_HP_bvalid;
//write data phase
input [63:0] S_AXI_HP_wdata;
input [5:0] S_AXI_HP_wid;
input S_AXI_HP_wlast;
output S_AXI_HP_wready;
input [7:0] S_AXI_HP_wstrb;
input S_AXI_HP_wvalid;
//read address pahse
input [31:0] S_AXI_HP_araddr;
input [1:0] S_AXI_HP_arburst;
input [3:0] S_AXI_HP_arcache;
input [5:0] S_AXI_HP_arid;
input [3:0] S_AXI_HP_arlen;
input [1:0] S_AXI_HP_arlock;
input [2:0] S_AXI_HP_arprot;
input [3:0] S_AXI_HP_arqos;
output S_AXI_HP_arready;
input [2:0] S_AXI_HP_arsize;
input S_AXI_HP_arvalid;
//read data phase
output [63:0]S_AXI_HP_rdata;
output [5:0] S_AXI_HP_rid;
output S_AXI_HP_rlast;
input S_AXI_HP_rready;
output [1:0] S_AXI_HP_rresp;
output S_AXI_HP_rvalid;
//////////////////////////////////////////////
//HP1 slave port
//write address phase
input [31:0] S_AXI_HP1_awaddr;
input [1:0] S_AXI_HP1_awburst;
input [3:0] S_AXI_HP1_awcache;
input [5:0] S_AXI_HP1_awid;
input [3:0] S_AXI_HP1_awlen;
input [1:0] S_AXI_HP1_awlock;
input [2:0] S_AXI_HP1_awprot;
input [3:0] S_AXI_HP1_awqos;
output S_AXI_HP1_awready;
input [2:0] S_AXI_HP1_awsize;
input S_AXI_HP1_awvalid;
//write response phase
output [5:0] S_AXI_HP1_bid;
input S_AXI_HP1_bready;
output [1:0] S_AXI_HP1_bresp;
output S_AXI_HP1_bvalid;
//write data phase
input [63:0] S_AXI_HP1_wdata;
input [5:0] S_AXI_HP1_wid;
input S_AXI_HP1_wlast;
output S_AXI_HP1_wready;
input [7:0] S_AXI_HP1_wstrb;
input S_AXI_HP1_wvalid;
//read address pahse
input [31:0] S_AXI_HP1_araddr;
input [1:0] S_AXI_HP1_arburst;
input [3:0] S_AXI_HP1_arcache;
input [5:0] S_AXI_HP1_arid;
input [3:0] S_AXI_HP1_arlen;
input [1:0] S_AXI_HP1_arlock;
input [2:0] S_AXI_HP1_arprot;
input [3:0] S_AXI_HP1_arqos;
output S_AXI_HP1_arready;
input [2:0] S_AXI_HP1_arsize;
input S_AXI_HP1_arvalid;
//read data phase
output [63:0]S_AXI_HP1_rdata;
output [5:0] S_AXI_HP1_rid;
output S_AXI_HP1_rlast;
input S_AXI_HP1_rready;
output [1:0] S_AXI_HP1_rresp;
output S_AXI_HP1_rvalid;
 
//
//read phase
wire [1:0] S_AXI_HP_rresp = 2'b0;
reg S_AXI_HP_arready;
wire [63:0]S_AXI_HP_rdata;
wire [5:0] S_AXI_HP_rid;
wire S_AXI_HP_rlast;
reg S_AXI_HP_rvalid;
//control
reg [3:0] read_addr_count_w, read_addr_count_r;
reg [3:0] read_data_count;
reg [5:0] space_count;
reg ready_for_read;
//FIFO keep
reg [31:0] s_axi_araddr[31:0];
reg [5:0] s_axi_arid[15:0];
 
wire [3:0] stop_addr_read_ok2 = (read_addr_count_r - 2);
wire [3:0] stop_addr_read_ok = (read_addr_count_r - 1);
wire stop_addr_read1 = (read_addr_count_w == stop_addr_read_ok2);
wire stop_addr_read = (read_addr_count_w == stop_addr_read_ok);
 
wire read_data_finish = ((read_addr_count_w -1) == read_addr_count_r) & S_AXI_HP_rlast;
wire read_data_go = (space_count == `read_ready_timeX);
reg first_read_addr, first_read_addr_d;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP_arready <= 1'b1;
else if (stop_addr_read | stop_addr_read1) S_AXI_HP_arready <= 1'b0;
else if (S_AXI_HP_arvalid) S_AXI_HP_arready <= 1'b1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read_addr_count_w <= 0;
else if (read_data_finish) read_addr_count_w <= 0;
else if (stop_addr_read) read_addr_count_w <= read_addr_count_w;
else if (S_AXI_HP_arvalid & S_AXI_HP_arready) read_addr_count_w <= read_addr_count_w + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read_addr_count_r <= 0;
else if (read_data_finish & first_read_addr) read_addr_count_r <= 0; //read_addr_count_r;
else if (S_AXI_HP_rlast) read_addr_count_r <= read_addr_count_r + 1;
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_HP_arready & S_AXI_HP_arvalid) begin
s_axi_araddr[read_addr_count_w] <= S_AXI_HP_araddr;
s_axi_arid[read_addr_count_w] <= S_AXI_HP_arid;
end
end
//
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first_read_addr <= 0;
else if (read_data_finish) first_read_addr <= 0;
else if (S_AXI_HP_arvalid & S_AXI_HP_arready) first_read_addr <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first_read_addr_d <= 0;
else first_read_addr_d <= first_read_addr;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) ready_for_read <= 0;
else if (space_count == `read_ready_timeX) ready_for_read <= 0;
else if (first_read_addr & !first_read_addr_d) ready_for_read <= 1;
else if (S_AXI_HP_rlast) ready_for_read <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) space_count <= 0;
else if (ready_for_read) space_count <= space_count + 1;
else space_count <= 0;
end
//
wire read_data_ok = S_AXI_HP_rvalid & S_AXI_HP_rready;
assign S_AXI_HP_rlast = (read_data_count == S_AXI_HP_arlen) & read_data_ok;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP_rvalid <= 0;
else if (S_AXI_HP_rlast | read_data_finish) S_AXI_HP_rvalid <= 0;
else if (read_data_go) S_AXI_HP_rvalid <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read_data_count <= 0;
else if (S_AXI_HP_rlast) read_data_count <= 0;
else if (read_data_ok) read_data_count <= read_data_count + 1;
end
//
assign S_AXI_HP_rid = s_axi_arid[read_addr_count_r];
wire [31:0] tmp_read_addr = s_axi_araddr[read_addr_count_r];
//////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////
// write phase
///////////////////////////////////////////////////////////////////////////////////////////////
//write address phase
wire [31:0] S_AXI_HP_awaddr;
wire [1:0] S_AXI_HP_awburst;
wire [3:0] S_AXI_HP_awcache;
wire [5:0] S_AXI_HP_awid;
wire [3:0] S_AXI_HP_awlen;
wire [1:0] S_AXI_HP_awlock;
wire [2:0] S_AXI_HP_awprot;
wire [3:0] S_AXI_HP_awqos;
reg S_AXI_HP_awready;
wire [2:0] S_AXI_HP_awsize;
wire S_AXI_HP_awvalid;
//write response phase
wire [5:0] S_AXI_HP_bid;
wire S_AXI_HP_bready;
wire [1:0] S_AXI_HP_bresp = 2'b0;
reg S_AXI_HP_bvalid;
//write data phase
wire [63:0] S_AXI_HP_wdata;
wire [5:0] S_AXI_HP_wid;
wire S_AXI_HP_wlast;
reg S_AXI_HP_wready;
wire [7:0] S_AXI_HP_wstrb;
wire S_AXI_HP_wvalid;
 
//////////////////////////////////////////////////////
//control
reg [3:0] write_addr_count_w, write_addr_count_r;
reg [3:0] write_data_count;
reg [5:0] w_space_count;
reg ready_for_write;
//FIFO keep
reg [31:0] s_axi_awaddr[31:0];
reg [5:0] s_axi_awid[15:0];
 
wire [3:0] stop_addr_write_ok2 = (write_addr_count_r - 2);
wire [3:0] stop_addr_write_ok = (write_addr_count_r - 1);
wire stop_addr_write1 = (write_addr_count_w == stop_addr_write_ok2);
wire stop_addr_write = (write_addr_count_w == stop_addr_write_ok);
 
wire write_data_finish = ((write_addr_count_w) == write_addr_count_r) & (write_addr_count_w != 0);
wire write_data_go = (w_space_count == `write_ready_time);
reg first_write_addr, first_write_addr_d;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP_awready <= 1'b1;
else if (stop_addr_write | stop_addr_write1) S_AXI_HP_awready <= 1'b0;
else if (S_AXI_HP_awvalid) S_AXI_HP_awready <= 1'b1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_addr_count_w <= 0;
else if (stop_addr_write) write_addr_count_w <= write_addr_count_w;
else if (S_AXI_HP_awvalid & S_AXI_HP_awready) write_addr_count_w <= write_addr_count_w + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_addr_count_r <= 0;
else if (write_data_finish & first_write_addr) write_addr_count_r <= write_addr_count_r;
else if (S_AXI_HP_wlast) write_addr_count_r <= write_addr_count_r + 1;
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_HP_awready & S_AXI_HP_awvalid) begin
s_axi_awaddr[write_addr_count_w] <= S_AXI_HP_awaddr;
s_axi_awid[write_addr_count_w] <= S_AXI_HP_awid;
end
end
//
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first_write_addr <= 0;
else if (write_data_finish) first_write_addr <= 0;
else if (S_AXI_HP_awvalid & S_AXI_HP_awready) first_write_addr <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first_write_addr_d <= 0;
else first_write_addr_d <= first_write_addr;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) ready_for_write <= 0;
else if (w_space_count == `write_ready_time) ready_for_write <= 0;
else if (first_write_addr & !first_write_addr_d) ready_for_write <= 1;
else if (S_AXI_HP_bvalid) ready_for_write <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) w_space_count <= 0;
else if (ready_for_write) w_space_count <= w_space_count + 1;
else w_space_count <= 0;
end
//
reg [2:0] write_data_resp;
wire write_data_ok = S_AXI_HP_wvalid & S_AXI_HP_wready;
//assign S_AXI_HP_bvalid = (write_data_count == S_AXI_HP_awlen) & (write_data_resp == 3'h7);
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP_bvalid <= 0;
else S_AXI_HP_bvalid <= S_AXI_HP_wlast;
end
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP_wready <= 0;
else if (S_AXI_HP_bvalid | write_data_finish) S_AXI_HP_wready <= 0;
else if (write_data_go) S_AXI_HP_wready <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_data_count <= 0;
else if (S_AXI_HP_wlast) write_data_count <= 0;
else if (write_data_ok) write_data_count <= write_data_count + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_data_resp <= 0;
else if (write_data_finish) write_data_resp <= 0;
else if (S_AXI_HP_wlast ) write_data_resp <= write_data_resp + 1;
// else write_data_resp <= 0;
end
assign S_AXI_HP_bid = s_axi_awid[write_addr_count_r];
wire [31:0] tmp_write_addr = s_axi_awaddr[write_addr_count_r];
////////////////////////////////////////////////////////////////////////////////////////////
///HP1
////////////////////////////////////////////////////////////////////////////////////////////
//read phase
wire [1:0] S_AXI_HP1_rresp = 2'b0;
reg S_AXI_HP1_arready;
wire [63:0]S_AXI_HP1_rdata;
wire [5:0] S_AXI_HP1_rid;
wire S_AXI_HP1_rlast;
reg S_AXI_HP1_rvalid;
//control
reg [3:0] read1_addr_count_w, read1_addr_count_r;
reg [3:0] read1_data_count;
reg [5:0] space1_count;
reg ready1_for_read;
//FIFO keep
reg [31:0] s_axi1_araddr[31:0];
reg [5:0] s_axi1_arid[15:0];
 
wire [3:0] stop1_addr_read_ok2 = (read1_addr_count_r - 2);
wire [3:0] stop1_addr_read_ok = (read1_addr_count_r - 1);
wire stop1_addr_read1 = (read1_addr_count_w == stop1_addr_read_ok2);
wire stop1_addr_read = (read1_addr_count_w == stop1_addr_read_ok);
 
//wire read1_data_finish = ((read1_addr_count_w -1) == read1_addr_count_r);
wire read1_data_finish = ((read1_addr_count_w ) == read1_addr_count_r);
wire read1_data_go = (space1_count == `read_ready_time);
reg first1_read_addr, first1_read_addr_d;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP1_arready <= 1'b1;
else if (stop1_addr_read | stop1_addr_read1) S_AXI_HP1_arready <= 1'b0;
else if (S_AXI_HP1_arvalid) S_AXI_HP1_arready <= 1'b1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read1_addr_count_w <= 0;
else if (stop1_addr_read) read1_addr_count_w <= read1_addr_count_w;
else if (S_AXI_HP1_arvalid & S_AXI_HP1_arready) read1_addr_count_w <= read1_addr_count_w + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read1_addr_count_r <= 0;
else if (read1_data_finish & first1_read_addr) read1_addr_count_r <= read1_addr_count_r;
else if (S_AXI_HP1_rlast) read1_addr_count_r <= read1_addr_count_r + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
s_axi1_araddr[0] <= 0;
s_axi1_arid[0] <= 0;
end else if (S_AXI_HP1_arready & S_AXI_HP1_arvalid) begin
s_axi1_araddr[read1_addr_count_w] <= S_AXI_HP1_araddr;
s_axi1_arid[read1_addr_count_w] <= S_AXI_HP1_arid;
end
end
//
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first1_read_addr <= 0;
else if (read1_data_finish) first1_read_addr <= 0;
else if (S_AXI_HP1_arvalid & S_AXI_HP1_arready) first1_read_addr <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first1_read_addr_d <= 0;
else first1_read_addr_d <= first1_read_addr;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) ready1_for_read <= 0;
else if (space1_count == `read_ready_time) ready1_for_read <= 0;
else if (first1_read_addr & !first1_read_addr_d) ready1_for_read <= 1;
else if (S_AXI_HP1_rlast) ready1_for_read <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) space1_count <= 0;
else if (ready1_for_read) space1_count <= space1_count + 1;
else space1_count <= 0;
end
//
wire read1_data_ok = S_AXI_HP1_rvalid & S_AXI_HP1_rready;
assign S_AXI_HP1_rlast = (read1_data_count == S_AXI_HP1_arlen) & read1_data_ok;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP1_rvalid <= 0;
else if (S_AXI_HP1_rlast | read1_data_finish) S_AXI_HP1_rvalid <= 0;
else if (read1_data_go) S_AXI_HP1_rvalid <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) read1_data_count <= 0;
else if (S_AXI_HP1_rlast) read1_data_count <= 0;
else if (read1_data_ok) read1_data_count <= read1_data_count + 1;
end
//
assign S_AXI_HP1_rid = s_axi1_arid[read1_addr_count_r];
wire [31:0] tmp1_read_addr = s_axi1_araddr[read1_addr_count_r];
//////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////
// write phase
///////////////////////////////////////////////////////////////////////////////////////////////
//write address phase
wire [31:0] S_AXI_HP1_awaddr;
wire [1:0] S_AXI_HP1_awburst;
wire [3:0] S_AXI_HP1_awcache;
wire [5:0] S_AXI_HP1_awid;
wire [3:0] S_AXI_HP1_awlen;
wire [1:0] S_AXI_HP1_awlock;
wire [2:0] S_AXI_HP1_awprot;
wire [3:0] S_AXI_HP1_awqos;
reg S_AXI_HP1_awready;
wire [2:0] S_AXI_HP1_awsize;
wire S_AXI_HP1_awvalid;
//write response phase
wire [5:0] S_AXI_HP1_bid;
wire S_AXI_HP1_bready;
wire [1:0] S_AXI_HP1_bresp = 2'b0;
reg S_AXI_HP1_bvalid;
//write data phase
wire [63:0] S_AXI_HP1_wdata;
wire [5:0] S_AXI_HP1_wid;
wire S_AXI_HP1_wlast;
reg S_AXI_HP1_wready;
wire [7:0] S_AXI_HP1_wstrb;
wire S_AXI_HP1_wvalid;
//////////////////////////////////////////////////////
//control
reg [3:0] write_addr_count1_w, write_addr_count1_r;
reg [3:0] write_data_count1;
reg [5:0] w_space_count1;
reg ready_for_write1;
//FIFO keep
reg [31:0] s_axi_awaddr1[31:0];
reg [5:0] s_axi_awid1[15:0];
 
wire [3:0] stop_addr_write1_ok2 = (write_addr_count1_r - 2);
wire [3:0] stop_addr_write1_ok = (write_addr_count1_r - 1);
wire stop_addr_write1_1 = (write_addr_count1_w == stop_addr_write1_ok2);
wire stop_addr_write_1 = (write_addr_count1_w == stop_addr_write1_ok);
 
//wire write_data1_finish = ((write_addr_count1_w -1) == write_addr_count1_r);
wire write_data1_finish = ((write_addr_count1_w) == write_addr_count1_r) & (write_addr_count1_w != 0);
wire write_data1_go = (w_space_count1 == `write_ready_time);
reg first1_write_addr, first1_write_addr_d;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP1_awready <= 1'b1;
else if (stop_addr_write_1 | stop_addr_write1_1) S_AXI_HP1_awready <= 1'b0;
else if (S_AXI_HP1_awvalid) S_AXI_HP1_awready <= 1'b1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_addr_count1_w <= 0;
else if (stop_addr_write_1) write_addr_count1_w <= write_addr_count1_w;
else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready) write_addr_count1_w <= write_addr_count1_w + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_addr_count1_r <= 0;
else if (write_data1_finish & first1_write_addr) write_addr_count1_r <= write_addr_count1_r;
else if (S_AXI_HP1_wlast & S_AXI_HP1_wvalid & S_AXI_HP1_wready) write_addr_count1_r <= write_addr_count1_r + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) begin
s_axi_awaddr1[0] <= 0;
s_axi_awid1[0] <= 0;
end else if (S_AXI_HP1_awready & S_AXI_HP1_awvalid) begin
s_axi_awaddr1[write_addr_count1_w] <= S_AXI_HP1_awaddr;
s_axi_awid1[write_addr_count1_w] <= S_AXI_HP1_awid;
end
end
//To check addr and data count
reg [31:0] count_addr, count_data;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) count_addr <= 0;
else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready) count_addr <= count_addr + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) count_data <= 0;
else if (S_AXI_HP1_wlast & S_AXI_HP1_wvalid & S_AXI_HP1_wready) count_data <= count_data + 1;
end
 
//
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first1_write_addr <= 0;
else if (write_data1_finish) first1_write_addr <= 0;
else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready) first1_write_addr <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) first1_write_addr_d <= 0;
else first1_write_addr_d <= first1_write_addr;
end
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) ready_for_write1 <= 0;
else if (w_space_count1 == `write_ready_time) ready_for_write1 <= 0;
else if (first1_write_addr & !first1_write_addr_d) ready_for_write1 <= 1;
else if (S_AXI_HP1_bvalid) ready_for_write1 <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) w_space_count1 <= 0;
else if (ready_for_write1) w_space_count1 <= w_space_count1 + 1;
else w_space_count1 <= 0;
end
//
reg [2:0] write_data1_resp;
wire write_data1_ok = S_AXI_HP1_wvalid & S_AXI_HP1_wready;
//assign S_AXI_HP_bvalid = (write_data_count == S_AXI_HP_awlen) & (write_data_resp == 3'h7);
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP1_bvalid <= 0;
else S_AXI_HP1_bvalid <= S_AXI_HP1_wlast;
end
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) S_AXI_HP1_wready <= 0;
else if (S_AXI_HP1_bvalid | write_data1_finish) S_AXI_HP1_wready <= 0;
else if (write_data1_go) S_AXI_HP1_wready <= 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_data_count1 <= 0;
else if (S_AXI_HP1_wlast) write_data_count1 <= 0;
else if (write_data1_ok) write_data_count1 <= write_data_count1 + 1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN) write_data1_resp <= 0;
else if (write_data1_finish) write_data1_resp <= 0;
else if (S_AXI_HP1_wlast ) write_data1_resp <= write_data1_resp + 1;
// else write_data_resp <= 0;
end
assign S_AXI_HP1_bid = s_axi_awid1[write_addr_count1_r];
wire [31:0] tmp_write_addr1 = s_axi_awaddr1[write_addr_count1_r];
 
//
sram U_sram(
.clk (S_AXI_ACLK),
//port0
.we (write_data_ok ),
.a ({tmp_write_addr[26:3] + write_data_count}),
.dpra ({tmp_read_addr[26:3] + read_data_count}),
.di (S_AXI_HP_wdata),
.dpo (S_AXI_HP_rdata),
//port1
.dpra1 ({tmp1_read_addr[26:3] + read1_data_count}),
.dpo1 (S_AXI_HP1_rdata),
.a1 ({tmp_write_addr1[26:3] + write_data_count1}),
.we1 (write_data1_ok ),
.di1 (S_AXI_HP1_wdata)
);
 
endmodule
/axi_vga/trunk/model/sram.v
0,0 → 1,41
`define ram_len 24
//`define ram_dep (16*1024 * 1024) //2^12
`define ram_dep (1024 * 1024) //2^12
module sram (clk, we, a, dpra, di, dpo,
dpra1, dpo1, we1, a1, di1
);
 
input clk;
//input [1:0] we;
input we;
input [`ram_len - 1:0] a;
input [`ram_len - 1:0] dpra;
input [63:0] di;
//output [63:0] spo;
output [63:0] dpo;
//port1
input [`ram_len - 1:0] dpra1;
output [63:0] dpo1;
input we1;
input [`ram_len - 1:0] a1;
input [63:0] di1;
 
 
//
reg [63:0] ram [`ram_dep-1:0];
 
initial begin
$readmemh("test.txt", ram);
end
//
 
 
always @(posedge clk) begin
if (we) ram[a] <= di;
if (we1) ram[a1] <= di1;
end
 
assign dpo = ram[dpra];
assign dpo1 = ram[dpra1];
 
endmodule
/axi_vga/trunk/model/vga_test.v
0,0 → 1,80
`define ram_dep (1024 * 1024) //2^12
 
module vga_test (
reset_n ,
pixel_clk ,
hsync ,
vsync ,
de ,
r8 ,
g8 ,
b8
);
input reset_n, pixel_clk, hsync,vsync,de;
input [7:0] r8, g8, b8;
 
reg [63:0] ram [`ram_dep-1:0];
initial begin
$readmemh("test.txt", ram);
end
 
reg vsync_d, hsync_d;
reg [15:0] countX, countY, count_de;
reg [23:0] count_data;
reg [7:0] r8_d, g8_d, b8_d;
wire vsync_high_puls = vsync & !vsync_d;
wire hsync_high_puls = hsync & !hsync_d;
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) count_de <= 0;
else if (de) count_de <= count_de +1;
else count_de <= 0;
end
wire active_line_err = (count_de > 800);
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) count_data <= 0;
else if (vsync_high_puls) count_data <= 0;
else if (de) count_data <= count_data +1;
end
always @(posedge pixel_clk) vsync_d <= vsync;
always @(posedge pixel_clk) hsync_d <= hsync;
 
reg data_err;
always @(posedge pixel_clk) if (de) r8_d <= r8;
always @(posedge pixel_clk) if (de) g8_d <= g8;
always @(posedge pixel_clk) if (de) b8_d <= b8;
wire [63:0] data_in = {8'h0, r8,g8,b8, 8'h0,r8_d,g8_d,b8_d};
wire [63:0] data_check = ram[count_data[23:1]];
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) data_err <= 0;
else if (de) begin
if (count_data[0]) begin
data_err <= (data_in != data_check);
end
else data_err <= 0;
end
else data_err <= 0;
end
 
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) countY <= 0;
else if (vsync_high_puls) countY <= 0;
else if (hsync_high_puls) countY <= countY +1;
end
reg [15:0] line_no;
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) line_no <= 0;
else if (vsync_high_puls) line_no <= countY;
end
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) countX <= 0;
else if (hsync_high_puls) countX <= 0;
else countX <= countX +1;
end
reg [15:0] pixel_no;
always @(negedge reset_n or posedge pixel_clk) begin
if (!reset_n) pixel_no <= 0;
else if (hsync_high_puls) pixel_no <= countX;
end
 
endmodule

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