URL
https://opencores.org/ocsvn/artec_dongle_ii_fpga/artec_dongle_ii_fpga/trunk
Subversion Repositories artec_dongle_ii_fpga
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.pof
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.pof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.pin
===================================================================
--- tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.pin (nonexistent)
+++ tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.pin (revision 3)
@@ -0,0 +1,331 @@
+ -- Copyright (C) 1991-2008 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the needs of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10 kohm resistor
+ -- to GND or tie all pins together and connect through a single 10 kohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition
+CHIP "dongle_syn" ASSIGNED TO AN: EP3C5F256C7
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCIO8 : A1 : power : : 3.3V : 8 :
+seg_out[0] : A2 : output : 3.3-V LVTTL : : 8 : Y
+seg_out[3] : A3 : output : 3.3-V LVTTL : : 8 : Y
+scn_seg[1] : A4 : output : 3.3-V LVTTL : : 8 : Y
+seg_out[4] : A5 : output : 3.3-V LVTTL : : 8 : Y
+seg_out[7] : A6 : output : 3.3-V LVTTL : : 8 : Y
+led_green : A7 : output : 3.3-V LVCMOS : : 8 : Y
+scn_seg[2] : A8 : output : 3.3-V LVTTL : : 8 : Y
+hdr[4] : A9 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[5] : A10 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[7] : A11 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[9] : A12 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[10] : A13 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[12] : A14 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[14] : A15 : bidir : 3.3-V LVCMOS : : 7 : Y
+VCCIO7 : A16 : power : : 3.3V : 7 :
+usb_rxf_n : B1 : input : 3.3-V LVCMOS : : 1 : Y
+GND : B2 : gnd : : : :
+seg_out[2] : B3 : output : 3.3-V LVTTL : : 8 : Y
+scn_seg[0] : B4 : output : 3.3-V LVTTL : : 8 : Y
+scn_seg[3] : B5 : output : 3.3-V LVTTL : : 8 : Y
+seg_out[6] : B6 : output : 3.3-V LVTTL : : 8 : Y
+led_red : B7 : output : 3.3-V LVCMOS : : 8 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
+hdr[3] : B9 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[6] : B10 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[8] : B11 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[11] : B12 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[13] : B13 : bidir : 3.3-V LVCMOS : : 7 : Y
+hdr[15] : B14 : bidir : 3.3-V LVCMOS : : 7 : Y
+GND : B15 : gnd : : : :
+ldev_present : B16 : output : 3.3-V LVTTL : : 6 : Y
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVCMOS : : 1 : N
+usb_txe_n : C2 : input : 3.3-V LVCMOS : : 1 : Y
+seg_out[1] : C3 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : C4 : power : : 3.3V : 8 :
+GND : C5 : gnd : : : :
+seg_out[5] : C6 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : C7 : power : : 3.3V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
+hdr[2] : C9 : bidir : 3.3-V LVCMOS : : 7 : Y
+VCCIO7 : C10 : power : : 3.3V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
+GND : C12 : gnd : : : :
+VCCIO7 : C13 : power : : 3.3V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
+lad[0] : C15 : bidir : 3.3-V LVCMOS : : 6 : Y
+lad[2] : C16 : bidir : 3.3-V LVCMOS : : 6 : Y
+usb_bd[1] : D1 : bidir : 3.3-V LVCMOS : : 1 : Y
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVCMOS : : 1 : N
+buf_oe_n : D3 : output : 3.3-V LVCMOS : : 8 : Y
+usb_wr : D4 : bidir : 3.3-V LVCMOS : : 1 : Y
+mode[0] : D5 : bidir : 3.3-V LVCMOS : : 8 : Y
+mode[2] : D6 : bidir : 3.3-V LVCMOS : : 8 : Y
+GND : D7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
+hdr[1] : D9 : bidir : 3.3-V LVCMOS : : 7 : Y
+GND : D10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
+VCCD_PLL2 : D13 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
+lreset_n : D15 : input : 3.3-V LVCMOS : : 6 : Y
+lad[3] : D16 : bidir : 3.3-V LVCMOS : : 6 : Y
+sys_clk : E1 : input : 3.3-V LVCMOS : : 1 : Y
+GND+ : E2 : : : : 1 :
+VCCIO1 : E3 : power : : 3.3V : 1 :
+GND : E4 : gnd : : : :
+usb_bd[0] : E5 : bidir : 3.3-V LVCMOS : : 1 : Y
+mode[1] : E6 : bidir : 3.3-V LVCMOS : : 8 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
+hdr[0] : E9 : bidir : 3.3-V LVCMOS : : 7 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 :
+GNDA : E12 : gnd : : : :
+GND : E13 : gnd : : : :
+VCCIO6 : E14 : power : : 3.3V : 6 :
+lclk : E15 : input : 3.3-V LVCMOS : : 6 : Y
+GND+ : E16 : : : : 6 :
+usb_bd[3] : F1 : bidir : 3.3-V LVCMOS : : 1 : Y
+usb_bd[4] : F2 : bidir : 3.3-V LVCMOS : : 1 : Y
+usb_bd[2] : F3 : bidir : 3.3-V LVCMOS : : 1 : Y
+nSTATUS : F4 : : : : 1 :
+usb_bd[6] : F5 : bidir : 3.3-V LVCMOS : : 1 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 :
+VCCA2 : F12 : power : : 2.5V : :
+lframe_n : F13 : input : 3.3-V LVCMOS : : 6 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 :
+~ALTERA_nCEO~ : F16 : output : 3.3-V LVCMOS : : 6 : N
+usb_bd[7] : G1 : bidir : 3.3-V LVCMOS : : 1 : Y
+usb_bd[5] : G2 : bidir : 3.3-V LVCMOS : : 1 : Y
+VCCIO1 : G3 : power : : 3.3V : 1 :
+GND : G4 : gnd : : : :
+usb_rd_n : G5 : bidir : 3.3-V LVCMOS : : 1 : Y
+VCCINT : G6 : power : : 1.2V : :
+VCCINT : G7 : power : : 1.2V : :
+VCCINT : G8 : power : : 1.2V : :
+VCCINT : G9 : power : : 1.2V : :
+VCCINT : G10 : power : : 1.2V : :
+lad[1] : G11 : bidir : 3.3-V LVCMOS : : 6 : Y
+MSEL2 : G12 : : : : 6 :
+GND : G13 : gnd : : : :
+VCCIO6 : G14 : power : : 3.3V : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 :
+~ALTERA_DCLK~ : H1 : output : 3.3-V LVCMOS : : 1 : N
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 3.3-V LVCMOS : : 1 : N
+TCK : H3 : input : : : 1 :
+TDI : H4 : input : : : 1 :
+nCONFIG : H5 : : : : 1 :
+VCCINT : H6 : power : : 1.2V : :
+GND : H7 : gnd : : : :
+GND : H8 : gnd : : : :
+GND : H9 : gnd : : : :
+GND : H10 : gnd : : : :
+VCCINT : H11 : power : : 1.2V : :
+MSEL1 : H12 : : : : 6 :
+MSEL0 : H13 : : : : 6 :
+CONF_DONE : H14 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 :
+fl_data[4] : J1 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[11] : J2 : bidir : 3.3-V LVCMOS : : 2 : Y
+nCE : J3 : : : : 1 :
+TDO : J4 : output : : : 1 :
+TMS : J5 : input : : : 1 :
+fl_data[5] : J6 : bidir : 3.3-V LVCMOS : : 2 : Y
+GND : J7 : gnd : : : :
+GND : J8 : gnd : : : :
+GND : J9 : gnd : : : :
+GND : J10 : gnd : : : :
+hdr_b[1] : J11 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[3] : J12 : bidir : 3.3-V LVCMOS : : 5 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 :
+fl_sts_en : J15 : output : 3.3-V LVCMOS : : 5 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 :
+fl_data[10] : K1 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[2] : K2 : bidir : 3.3-V LVCMOS : : 2 : Y
+VCCIO2 : K3 : power : : 3.3V : 2 :
+GND : K4 : gnd : : : :
+fl_data[3] : K5 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[12] : K6 : bidir : 3.3-V LVCMOS : : 2 : Y
+VCCINT : K7 : power : : 1.2V : :
+fl_addr[5] : K8 : output : 3.3-V LVCMOS : : 3 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 :
+hdr_b[0] : K11 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[2] : K12 : bidir : 3.3-V LVCMOS : : 5 : Y
+GND : K13 : gnd : : : :
+VCCIO5 : K14 : power : : 3.3V : 5 :
+fl_rp_n : K15 : output : 3.3-V LVCMOS : : 5 : N
+resetn : K16 : input : 3.3-V LVCMOS : : 5 : Y
+fl_data[1] : L1 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[9] : L2 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[8] : L3 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[0] : L4 : bidir : 3.3-V LVCMOS : : 2 : Y
+VCCA1 : L5 : power : : 2.5V : :
+fl_data[7] : L6 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_addr[6] : L7 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[7] : L8 : output : 3.3-V LVCMOS : : 3 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 :
+hdr_b[7] : L12 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[5] : L13 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[12] : L14 : bidir : 3.3-V LVCMOS : : 5 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 :
+hdr_b[14] : L16 : bidir : 3.3-V LVCMOS : : 5 : Y
+GND+ : M1 : : : : 2 :
+GND+ : M2 : : : : 2 :
+VCCIO2 : M3 : power : : 3.3V : 2 :
+GND : M4 : gnd : : : :
+GNDA : M5 : gnd : : : :
+fl_addr[23] : M6 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[1] : M7 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[2] : M8 : output : 3.3-V LVCMOS : : 3 : Y
+ps_msb_en : M9 : output : 3.3-V LVCMOS : : 4 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 :
+hdr_b[4] : M12 : bidir : 3.3-V LVCMOS : : 5 : Y
+GND : M13 : gnd : : : :
+VCCIO5 : M14 : power : : 3.3V : 5 :
+GND+ : M15 : : : : 5 :
+GND+ : M16 : : : : 5 :
+fl_sts : N1 : input : 3.3-V LVCMOS : : 2 : Y
+fl_data[15] : N2 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_addr[0] : N3 : output : 3.3-V LVCMOS : : 3 : Y
+VCCD_PLL1 : N4 : power : : 1.2V : :
+fl_we_n : N5 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[4] : N6 : output : 3.3-V LVCMOS : : 3 : Y
+GND : N7 : gnd : : : :
+fl_addr[3] : N8 : output : 3.3-V LVCMOS : : 3 : Y
+ps_ram_en : N9 : output : 3.3-V LVCMOS : : 4 : Y
+GND : N10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 :
+hdr_b[9] : N13 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[6] : N14 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[11] : N15 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[15] : N16 : bidir : 3.3-V LVCMOS : : 5 : Y
+fl_data[13] : P1 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_data[6] : P2 : bidir : 3.3-V LVCMOS : : 2 : Y
+fl_addr[21] : P3 : output : 3.3-V LVCMOS : : 3 : Y
+VCCIO3 : P4 : power : : 3.3V : 3 :
+GND : P5 : gnd : : : :
+fl_addr[14] : P6 : output : 3.3-V LVCMOS : : 3 : Y
+VCCIO3 : P7 : power : : 3.3V : 3 :
+fl_addr[9] : P8 : output : 3.3-V LVCMOS : : 3 : Y
+ps_addr_val : P9 : output : 3.3-V LVCMOS : : 4 : Y
+VCCIO4 : P10 : power : : 3.3V : 4 :
+ee_di : P11 : output : 3.3-V LVCMOS : : 4 : Y
+GND : P12 : gnd : : : :
+VCCIO4 : P13 : power : : 3.3V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 :
+hdr_b[8] : P15 : bidir : 3.3-V LVCMOS : : 5 : Y
+hdr_b[10] : P16 : bidir : 3.3-V LVCMOS : : 5 : Y
+fl_data[14] : R1 : bidir : 3.3-V LVCMOS : : 2 : Y
+GND : R2 : gnd : : : :
+fl_addr[20] : R3 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[18] : R4 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[16] : R5 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[13] : R6 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[11] : R7 : output : 3.3-V LVCMOS : : 3 : Y
+ps_clk : R8 : output : 3.3-V LVCMOS : : 3 : Y
+fl_oe_n : R9 : output : 3.3-V LVCMOS : : 4 : Y
+ps_lsb_en : R10 : output : 3.3-V LVCMOS : : 4 : Y
+ee_hold_n : R11 : output : 3.3-V LVCMOS : : 4 : Y
+ee_cs_n : R12 : output : 3.3-V LVCMOS : : 4 : Y
+ee_do : R13 : input : 3.3-V LVCMOS : : 4 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 :
+GND : R15 : gnd : : : :
+hdr_b[13] : R16 : bidir : 3.3-V LVCMOS : : 5 : Y
+VCCIO3 : T1 : power : : 3.3V : 3 :
+fl_addr[22] : T2 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[19] : T3 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[17] : T4 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[15] : T5 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[12] : T6 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[10] : T7 : output : 3.3-V LVCMOS : : 3 : Y
+fl_addr[8] : T8 : output : 3.3-V LVCMOS : : 3 : Y
+ps_confr_en : T9 : output : 3.3-V LVCMOS : : 4 : Y
+ps_wait : T10 : input : 3.3-V LVCMOS : : 4 : Y
+fl_ce_n : T11 : output : 3.3-V LVCMOS : : 4 : Y
+ee_clk : T12 : output : 3.3-V LVCMOS : : 4 : Y
+ee_write : T13 : output : 3.3-V LVCMOS : : 4 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 :
+VCCIO4 : T16 : power : : 3.3V : 4 :
Index: tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qpf
===================================================================
--- tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qpf (nonexistent)
+++ tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qpf (revision 3)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "6.0"
+DATE = "13:34:29 August 31, 2006"
+
+
+# Revisions
+
+PROJECT_REVISION = "dongle_syn"
Index: tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qsf
===================================================================
--- tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qsf (nonexistent)
+++ tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.qsf (revision 3)
@@ -0,0 +1,226 @@
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# dongle_syn_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C5F256C7
+set_global_assignment -name TOP_LEVEL_ENTITY design_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:34:29 AUGUST 31, 2006"
+set_global_assignment -name LAST_QUARTUS_VERSION 8.0
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to lad
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_data
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hdr
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_bd
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_addr
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_ce_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_oe_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_rp_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_we_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_green
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_red
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to scn_seg
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to seg_out
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_rd_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_wr
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[5]
+set_global_assignment -name VHDL_FILE ../src/postcode_ser/fifo.vhd
+set_global_assignment -name VHDL_FILE ../src/postcode_ser/pc_serializer.vhd
+set_global_assignment -name VHDL_FILE ../src/usb/usb2mem.vhd
+set_global_assignment -name VHDL_FILE ../src/lpc_proto/lpc_byte.vhd
+set_global_assignment -name VHDL_FILE ../src/flash/flsh_if.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/led_coder.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/byte_scan_mux.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/led_sys.vhd
+set_global_assignment -name VHDL_FILE ../src/design_top/design_top_thincandbg.vhd
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name POWER_USE_INPUT_FILES OFF
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER sys_clk -section_id sys25
+set_instance_assignment -name CLOCK_SETTINGS design_top|lclk -to lclk
+set_instance_assignment -name CLOCK_SETTINGS design_top|sys_clk -to sys_clk
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name FMAX_REQUIREMENT "25 MHz" -section_id design_top|sys_clk
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id design_top|lclk
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 100%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 100%
+set_global_assignment -name POWER_USE_PVA OFF
+set_location_assignment PIN_L4 -to fl_data[0]
+set_location_assignment PIN_L1 -to fl_data[1]
+set_location_assignment PIN_K2 -to fl_data[2]
+set_location_assignment PIN_K5 -to fl_data[3]
+set_location_assignment PIN_J1 -to fl_data[4]
+set_location_assignment PIN_J6 -to fl_data[5]
+set_location_assignment PIN_P2 -to fl_data[6]
+set_location_assignment PIN_L6 -to fl_data[7]
+set_location_assignment PIN_L3 -to fl_data[8]
+set_location_assignment PIN_L2 -to fl_data[9]
+set_location_assignment PIN_K1 -to fl_data[10]
+set_location_assignment PIN_J2 -to fl_data[11]
+set_location_assignment PIN_K6 -to fl_data[12]
+set_location_assignment PIN_P1 -to fl_data[13]
+set_location_assignment PIN_R1 -to fl_data[14]
+set_location_assignment PIN_N2 -to fl_data[15]
+set_location_assignment PIN_N1 -to fl_sts
+set_location_assignment PIN_N3 -to fl_addr[0]
+set_location_assignment PIN_M7 -to fl_addr[1]
+set_location_assignment PIN_M8 -to fl_addr[2]
+set_location_assignment PIN_N8 -to fl_addr[3]
+set_location_assignment PIN_N6 -to fl_addr[4]
+set_location_assignment PIN_K8 -to fl_addr[5]
+set_location_assignment PIN_L7 -to fl_addr[6]
+set_location_assignment PIN_L8 -to fl_addr[7]
+set_location_assignment PIN_T8 -to fl_addr[8]
+set_location_assignment PIN_P8 -to fl_addr[9]
+set_location_assignment PIN_T7 -to fl_addr[10]
+set_location_assignment PIN_R7 -to fl_addr[11]
+set_location_assignment PIN_T6 -to fl_addr[12]
+set_location_assignment PIN_R6 -to fl_addr[13]
+set_location_assignment PIN_P6 -to fl_addr[14]
+set_location_assignment PIN_T5 -to fl_addr[15]
+set_location_assignment PIN_R5 -to fl_addr[16]
+set_location_assignment PIN_T4 -to fl_addr[17]
+set_location_assignment PIN_R4 -to fl_addr[18]
+set_location_assignment PIN_T3 -to fl_addr[19]
+set_location_assignment PIN_R3 -to fl_addr[20]
+set_location_assignment PIN_P3 -to fl_addr[21]
+set_location_assignment PIN_T2 -to fl_addr[22]
+set_location_assignment PIN_M6 -to fl_addr[23]
+set_location_assignment PIN_N5 -to fl_we_n
+set_location_assignment PIN_P9 -to ps_addr_val
+set_location_assignment PIN_R8 -to ps_clk
+set_location_assignment PIN_T9 -to ps_confr_en
+set_location_assignment PIN_R10 -to ps_lsb_en
+set_location_assignment PIN_M9 -to ps_msb_en
+set_location_assignment PIN_T10 -to ps_wait
+set_location_assignment PIN_T12 -to ee_clk
+set_location_assignment PIN_R12 -to ee_cs_n
+set_location_assignment PIN_P11 -to ee_di
+set_location_assignment PIN_R13 -to ee_do
+set_location_assignment PIN_R11 -to ee_hold_n
+set_location_assignment PIN_T13 -to ee_write
+set_location_assignment PIN_T11 -to fl_ce_n
+set_location_assignment PIN_R9 -to fl_oe_n
+set_location_assignment PIN_E5 -to usb_bd[0]
+set_location_assignment PIN_D1 -to usb_bd[1]
+set_location_assignment PIN_F3 -to usb_bd[2]
+set_location_assignment PIN_F1 -to usb_bd[3]
+set_location_assignment PIN_F2 -to usb_bd[4]
+set_location_assignment PIN_G2 -to usb_bd[5]
+set_location_assignment PIN_F5 -to usb_bd[6]
+set_location_assignment PIN_G1 -to usb_bd[7]
+set_location_assignment PIN_G5 -to usb_rd_n
+set_location_assignment PIN_B1 -to usb_rxf_n
+set_location_assignment PIN_C2 -to usb_txe_n
+set_location_assignment PIN_D4 -to usb_wr
+set_location_assignment PIN_E15 -to lclk
+set_location_assignment PIN_E1 -to sys_clk
+set_location_assignment PIN_B7 -to led_red
+set_location_assignment PIN_A7 -to led_green
+set_location_assignment PIN_B4 -to scn_seg[0]
+set_location_assignment PIN_A4 -to scn_seg[1]
+set_location_assignment PIN_A8 -to scn_seg[2]
+set_location_assignment PIN_B5 -to scn_seg[3]
+set_location_assignment PIN_A2 -to seg_out[0]
+set_location_assignment PIN_C3 -to seg_out[1]
+set_location_assignment PIN_B3 -to seg_out[2]
+set_location_assignment PIN_A3 -to seg_out[3]
+set_location_assignment PIN_A5 -to seg_out[4]
+set_location_assignment PIN_C6 -to seg_out[5]
+set_location_assignment PIN_B6 -to seg_out[6]
+set_location_assignment PIN_A6 -to seg_out[7]
+set_location_assignment PIN_D5 -to mode[0]
+set_location_assignment PIN_E6 -to mode[1]
+set_location_assignment PIN_D6 -to mode[2]
+set_location_assignment PIN_D3 -to buf_oe_n
+set_location_assignment PIN_C15 -to lad[0]
+set_location_assignment PIN_G11 -to lad[1]
+set_location_assignment PIN_C16 -to lad[2]
+set_location_assignment PIN_D16 -to lad[3]
+set_location_assignment PIN_D15 -to lreset_n
+set_location_assignment PIN_F13 -to lframe_n
+set_location_assignment PIN_K16 -to resetn
+set_location_assignment PIN_E9 -to hdr[0]
+set_location_assignment PIN_D9 -to hdr[1]
+set_location_assignment PIN_C9 -to hdr[2]
+set_location_assignment PIN_B9 -to hdr[3]
+set_location_assignment PIN_A9 -to hdr[4]
+set_location_assignment PIN_A10 -to hdr[5]
+set_location_assignment PIN_B10 -to hdr[6]
+set_location_assignment PIN_A11 -to hdr[7]
+set_location_assignment PIN_B11 -to hdr[8]
+set_location_assignment PIN_A12 -to hdr[9]
+set_location_assignment PIN_A13 -to hdr[10]
+set_location_assignment PIN_B12 -to hdr[11]
+set_location_assignment PIN_A14 -to hdr[12]
+set_location_assignment PIN_B13 -to hdr[13]
+set_location_assignment PIN_A15 -to hdr[14]
+set_location_assignment PIN_B14 -to hdr[15]
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg_out
+set_location_assignment PIN_B16 -to ldev_present
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[1]
+set_location_assignment PIN_K11 -to hdr_b[0]
+set_location_assignment PIN_J11 -to hdr_b[1]
+set_location_assignment PIN_K12 -to hdr_b[2]
+set_location_assignment PIN_J12 -to hdr_b[3]
+set_location_assignment PIN_M12 -to hdr_b[4]
+set_location_assignment PIN_L13 -to hdr_b[5]
+set_location_assignment PIN_N14 -to hdr_b[6]
+set_location_assignment PIN_L12 -to hdr_b[7]
+set_location_assignment PIN_P15 -to hdr_b[8]
+set_location_assignment PIN_N13 -to hdr_b[9]
+set_location_assignment PIN_P16 -to hdr_b[10]
+set_location_assignment PIN_N15 -to hdr_b[11]
+set_location_assignment PIN_L14 -to hdr_b[12]
+set_location_assignment PIN_R16 -to hdr_b[13]
+set_location_assignment PIN_L16 -to hdr_b[14]
+set_location_assignment PIN_N16 -to hdr_b[15]
+set_location_assignment PIN_N9 -to ps_ram_en
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buf_oe_n
+set_global_assignment -name VHDL_FILE ../src/spi_eeprom/spi_master.vhd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ldev_present
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ldev_present
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ps_ram_en
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_we_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_ce_n
\ No newline at end of file
Index: tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn_assignment_defaults.qdf
===================================================================
--- tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn_assignment_defaults.qdf (nonexistent)
+++ tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn_assignment_defaults.qdf (revision 3)
@@ -0,0 +1,422 @@
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_IO_BUFFER_CONVERSION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS -value OFF
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS -value ON
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF -value ON
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE -value OFF
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off
+set_global_assignment -name HCII_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_USE_VOLTAGE NOMINAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
+set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs"
+set_global_assignment -name MUX_RESTRUCTURE AUTO
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY Stratix
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off
+set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION On
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name IGNORE_DUPLICATE_DESIGN_ENTITY Off
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1"
+set_global_assignment -name IGNORE_TRANSLATE_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name INCREMENTAL_COMPILATION Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths"
+set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT -value "AUTO FIT"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name DRC_REPORT_TOP_FANOUT On
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING On
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name SIGNALRACE_RULE_TRISTATE On
+set_global_assignment -name SIGNALRACE_RULE_RESET_RACE On
+set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM On
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_CAT On
+set_global_assignment -name CLK_RULE_COMB_CLOCK On
+set_global_assignment -name CLK_RULE_INV_CLOCK On
+set_global_assignment -name CLK_RULE_GATING_SCHEME On
+set_global_assignment -name CLK_RULE_INPINS_CLKNET On
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES On
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name CLK_RULE_MIX_EDGES On
+set_global_assignment -name RESET_CAT On
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET On
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET On
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET On
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN On
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN On
+set_global_assignment -name TIMING_CAT On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE On
+set_global_assignment -name NONSYNCHSTRUCT_CAT On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED On
+set_global_assignment -name SIGNALRACE_CAT On
+set_global_assignment -name ACLK_CAT On
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN On
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN On
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN On
+set_global_assignment -name HCPY_CAT On
+set_global_assignment -name HCPY_VREF_PINS On
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY -value OFF
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
Index: tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.cdf
===================================================================
--- tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.cdf (nonexistent)
+++ tags/google_release_of_0x20_firmware/altera_quartus_proj/dongle_syn.cdf (revision 3)
@@ -0,0 +1,13 @@
+/* Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Cfg)
+ Device PartName(EPCS4) Path("C:/projects/gDongle_Board/altera_quartus_proj/") File("dongle_syn.pof") MfrSpec(OpMask(1) Child_OpMask(1 1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(asc);
+AlteraEnd;
Index: tags/google_release_of_0x20_firmware/update/update.py
===================================================================
--- tags/google_release_of_0x20_firmware/update/update.py (nonexistent)
+++ tags/google_release_of_0x20_firmware/update/update.py (revision 3)
@@ -0,0 +1,504 @@
+#! /usr/bin/python
+# -*- coding: ISO-8859-1 -*-
+
+##########################################################################
+# Programming utility for Altera EPCS memory on USB Dongle PCB
+#
+# Copyright (C) 2008 Artec Design
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This software is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##########################################################################
+
+#-------------------------------------------------------------------------
+# Project: Programming utility for Altera EPCS memory on USB Dongle PCB
+# Name: update.py
+# Purpose: Executable command line tool
+#
+# Author: Jüri Toomessoo
+# Copyright: (c) 2008 by Artec Design
+# Licence: LGPL
+#
+# Created: 12 Mar. 2008
+# History: 12 Mar. 2008 Version 0.2 released
+#-------------------------------------------------------------------------
+
+import os
+import sys
+import string
+import time
+
+
+
+#### EPCS code starts here ##################################################################
+
+
+#### global funcs ####
+def usage(s):
+ print "Artec's Altera EPCS programming utility ver. 0.2.1 for USB Dongle"
+ print "Use with Altera ByteBlaster II programmer or compatible clone on LPT1"
+ print "like X-Blaster http://www.customcircuitsolutions.com/cable.html or"
+ print "http://fpgaguy.110mb.com/"
+ print "Usage:"
+ print "Query : ",s," -q"
+ print "Write file : ",s," [-v] "
+ print "Readback file : ",s," [-v] -r "
+ print "Options:"
+ print " -v Enable verbose mode. Displays more progress information"
+ print " -q Perform EPCS and ByteBlaster II query to see if all is ok"
+ print ""
+ print "Examples:"
+ print ""
+ print " ",s," dongle_syn.rpd "
+ print " ",s," -r epcs_content.rpd "
+######################
+
+
+class DeviceMode:
+ def __init__(self):
+ self.v = 0
+ self.f = 0
+ self.d = 0
+ self.q = 0
+ self.r = 0
+ self.t = 0
+ self.e = 0
+ self.b = 0
+ self.l = 0
+ self.filename=""
+ self.portname=""
+ self.address=-1
+ self.offset=-1
+ self.length=-1
+ self.version=4
+
+ def convParamStr(self,param):
+ mult = 1
+ value = 0
+ str = param
+ if str.find("K")>-1:
+ mult = 1024
+ str=str.strip("K")
+ if str.find("M")>-1:
+ mult = 1024*1024
+ str=str.strip("M")
+ try:
+ if str.find("x")>-1:
+ value = int(str,0)*mult #conver hex string to int
+ else:
+ value = int(str)*mult #conver demical string to int
+ except ValueError:
+ print "Bad parameter format given for: ",param
+
+ return value
+
+
+
+
+class EPCSDevice:
+
+ def __init__(self):
+ self._data = 0xFF
+ self.mode = 0 #commands are bit flipped
+ self.CMD_WRITE_ENABLE = 0x60 #0x06
+ self.CMD_WRITE_DISABLE= 0x20 #0x04
+ self.CMD_READ_STATUS=0xA0 #0x05
+ self.CMD_READ_BYTES=0xC0 #0x03
+ self.CMD_READ_ID=0xD5 #0xAB
+ self.CMD_WRITE_STATUS=0x80 #0x01
+ self.CMD_WRITE_BYTES=0x40 #0x02
+ self.CMD_ERASE_BULK=0xE3 #0xC7
+ self.CMD_ERASE_SECTOR=0x1B #0xD8
+ if sys.platform=='win32':
+ try:
+ import parallel
+ except ImportError:
+ print "Can't find pyparallel module"
+ print "pyparallel is available at: "
+ print "http://pyserial.sourceforge.net/pyparallel.html"
+ print "Supports Windows NT/2k/XP trough giveio.sys"
+ sys.exit()
+ self.pport = parallel.Parallel()
+
+ else:
+ try:
+ import parallel
+ except ImportError:
+ print "Can't find pyparallel module"
+ print "pyparallel is available at: "
+ print "http://pyserial.sourceforge.net/pyparallel.html"
+ print "Supports Linux trough ppdev driver"
+ sys.exit()
+ self.pport = parallel.Parallel()
+
+ def open(self):
+ i=0
+ self.pport.setAutoFeed(1) #enable BB II tristate buffers to drive
+ #self.pport.setDataDir(0xFF) #enable out mode on pport
+ self.pport.setData(0x10) # set pport D4 this is looped back to ACK when tri's are enabled
+ if self.pport.getInAcknowledge():
+ i=i+1
+ self.pport.setData(0x00) # set pport D4 this is looped back to ACK when tri's are enabled
+ if not self.pport.getInAcknowledge():
+ i=i+1
+ if i==2:
+ print "Found ByteBlaster II compatible programmer"
+ else:
+ print "Can't find ByteBlaster II on parallel port"
+ sys.exit()
+ self.pport.setData(0xFF)
+ self._data = 0xFF
+
+
+ def close(self):
+ epcs.pport.setData(0xFF)
+ epcs.pport.setAutoFeed(1) #disable BB II tristate buffers to drive
+ epcs.clearPPDataBit(3) #enable Cyclon chip
+ epcs.clearPPDataBit(2) #enable Cyclon chip
+
+ def setPPDataBit(self,bit_no):
+ self._data = self._data|(1<> 1
+ i+=1
+ #print "-------------------"
+
+ def writeFlippedByte(self,byte):
+ #ok lets do bit reversal in a byte
+ #it would be faster with a look up table (even with autogenerated one) FIXME
+ i=0
+ while i<8:
+ self.setASDI(byte&0x01)
+ self.clockCycle()
+ byte = byte >> 1
+ i+=1
+
+ def writeByte(self,byte):
+ #ok lets do bit reversal in a byte
+ #it would be faster with a look up table (even with autogenerated one) FIXME
+ etyb = ((byte&0x01)<<7)|((byte&0x02)<<5)|((byte&0x04)<<3)|((byte&0x08)<<1)|((byte&0x10)>>1)|((byte&0x20)>>3)|((byte&0x40)>>5)|((byte&0x80)>>7)
+ i=0
+ while i<8:
+ self.setASDI(etyb&0x01)
+ self.clockCycle()
+ etyb = etyb >> 1
+ i+=1
+
+ def writeAddress(self,address):
+ byte = (address&0x00FF0000)>>16
+ self.writeByte(byte) #this is used to write byte of address
+ byte = (address&0x0000FF00)>>8
+ self.writeByte(byte)
+ byte = (address&0x000000FF)
+ self.writeByte(byte)
+
+
+ def readByte(self):
+ i=0
+ byte = 0
+ #print "-------------------"
+ while i<8:
+ byte = byte << 1
+ self.clearPPDataBit(0) # make falling edge for read
+ if self.pport.getInSelected():
+ byte=byte|0x01
+ self.setPPDataBit(0) # make rising edge for read
+ i+=1
+ #print "-------------------"
+ return byte
+
+ ######################### EPCS command calls #############################
+ def getDeviceID(self):
+ self.startCycle()
+ self.writeCommand(self.CMD_READ_ID)
+ self.writeCommand(0x00) # dummy write
+ self.writeCommand(0x00) # dummy write
+ self.writeCommand(0x00) # dummy write
+ byte = self.readByte()
+ self.endCycle()
+ return byte
+
+ def setWriteEnable(self):
+ self.startCycle()
+ self.writeCommand(self.CMD_WRITE_ENABLE)
+ self.endCycle()
+
+ def setWriteDisable(self):
+ self.startCycle()
+ self.writeCommand(self.CMD_WRITE_DISABLE)
+ self.endCycle()
+
+ def getStatusReg(self):
+ self.startCycle()
+ self.writeCommand(self.CMD_READ_STATUS)
+ byte = self.readByte()
+ self.endCycle()
+ return byte
+
+ def readBytes(self,address,count):
+ buffer = ""
+ i = 0
+ self.startCycle()
+ self.writeCommand(self.CMD_READ_BYTES)
+ self.writeAddress(address)
+ while(i>1)|((byte&0x20)>>3)|((byte&0x40)>>5)|((byte&0x80)>>7)
+ #print "Reading %2x"%(byte)
+ buffer = buffer + chr(etyb) #this can continue endlessly if needed the address is auto INC'ed and is freerunning
+ i+=1
+ self.endCycle()
+ return buffer
+
+ def writeBytes(self,address,buffer): #256 is maximum and is physical page limit of EPCS devices
+ count = len(buffer)
+ i = 0
+ self.setWriteEnable() #will be autoreset after this
+ self.startCycle()
+ self.writeCommand(self.CMD_WRITE_BYTES)
+ self.writeAddress(address)
+ while(i= last_ops + 2:
+ print "Too many parameters provided"
+ sys.exit()
+
+############## END PARSE ARGUMENTS ###############################################33
+
+
+epcs = EPCSDevice()
+epcs.open()
+if epcs.pport.getInError():
+ print "No Voltage source detected"
+else:
+ print "Voltage source OK"
+
+byte = epcs.getDeviceID()
+if byte == 0x10:
+ print "EPCS1 Configuration device found"
+ if mode.q == 1:
+ print "EPCS Silicon ID = 0x%2x"%(byte)
+ sys.exit() # if q then exit
+elif not byte == 0xFF:
+ print "Not supported device found"
+ if mode.q == 1:
+ print "Silicon ID = 0x%2x"%(byte)
+ sys.exit()
+else:
+ if not epcs.pport.getInError():
+ print "No device attached to cable"
+ if mode.q == 1:
+ print "Got 0x%2x for ID "%(byte)
+ epcs.close()
+ sys.exit()
+
+if mode.e == 1:
+ print "Erasing EPCS device"
+ epcs.eraseBulk()
+ print "Done"
+
+if mode.filename!="" and mode.r==0:
+ print "Erasing EPCS device"
+ epcs.eraseBulk()
+ print "Done"
+ size = 0
+ mode.address = 0
+ try:
+ f=open(mode.filename,"rb")
+ f.seek(0,2) #seek to end
+ size = f.tell()
+ f.seek(0) #seek to start
+ print 'File size %iK '%(size/1024)
+ f.close()
+ except IOError:
+ print "IO Error on file open"
+ sys.exit()
+ #all seems in order so lest start
+ f=open(mode.filename,"rb")
+ f.seek(0) #seek to start
+ address = mode.address
+ print 'Writing %iK'%(size/1024)
+ while 1:
+ if (address/(1024*4) != (address-16)/(1024*4)) and address != mode.address: # get bytes from words if 512
+ if mode.v == 1:
+ print 'Progress: %iK of %iK at 0x%06x'%((address-mode.address)/1024,size/1024,address)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ buf = f.read(256) #we can write 256 bytes at a time
+ if len(buf)==256:
+ epcs.writeFlippedBytes(address,buf)
+ address = address + 256 #we use byte address
+ elif len(buf)>0:
+ epcs.writeFlippedBytes(address,buf) #write last bytes
+ break
+ else:
+ break
+ if mode.v == 0:
+ print " "
+ print "Write DONE!"
+ f.close()
+elif mode.filename!="": # then read flag must be up
+ size = 0x20000 #byte count of EPCS1 device
+ try:
+ f=open(mode.filename,"wb") #if this fails no point in reading as there is nowhere to write
+ address = 0 # set word address
+ buf=""
+ print "Start readback"
+ buf=epcs.readFlippedBytes(address,size)
+ print "Read done"
+ f.write(buf)
+ f.close()
+ print "Done"
+ except IOError:
+ print "IO Error on file open"
+ sys.exit()
+
+epcs.close()
+time.sleep(0.5)
+
Index: tags/google_release_of_0x20_firmware/update/BBII_schematic.odg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/update/BBII_schematic.odg
===================================================================
--- tags/google_release_of_0x20_firmware/update/BBII_schematic.odg (nonexistent)
+++ tags/google_release_of_0x20_firmware/update/BBII_schematic.odg (revision 3)
tags/google_release_of_0x20_firmware/update/BBII_schematic.odg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/update/BBII_schematic.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/update/BBII_schematic.pdf
===================================================================
--- tags/google_release_of_0x20_firmware/update/BBII_schematic.pdf (nonexistent)
+++ tags/google_release_of_0x20_firmware/update/BBII_schematic.pdf (revision 3)
tags/google_release_of_0x20_firmware/update/BBII_schematic.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/doc/Dongle_II_wishlist.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/doc/Dongle_II_wishlist.odt
===================================================================
--- tags/google_release_of_0x20_firmware/doc/Dongle_II_wishlist.odt (nonexistent)
+++ tags/google_release_of_0x20_firmware/doc/Dongle_II_wishlist.odt (revision 3)
tags/google_release_of_0x20_firmware/doc/Dongle_II_wishlist.odt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/doc/SPI_ROM_Register_description.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/doc/SPI_ROM_Register_description.odt
===================================================================
--- tags/google_release_of_0x20_firmware/doc/SPI_ROM_Register_description.odt (nonexistent)
+++ tags/google_release_of_0x20_firmware/doc/SPI_ROM_Register_description.odt (revision 3)
tags/google_release_of_0x20_firmware/doc/SPI_ROM_Register_description.odt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/doc/dongle_II_v20_datasheet_ver1_03.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/doc/dongle_II_v20_datasheet_ver1_03.odt
===================================================================
--- tags/google_release_of_0x20_firmware/doc/dongle_II_v20_datasheet_ver1_03.odt (nonexistent)
+++ tags/google_release_of_0x20_firmware/doc/dongle_II_v20_datasheet_ver1_03.odt (revision 3)
tags/google_release_of_0x20_firmware/doc/dongle_II_v20_datasheet_ver1_03.odt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/doc/dongle_board_base.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/doc/dongle_board_base.png
===================================================================
--- tags/google_release_of_0x20_firmware/doc/dongle_board_base.png (nonexistent)
+++ tags/google_release_of_0x20_firmware/doc/dongle_board_base.png (revision 3)
tags/google_release_of_0x20_firmware/doc/dongle_board_base.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/doc/dongle_board_base.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/doc/dongle_board_base.odt
===================================================================
--- tags/google_release_of_0x20_firmware/doc/dongle_board_base.odt (nonexistent)
+++ tags/google_release_of_0x20_firmware/doc/dongle_board_base.odt (revision 3)
tags/google_release_of_0x20_firmware/doc/dongle_board_base.odt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/src/lpc_proto/lpc_byte.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/lpc_proto/lpc_byte.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/lpc_proto/lpc_byte.vhd (revision 3)
@@ -0,0 +1,303 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity lpc_iow is
+ port (
+ --system signals
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ lena_reads : in std_logic; --enable read capabilities
+ --LPC bus from host
+ lad_i : in std_logic_vector(3 downto 0);
+ lad_o : out std_logic_vector(3 downto 0);
+ lad_oe : out std_logic;
+ lframe_n : in std_logic;
+ --memory interface
+ lpc_addr : out std_logic_vector(23 downto 0); --shared address
+ lpc_wr : out std_logic; --shared write not read
+ lpc_data_i : in std_logic_vector(7 downto 0);
+ lpc_data_o : out std_logic_vector(7 downto 0);
+ lpc_val : out std_logic;
+ lpc_ack : in std_logic
+ );
+end lpc_iow;
+
+architecture rtl of lpc_iow is
+type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
+type cycle is (LPC_IO_W,LPC_MEM_R,LPC_FW_R); -- simple LPC bus cycle types
+
+signal CS : state;
+signal r_lad : std_logic_vector(3 downto 0);
+signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
+ --adress 23 bits on flash
+signal r_data : std_logic_vector(7 downto 0);
+signal r_cnt : std_logic_vector(2 downto 0);
+signal cycle_type : cycle;
+--signal r_fw_msize : std_logic_vector(3 downto 0);
+
+
+signal data_valid : std_logic;
+
+signal lad_rising_o : std_logic_vector(3 downto 0);
+signal lad_rising_oe : std_logic;
+
+constant START_FW_READ : std_logic_vector(3 downto 0):="1101";
+constant START_LPC : std_logic_vector(3 downto 0):="0000";
+constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0):="0000"; --0000 is boot device on ThinCan
+constant MSIZE_FW_1B : std_logic_vector(3 downto 0):="0000"; --0000 is 1 byte read
+constant SYNC_OK : std_logic_vector(3 downto 0):="0000"; --sync done
+constant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the bus
+constant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the bus
+constant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave
+
+
+
+
+begin -- rtl
+
+lad_o<= lad_rising_o;
+lad_oe <= lad_rising_oe;
+
+
+
+--Pass the whole LPC address to the system
+lpc_addr <= r_addr(23 downto 0);
+lpc_data_o<= r_data;
+
+
+
+
+-- purpose: LPC IO write/LPC MEM read/LPC FW read handler
+-- type : sequential
+-- inputs : lclk, lreset_n
+-- outputs:
+LPC: process (lclk, lreset_n)
+begin -- process LPC
+ if lreset_n = '0' then -- asynchronous reset (active low)
+ CS<= RESETs;
+ lad_rising_oe<='0';
+ data_valid <='1';
+ lad_rising_o<="0000";
+ lpc_val <='0';
+ lpc_wr <='0';
+ r_lad <= (others=>'0');
+ cycle_type <= LPC_IO_W; --initial value
+ r_addr <= (others=>'0');
+ r_cnt <= (others=>'0');
+ elsif lclk'event and lclk = '1' then -- rising clock edge
+ case CS is
+ when RESETs => ----------------------------------------------------------
+ lpc_wr <='0';
+ lpc_val <='0';
+ if lframe_n='0' then
+ CS <= STARTs;
+ r_lad <= lad_i;
+ else
+ CS <= RESETs;
+ end if;
+ when STARTs => ----------------------------------------------------------
+ if lframe_n = '0' then
+ r_lad <= lad_i; -- latch lad state for next cycle
+ CS <= STARTs;
+ elsif r_lad = START_LPC then
+ --must identify CYCTYPE
+ if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
+ --next 4 states must be address states
+ CS<=ADDRs;
+ cycle_type <= LPC_IO_W;
+ r_cnt <= "000";
+ elsif lad_i(3 downto 1)="010" and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
+ CS<=ADDRs;
+ cycle_type <= LPC_MEM_R;
+ r_cnt <= "000";
+ else
+ CS<= RESETs;
+ end if;
+ elsif r_lad = START_FW_READ then --FW READ is always allowed
+ if lad_i = IDSEL_FW_BOOT and lena_reads='1' then
+ CS<=ADDRs;
+ cycle_type <= LPC_FW_R;
+ r_cnt <= "000";
+ else
+ CS<= RESETs;
+ end if;
+ end if;
+ when ADDRs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ if r_cnt ="011" then
+ if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
+ r_addr<= r_addr(27 downto 0)&lad_i;
+ r_cnt <= "000";
+ CS<=DATAs;
+ elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then --for debug switch
+ r_addr<= r_addr(27 downto 0)&lad_i;
+ r_cnt <= "000";
+ CS<=DATAs;
+ else
+ --not for this device
+ CS<=RESETs;
+ end if;
+ else
+ r_addr<= r_addr(27 downto 0)&lad_i;
+ r_cnt<=r_cnt + 1;
+ CS<=ADDRs;
+ end if;
+ when LPC_MEM_R => --Memory read cycle
+ if r_cnt ="111" then
+ r_addr<= r_addr(27 downto 0)&lad_i;
+ r_cnt <= "000";
+ lpc_wr <='0'; --memory read mus accure
+ lpc_val <='1';
+ data_valid <='0';
+ CS<=TARs;
+ else
+ r_addr<= r_addr(27 downto 0)&lad_i;
+ r_cnt<=r_cnt + 1;
+ CS<=ADDRs;
+ end if;
+ when LPC_FW_R => --Firmware read
+ if r_cnt ="111" then
+ --r_fw_msize <= lad_i; --8'th cycle on FW read is mem size
+ r_cnt <= "000";
+ lpc_wr <='0'; --memory read must accure
+ lpc_val <='1';
+ data_valid <='0';
+ if lad_i = MSIZE_FW_1B then
+ CS<=TARs;
+ else
+ --over byte fw read not supported
+ CS<=RESETs;
+ end if;
+ else
+ r_addr<= r_addr(27 downto 0)&lad_i; --28 bit address is given
+ r_cnt<=r_cnt + 1;
+ CS<=ADDRs;
+ end if;
+
+ when others => null;
+ end case;
+ when DATAs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ if r_cnt ="001" then
+ r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
+ r_cnt <= "000";
+ lpc_wr <='1'; --IO write must accure
+ lpc_val <='1';
+ CS <= TARs;
+ else
+ r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
+ r_cnt<=r_cnt + 1;
+ CS <= DATAs;
+ end if;
+ when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
+ if r_cnt ="001" then
+ lad_rising_o<= r_data(7 downto 4);
+ r_cnt <= "000";
+ CS <= LOCAL_TARs;
+ else
+ lad_rising_o<= r_data(3 downto 0);
+ r_cnt<=r_cnt + 1;
+ CS <= DATAs;
+ end if;
+ when others => null;
+ end case;
+ when TARs => ------------------------------------------------------------
+ if cycle_type /= LPC_IO_W and lpc_ack='1' and r_cnt ="001" then --if mem_read or fr_read
+ r_data <= lpc_data_i;
+ lpc_val <='0';
+ data_valid <='1';
+ CS<= SYNCs;
+ r_cnt <= "000";
+ elsif lpc_ack='1' and r_cnt ="001" then
+ lad_rising_o<=SYNC_OK; --added to avoid trouble as SYNC is OK allready
+ lpc_val <='0';
+ CS<= SYNCs;
+ r_cnt <= "000";
+ end if;
+
+ if r_cnt ="001" then
+ if lpc_ack='0' then
+ lad_rising_o <= SYNC_LWAIT; --added to avoid trouble
+ end if;
+ lad_rising_oe<='1';
+ elsif lad_i = TAR_OK then
+ r_cnt<=r_cnt + 1;
+ --lad_rising_oe<='1'; --BUG fix by LPC stanard TAR cycle part 2 must be tri-stated by host and device
+ lad_rising_o <= TAR_OK; --drive to F on the bus
+ CS <= TARs;
+ else
+ CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
+ end if;
+ when SYNCs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ -- just passing r_lad on bus again
+ lad_rising_o<= TAR_OK;
+ CS <= LOCAL_TARs;
+ when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
+ if data_valid ='1' then
+ lad_rising_o<=SYNC_OK;
+ CS <= DATAs;
+ else
+ if lpc_ack='1' then
+ r_data <= lpc_data_i;
+ data_valid <= '1';
+ lad_rising_o<=SYNC_OK; --SYNC ok now
+ lpc_val <='0';
+ CS <= DATAs;
+ end if;
+ end if;
+ when others => null;
+ end case;
+ when LOCAL_TARs => ------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ lpc_wr <='0';
+ lad_rising_oe <='0';
+ CS <= RESETs;
+ when LPC_MEM_R | LPC_FW_R => --Memory read cycle
+ if r_cnt ="000" then
+ lad_rising_o<= TAR_OK;
+ r_cnt <= r_cnt + 1;
+ else
+ lad_rising_oe <= '0';
+ r_cnt <="000";
+ CS <= RESETs;
+ end if;
+ when others => null;
+ end case;
+ end case; -----------------------------------------------------------------
+ end if;
+end process LPC;
+
+end rtl;
Index: tags/google_release_of_0x20_firmware/src/led_sys/byte_scan_mux.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/led_sys/byte_scan_mux.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/led_sys/byte_scan_mux.vhd (revision 3)
@@ -0,0 +1,111 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+-- Select signal order
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- sel(3) sel(2) sel(1) sel(0)
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity byte_scan is
+ port (
+ clk : in std_logic;
+ hi_seg_1 : in std_logic_vector(7 downto 0);
+ lo_seg_1 : in std_logic_vector(7 downto 0);
+ hi_seg_0 : in std_logic_vector(7 downto 0);
+ lo_seg_0 : in std_logic_vector(7 downto 0);
+ seg_out : out std_logic_vector(7 downto 0);
+ sel_out : out std_logic_vector(3 downto 0)
+ );
+end byte_scan;
+
+architecture rtl of byte_scan is
+
+signal sel_p : std_logic_vector(3 downto 0);
+signal count : std_logic_vector(1 downto 0):="00";
+signal hi_seg_1_3 : std_logic_vector(7 downto 0);
+signal lo_seg_1_3 : std_logic_vector(7 downto 0);
+signal hi_seg_0_2 : std_logic_vector(7 downto 0);
+signal lo_seg_0_2 : std_logic_vector(7 downto 0);
+
+begin -- rtl
+
+
+hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
+lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
+hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
+lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
+
+
+seg_out <=hi_seg_1_3 when count="01" else
+ lo_seg_1_3 when count="10" else
+ hi_seg_0_2 when count="11" else
+ lo_seg_0_2 when count="00";
+
+sel_out <= not sel_p;
+
+sel_p <= "1110" when count="00" else
+ "0111" when count="01" else
+ "1011" when count="10" else
+ "1101" when count="11";
+
+
+
+
+process (clk) --enable the scanning while in reset (simulation will be incorrect)
+begin -- process
+ if clk'event and clk = '1' then -- rising clock edge
+ count <= count + 1;
+ end if;
+end process;
+
+end rtl;
Index: tags/google_release_of_0x20_firmware/src/led_sys/led_coder.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/led_sys/led_coder.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/led_sys/led_coder.vhd (revision 3)
@@ -0,0 +1,112 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity led_coder is
+ port (
+ led_data_i : in std_logic_vector(7 downto 0);
+ hi_seg : out std_logic_vector(7 downto 0);
+ lo_seg : out std_logic_vector(7 downto 0)
+ );
+end led_coder;
+
+architecture rtl of led_coder is
+signal r_led_data : std_logic_vector(7 downto 0);
+signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0);
+
+begin -- rtl
+hi_seg <= not decoded_hi;
+lo_seg <= not decoded_lo;
+
+ -- purpose: binary to led segments decoder
+ -- type : combinational
+ -- inputs : nibble,reset
+ -- outputs:
+ decode_nibble_lo: process (led_data_i)
+ begin -- process decode_nibble
+ case led_data_i(3 downto 0) is--HGFEDCBA
+ when "0000" => decoded_lo <= "00111111"; -- 0
+ when "0001" => decoded_lo <= "00000110"; -- 1
+ when "0010" => decoded_lo <= "01011011"; -- 2
+ when "0011" => decoded_lo <= "01001111"; -- 3
+ when "0100" => decoded_lo <= "01100110"; -- 4
+ when "0101" => decoded_lo <= "01101101"; -- 5
+ when "0110" => decoded_lo <= "01111101"; -- 6
+ when "0111" => decoded_lo <= "00000111"; -- 7
+ when "1000" => decoded_lo <= "01111111"; -- 8
+ when "1001" => decoded_lo <= "01101111"; -- 9
+ when "1010" => decoded_lo <= "01110111"; -- a
+ when "1011" => decoded_lo <= "01111100"; -- b
+ when "1100" => decoded_lo <= "00111001"; -- c
+ when "1101" => decoded_lo <= "01011110"; -- d
+ when "1110" => decoded_lo <= "01111001"; -- e
+ when others => decoded_lo <= "01110001"; -- f
+ end case;
+ end process decode_nibble_lo;
+
+ decode_nibble_hi: process (led_data_i)
+ begin -- process decode_nibble
+ case led_data_i(7 downto 4) is--HGFEDCBA
+ when "0000" => decoded_hi <= "00111111"; -- 0
+ when "0001" => decoded_hi <= "00000110"; -- 1
+ when "0010" => decoded_hi <= "01011011"; -- 2
+ when "0011" => decoded_hi <= "01001111"; -- 3
+ when "0100" => decoded_hi <= "01100110"; -- 4
+ when "0101" => decoded_hi <= "01101101"; -- 5
+ when "0110" => decoded_hi <= "01111101"; -- 6
+ when "0111" => decoded_hi <= "00000111"; -- 7
+ when "1000" => decoded_hi <= "01111111"; -- 8
+ when "1001" => decoded_hi <= "01101111"; -- 9
+ when "1010" => decoded_hi <= "01110111"; -- a
+ when "1011" => decoded_hi <= "01111100"; -- b
+ when "1100" => decoded_hi <= "00111001"; -- c
+ when "1101" => decoded_hi <= "01011110"; -- d
+ when "1110" => decoded_hi <= "01111001"; -- e
+ when others => decoded_hi <= "01110001"; -- f
+ end case;
+ end process decode_nibble_hi;
+
+
+end rtl;
Index: tags/google_release_of_0x20_firmware/src/led_sys/led_sys.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/led_sys/led_sys.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/led_sys/led_sys.vhd (revision 3)
@@ -0,0 +1,169 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+-- Select signal order
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- sel(3) sel(2) sel(1) sel(0)
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity led_sys is --toplevel for led system
+ generic(
+ msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
+ msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
+ );
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ led_data_i : in std_logic_vector(15 downto 0); --binary data in
+ seg_out : out std_logic_vector(7 downto 0); --one segment out
+ sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+end led_sys;
+
+architecture rtl of led_sys is
+
+component led_coder
+ port (
+ led_data_i : in std_logic_vector(7 downto 0);
+ hi_seg : out std_logic_vector(7 downto 0);
+ lo_seg : out std_logic_vector(7 downto 0)
+ );
+end component;
+
+component byte_scan
+ port (
+ clk : in std_logic;
+ hi_seg_1 : in std_logic_vector(7 downto 0);
+ lo_seg_1 : in std_logic_vector(7 downto 0);
+ hi_seg_0 : in std_logic_vector(7 downto 0);
+ lo_seg_0 : in std_logic_vector(7 downto 0);
+ seg_out : out std_logic_vector(7 downto 0);
+ sel_out : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+
+-- input signals
+signal hi_seg1 : std_logic_vector(7 downto 0);
+signal lo_seg1 : std_logic_vector(7 downto 0);
+signal hi_seg0 : std_logic_vector(7 downto 0);
+signal lo_seg0 : std_logic_vector(7 downto 0);
+
+--data containing signals
+signal data_hi_seg1 : std_logic_vector(7 downto 0);
+signal data_lo_seg1 : std_logic_vector(7 downto 0);
+signal data_hi_seg0 : std_logic_vector(7 downto 0);
+signal data_lo_seg0 : std_logic_vector(7 downto 0);
+
+--constant display
+signal cons_hi_seg1 : std_logic_vector(7 downto 0);
+signal cons_lo_seg1 : std_logic_vector(7 downto 0);
+signal cons_hi_seg0 : std_logic_vector(7 downto 0);
+signal cons_lo_seg0 : std_logic_vector(7 downto 0);
+
+signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
+
+begin -- rtl
+---------------------------HGFEDCBA
+cons_hi_seg1 <= msn_hib;--"01111111"; --8
+cons_lo_seg1 <= lsn_hib;--"01111101"; --6
+cons_hi_seg0 <= msn_lob;--"01011100"; -- small o
+cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o
+
+
+
+
+process (clk) --enable the scanning while in reset
+begin -- process
+ if clk'event and clk = '0' then -- rising clock edge
+ disp_cnt <= disp_cnt + 1;
+ end if;
+end process;
+
+LED_CODE0: led_coder
+ port map(
+ led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0);
+ hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0);
+ lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0)
+ );
+
+LED_CODE1: led_coder
+ port map(
+ led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0);
+ hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0);
+ lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0)
+ );
+
+
+lo_seg1 <= data_lo_seg1; --when reset_n='1' else cons_hi_seg1;
+hi_seg1 <= data_hi_seg1; --when reset_n='1' else cons_lo_seg1;
+
+lo_seg0 <= data_lo_seg0; --when reset_n='1' else cons_hi_seg0;
+hi_seg0 <= data_hi_seg0; --when reset_n='1' else cons_lo_seg0;
+
+SCAN : byte_scan
+ port map(
+ clk => disp_cnt(15), -- in std_logic;
+ hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0);
+ lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0);
+ hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0);
+ lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0);
+ seg_out => seg_out, -- out std_logic_vector(7 downto 0);
+ sel_out => sel_out -- out std_logic_vector(3 downto 0)
+ );
+
+
+
+
+end rtl;
Index: tags/google_release_of_0x20_firmware/src/spi_eeprom/spi_master.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/spi_eeprom/spi_master.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/spi_eeprom/spi_master.vhd (revision 3)
@@ -0,0 +1,147 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2008 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity spi_if is
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ --------------------------
+ -- EEPROM signals
+ ee_do : out std_logic;
+ ee_di : in std_logic;
+ ee_hold_n : out std_logic;
+ ee_cs_n : out std_logic;
+ ee_clk : out std_logic;
+ ee_wrp_n : out std_logic; --write protect signal active low
+ -- Mem bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+
+ );
+end spi_if;
+
+
+architecture RTL of spi_if is
+ type state_type is (RESETs,SPI_CYCLEs,WAITs);
+ signal CS : state_type;
+
+ signal spi_cnt : std_logic_vector(4 downto 0);
+ signal spi_shiftr : std_logic_vector(0 to 23);
+ signal spi_wren_done : std_logic;
+
+
+ constant SPI_READ : std_logic_vector(0 to 2):="011";
+ constant SPI_WRITE : std_logic_vector(0 to 2):="010";
+ constant SPI_SET_WEN : std_logic_vector(0 to 2):="110";
+ constant SPI_CLR_WEN : std_logic_vector(0 to 2):="100";
+
+
+begin
+
+
+ee_do <= spi_shiftr(0);
+
+SPI_SM: process (clk, reset_n)
+begin -- process READ
+ if reset_n='0' then
+ ee_cs_n <='1';
+ CS <= RESETs;
+ ee_clk <='0';
+ ee_wrp_n <='1'; --active low write protect
+ ee_hold_n <='1';
+ spi_wren_done <='0';
+ spi_cnt <=(others=>'0');
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case CS is
+ when RESETs =>
+ mem_ack <='0';
+ ee_cs_n <= (not mem_val); --chipselect 4 spi
+ fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
+ if spi_wren_done ='0' then
+ spi_cnt <= "01111"; --only 8 bit command needs to be sent
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= '0';
+ spi_shiftr(5 to 7) <= SPI_SET_WEN;
+ CS <= SPI_CYCLEs;
+ elsif mem_val='1' and mem_wr = '0' then --READ
+ spi_cnt <=(others=>'0');
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= mem_addr(8);
+ spi_shiftr(5 to 7) <= SPI_READ;
+ spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
+ CS <= SPI_CYCLEs;
+ elsif mem_val='1' and mem_wr = '1' then --WRITE
+ spi_cnt <=(others=>'0');
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= mem_addr(8);
+ spi_shiftr(5 to 7) <= SPI_WRITE;
+ spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
+ spi_shiftr(16 to 23) <= mem_di(7 downto 0);
+ CS <= SPI_CYCLEs;
+ end if; --elsif mem_cmd
+ when SPI_CYCLEs =>
+ if spi_cnt < 24 then
+ ee_clk <= not ee_clk;
+ elsif
+ mem_do <= x"00"&spi_shiftr(16 to 23); --this may be done always as this is don't care to all but read
+ ee_clk <= '0';
+ if spi_wren_done ='0' then
+ spi_wren_done <='1';
+ CS <= RESETs;
+ else
+ mem_ack <='1';
+ CS <= WAITs;
+ end if;
+ end if;
+
+ if ee_clk='1' then
+ spi_shiftr <= spi_shiftr(1 to 23)&ee_di;
+ spi_cnt <= spi_cnt + 1;
+ end if;
+ when WAITs =>
+ if mem_val='0' then -- wait untill val is removed
+ mem_ack <='0';
+ CS <= RESETs;
+ end if;
+
+ end case;
+
+ end if; --system
+end process SPI_SM;
+
+
+
+
+end RTL;
\ No newline at end of file
Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_waveforms.html
===================================================================
--- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_waveforms.html (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_waveforms.html (revision 3)
@@ -0,0 +1,13 @@
+
+
+Sample Waveforms for fifo.vhd
+
+
+
+
Fig. 1 : Wave showing read and write operation.
+
Sample behavioral waveforms for design file fifo.vhd
+The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design fifo.vhd. The design fifo.vhd has a depth of 8192 words of 8 bits each. The output of the fifo is registered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.
+ The above waveform shows the behavior of the design under normal read and write conditions with aclr .
+ + + Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_inst.vhd =================================================================== --- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_inst.vhd (nonexistent) +++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_inst.vhd (revision 3) @@ -0,0 +1,12 @@ +fifo_inst : fifo PORT MAP ( + aclr => aclr_sig, + clock => clock_sig, + data => data_sig, + rdreq => rdreq_sig, + wrreq => wrreq_sig, + almost_full => almost_full_sig, + empty => empty_sig, + full => full_sig, + q => q_sig, + usedw => usedw_sig + ); Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.cmp =================================================================== --- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.cmp (nonexistent) +++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.cmp (revision 3) @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_full : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) + ); +end component; Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.vhd =================================================================== --- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.vhd (nonexistent) +++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.vhd (revision 3) @@ -0,0 +1,201 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: scfifo + +-- ============================================================ +-- File Name: fifo.vhd +-- Megafunction Name(s): +-- scfifo +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY fifo IS + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_full : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) + ); +END fifo; + + +ARCHITECTURE SYN OF fifo IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + almost_full_value : NATURAL; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + almost_full : OUT STD_LOGIC ; + usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); + rdreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + full : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + almost_full <= sub_wire0; + usedw <= sub_wire1(12 DOWNTO 0); + empty <= sub_wire2; + q <= sub_wire3(7 DOWNTO 0); + full <= sub_wire4; + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "ON", + almost_full_value => 8000, + intended_device_family => "Cyclone", + lpm_numwords => 8192, + lpm_showahead => "OFF", + lpm_type => "scfifo", + lpm_width => 8, + lpm_widthu => 13, + overflow_checking => "ON", + underflow_checking => "ON", + use_eab => "ON" + ) + PORT MAP ( + rdreq => rdreq, + aclr => aclr, + clock => clock, + wrreq => wrreq, + data => data, + almost_full => sub_wire0, + usedw => sub_wire1, + empty => sub_wire2, + q => sub_wire3, + full => sub_wire4 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "8000" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "8192" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "1" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON" +-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "8000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0] +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +-- Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0 +-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_wave0.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_wave0.jpg =================================================================== --- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_wave0.jpg (nonexistent) +++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_wave0.jpg (revision 3)
tags/google_release_of_0x20_firmware/src/postcode_ser/fifo_wave0.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/src/postcode_ser/Thumbs.db
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/google_release_of_0x20_firmware/src/postcode_ser/Thumbs.db
===================================================================
--- tags/google_release_of_0x20_firmware/src/postcode_ser/Thumbs.db (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/postcode_ser/Thumbs.db (revision 3)
tags/google_release_of_0x20_firmware/src/postcode_ser/Thumbs.db
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/google_release_of_0x20_firmware/src/postcode_ser/pc_serializer.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/postcode_ser/pc_serializer.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/postcode_ser/pc_serializer.vhd (revision 3)
@@ -0,0 +1,327 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+
+----------------------------------------------------------------------------------
+-- Company: ArtecDesign
+-- Engineer: Jüri Toomessoo
+--
+-- Create Date: 12:57:23 28/02/2008
+-- Design Name: Postcode serial pipe Hardware
+-- Module Name: pc_serializer - rtl
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pc_serializer is
+ Port ( --system signals
+ sys_clk : in STD_LOGIC;
+ resetn : in STD_LOGIC;
+ --postcode data port
+ dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
+ dbg_wr : in STD_LOGIC; --write not read
+ dbg_full : out STD_LOGIC; --write not read
+ dbg_almost_full : out STD_LOGIC;
+ dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
+ --debug USB port
+ dbg_usb_mode_en: in std_logic; -- enable this debug mode
+ dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
+);
+
+end pc_serializer;
+
+architecture rtl of pc_serializer is
+
+ component fifo
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
+
+ );
+ end component;
+
+
+
+ --type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
+ signal CS : std_logic_vector(8 downto 0);--state;
+ signal RETS : std_logic_vector(8 downto 0); --state;
+ signal next_char : std_logic_vector(7 downto 0); --bus data
+ signal ascii_char : std_logic_vector(7 downto 0); --bus data
+ signal in_nibble : std_logic_vector(3 downto 0); --bus data
+ signal usb_send_char : std_logic_vector(7 downto 0); --bus data
+
+ signal count : std_logic_vector(3 downto 0); --internal counter
+ signal dly_count : std_logic_vector(15 downto 0); --internal counter
+ signal dbg_wr_pulse : std_logic; --active reset
+ signal dbg_wrd : std_logic; --active reset
+ signal dbg_wr_len : std_logic; --active reset
+ signal usb_send : std_logic; --active reset
+
+
+ signal rdreq_sig : std_logic; --active reset
+ signal empty_sig : std_logic; --active reset
+ signal full_sig : std_logic; --active reset
+ signal almost_full : std_logic; --active reset
+
+ signal q_sig : std_logic_vector(7 downto 0); --bus data
+
+ signal reset : std_logic; --active reset
+ signal half_clk : std_logic; --active reset
+
+
+ --RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
+ constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n
+ constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n
+ constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n
+ constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n
+ constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n
+ constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n
+ constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n
+ constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n
+ constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n
+
+
+ constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n
+ constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n
+ constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space
+ constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x
+ constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker
+ constant CHAR_0 : std_logic_vector(7 downto 0):= x"30";
+ constant CHAR_1 : std_logic_vector(7 downto 0):= x"31";
+ constant CHAR_2 : std_logic_vector(7 downto 0):= x"32";
+ constant CHAR_3 : std_logic_vector(7 downto 0):= x"33";
+ constant CHAR_4 : std_logic_vector(7 downto 0):= x"34";
+ constant CHAR_5 : std_logic_vector(7 downto 0):= x"35";
+ constant CHAR_6 : std_logic_vector(7 downto 0):= x"36";
+ constant CHAR_7 : std_logic_vector(7 downto 0):= x"37";
+ constant CHAR_8 : std_logic_vector(7 downto 0):= x"38";
+ constant CHAR_9 : std_logic_vector(7 downto 0):= x"39";
+ constant CHAR_a : std_logic_vector(7 downto 0):= x"41";
+ constant CHAR_b : std_logic_vector(7 downto 0):= x"42";
+ constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
+ constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
+ constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
+ constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
+
+
+
+begin
+
+ ascii_char <=CHAR_0 when in_nibble = x"0" else
+ CHAR_1 when in_nibble = x"1" else
+ CHAR_2 when in_nibble = x"2" else
+ CHAR_3 when in_nibble = x"3" else
+ CHAR_4 when in_nibble = x"4" else
+ CHAR_5 when in_nibble = x"5" else
+ CHAR_6 when in_nibble = x"6" else
+ CHAR_7 when in_nibble = x"7" else
+ CHAR_8 when in_nibble = x"8" else
+ CHAR_9 when in_nibble = x"9" else
+ CHAR_a when in_nibble = x"a" else
+ CHAR_b when in_nibble = x"b" else
+ CHAR_c when in_nibble = x"c" else
+ CHAR_d when in_nibble = x"d" else
+ CHAR_e when in_nibble = x"e" else
+ CHAR_f when in_nibble = x"f";
+
+
+
+ dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
+ (others=>'Z');
+
+ dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
+ 'Z';
+
+ SER_SM: process (sys_clk,resetn)
+ begin -- process
+
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn='0' then --active low reset
+ CS<= RESETs;
+ in_nibble <= (others=>'0');
+ usb_send_char <= (others=>'0');
+ dly_count<= (others=>'0');
+ usb_send <='0';
+ RETS <= RESETs;
+ rdreq_sig <='0';
+ count<= (others=>'1');
+ else
+ case CS is
+ when RESETs => ----------------------------------------------------------
+
+ if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send
+ rdreq_sig <='1';
+ count <= count + 1;
+ RETS <= HEXMARKs;
+ dly_count <= x"000F";
+ CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
+ else
+ usb_send <='0';
+ rdreq_sig <='0';
+ CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
+ end if;
+ when HEXMARKs => ----------------------------------------------------------
+ rdreq_sig <='0'; --data will be ready on output 'till next read request
+ --if almost_full='0' then
+ usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
+ --else
+ -- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
+ --end if;
+ in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
+ RETS <= MSNIBBLEs;
+ CS <= START_WRITEs;
+ when MSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
+ RETS <= LSNIBBLEs;
+ CS <= START_WRITEs;
+ when LSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ if count = x"f" then
+ RETS <= CRs;
+ else
+ RETS <= LINEFDs;
+ end if;
+ CS <= START_WRITEs;
+ when CRs => ----------------------------------------------------------
+ --if count = x"f" then
+ usb_send_char <= CHAR_CR; --put line feed
+ --else
+ -- usb_send_char <= CHAR_SP; --put space
+ --end if;
+ RETS <= LINEFDs;
+ CS <= START_WRITEs;
+ when LINEFDs => ----------------------------------------------------------
+ if count = x"f" then
+ usb_send_char <= CHAR_LF; --put line feed
+ else
+ usb_send_char <= CHAR_SP; --put space
+ end if;
+ RETS <= RESETs;
+ CS <= START_WRITEs;
+
+ when START_WRITEs => ----------------------------------------------------------
+ if dly_count /= x"0004" then
+ if dbg_usb_txe_n='0' then
+ usb_send <='1';
+ dly_count <= dly_count + 1;
+ else
+ usb_send <='0'; --remove send signal when txe is falsely asserted
+ end if;
+ else
+ usb_send <='0';
+ CS <= WAITs;
+ end if;
+ when WAITs => ----------------------------------------------------------
+ usb_send <='0';
+ CS <= END_WRITEs;
+ when END_WRITEs => ----------------------------------------------------------
+ rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets
+ if dly_count /= x"000F" then
+ if dbg_usb_txe_n='0' then
+ dly_count <= dly_count + 1;
+ end if;
+ else
+ dly_count <= (others=>'0');
+ CS <= RETS;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process SER_SM;
+
+
+ SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
+ begin -- process
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn='0' then --active low reset
+ dbg_wr_pulse <='0';
+ dbg_wr_len <='0';
+ dbg_wrd <='0';
+ else
+ dbg_wrd <= dbg_wr;
+ if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
+ dbg_wr_pulse <='1';
+ else
+ dbg_wr_pulse <='0';
+ end if;
+ end if;
+ end if;
+ end process SYNCER;
+
+
+ reset <= not resetn;
+ dbg_full <= full_sig;
+ dbg_almost_full<= almost_full;
+ fifo_inst : fifo PORT MAP (
+ --system signals
+ aclr => reset,
+ clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
+ -- push interface
+ data => dbg_data,
+ wrreq => dbg_wr_pulse,
+ almost_full => almost_full,
+ usedw => dbg_usedw,
+ --pop interface
+ rdreq => rdreq_sig,
+ empty => empty_sig,
+ full => full_sig,
+ q => q_sig
+ );
+
+
+
+
+end rtl;
+
Index: tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.bsf
===================================================================
--- tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.bsf (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/postcode_ser/fifo.bsf (revision 3)
@@ -0,0 +1,107 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 160)
+ (text "fifo" (rect 72 1 90 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 144 25 156)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+ (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 160 32)
+ (output)
+ (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8)))
+ (line (pt 160 32)(pt 144 32)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+ (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 1))
+ )
+ (port
+ (pt 160 88)
+ (output)
+ (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
+ (line (pt 160 88)(pt 144 88)(line_width 1))
+ )
+ (port
+ (pt 160 104)
+ (output)
+ (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+ (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8)))
+ (line (pt 160 104)(pt 144 104)(line_width 3))
+ )
+ (drawing
+ (text "8 bits x 8192 words" (rect 63 132 144 144)(font "Arial" ))
+ (text "almost_full at 8000" (rect 64 122 144 134)(font "Arial" ))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 144)(line_width 1))
+ (line (pt 144 144)(pt 16 144)(line_width 1))
+ (line (pt 16 144)(pt 16 16)(line_width 1))
+ (line (pt 16 116)(pt 144 116)(line_width 1))
+ (line (pt 16 90)(pt 22 96)(line_width 1))
+ (line (pt 22 96)(pt 16 102)(line_width 1))
+ )
+)
Index: tags/google_release_of_0x20_firmware/src/usb/usb2mem.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/usb/usb2mem.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/usb/usb2mem.vhd (revision 3)
@@ -0,0 +1,424 @@
+--COMMAND STRUCTURE OF SERAL USB PROTOCOL
+
+-- MSBYTE LSBYTE
+
+-- DATA CODE
+
+--Dongle internal command codes
+-- 0x00 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
+-- 0x01 0xC5 --Get Dongle version code
+-- 0x02 0xC5 --PCB version code
+-- 0x03 0xC5 --Get Mode switch setting
+
+-- 0xC1 0xC5 --Release memeory interface to LPC
+-- 0xC2 0xC5 --Put the device in USB programming mode (pulldown buf_en)
+-- 0xC3 0xC5 --Force the dongle to indicate it's disconnected
+-- 0xC4 0xC5 --Force the dongle to indicate it's connected
+
+-- 0xC5 0xC5 --Force the dongle to lock memory interface
+-- 0xC6 0xC5 --Force the dongle to unlock memory interface
+
+-- 0x-- 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
+
+
+-- 0xNN 0xCD --Get Data from flash (performs read from current address) NN count of words auto increment address
+-- 0xAA 0xA0 --Addr LSByte write
+-- 0xAA 0xA1 --Addr Byte write
+-- 0xAA 0xA2 --Addr MSByte write
+-- 0x-- 0x3F --NOP
+
+--Flash operations codes
+-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0x-- 0xD0 -- 0xD0 is flash confirm command
+
+--PSRAM operations codes
+-- 0xNN 0xE9 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
+
+
+--write flash buffer sequence
+-- ??? -- set address if needed
+-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0x-- 0xNN --0xNN is word count for flash ges directly to flash and is wordCount - 1
+-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
+-- ...
+-- 0x-- 0xD0 -- 0xD0 is flash confirm command
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity usb2mem is
+ port (
+ clk25 : in std_logic;
+ reset_n : in std_logic;
+ dongle_ver: in std_logic_vector(15 downto 0);
+ pcb_ver : in std_logic_vector(15 downto 0);
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en : out std_logic;
+ dev_present_n : out std_logic;
+ -- mem Bus
+ mem_busy_n: in std_logic;
+ mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
+ mem_addr : out std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : out std_logic;
+ mem_val : out std_logic;
+ mem_ack : in std_logic;
+ mem_cmd : out std_logic;
+ -- USB port
+ usb_mode_en: in std_logic; -- enable this block
+ usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : out std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd : inout std_logic_vector(7 downto 0) --bus data
+ );
+end usb2mem;
+
+
+architecture RTL of usb2mem is
+
+
+
+
+ type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s,STS_WAITs);
+ signal CS : state_type;
+
+ signal data_reg_i : std_logic_vector(15 downto 0);
+ signal data_reg_o : std_logic_vector(15 downto 0);
+ signal data_oe : std_logic; -- rx fifo empty (data redy if low)
+ signal usb_wr_d : std_logic; -- internal readable output state for write
+ signal addr_reg: std_logic_vector(23 downto 0);
+
+ --State machine
+ signal cmd_cnt : std_logic_vector(15 downto 0);
+ signal state_cnt : std_logic_vector(3 downto 0);
+ --shyncro to USB
+ signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
+ signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
+ signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
+
+ signal read_mode : std_logic;
+ signal write_mode : std_logic;
+ signal write_count : std_logic;
+ signal first_word : std_logic;
+ signal mem_busy_nd : std_logic;
+
+
+
+begin
+
+--define internal command codes
+internal_cmd <='1' when data_reg_i(7 downto 0) = x"C5" else
+ '1' when data_reg_i(7 downto 0) = x"CD" else
+ '1' when data_reg_i(7 downto 0) = x"A0" else
+ '1' when data_reg_i(7 downto 0) = x"A1" else
+ '1' when data_reg_i(7 downto 0) = x"A2" else
+ '1' when data_reg_i(7 downto 0) = x"3F" else
+ --These are spechial attention Flash commands
+ '1' when data_reg_i(7 downto 0) = x"E8" else
+ '1' when data_reg_i(7 downto 0) = x"E9" else
+ '0';
+
+
+usb_wr <= usb_wr_d when usb_mode_en='1' else
+ 'Z';
+
+
+-- this goes to byte buffer for that reason send LSB first and MSB second
+usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
+ data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else --MSB byte second
+ (others=>'Z');
+
+
+process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
+begin -- process
+ if reset_n='0' then
+ CS <= RESETs;
+ usb_rd_n <= '1';
+ usb_wr_d <= '0';
+ usb_txe_nd <= '1';
+ usb_rxf_nd <= '1';
+ data_oe <='0';
+ state_cnt <=(others=>'0'); --init command counter
+ mem_do <= (others=>'Z');
+ mem_addr <= (others=>'Z');
+ addr_reg <= (others=>'0');
+ mem_val <= '0';
+ mem_wr <='0';
+ mem_cmd <='0';
+ cmd_cnt <= (others=>'0');
+ read_mode <='0';
+ write_mode <='0';
+ write_count <='0';
+ first_word <='0';
+ mem_idle <='1'; --set idle
+ mem_busy_nd <='1';
+ usb_buf_en <='1'; -- default mode (USB prog disabled, buffer with HiZ outputs)
+ dev_present_n <='0'; --indicate that device is present on LPC bus for thincans
+ elsif clk25'event and clk25 = '1' then -- rising clock edge
+ usb_txe_nd <= usb_txe_n; --syncronize
+ usb_rxf_nd <= usb_rxf_n; --syncronize
+ mem_busy_nd <=mem_busy_n; --syncronize
+ case CS is
+ when RESETs =>
+ if usb_rxf_nd='0' and usb_mode_en='1' and mem_busy_nd='1' then
+ state_cnt <=(others=>'0'); --init command counter
+ data_oe <='0'; --we will read command in
+ --mem_idle <='0'; --set busy untill return here
+ CS <= RXCMD0s;
+ end if;
+ when RXCMD0s =>
+ if state_cnt="0000" then
+ usb_rd_n <='0'; -- set read low
+ state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
+ elsif state_cnt="0001" then
+ state_cnt <= state_cnt + 1;-- one wait cycle
+ elsif state_cnt="0010" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_reg_i(15 downto 8) <= usb_bd; --get data form bus MSByte must come first
+ elsif state_cnt="0011" then
+ usb_rd_n <='1'; -- set read back to high
+ state_cnt <= state_cnt + 1;-- start wait
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
+ elsif state_cnt="0101" then
+ state_cnt <= state_cnt + 1;-- wait
+ elsif state_cnt="0110" then
+ state_cnt <= state_cnt + 1;-- now is ok prob.
+ else
+ if usb_rxf_nd='0' then --wait untill next byte is available
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= RXCMD1s;
+ end if;
+ end if;
+ when RXCMD1s =>
+ if state_cnt="0000" then
+ usb_rd_n <='0'; -- set read low
+ state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
+ elsif state_cnt="0001" then
+ state_cnt <= state_cnt + 1;-- one wait cycle
+ elsif state_cnt="0010" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_reg_i(7 downto 0) <= usb_bd; --get data form bus LSByte must come last
+ elsif state_cnt="0011" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ usb_rd_n <='1'; -- set read back to high
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
+ elsif state_cnt="0101" then
+ state_cnt <= state_cnt + 1;-- wait
+ elsif state_cnt="0110" then
+ state_cnt <= state_cnt + 1;-- now is ok prob.
+ else
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= INTERNs;
+ end if;
+ when INTERNs =>
+ if cmd_cnt=x"0000" then
+ if data_reg_i(7 downto 0)=x"A0" then
+ addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"A1" then
+ addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"A2" then
+ addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"3F" then
+ CS <= RESETs; --go back to resets --NOP command
+ elsif data_reg_i(7 downto 0)=x"C5" then
+ if (data_reg_i(15 downto 8))=x"00" then
+ data_reg_o <=x"3210";
+ elsif(data_reg_i(15 downto 8))=x"01" then
+ data_reg_o <=dongle_ver;
+ elsif(data_reg_i(15 downto 8))=x"02" then
+ data_reg_o <=pcb_ver;
+ elsif(data_reg_i(15 downto 8))=x"03" then
+ data_reg_o <="0000000000000"&mode;
+ elsif(data_reg_i(15 downto 8))=x"C1" then --release flash to LPC interface
+ data_reg_o <=x"C1C5";
+ mem_idle <='1'; --set idle
+ elsif(data_reg_i(15 downto 8))=x"C2" then --force USB prog mode
+ usb_buf_en <='0';
+ data_reg_o <=x"C2C5";
+ elsif(data_reg_i(15 downto 8))=x"C3" then --fake dongle disconnect
+ data_reg_o <=x"C3C5";
+ dev_present_n <='0';
+ elsif(data_reg_i(15 downto 8))=x"C4" then --fake dongle connect
+ data_reg_o <=x"C4C5";
+ dev_present_n <='1';
+ elsif(data_reg_i(15 downto 8))=x"C5" then --fake dongle connect
+ data_reg_o <=x"C5C5";
+ mem_idle <='0'; --lock LPC out from memory interface
+ elsif(data_reg_i(15 downto 8))=x"C6" then --fake dongle connect
+ data_reg_o <=x"C6C5";
+ mem_idle <='1'; --unlock memory interface
+ else
+ data_reg_o <=x"3210"; --always return even on unknown commands
+ end if;
+ CS <= TXCMD0s;
+ elsif data_reg_i(7 downto 0)=x"CD" then
+ if (data_reg_i(15 downto 8))=x"00" then --64K word read coming
+ cmd_cnt <= (others=>'1'); --64K word count
+ else
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now (cmd_cnt words)
+ end if;
+ CS <= VCIRDs; --go perform a read
+ read_mode <='1';
+ elsif data_reg_i(7 downto 0)=x"E8" then
+ --write_mode <='1';
+ write_count <='0';
+ first_word <='0';
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
+ data_reg_i(15 downto 8)<=(others=>'0');
+ CS <= VCIWRs; --go perform a write
+ elsif data_reg_i(7 downto 0)=x"E9" then
+ write_count <='1'; --no initial command write
+ first_word <='0';
+ if (data_reg_i(15 downto 8))=x"00" then --64K word write coming
+ cmd_cnt <= (others=>'1'); --64K word count
+ else
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8);
+ end if;
+ data_reg_i(15 downto 8)<=(others=>'0');
+ CS <= RESETs; --PSRAM does not need command
+ else
+ CS <= VCIWRs;
+ end if;
+ else
+ if cmd_cnt>x"0000" then
+ cmd_cnt<= cmd_cnt - 1;
+ if write_count='0' then
+ write_count<='1';
+ elsif write_count='1' and first_word ='0' then
+ first_word <='1';
+ elsif write_count='1' and first_word ='1' then
+ addr_reg <= addr_reg + 1; --autoincrement address in in block mode
+ end if;
+ --if cmd_cnt>x"02" then --so not to increase too many times on write buffer
+ -- addr_reg <= addr_reg + 1; --autoincrement address in in block mode
+ --end if;
+ end if;
+ CS <= VCIWRs;
+ end if;
+ when VCIRDs => --flash read
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
+ mem_val <= '1';
+ if mem_ack='1' then
+ data_reg_o <= mem_di;
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_val <= '0';
+ CS <= TXCMD0s;
+ end if;
+ when VCIWRs => --flash write
+ mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
+ if mode(2)='1' then
+ --this HW swap removes the need to swap bytes in python for PSRAM region
+ mem_do <= data_reg_i(7 downto 0)&data_reg_i(15 downto 8); --SWAP data for PSRAM region
+ else
+ mem_do <= data_reg_i; --USB data in will go to mem_out
+ end if;
+ mem_wr <='1'; --this is VCI write_not_read
+ mem_cmd <='1';
+ mem_val <= '1';
+ if mem_ack='1' then
+ mem_do <= (others=>'Z');
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_val <= '0';
+ --if write_mode='0' then
+
+ if cmd_cnt=x"0000" then --if flash command and not data
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= STS_WAITs;
+ else
+ CS <= RESETs;
+ end if;
+ --else --else if was 0xE8 must read and return XSR
+ -- write_mode <='0'; --XSR return will no follow clear this bit
+ -- CS <= VCIRDs;
+ --end if;
+ end if;
+ when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
+
+ if state_cnt="0000" then
+ if usb_txe_nd='0' then
+ usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
+ state_cnt <= state_cnt + 1;-- now is ok
+ end if;
+ elsif state_cnt="0010" then
+ data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0011" then
+ usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_oe<='0';
+ elsif state_cnt="0111" then --must stay low at least 50ns
+ CS <= TXCMD1s;
+ state_cnt <= (others=>'0');
+ else
+ state_cnt <= state_cnt + 1;-- if intermediate cnt then count
+ end if;
+
+ when TXCMD1s =>
+
+ if state_cnt="0000" then
+ if usb_txe_nd='0' then
+ usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
+ state_cnt <= state_cnt + 1;-- now is ok
+ end if;
+ elsif state_cnt="0010" then
+ data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0011" then
+ usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_oe<='0';
+ elsif state_cnt="0111" then --must stay low at least 50ns
+ if read_mode='0' then
+ CS <= RESETs;
+ elsif cmd_cnt="0000" then --last word sent
+ addr_reg <= addr_reg + 1; --autoincrement address in read mode
+ read_mode <='0';
+ CS <= RESETs;
+ else
+ cmd_cnt<= cmd_cnt - 1;
+ addr_reg <= addr_reg + 1; --autoincrement address in read mode
+ CS <= VCIRDs; --more data to be read
+ end if;
+ state_cnt <= (others=>'0');
+ else
+ state_cnt <= state_cnt + 1;-- if intermediate cnt then count
+ end if;
+ when STS_WAITs =>
+ if mem_busy_nd='0' or mode(2)='1' then --go to RESETs if PSRAM mode is selected
+ CS <= RESETs; --now it's ok to go here
+ else
+ state_cnt <= state_cnt + 1;
+ if state_cnt="1111" then
+ --sts cant take longer than 500 ns to go low
+ CS <= RESETs; --time out go to resets anyway
+ end if;
+ end if;
+ when others => null;
+ end case;
+ end if;
+end process;
+
+
+
+end RTL;
+
Index: tags/google_release_of_0x20_firmware/src/design_top/Copyright.txt
===================================================================
--- tags/google_release_of_0x20_firmware/src/design_top/Copyright.txt (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/design_top/Copyright.txt (revision 3)
@@ -0,0 +1,22 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
Index: tags/google_release_of_0x20_firmware/src/design_top/lesser.txt
===================================================================
--- tags/google_release_of_0x20_firmware/src/design_top/lesser.txt (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/design_top/lesser.txt (revision 3)
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
+ordinary GNU General Public License. This license, the GNU Lesser
+General Public License, applies to certain designated libraries, and
+is quite different from the ordinary General Public License. We use
+this license for certain libraries in order to permit linking those
+libraries into non-free programs.
+
+ When a program is linked with a library, whether statically or using
+a shared library, the combination of the two is legally speaking a
+combined work, a derivative of the original library. The ordinary
+General Public License therefore permits such linking only if the
+entire combination fits its criteria of freedom. The Lesser General
+Public License permits more lax criteria for linking other code with
+the library.
+
+ We call this license the "Lesser" General Public License because it
+does Less to protect the user's freedom than the ordinary General
+Public License. It also provides other free software developers Less
+of an advantage over competing non-free programs. These disadvantages
+are the reason we use the ordinary General Public License for many
+libraries. However, the Lesser license provides advantages in certain
+special circumstances.
+
+ For example, on rare occasions, there may be a special need to
+encourage the widest possible use of a certain library, so that it becomes
+a de-facto standard. To achieve this, non-free programs must be
+allowed to use the library. A more frequent case is that a free
+library does the same job as widely used non-free libraries. In this
+case, there is little to gain by limiting the free library to free
+software only, so we use the Lesser General Public License.
+
+ In other cases, permission to use a particular library in non-free
+programs enables a greater number of people to use a large body of
+free software. For example, permission to use the GNU C Library in
+non-free programs enables many more people to use the whole GNU
+operating system, as well as its variant, the GNU/Linux operating
+system.
+
+ Although the Lesser General Public License is Less protective of the
+users' freedom, it does ensure that the user of a program that is
+linked with the Library has the freedom and the wherewithal to run
+that program using a modified version of the Library.
+
+ The precise terms and conditions for copying, distribution and
+modification follow. Pay close attention to the difference between a
+"work based on the library" and a "work that uses the library". The
+former contains code derived from the library, whereas the latter must
+be combined with the library in order to run.
+
+ GNU LESSER GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License Agreement applies to any software library or other
+program which contains a notice placed by the copyright holder or
+other authorized party saying it may be distributed under the terms of
+this Lesser General Public License (also called "this License").
+Each licensee is addressed as "you".
+
+ A "library" means a collection of software functions and/or data
+prepared so as to be conveniently linked with application programs
+(which use some of those functions and data) to form executables.
+
+ The "Library", below, refers to any such software library or work
+which has been distributed under these terms. A "work based on the
+Library" means either the Library or any derivative work under
+copyright law: that is to say, a work containing the Library or a
+portion of it, either verbatim or with modifications and/or translated
+straightforwardly into another language. (Hereinafter, translation is
+included without limitation in the term "modification".)
+
+ "Source code" for a work means the preferred form of the work for
+making modifications to it. For a library, complete source code means
+all the source code for all modules it contains, plus any associated
+interface definition files, plus the scripts used to control compilation
+and installation of the library.
+
+ Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running a program using the Library is not restricted, and output from
+such a program is covered only if its contents constitute a work based
+on the Library (independent of the use of the Library in a tool for
+writing it). Whether that is true depends on what the Library does
+and what the program that uses the Library does.
+
+ 1. You may copy and distribute verbatim copies of the Library's
+complete source code as you receive it, in any medium, provided that
+you conspicuously and appropriately publish on each copy an
+appropriate copyright notice and disclaimer of warranty; keep intact
+all the notices that refer to this License and to the absence of any
+warranty; and distribute a copy of this License along with the
+Library.
+
+ You may charge a fee for the physical act of transferring a copy,
+and you may at your option offer warranty protection in exchange for a
+fee.
+
+ 2. You may modify your copy or copies of the Library or any portion
+of it, thus forming a work based on the Library, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) The modified work must itself be a software library.
+
+ b) You must cause the files modified to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ c) You must cause the whole of the work to be licensed at no
+ charge to all third parties under the terms of this License.
+
+ d) If a facility in the modified Library refers to a function or a
+ table of data to be supplied by an application program that uses
+ the facility, other than as an argument passed when the facility
+ is invoked, then you must make a good faith effort to ensure that,
+ in the event an application does not supply such function or
+ table, the facility still operates, and performs whatever part of
+ its purpose remains meaningful.
+
+ (For example, a function in a library to compute square roots has
+ a purpose that is entirely well-defined independent of the
+ application. Therefore, Subsection 2d requires that any
+ application-supplied function or table used by this function must
+ be optional: if the application does not supply it, the square
+ root function must still compute square roots.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Library,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Library, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Library.
+
+In addition, mere aggregation of another work not based on the Library
+with the Library (or with a work based on the Library) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may opt to apply the terms of the ordinary GNU General Public
+License instead of this License to a given copy of the Library. To do
+this, you must alter all the notices that refer to this License, so
+that they refer to the ordinary GNU General Public License, version 2,
+instead of to this License. (If a newer version than version 2 of the
+ordinary GNU General Public License has appeared, then you can specify
+that version instead if you wish.) Do not make any other change in
+these notices.
+
+ Once this change is made in a given copy, it is irreversible for
+that copy, so the ordinary GNU General Public License applies to all
+subsequent copies and derivative works made from that copy.
+
+ This option is useful when you wish to copy part of the code of
+the Library into a program that is not a library.
+
+ 4. You may copy and distribute the Library (or a portion or
+derivative of it, under Section 2) in object code or executable form
+under the terms of Sections 1 and 2 above provided that you accompany
+it with the complete corresponding machine-readable source code, which
+must be distributed under the terms of Sections 1 and 2 above on a
+medium customarily used for software interchange.
+
+ If distribution of object code is made by offering access to copy
+from a designated place, then offering equivalent access to copy the
+source code from the same place satisfies the requirement to
+distribute the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 5. A program that contains no derivative of any portion of the
+Library, but is designed to work with the Library by being compiled or
+linked with it, is called a "work that uses the Library". Such a
+work, in isolation, is not a derivative work of the Library, and
+therefore falls outside the scope of this License.
+
+ However, linking a "work that uses the Library" with the Library
+creates an executable that is a derivative of the Library (because it
+contains portions of the Library), rather than a "work that uses the
+library". The executable is therefore covered by this License.
+Section 6 states terms for distribution of such executables.
+
+ When a "work that uses the Library" uses material from a header file
+that is part of the Library, the object code for the work may be a
+derivative work of the Library even though the source code is not.
+Whether this is true is especially significant if the work can be
+linked without the Library, or if the work is itself a library. The
+threshold for this to be true is not precisely defined by law.
+
+ If such an object file uses only numerical parameters, data
+structure layouts and accessors, and small macros and small inline
+functions (ten lines or less in length), then the use of the object
+file is unrestricted, regardless of whether it is legally a derivative
+work. (Executables containing this object code plus portions of the
+Library will still fall under Section 6.)
+
+ Otherwise, if the work is a derivative of the Library, you may
+distribute the object code for the work under the terms of Section 6.
+Any executables containing that work also fall under Section 6,
+whether or not they are linked directly with the Library itself.
+
+ 6. As an exception to the Sections above, you may also combine or
+link a "work that uses the Library" with the Library to produce a
+work containing portions of the Library, and distribute that work
+under terms of your choice, provided that the terms permit
+modification of the work for the customer's own use and reverse
+engineering for debugging such modifications.
+
+ You must give prominent notice with each copy of the work that the
+Library is used in it and that the Library and its use are covered by
+this License. You must supply a copy of this License. If the work
+during execution displays copyright notices, you must include the
+copyright notice for the Library among them, as well as a reference
+directing the user to the copy of this License. Also, you must do one
+of these things:
+
+ a) Accompany the work with the complete corresponding
+ machine-readable source code for the Library including whatever
+ changes were used in the work (which must be distributed under
+ Sections 1 and 2 above); and, if the work is an executable linked
+ with the Library, with the complete machine-readable "work that
+ uses the Library", as object code and/or source code, so that the
+ user can modify the Library and then relink to produce a modified
+ executable containing the modified Library. (It is understood
+ that the user who changes the contents of definitions files in the
+ Library will not necessarily be able to recompile the application
+ to use the modified definitions.)
+
+ b) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (1) uses at run time a
+ copy of the library already present on the user's computer system,
+ rather than copying library functions into the executable, and (2)
+ will operate properly with a modified version of the library, if
+ the user installs one, as long as the modified version is
+ interface-compatible with the version that the work was made with.
+
+ c) Accompany the work with a written offer, valid for at
+ least three years, to give the same user the materials
+ specified in Subsection 6a, above, for a charge no more
+ than the cost of performing this distribution.
+
+ d) If distribution of the work is made by offering access to copy
+ from a designated place, offer equivalent access to copy the above
+ specified materials from the same place.
+
+ e) Verify that the user has already received a copy of these
+ materials or that you have already sent this user a copy.
+
+ For an executable, the required form of the "work that uses the
+Library" must include any data and utility programs needed for
+reproducing the executable from it. However, as a special exception,
+the materials to be distributed need not include anything that is
+normally distributed (in either source or binary form) with the major
+components (compiler, kernel, and so on) of the operating system on
+which the executable runs, unless that component itself accompanies
+the executable.
+
+ It may happen that this requirement contradicts the license
+restrictions of other proprietary libraries that do not normally
+accompany the operating system. Such a contradiction means you cannot
+use both them and the Library together in an executable that you
+distribute.
+
+ 7. You may place library facilities that are a work based on the
+Library side-by-side in a single library together with other library
+facilities not covered by this License, and distribute such a combined
+library, provided that the separate distribution of the work based on
+the Library and of the other library facilities is otherwise
+permitted, and provided that you do these two things:
+
+ a) Accompany the combined library with a copy of the same work
+ based on the Library, uncombined with any other library
+ facilities. This must be distributed under the terms of the
+ Sections above.
+
+ b) Give prominent notice with the combined library of the fact
+ that part of it is a work based on the Library, and explaining
+ where to find the accompanying uncombined form of the same work.
+
+ 8. You may not copy, modify, sublicense, link with, or distribute
+the Library except as expressly provided under this License. Any
+attempt otherwise to copy, modify, sublicense, link with, or
+distribute the Library is void, and will automatically terminate your
+rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses
+terminated so long as such parties remain in full compliance.
+
+ 9. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Library or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Library (or any work based on the
+Library), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Library or works based on it.
+
+ 10. Each time you redistribute the Library (or any work based on the
+Library), the recipient automatically receives a license from the
+original licensor to copy, distribute, link with or modify the Library
+subject to these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties with
+this License.
+
+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Library at all. For example, if a patent
+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ , 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
+
+
Index: tags/google_release_of_0x20_firmware/src/design_top/design_top_thincandbg.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/design_top/design_top_thincandbg.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/design_top/design_top_thincandbg.vhd (revision 3)
@@ -0,0 +1,640 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+
+-- Coding for seg_out(7:0)
+--
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+-- Revision history
+--
+-- Version 1.01
+-- 15 oct 2006 version code 86 01 jyrit
+-- Added IO write to address 0x0088 with commands F1 and F4 to
+-- enable switching dongle to 4Meg mode for external reads
+-- Changed USB interface to address all 4 Meg on any mode jumper configuration
+--
+-- Version 1.02
+-- 04 dec 2006 version code 86 02 jyrit
+-- Added listen only mode for mode pin configuration "00" to enable post code
+-- spy mode (does not respond to external reads).
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity design_top is
+ port (
+ --system signals
+ sys_clk : in std_logic; --25 MHz clk
+ resetn : in std_logic;
+ hdr : inout std_logic_vector(15 downto 0);
+ hdr_b : inout std_logic_vector(15 downto 0);
+ --alt_clk : out std_logic;
+ mode : inout std_logic_vector(2 downto 0); --sel upper addr bits
+ --lpc slave interf
+ lad : inout std_logic_vector(3 downto 0);
+ lframe_n : in std_logic;
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ ldev_present: out std_logic;
+ --led system
+ seg_out : out std_logic_vector(7 downto 0);
+ scn_seg : out std_logic_vector(3 downto 0);
+ led_green : out std_logic;
+ led_red : out std_logic;
+ --flash interface
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select
+ fl_oe_n : out std_logic; --output enable for flash
+ fl_we_n : out std_logic; --write enable
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_sts : in std_logic; --status signal
+ fl_sts_en : out std_logic; --enable status signal wiht highZ out
+ -- PSRAM aditional signals to flash
+ ps_ram_en : out std_logic;
+ ps_clk : out std_logic; --PSRAM clock
+ ps_wait : in std_logic;
+ ps_addr_val: out std_logic; --active low
+ ps_confr_en: out std_logic;
+ ps_lsb_en : out std_logic;
+ ps_msb_en : out std_logic;
+ -- EEPROM signals
+ ee_di : out std_logic;
+ ee_do : in std_logic;
+ ee_hold_n : out std_logic;
+ ee_cs_n : out std_logic;
+ ee_clk : out std_logic;
+ ee_write : out std_logic;
+ -- PROG enable
+ buf_oe_n : out std_logic;
+ --USB parallel interface
+ usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : inout std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo has data if low
+ usb_bd : inout std_logic_vector(7 downto 0) --bus data
+ );
+end design_top;
+
+
+
+architecture rtl of design_top is
+
+component led_sys --toplevel for led system
+ generic(
+ msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
+ msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
+ );
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ led_data_i : in std_logic_vector(15 downto 0); --binary data in
+ seg_out : out std_logic_vector(7 downto 0); --one segment out
+ sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+end component;
+
+
+component lpc_iow
+ port (
+ --system signals
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ lena_mem_r : in std_logic; --enable full adress range covering memory read block
+ lena_reads : in std_logic; --enable read capabilities
+ --LPC bus from host
+ lad_i : in std_logic_vector(3 downto 0);
+ lad_o : out std_logic_vector(3 downto 0);
+ lad_oe : out std_logic;
+ lframe_n : in std_logic;
+ --memory interface
+ lpc_addr : out std_logic_vector(23 downto 0); --shared address
+ lpc_wr : out std_logic; --shared write not read
+ lpc_data_i : in std_logic_vector(7 downto 0);
+ lpc_data_o : out std_logic_vector(7 downto 0);
+ lpc_val : out std_logic;
+ lpc_ack : in std_logic
+ );
+end component;
+
+
+component flash_if
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select
+ fl_oe_n : out std_logic; --output enable for flash
+ fl_we_n : out std_logic; --write enable
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_byte_n : out std_logic; --hold in byte mode
+ fl_sts : in std_logic; --status signal
+ -- mem Bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+ );
+end component;
+
+
+component usb2mem
+ port (
+ clk25 : in std_logic;
+ reset_n : in std_logic;
+ dongle_ver: in std_logic_vector(15 downto 0);
+ pcb_ver : in std_logic_vector(15 downto 0);
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en : out std_logic;
+ dev_present_n : out std_logic;
+ -- mem Bus
+ mem_busy_n: in std_logic;
+ mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
+ mem_addr : out std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : out std_logic;
+ mem_val : out std_logic;
+ mem_ack : in std_logic;
+ mem_cmd : out std_logic;
+ -- USB port
+ usb_mode_en: in std_logic; -- enable this block
+ usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : out std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd : inout std_logic_vector(7 downto 0) --bus data
+ );
+end component;
+
+component pc_serializer
+ Port ( --system signals
+ sys_clk : in STD_LOGIC;
+ resetn : in STD_LOGIC;
+ --postcode data port
+ dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
+ dbg_wr : in STD_LOGIC; --write not read
+ dbg_full : out STD_LOGIC; --write not read
+ dbg_almost_full : out STD_LOGIC;
+ dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
+ --debug USB port
+ dbg_usb_mode_en: in std_logic; -- enable this debug mode
+ dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
+);
+end component;
+
+
+--LED signals
+signal data_to_disp : std_logic_vector(15 downto 0);
+--END LED SIGNALS
+
+--lpc signals
+signal lad_i : std_logic_vector(3 downto 0);
+signal lad_o : std_logic_vector(3 downto 0);
+signal lad_oe : std_logic;
+
+signal lpc_debug : std_logic_vector(31 downto 0);
+signal lpc_debug_cnt : std_logic_vector(15 downto 0);
+signal lpc_addr : std_logic_vector(23 downto 0); --shared address
+signal lpc_data_o : std_logic_vector(7 downto 0);
+signal lpc_data_i : std_logic_vector(7 downto 0);
+signal lpc_wr : std_logic; --shared write not read
+signal lpc_ack : std_logic;
+signal lpc_val : std_logic;
+signal lena_mem_r : std_logic; --enable full adress range covering memory read block
+signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
+
+signal c25_lpc_val : std_logic;
+signal c25_lpc_wr : std_logic; --shared write not read
+signal c25_lpc_wr_long : std_logic; --for led debug data latching
+
+signal c33_lpc_wr_long : std_logic; --for led debug data latching
+signal c33_lpc_wr : std_logic; --for led debug data latching
+signal c33_lpc_wr_wait: std_logic; --for led debug data latching
+signal c33_lpc_wr_waitd: std_logic; --for led debug data latching
+signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
+
+
+--End lpc signals
+
+--Flash signals
+signal mem_addr : std_logic_vector(23 downto 0);
+signal mem_do : std_logic_vector(15 downto 0);
+signal mem_di : std_logic_vector(15 downto 0);
+signal mem_wr : std_logic; --write not read signal
+signal mem_val : std_logic;
+signal mem_ack : std_logic;
+
+signal c33_mem_ack : std_logic; --sync signal
+
+
+
+signal fl_ce_n_w : std_logic; --chip select
+signal fl_oe_n_w : std_logic; --output enable for flash
+signal fl_we_n_w : std_logic; --output enable for flash
+
+
+
+--END flash signals
+
+--USB signals
+signal dbg_data : STD_LOGIC_VECTOR (7 downto 0);
+signal c25_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
+signal c33_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
+
+signal dbg_wr : STD_LOGIC; --write not read
+signal dbg_full : STD_LOGIC; --write not read
+signal dbg_almost_full : STD_LOGIC;
+signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
+
+signal dbg_usb_mode_en : std_logic;
+signal usb_mode_en : std_logic;
+signal mem_idle : std_logic;
+signal umem_addr : std_logic_vector(23 downto 0);
+signal umem_do : std_logic_vector(15 downto 0);
+signal umem_wr : std_logic;
+signal umem_val : std_logic;
+signal umem_ack : std_logic;
+signal umem_cmd : std_logic;
+signal enable_4meg: std_logic;
+signal dongle_con_n : std_logic;
+
+signal jmp_settings : std_logic_vector(7 downto 0);
+signal jmp_value : std_logic_vector(7 downto 0);
+signal jmp_leds : std_logic_vector(7 downto 0);
+signal jmp_cnt : std_logic_vector(7 downto 0);
+
+constant dongle_ver : std_logic_vector(15 downto 0):=x"8620";
+constant pcb_ver : std_logic_vector(15 downto 0):=x"0835"; -- proj. no and PCB ver in hexademical
+--END USB signals
+
+begin
+
+
+
+--PSRAM static signals
+ps_lsb_en <='0';
+ps_msb_en <='0';
+ps_addr_val <='0'; --use async PSRAM access
+ps_clk <='0';
+ps_confr_en <='0';
+
+ps_ram_en <= fl_ce_n_w when mode(2)='1' else '1';
+
+
+--GPIO PINS START
+fl_sts_en <='Z';
+
+
+JMP_FETCH: process (sys_clk, resetn) --c33
+begin
+ if resetn = '0' then
+ jmp_settings <=x"00";
+ jmp_cnt <=x"00";
+ jmp_leds <=x"FF";
+ elsif sys_clk'event and sys_clk = '1' then -- rising clock edge
+ jmp_cnt <= jmp_cnt + 1;
+ if jmp_cnt = x"FE" then
+ jmp_leds <= x"00"; --light leds
+ elsif jmp_cnt = x"00" then
+ jmp_settings <= jmp_value;
+ jmp_leds <= jmp_settings; --show last settings this is ok as leds are slow
+ end if;
+
+ end if;
+end process JMP_FETCH;
+
+
+
+
+hdr(14) <= jmp_leds(7);
+hdr(12) <= jmp_leds(6);
+hdr(10) <= jmp_leds(5);
+hdr(8) <= jmp_leds(4);
+hdr(6) <= jmp_leds(3);
+hdr(4) <= jmp_leds(2);
+hdr(2) <= jmp_leds(1);
+hdr(0) <= jmp_leds(0);
+
+jmp_value(0) <= hdr(1);
+jmp_value(1) <= hdr(3);
+jmp_value(2) <= hdr(5);
+jmp_value(3) <= hdr(7);
+jmp_value(4) <= hdr(9);
+jmp_value(5) <= hdr(11);
+jmp_value(6) <= hdr(13);
+jmp_value(7) <= hdr(15);
+
+
+
+
+--hdr(1) <= dongle_con_n; --commented out for firm rev 0x20
+
+--hdr(1) <= fl_sts when resetn='1' else
+-- '0';
+
+--SETTING #0
+--when jumper on then mem read and firmware read enabled else only firmware read
+--hdr(0) <= '0'; --commented out for firm rev 0x20
+lena_mem_r <= not jmp_settings(0); -- disabled if jumper is not on header pins 1-2
+
+--SETTING #1
+-- jumper on pins 5,6 then postcode only mode (no mem device)
+--hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header) --commented out for firm rev 0x20
+lena_reads <= jmp_settings(1) and mem_idle and (not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
+
+
+--SETTING #2
+-- when jumper on pins 7,8 then post code capture mode enabled
+--hdr(4)<= '0'; --commented out for firm rev 0x20
+dbg_usb_mode_en <= not jmp_settings(2); --weak pullup on hdr(5) paired with hdr(4)
+usb_mode_en <= not dbg_usb_mode_en;
+
+
+--GPIO PINS END
+
+
+
+--LED SUBSYSTEM START
+data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' and resetn='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
+ "000"&dbg_usedw when usb_mode_en='0' and resetn='1' else
+ dongle_ver; --show tx fifo state on leds when postcode capture mode
+
+
+--########################################--
+ --VERSION CONSTATNS
+--########################################--
+led_red <= not enable_4meg;
+led_green <= not mem_val;
+
+LEDS: led_sys --toplevel for led system
+ generic map(
+ msn_hib => "01111111",--8 --Most signif. of hi byte
+ lsn_hib => "01111101",--6 --Least signif. of hi byte
+ msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
+ --lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
+ --lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
+ lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
+
+ )
+ port map(
+ clk => sys_clk , -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
+ seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
+ sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+
+--LED SUBSYSTEM END
+
+
+--MAIN DATAPATH CONNECTIONS
+--LPC bus logic
+lad_i <= lad;
+lad <= lad_o when lad_oe='1' else
+ (others=>'Z');
+
+--END LPC bus logic
+
+LPCBUS : lpc_iow
+ port map(
+ --system signals
+ lreset_n => lreset_n, -- in std_logic;
+ lclk => lclk, -- in std_logic;
+ lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
+ lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
+ --LPC bus from host
+ lad_i => lad_i, -- in std_logic_vector(3 downto 0);
+ lad_o => lad_o, -- out std_logic_vector(3 downto 0);
+ lad_oe => lad_oe, -- out std_logic;
+ lframe_n => lframe_n, -- in std_logic;
+ --memory interface
+ lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
+ lpc_wr => lpc_wr, -- out std_logic; --shared write not read
+ lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
+ lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
+ lpc_val => lpc_val, -- out std_logic;
+ lpc_ack => lpc_ack -- in std_logic
+ );
+
+
+--memory data bus logic
+ mem_addr <= mode(1 downto 0)&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
+ mode(1 downto 0)&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
+ mode(1 downto 0)&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
+ (others=>'Z');
+
+ mem_di <= (others=>'Z') when c25_lpc_val='1' else
+ umem_do when umem_val='1' else
+ (others=>'Z');
+
+
+ mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
+ umem_wr when umem_val='1' else
+ '0';
+
+ mem_val <= c25_lpc_val or umem_val;
+
+
+
+ umem_ack <= mem_ack when umem_val='1' else
+ '0';
+
+
+ lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
+ mem_do(15 downto 8);
+
+ lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
+ (not dbg_almost_full) when lpc_val='1' and lpc_wr='1' else
+ '0';
+
+
+
+ SYNC1: process (lclk, lreset_n) --c33
+ begin
+ if lclk'event and lclk = '1' then -- rising clock edge
+ c33_mem_ack <= mem_ack;
+
+ end if;
+ end process SYNC1;
+
+
+ dbg_data <= lpc_debug(7 downto 0);
+ SYNC2: process (sys_clk) --c25
+ begin
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ c25_lpc_val <= lpc_val; --syncro two clock domains
+ c25_lpc_wr <= c33_lpc_wr; --syncro two clock domains
+ c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
+ if usb_mode_en ='0' and c25_dbg_addr_d=x"80" then --don't fill fifo in regular mode
+ dbg_wr<= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
+ else
+ dbg_wr<='0'; --write never rises when usb_mode_en = 1
+ end if;
+ end if;
+ end process SYNC2;
+
+
+
+ LATCHled: process (lclk,lreset_n) --c33
+ begin
+ if lreset_n='0' then
+ lpc_debug(7 downto 0)<=(others=>'0');
+ c33_dbg_addr_d <=(others=>'0');
+ enable_4meg <='0';
+ c33_lpc_wr <='0';
+ dongle_con_n <='0'; -- pin 3 in GPIO make it toggleable
+ elsif lclk'event and lclk = '1' then -- rising clock edge
+ c33_lpc_wr <= lpc_wr;
+ if c33_lpc_wr='0' and lpc_wr='1' then
+ c33_dbg_addr_d <= lpc_addr(7 downto 0);
+ lpc_debug(7 downto 0)<= lpc_data_o;
+ if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
+ enable_4meg <='1';
+ elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F1" then --Flash 1 Mega enalbe
+ enable_4meg <='0';
+ elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
+ dongle_con_n <='1'; -- pin 3 in GPIO make it 1
+ elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
+ dongle_con_n <='0'; -- pin 3 in GPIO make it 1
+ end if;
+ end if;
+ end if;
+ end process LATCHled;
+
+
+
+
+
+
+--END memory data bus logic
+fl_ce_n<= fl_ce_n_w when mode(2)='0' else '1';
+fl_oe_n<= fl_oe_n_w;
+fl_we_n <= fl_we_n_w;
+
+FLASH : flash_if
+ port map(
+ clk => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ mode => mode,-- : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
+ fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
+ fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
+ fl_we_n => fl_we_n_w, -- out std_logic; --write enable
+ fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
+ fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
+ --fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
+ fl_sts => fl_sts, -- in std_logic; --status signal
+ -- mem Bus
+ mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
+ mem_do => mem_do, -- out std_logic_vector(15 downto 0);
+ mem_di => mem_di, -- in std_logic_vector(15 downto 0);
+
+ mem_wr => mem_wr, -- in std_logic; --write not read signal
+ mem_val => mem_val, -- in std_logic;
+ mem_ack => mem_ack -- out std_logic
+ );
+
+
+
+USB: usb2mem
+ port map(
+ clk25 => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ dongle_ver => dongle_ver,
+ pcb_ver => pcb_ver, --: in std_logic_vector(15 downto 0);
+ mode => mode,-- : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en => buf_oe_n, --: out std_logic;
+ dev_present_n => ldev_present,--: out std_logic;
+ -- mem Bus
+ mem_busy_n=> fl_sts, --check flash status before starting new command on flash
+ mem_idle => mem_idle,
+ mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
+ mem_do => umem_do, -- out std_logic_vector(15 downto 0);
+ mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
+ mem_wr => umem_wr, -- out std_logic;
+ mem_val => umem_val, -- out std_logic;
+ mem_ack => umem_ack, -- in std_logic; --from flash
+ mem_cmd => umem_cmd, -- out std_logic;
+ -- USB port
+ usb_mode_en => usb_mode_en,
+ usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
+ usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
+ );
+
+
+DBG : pc_serializer
+ port map ( --system signals
+ sys_clk => sys_clk, -- in STD_LOGIC;
+ resetn => resetn, -- in STD_LOGIC;
+ --postcode data port
+ dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
+ dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
+ dbg_full => dbg_full,--: out STD_LOGIC; --write not read
+ dbg_almost_full => dbg_almost_full,
+ dbg_usedw => dbg_usedw,
+
+ --debug USB port
+ dbg_usb_mode_en=> dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
+ dbg_usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
+);
+
+
+--END MAIN DATAPATH CONNECTIONS
+
+end rtl;
+
+
+
Index: tags/google_release_of_0x20_firmware/src/flash/flsh_if.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/src/flash/flsh_if.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/src/flash/flsh_if.vhd (revision 3)
@@ -0,0 +1,136 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity flash_if is
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
+ fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
+ fl_we_n : out std_logic; --write enable (timing is very chip dependent)
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_byte_n : out std_logic; --hold in byte mode
+ fl_sts : in std_logic; --status signal
+ -- mem Bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+ );
+end flash_if;
+
+
+architecture RTL of flash_if is
+ type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
+ signal CS : state_type;
+ signal fl_cnt : std_logic_vector(3 downto 0);
+ signal fl_oe_nd : std_logic; --output enable for flash
+ signal mode_d : std_logic_vector(2 downto 0); --sel upper addr bits
+begin
+
+fl_rp_n <= reset_n; --make flash reset
+fl_addr <= mem_addr(23 downto 0);
+fl_byte_n <= '0'; --all byte accesses
+
+
+fl_oe_n<=fl_oe_nd;
+fl_data <= mem_di when fl_oe_nd ='1' else
+ (others =>'Z');
+
+
+
+RD: process (clk, reset_n)
+begin -- process READ
+ if reset_n='0' then
+ fl_we_n <='1';
+ fl_ce_n <='1';
+ fl_oe_nd <='1';
+ CS <= RESETs;
+ fl_cnt <= (others=>'0');
+ mem_do <= (others=>'0');
+ mem_ack <='0';
+ elsif clk'event and clk = '1' then -- rising clock edge
+ mode_d <= mode;
+ case CS is
+ when RESETs =>
+ mem_ack <='0';
+ fl_ce_n <= (not mem_val); --chipselect 4 flash
+ fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
+ if mem_val='1' and mem_wr = '0' then --READ
+ fl_oe_nd <='0';
+ CS <= FLREADs;
+ elsif mem_val='1' and mem_wr = '1' then --WRITE
+ fl_oe_nd <='1';
+ CS <= FLWRITEs;
+ end if; --elsif mem_cmd
+ --Lets set the cnt for flash and PSRAM separately
+ if (mode_d(2)='0')then
+ fl_cnt <= (others=>'0');
+ else
+ fl_cnt <= x"2"; --PSRAM cycle is 80 ns with 25MHz clock
+ end if;
+ when FLREADs =>
+ fl_cnt <= fl_cnt + 1;
+ if fl_cnt=x"3" then --3 cycles later
+ mem_ack <='1';
+ mem_do <= fl_data; --registered is nicer
+ elsif fl_cnt=x"4" then --4 cycles later
+ mem_ack <='0';
+ fl_oe_nd <='1';
+ CS <= WAITs;
+ end if;
+ when FLWRITEs =>
+ fl_cnt <= fl_cnt + 1;
+ if fl_cnt=x"3" then --3 cycles later
+ mem_ack <='1';
+ elsif fl_cnt=x"4" then --4 cycles later
+ mem_ack <='0';
+ CS <= WAITs;
+ end if;
+ when WAITs =>
+ if mem_val='0' then -- wait untill val is removed
+ CS <= RESETs;
+ end if;
+ end case;
+
+ end if; --system
+end process RD;
+
+
+
+
+end RTL;
+
Index: tags/google_release_of_0x20_firmware/sw/dongle.py
===================================================================
--- tags/google_release_of_0x20_firmware/sw/dongle.py (nonexistent)
+++ tags/google_release_of_0x20_firmware/sw/dongle.py (revision 3)
@@ -0,0 +1,1862 @@
+#! /usr/bin/python
+# -*- coding: ISO-8859-1 -*-
+
+##########################################################################
+# LPC Dongle programming software
+#
+# Copyright (C) 2008 Artec Design
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This software is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##########################################################################
+
+#-------------------------------------------------------------------------
+# Project: LPC Dongle programming software
+# Name: dongle.py
+# Purpose: Executable command line tool
+#
+# Author: Jüri Toomessoo
+# Copyright: (c) 2008 by Artec Design
+# Licence: LGPL
+#
+# Created: 06 Oct. 2006
+# History: 12 oct. 2006 Version 1.0 released
+# 22 Feb. 2007 Test options added to test PCB board
+# 10 Nov. 2007 Added open retry code to dongle
+# 14 Nov. 2007 Moved dongle specific code to class Dongle from USPP
+# USPP is allmost standard now (standard USPP would work)
+# Artec USPP has serial open retry
+# 14 Nov. 2007 Improved help.
+# 10 Mar. 2008 Forced code to hw flow control settings made linux 1 byte read to 2 bytes
+# as dongle never reads 1 byte at the time
+# 18 Apr. 2008 Added file size boundary check on write to see if remaining size from
+# given offset fits the file size
+
+# 24 Apr. 2008 Mac OS X support by Stefan Reinauer
+# 09 Oct. 2008 Added Dongle ver 86 06 support. Support for mode setting
+# PCB ver read and PSRAM read write support. (PSRAM is on Dongle II boards)
+# 03 Nov. 2008 Added Dongle II board changes to PSRAM write so that the bytes are not swapped
+# by dongle.py but in hardware pipeline
+#-------------------------------------------------------------------------
+
+import os
+import sys
+import string
+import time
+import struct
+from sets import *
+from struct import *
+
+#### inline of artec FTDI specific Uspp code ###################################################
+
+##########################################################################
+# USPP Library (Universal Serial Port Python Library)
+#
+# Copyright (C) 2006 Isaac Barona
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##########################################################################
+
+#-------------------------------------------------------------------------
+# Project: USPP Library (Universal Serial Port Python Library)
+# Name: uspp.py
+# Purpose: Main module. Imports the correct module for the platform
+# in which it is running.
+#
+# Author: Isaac Barona Martinez
+# Contributors:
+# Damien Géranton
+# Douglas Jones
+# J.Grauheding
+# J.Toomessoo jyrit@artecdesign.ee
+#
+# Copyright: (c) 2006 by Isaac Barona Martinez
+# Licence: LGPL
+#
+# Created: 26 June 2001
+# History:
+# 05/08/2001: Release version 0.1.
+# 24/02/2006: Final version 1.0.
+# 10/11/2007: Added open retry code to dongle
+# by Jyri Toomessoo jyrit@artecdesign.ee
+# 14/11/2007: Moved dongle specific code to class Dongle from USPP
+# USPP is allmost standard now (standard USPP would work)
+# Artec USPP has serial open retry
+# by Jyri Toomessoo jyrit@artecdesign.ee
+# 10/03/2008: Forced code to hw flow control settings made linux 1 byte read to 2 bytes
+# as dongle never reads 1 byte at the time
+# by Jyri Toomessoo jyrit@artecdesign.ee
+# 10/03/2008: Copose single infile bundle for FTDI USB serial 1.2
+# this is nonuniversal modification of the code to suite the need of Artec Design Dongle
+# by Jyri Toomessoo jyrit@artecdesign.ee
+#-------------------------------------------------------------------------
+
+
+drv_ok = 0
+if sys.platform=='win32':
+ print "Windows platform detected:"
+ if drv_ok == 0:
+ try:
+ from win32file import *
+ from win32event import *
+ import win32con
+ import exceptions
+
+ print "Using VCP FTDI driver"
+ except ImportError,SerialPortException:
+ print "Python for winiows extensions for COM not found"
+ print "(see https://sourceforge.net/projects/pywin32/)"
+ print "Could not find any usable support for FTDI chip in python"
+ print "Try installing python support from one of the links."
+ sys.exit()
+elif sys.platform=='linux2':
+ from termios import *
+ import fcntl
+ import exceptions
+ import array
+ print "Linux platform detected:"
+elif sys.platform=='darwin':
+ from termios import *
+ import fcntl
+ import exceptions
+ import array
+ print "Mac OS X platform detected:"
+else:
+ sys.exit('Sorry, no implementation for this platform yet')
+
+
+
+class SerialPortException(exceptions.Exception):
+ """Exception raise in the SerialPort methods"""
+ def __init__(self, args=None):
+ self.args=args
+ def __str__(self):
+ return repr(self.args)
+
+
+if sys.platform=='win32':
+ class SerialPortWin:
+ BaudRatesDic={110: CBR_110,
+ 300: CBR_300,
+ 600: CBR_600,
+ 1200: CBR_1200,
+ 2400: CBR_2400,
+ 4800: CBR_4800,
+ 9600: CBR_9600,
+ 19200: CBR_19200,
+ 38400: CBR_38400,
+ 57600: CBR_57600,
+ 115200: CBR_115200,
+ 128000: CBR_128000,
+ 256000: CBR_256000
+ }
+
+ def __init__(self, dev, timeout=None, speed=115200, mode='232', params=None):
+ self.__devName, self.__timeout, self.__speed=dev, timeout, speed
+ self.__mode=mode
+ self.__params=params
+ self.__speed = 0
+ self.__reopen = 0
+ while 1:
+ try:
+ self.__handle=CreateFile (dev,
+ win32con.GENERIC_READ|win32con.GENERIC_WRITE,
+ 0, # exclusive access
+ None, # no security
+ win32con.OPEN_EXISTING,
+ win32con.FILE_ATTRIBUTE_NORMAL,
+ None)
+ break
+
+ except:
+ n=0
+ while (n < 2000000):
+ n += 1;
+ self.__reopen = self.__reopen + 1
+ if self.__reopen > 32:
+ print "Port does not exist... retries exhausted..."
+ raise SerialPortException('Port does not exist...')
+ break
+ #sys.exit()
+ self.__configure()
+
+ def __del__(self):
+ if self.__speed:
+ try:
+ CloseHandle(self.__handle)
+ except:
+ raise SerialPortException('Unable to close port')
+
+
+
+
+ def __configure(self):
+ if not self.__speed:
+ self.__speed=115200
+ # Tell the port we want a notification on each char
+ SetCommMask(self.__handle, EV_RXCHAR)
+ # Setup a 4k buffer
+ SetupComm(self.__handle, 4096, 4096)
+ # Remove anything that was there
+ PurgeComm(self.__handle, PURGE_TXABORT|PURGE_RXABORT|PURGE_TXCLEAR|
+ PURGE_RXCLEAR)
+ if self.__timeout==None:
+ timeouts= 0, 0, 0, 0, 0
+ elif self.__timeout==0:
+ timeouts = win32con.MAXDWORD, 0, 0, 0, 1000
+ else:
+ timeouts= self.__timeout, 0, self.__timeout, 0 , 1000
+ SetCommTimeouts(self.__handle, timeouts)
+
+ # Setup the connection info
+ dcb=GetCommState(self.__handle)
+ dcb.BaudRate=SerialPortWin.BaudRatesDic[self.__speed]
+ if not self.__params:
+ dcb.ByteSize=8
+ dcb.Parity=NOPARITY
+ dcb.StopBits=ONESTOPBIT
+ dcb.fRtsControl=RTS_CONTROL_ENABLE
+ dcb.fOutxCtsFlow=1
+ else:
+ dcb.ByteSize, dcb.Parity, dcb.StopBits=self.__params
+ SetCommState(self.__handle, dcb)
+
+
+ def fileno(self):
+ return self.__handle
+
+
+ def read(self, num=1):
+ (Br, buff) = ReadFile(self.__handle, num)
+ if len(buff)<>num and self.__timeout!=0: # Time-out
+ print 'Expected %i bytes but got %i before timeout'%(num,len(buff))
+ raise SerialPortException('Timeout')
+ else:
+ return buff
+
+
+ def readline(self):
+ s = ''
+ while not '\n' in s:
+ s = s+SerialPortWin.read(self,1)
+
+ return s
+
+
+ def write(self, s):
+ """Write the string s to the serial port"""
+ errCode = 0
+ overlapped=OVERLAPPED()
+ overlapped.hEvent=CreateEvent(None, 0,0, None)
+ (errCode, bytesWritten) = WriteFile(self.__handle, s,overlapped)
+ # Wait for the write to complete
+ WaitForSingleObject(overlapped.hEvent, INFINITE)
+ return bytesWritten
+
+ def inWaiting(self):
+ """Returns the number of bytes waiting to be read"""
+ flags, comstat = ClearCommError(self.__handle)
+ return comstat.cbInQue
+
+ def flush(self):
+ """Discards all bytes from the output or input buffer"""
+ PurgeComm(self.__handle, PURGE_TXABORT|PURGE_RXABORT|PURGE_TXCLEAR|
+ PURGE_RXCLEAR)
+
+
+
+if sys.platform=='linux2':
+ class SerialPortLin:
+ """Encapsulate methods for accesing to a serial port."""
+
+ BaudRatesDic={
+ 110: B110,
+ 300: B300,
+ 600: B600,
+ 1200: B1200,
+ 2400: B2400,
+ 4800: B4800,
+ 9600: B9600,
+ 19200: B19200,
+ 38400: B38400,
+ 57600: B57600,
+ 115200: B115200,
+ 230400: B230400
+ }
+ buf = array.array('h', '\000'*4)
+
+ def __init__(self, dev, timeout=None, speed=115200, mode='232', params=None):
+ self.__devName, self.__timeout, self.__speed=dev, timeout, speed
+ self.__mode=mode
+ self.__params=params
+ self.__speed = 0
+ self.__reopen = 0
+ while 1:
+ try:
+ self.__handle=os.open(dev, os.O_RDWR)
+ break
+
+ except:
+ n=0
+ while (n < 2000000):
+ n += 1;
+ self.__reopen = self.__reopen + 1
+ if self.__reopen > 32:
+ print "Port does not exist..."
+ raise SerialPortException('Port does not exist...')
+ break
+
+ self.__configure()
+
+ def __del__(self):
+ if self.__speed:
+ #tcsetattr(self.__handle, TCSANOW, self.__oldmode)
+ pass
+ try:
+ pass
+ os.close(self.__handle)
+ except IOError:
+ raise SerialPortException('Unable to close port')
+
+
+ def __configure(self):
+ if not self.__speed:
+ self.__speed=115200
+
+ # Save the initial port configuration
+ self.__oldmode=tcgetattr(self.__handle)
+ if not self.__params:
+ # print "Create linux params for serialport..."
+ # self.__params is a list of attributes of the file descriptor
+ # self.__handle as follows:
+ # [c_iflag, c_oflag, c_cflag, c_lflag, c_ispeed, c_ospeed, cc]
+ # where cc is a list of the tty special characters.
+ self.__params=[]
+ # c_iflag
+ self.__params.append(IGNPAR)
+ # c_oflag
+ self.__params.append(0)
+ # c_cflag
+ self.__params.append(CS8|CREAD|CRTSCTS)
+ # c_lflag
+ self.__params.append(0)
+ # c_ispeed
+ self.__params.append(SerialPortLin.BaudRatesDic[self.__speed])
+ # c_ospeed
+ self.__params.append(SerialPortLin.BaudRatesDic[self.__speed])
+ cc=[0]*NCCS
+ if self.__timeout==None:
+ # A reading is only complete when VMIN characters have
+ # been received (blocking reading)
+ cc[VMIN]=1
+ cc[VTIME]=0
+ elif self.__timeout==0:
+ cc[VMIN]=0
+ cc[VTIME]=0
+ else:
+ cc[VMIN]=0
+ cc[VTIME]=self.__timeout #/100
+ self.__params.append(cc) # c_cc
+
+ tcsetattr(self.__handle, TCSANOW, self.__params)
+
+
+ def fileno(self):
+ return self.__handle
+
+
+ def __read1(self):
+ tryCnt = 0
+ byte = ""
+ while(len(byte)==0 and tryCnt<10):
+ tryCnt+=1
+ byte = os.read(self.__handle, 2)
+ if len(byte)==0 and self.__timeout!=0: # Time-out
+ print 'Time out cnt was %i'%(tryCnt)
+ print 'Expected 1 byte but got %i before timeout'%(len(byte))
+ sys.stdout.flush()
+ raise SerialPortException('Timeout')
+ else:
+ return byte
+
+
+ def read(self, num=1):
+ s=''
+ for i in range(num/2):
+ s=s+SerialPortLin.__read1(self)
+ return s
+
+
+ def readline(self):
+
+ s = ''
+ while not '\n' in s:
+ s = s+SerialPortLin.__read1(self)
+
+ return s
+
+
+ def write(self, s):
+ """Write the string s to the serial port"""
+ return os.write(self.__handle, s)
+
+ def inWaiting(self):
+ """Returns the number of bytes waiting to be read"""
+ data = struct.pack("L", 0)
+ data=fcntl.ioctl(self.__handle, TIOCINQ, data)
+ return struct.unpack("L", data)[0]
+
+ def outWaiting(self):
+ """Returns the number of bytes waiting to be write
+ mod. by J.Grauheding
+ result needs some finetunning
+ """
+ rbuf=fcntl.ioctl(self.__handle, TIOCOUTQ, self.buf)
+ return rbuf
+
+
+ def flush(self):
+ """Discards all bytes from the output or input buffer"""
+ tcflush(self.__handle, TCIOFLUSH)
+
+
+if sys.platform=='darwin':
+ class SerialPortOSX:
+ """Encapsulate methods for accesing to a serial port."""
+
+ BaudRatesDic={
+ 110: B110,
+ 300: B300,
+ 600: B600,
+ 1200: B1200,
+ 2400: B2400,
+ 4800: B4800,
+ 9600: B9600,
+ 19200: B19200,
+ 38400: B38400,
+ 57600: B57600,
+ 115200: B115200,
+ 230400: B230400
+ }
+ buf = array.array('h', '\000'*4)
+
+ def __init__(self, dev, timeout=None, speed=115200, mode='232', params=None):
+ self.__devName, self.__timeout, self.__speed=dev, timeout, speed
+ self.__mode=mode
+ self.__params=params
+ self.__speed = 0
+ self.__reopen = 0
+ while 1:
+ try:
+ self.__handle=os.open(dev, os.O_RDWR)
+ break
+
+ except:
+ n=0
+ while (n < 2000000):
+ n += 1;
+ self.__reopen = self.__reopen + 1
+ if self.__reopen > 32:
+ print "Port does not exist..."
+ raise SerialPortException('Port does not exist...')
+ break
+
+ self.__configure()
+
+ def __del__(self):
+ if self.__speed:
+ #tcsetattr(self.__handle, TCSANOW, self.__oldmode)
+ pass
+ try:
+ pass
+ #os.close(self.__handle)
+ except IOError:
+ raise SerialPortException('Unable to close port')
+
+
+ def __configure(self):
+ if not self.__speed:
+ self.__speed=115200
+
+ # Save the initial port configuration
+ self.__oldmode=tcgetattr(self.__handle)
+ if not self.__params:
+ # print "Create MacOSX params for serialport..."
+ # self.__params is a list of attributes of the file descriptor
+ # self.__handle as follows:
+ # [c_iflag, c_oflag, c_cflag, c_lflag, c_ispeed, c_ospeed, cc]
+ # where cc is a list of the tty special characters.
+ self.__params=[]
+ # c_iflag
+ self.__params.append(IGNPAR)
+ # c_oflag
+ self.__params.append(0)
+ # c_cflag
+ self.__params.append(CS8|CREAD|CRTSCTS)
+ # c_lflag
+ self.__params.append(0)
+ # c_ispeed
+ self.__params.append(SerialPortOSX.BaudRatesDic[self.__speed])
+ # c_ospeed
+ self.__params.append(SerialPortOSX.BaudRatesDic[self.__speed])
+ cc=[0]*NCCS
+ if self.__timeout==None:
+ # A reading is only complete when VMIN characters have
+ # been received (blocking reading)
+ cc[VMIN]=1
+ cc[VTIME]=0
+ elif self.__timeout==0:
+ cc[VMIN]=0
+ cc[VTIME]=0
+ else:
+ cc[VMIN]=0
+ cc[VTIME]=self.__timeout #/100
+ self.__params.append(cc) # c_cc
+
+ tcsetattr(self.__handle, TCSANOW, self.__params)
+
+
+ def fileno(self):
+ return self.__handle
+
+
+ def __read1(self):
+ tryCnt = 0
+ byte = ""
+ while(len(byte)==0 and tryCnt<10):
+ tryCnt+=1
+ byte = os.read(self.__handle, 2)
+ if len(byte)==0 and self.__timeout!=0: # Time-out
+ print 'Time out cnt was %i'%(tryCnt)
+ print 'Expected 1 byte but got %i before timeout'%(len(byte))
+ sys.stdout.flush()
+ raise SerialPortException('Timeout')
+ else:
+ return byte
+
+
+ def read(self, num=1):
+ s=''
+ for i in range(num/2):
+ s=s+SerialPortOSX.__read1(self)
+ return s
+
+
+ def readline(self):
+
+ s = ''
+ while not '\n' in s:
+ s = s+SerialPortOSX.__read1(self)
+
+ return s
+
+
+ def write(self, s):
+ """Write the string s to the serial port"""
+ return os.write(self.__handle, s)
+
+ def inWaiting(self):
+ """Returns the number of bytes waiting to be read"""
+ data = struct.pack("L", 0)
+ data=fcntl.ioctl(self.__handle, FIONREAD, data)
+ return struct.unpack("L", data)[0]
+
+ def outWaiting(self):
+ """Returns the number of bytes waiting to be write
+ mod. by J.Grauheding
+ result needs some finetunning
+ """
+ rbuf=fcntl.ioctl(self.__handle, FIONWRITE, self.buf)
+ return rbuf
+
+
+ def flush(self):
+ """Discards all bytes from the output or input buffer"""
+ tcflush(self.__handle, TCIOFLUSH)
+
+
+
+#### end inline of artec FTDI specific Uspp code ###############################################
+
+
+#### Dongle code starts here ##################################################################
+
+
+#### global funcs ####
+def usage(s):
+ print "Artec USB Dongle programming utility ver. 2.7 prerelease"
+ print "Usage:"
+ print "Write file : ",s," [-vq] -c "
+ print "Readback file : ",s," [-vq] -c [-vq] -r "
+ print "Options:"
+ print " When file and offset are given file will be written to dongle"
+ print " file: File name to be written to dongle"
+ print " offset: Specifies data writing starting point in bytes to 4M window"
+ print " For ThinCan boot code the offset = 4M - filesize. To write"
+ print " 256K file the offset must be 3840K or EOF"
+ print " EOF marker will cause the dongle.py to calculate suitable offset"
+ print " and also cause files with odd byte count to be front padded"
+ print " "
+ print " -c Indicate port name where the USB Serial Device is"
+ print " name: COM port name in Windows or Linux Examples: COM3,/dev/ttyS3"
+ print " See Device Manager in windows for USB Serial Port number"
+ print " "
+ print " -v Enable verbose mode. Displays more progress information"
+ print " "
+ print " -q Perform flash query to see if dongle flash is responding"
+ print " "
+ print " -r Readback data. Available window size is 4MB"
+ print " offset: Offset byte addres inside 4MB window. Example: 1M"
+ print " use M for MegaBytes, K for KiloBytes, none for bytes"
+ print " use 0x prefix to indicate hexademical number format"
+ print " length: Amount in bytes to read starting from offset. Example: 1M"
+ print " use M for MegaBytes, K for KiloBytes, none for bytes"
+ print " file: Filename where data will be written"
+ print " "
+ print " -e Erase device. Erases Full 4 MegaBytes"
+ print "Board test options: "
+ print " -t Marching one and zero test. Device must be empty"
+ print " To test dongle erase the flash with command -e"
+ print " Enables dongle memory tests to be executed by user"
+ print " "
+ print " -b Leave flash blank after test. Used with option -t"
+ print " -l Fast poll loop test. Does poll loop 1024 times"
+ print " used to stress test connection"
+ print " -p and -P Used to change ldev_present_n signal on dongle LPC interface"
+ print " -p will cause the signal to go low and -P to go high"
+ print " from reset and when dongle FPGA is not configured the signal is low."
+ print " The state is not held when power is disconnected"
+ print ""
+ print "Examples:"
+ print ""
+ print " ",s," -c COM3 loader.bin 0 "
+ print " ",s," -c /dev/ttyS3 boot.bin 3840K"
+ print " ",s," -c COM3 -r 0x3C0000 256K flashcontent.bin"
+ print " ",s," -c /dev/cu.usbserial-003011FD -v (Mac OS X)"
+######################
+
+
+class DongleMode:
+ def __init__(self):
+ self.v = 0
+ self.f = 0
+ self.d = 0
+ self.q = 0
+ self.r = 0
+ self.t = 0
+ self.e = 0
+ self.b = 0
+ self.l = 0
+ self.p = 0
+ self.u = 0
+ self.filename=""
+ self.portname=""
+ self.address=-1
+ self.eof=-1
+ self.oddSize=0
+ self.oddAddr=0
+ self.offset=-1
+ self.length=-1
+ self.version=4
+ self.region=-1
+
+ def convParamStr(self,param):
+ mult = 1
+ value = 0
+ str = param
+ if str.find("K")>-1:
+ mult = 1024
+ str=str.strip("K")
+ if str.find("M")>-1:
+ mult = 1024*1024
+ str=str.strip("M")
+ try:
+ if str.find("x")>-1:
+ value = int(str,0)*mult #conver hex string to int
+ else:
+ value = int(str)*mult #conver demical string to int
+ except ValueError:
+ print "Bad parameter format given for: ",param
+
+ return value
+
+
+
+
+class Dongle:
+ def __init__(self,name, baud, timeout): #time out in millis 1000 = 1s baud like 9600, 57600
+ self.mode = 0
+ try:
+ if sys.platform=='win32':
+ self.tty = SerialPortWin(name,timeout, baud)
+ elif sys.platform=='linux2':
+ self.tty = SerialPortLin(name,timeout, baud)
+ elif sys.platform=='darwin':
+ self.tty = SerialPortOSX(name,timeout, baud)
+
+ except SerialPortException , e:
+ print "Unable to open port " + name
+ sys.exit();
+
+ def testReturn(self,byteCount):
+ i=0
+ while don.tty.inWaiting()>8)&0xff
+ self.write_2bytes(msb,lsb)
+
+ def write_2bytes(self, msb,lsb):
+ """Write one word MSB,LSB to the serial port MSB first"""
+ #print "----------> CMD %02x %02x"%(msb,lsb)
+ s = pack('BB', msb, lsb)
+ ret = self.tty.write(s)
+ if(ret>8)&0xff
+ msbyte = (address>>16)&0xff
+ buffer = ""
+ buffer += chr(lsbyte)
+ buffer += chr(0xA0)
+ buffer += chr(byte)
+ buffer += chr(0xA1)
+ buffer += chr(msbyte)
+ buffer += chr(0xA2)
+ evaluate = (address>>24)
+ if evaluate != 0:
+ print "Addressign fault. Too large address passed"
+ sys.exit()
+ return buffer
+
+
+ def set_address(self,address): #set word address
+ lsbyte = address&0xff
+ byte = (address>>8)&0xff
+ msbyte = (address>>16)&0xff
+ evaluate = (address>>24)
+ if evaluate != 0:
+ print "Addressing fault. Too large address passed"
+ sys.exit()
+ self.write_2bytes(lsbyte,0xA0) #set internal address to dongle
+ self.write_2bytes(byte,0xA1) #set internal address to dongle
+ self.write_2bytes(msbyte,0xA2) #send query command
+
+ def read_data(self,wordCount,address):
+ command = 0
+ byteCount = wordCount<<1 #calc byte count
+ if wordCount>0 :
+ command = (command|wordCount)<<8
+ command = command|0xCD
+ self.set_address(address) # send read address
+ self.write_command(command) # send get data command
+ return self.getReturn(byteCount)
+ else:
+ print "Word count can't be under 1"
+ sys.exit()
+
+
+ def issue_blk_read(self):
+ command = 0
+ wordCount = 0
+ byteCount = wordCount<<1 #calc byte count
+ command = (command|wordCount)<<8
+ command = command|0xCD
+ self.write_command(command) # send get data command
+
+
+
+
+ def read_status(self):
+ don.write_command(0x0070) # 0x0098 //clear status
+ command = 0
+ wordCount= 1 #calc byte count
+ byteCount = wordCount<<1
+ command = (command|wordCount)<<8
+ command = command|0xCD
+ self.write_command(command) # send get data command
+ return self.getReturn(byteCount)
+
+
+ def get_block_no(self,address):
+ return address >> 16 # 16 bit mode block is 64Kwords
+
+ def wait_on_busy(self):
+ exit=0
+ while exit==0:
+ buf=self.read_status()
+ statReg = ord(buf[0]) #8 bit reg
+ if statReg>>7 == 1:
+ exit=1
+
+ def parse_status(self): # use only after wait on busy commad to get result of the operation
+ exit = 0
+ buf=self.read_status()
+ statReg = ord(buf[0]) #8 bit reg
+ if (statReg>>5)&1 == 1:
+ print "Block erase suspended"
+ exit = 1
+ if (statReg>>4)&3 == 3:
+ print "Error in command order" #if bits 4 and 5 are set then
+ exit = 1
+ if (statReg>>4)&3 == 1:
+ print "Error in setting lock bit"
+ exit = 1
+ if (statReg>>3)&1 == 1:
+ print "Low Programming Voltage Detected, Operation Aborted"
+ exit = 1
+ if (statReg>>2)&1 == 1:
+ print "Programming suspended"
+ exit = 1
+ if (statReg>>1)&1 == 1:
+ print "Block lock bit detected"
+ exit = 1
+ if exit == 1:
+ sys.exit()
+
+ def erase_block(self,blockNo):
+ blockAddress = blockNo << 16
+ command = 0x0020
+ self.set_address(blockAddress)
+ self.write_command(command) #issue block erase
+ command = 0x00D0
+ self.write_command(command) #issue block erase confirm
+ #self.wait_on_busy()
+ #self.parse_status()
+
+ def buffer_write_ram(self,startAddress,word_buf):
+ wordsWritten = 0
+ length = len(word_buf) # get the byte count
+ #print "block write request for word cnt= %i"%(length//2)
+ if length == 65536*2:
+ #print "block write word cnt = 65536"
+ adrBuf = self.get_address_buf(startAddress+wordsWritten) #6 bytes total
+ cmd_e8="" #8 bytes total
+ cmd_e8+= chr(0) #write word count 0 is 64K words
+ cmd_e8+= chr(0xE9)
+ buffer = adrBuf+cmd_e8 #prepare command
+ #i=0
+ #while i<65536*2:
+ # buffer = buffer + word_buf[wordsWritten*2+i+1]+word_buf[wordsWritten*2+i]
+ # i=i+2
+ #print "block write buffer size = %i"%(len(word_buf[:wordsWritten*2+65536*2]))
+ buffer = buffer + word_buf[0:wordsWritten*2+65536*2]
+ self.tty.write(buffer)
+ wordsWritten = wordsWritten + 65536 - 2 #two last words are written brokenly bu large block write
+ length = length - 65536*2 + 4 # this amout has been written (two last words are written brokenly bu large block write)
+ if length >= 32: # can't write in one go so we must loop the code
+ while length>=32: #if we have atleast 32 bytes
+ cmd_e8="" #8 bytes total
+ adrBuf = self.get_address_buf(startAddress+wordsWritten) #6 bytes total
+ #print "block write word cnt = 16"
+ cmd_e8+= chr(16) #write word count 16 is 32 bytes
+ cmd_e8+= chr(0xE9)
+ buffer = adrBuf + cmd_e8 #prepare command
+ #i=0
+ #while i<32:
+ # #print "Adding to write buffer %02x%02x"%(ord(word_buf[i+1]),ord(word_buf[i]))
+ # buffer = buffer + word_buf[wordsWritten*2+i+1]+word_buf[wordsWritten*2+i]
+ # i=i+2
+ #print "block write buffer size = %i"%(len(word_buf[wordsWritten*2:wordsWritten*2+32]))
+ buffer = buffer + word_buf[wordsWritten*2:wordsWritten*2+32]
+ self.tty.write(buffer) #ok buffer is filled
+ wordsWritten = wordsWritten + 16
+ length = length - 32 # this amout has been written
+ #and finally deal with smaller writes than 64K or 16 word blocks
+ if length%2==1: #uneven byte count given we must add one byte of padding
+ print "uneaven write byte count, length = %i padding the end with extra byte 0xff "%(length)
+ word_buf=word_buf+chr(0xFF)
+ if length > 0:
+ #print "block write tail word cnt= %i"%(length//2+length%2)
+ adrBuf = self.get_address_buf(startAddress+wordsWritten) #6 bytes total
+ cmd_e8="" #8 bytes total
+ cmd_e8+= chr(length//2+length%2) #write word count 0 is 64K words
+ cmd_e8+= chr(0xE9)
+ buffer = adrBuf + cmd_e8
+ #i=0
+ #while i>1 #make word address
+ try:
+ f=open(mode.filename,"rb")
+ f.seek(0,2) #seek to end
+ size = f.tell()
+ f.seek(0) #seek to start
+ print 'File size %iK '%(size/1024)
+ f.close()
+ except IOError:
+ print "IO Error on file open. File missing or no premission to open."
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+
+ if mode.eof==1:
+ if (size&1==1):
+ mode.oddSize = 1
+ region_size_w = 0x200000 # 4M region word count
+ #print "Given region size = %i bytes"%(region_size_w*2)
+ file_size_w = (size+ (size&1))>> 1
+ #print "Given file size = %i bytes"%(file_size_w*2)
+ mode.address = region_size_w - file_size_w
+ print "Offset will be 0x%x"%(mode.address*2)
+
+
+ #clear blockLock bits
+ don.write_command(0x0060) # 0x0098
+ don.write_command(0x00D0) # 0x0098
+ if mode.version < 5:
+ don.wait_on_busy()
+ don.parse_status()
+ wordSize = (size+ (size&1))>> 1 # round byte count up and make word address
+ endBlock = don.get_block_no(mode.address+wordSize - 1)
+ startBlock = don.get_block_no(mode.address)
+ if endBlock >= 32:
+ print "Given file does not fit into remaining space. File size is %i KB"%(size/1024)
+ print "Space left from given offset is %i KB"%((4*1024*1024-mode.address*2)/1024)
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ i=startBlock
+ print 'Erasing from block %i to %i '%(i,endBlock)
+ while i <= endBlock:
+ if mode.v == 1:
+ print 'Erasing block %i '%(i)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ don.erase_block(i)
+ if mode.version < 5:
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ i=i+1
+ if mode.v == 0:
+ print " "
+ f=open(mode.filename,"rb")
+ f.seek(0) #seek to start
+ address= mode.address
+ #don.set_address(address)
+ print 'Writing %iK'%(size/1024)
+ while 1:
+ if (address/(1024*64) != (address-16)/(1024*64)) and address != mode.address: # get bytes from words if 512
+ if mode.v == 1:
+ print 'Progress: %iK of %iK at 0x%06x'%((address-mode.address)/512,size/1024,address)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ if mode.oddSize==1 or mode.oddAddr==1:
+ mode.oddSize = 0 # odd file size when writing BIOS to the end of region should be also front padded
+ mode.oddAddr = 0 # as odd address is shifted right padding should be added in front of data
+ buf = "\xFF"+f.read(31) #16 words is maximum write here bytes are read
+ else:
+ buf = f.read(32) #16 words is maximum write here bytes are read
+
+ if len(buf)==32:
+ don.buffer_write(16,address,buf)
+ address = address + 16
+ elif len(buf)>0:
+ don.parse_status() #do this after programming all but uneaven ending
+ print "Doing an unaligned write..."
+ length = len(buf)
+ length = (length + (length&1))>> 1 #round up to get even word count
+ buf = buf+"\xff" #pad just in case rounding took place
+ don.buffer_write(len,address,buf)
+ address = address + 16 #inc word address
+ break
+ else:
+ break
+ if mode.v == 0:
+ print " "
+ if mode.version >= 5:
+ print "Waiting for buffers to empty"
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ print "Write DONE!"
+ don.parse_status() #do this after programming all but uneaven ending
+ f.close()
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+
+
+
+def psram_write(mode,don):
+ #Calculate number of blocks and start of blocks
+ size = 0
+ if mode.address&1 == 1:
+ mode.oddAddr=1
+ mode.address = mode.address>>1 #make word address
+ #check that file exists
+ try:
+ f=open(mode.filename,"rb")
+ f.seek(0,2) #seek to end
+ size = f.tell()
+ f.seek(0) #seek to start
+ print 'File size %iK '%(size/1024)
+ f.close()
+ except IOError:
+ print "IO Error on file open. File missing or no premission to open."
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+
+ if mode.eof==1:
+ if (size&1==1):
+ mode.oddSize = 1 # deal with odd file sizes
+ region_size_w = 0x200000 # 4M region word count
+ #print "Given region size = %i bytes"%(region_size_w*2)
+ file_size_w = (size+ (size&1))>> 1
+ #print "Given file size = %i bytes"%(file_size_w*2)
+ mode.address = region_size_w - file_size_w
+ print "Offset will be 0x%x"%(mode.address*2)
+
+
+ #check that file size fits to remaining space given
+ wordSize = (size+ (size&1))>> 1 # round byte count up and make word address
+ endBlock = don.get_block_no(mode.address+wordSize - 1)
+ startBlock = don.get_block_no(mode.address)
+ if endBlock >= 32:
+ print "Given file does not fit into remaining space. File size is %i KB"%(size/1024)
+ print "Space left from given offset is %i KB"%((4*1024*1024-mode.address*2)/1024)
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ i=startBlock
+ #Start writing the file content to dongle PSRAM
+ f=open(mode.filename,"rb")
+ f.seek(0) #seek to start
+ address= mode.address
+ #don.set_address(address)
+ print 'Writing %iK'%(size/1024)
+ while 1:
+ if (address/(1024*64) != (address-16)/(1024*64)) and address != mode.address: # get bytes from words if 512
+ if mode.v == 1:
+ print 'Progress: %iK of %iK at 0x%06x'%((address-mode.address)/512,size/1024,address)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ if mode.oddSize==1 or mode.oddAddr==1:
+ mode.oddSize = 0
+ mode.oddAddr = 0
+ buf = "\xFF"+f.read(65536*2-1) #65536 words is maximum write here bytes are read (*2 is byte count)
+ else:
+ buf = f.read(65536*2) #65536 words is maximum write here bytes are read (*2 is byte count)
+
+ if len(buf)==65536*2:
+ don.buffer_write_ram(address,buf)
+ address = address + 65536 # add word count
+ elif len(buf)>0:
+ print "Doing an unaligned write..."
+ length = len(buf)
+ don.buffer_write_ram(address,buf)
+ address = address + length//2 #inc word address
+ break
+ else:
+ break
+ if mode.v == 0:
+ print " "
+ print "Write DONE!"
+ f.close()
+
+
+def flash_read(mode,don):
+ if mode.offset!=-1 and mode.length!=-1 and mode.filename!="":
+ if mode.version >= 5:
+ ##################### from hw ver 5 readback code ##################################################
+ blockCount = (mode.length>>17)+1 #read this many 64K word blocks
+ mode.offset=mode.offset>>1 #make word offset
+ lastLength = mode.length&0x0001FFFF
+ mode.length= mode.length>>1 #make word length
+ if mode.length < 512:
+ print 'Reading %i bytes in single block '%(lastLength)
+ else:
+ print 'Reading %iK '%(mode.length/512)
+ don.write_command(0x00FF) # put flash to data read mode
+ try:
+ f=open(mode.filename,"wb") #if this fails no point in reading as there is nowhere to write
+ address = mode.offset # set word address
+ don.set_address(address)
+ i=0
+ while (i>1 #make word offset
+ mode.length= mode.length>>1 #make word length
+ print 'Reading %iK'%(mode.length/512)
+ try:
+ f=open(mode.filename,"wb")
+ don.write_command(0x00FF) # put flash to data read mode
+ address = mode.offset # set word address
+ while 1:
+ if address/(1024*32) != (address-128)/(1024*32): # get K bytes from words if 512
+ if mode.v == 1:
+ print 'Progress: %iK of %iK'%((address-mode.offset)/512,mode.length/512)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ buf=don.read_data(128,address) # word count and byte address read 64 words to speed up
+ f.write(buf)
+ #print "from address:",address<<1," ", len(buf)
+ if address+128 >= (mode.offset + mode.length): # 2+64 estimates the end to end in right place
+ break
+ address = address + 128 #this is word address
+ f.close()
+ if mode.v == 0:
+ print " "
+ print "Readback done!"
+ except IOError:
+ print "IO Error on file open"
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ ##################### end before hw ver 5 readback code ################################################
+ else:
+ print "Some of readback parameters missing..."
+ print mode.offset,mode.length, mode.filename
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+
+
+def psram_read(mode,don):
+ if mode.offset!=-1 and mode.length!=-1 and mode.filename!="":
+ if mode.version > 5: #should never be smaller here
+ blockCount = (mode.length>>17)+1 #read this many 64K word blocks
+ mode.offset=mode.offset>>1 #make word offset
+ lastLength = mode.length&0x0001FFFF
+ mode.length= mode.length>>1 #make word length
+ if mode.length < 512:
+ print 'Reading %i bytes in single block '%(lastLength)
+ sys.stdout.flush()
+ else:
+ print 'Reading %iK'%(mode.length/512)
+ sys.stdout.flush()
+ try:
+ f=open(mode.filename,"wb") #if this fails no point in reading as there is nowhere to write
+ address = mode.offset # set word address
+ don.set_address(address)
+ i=0
+ while (i>1) # word count and word address
+
+ print 'Data: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x '%(ord(buf[1]),ord(buf[0]),ord(buf[3]),ord(buf[2]),ord(buf[5]),ord(buf[4]),ord(buf[7]),ord(buf[6]) )
+
+
+def flash_test(mode,don):
+ print "FLASH TEST"
+ test_status = 1
+ if mode.e == 1:
+ #Erase Dongle
+ print "Erasing"
+ don.write_command(0x0060) # 0x0098
+ don.write_command(0x00D0) # 0x0098
+ don.wait_on_busy()
+ don.parse_status()
+ endBlock = 31
+ startBlock = 0
+ i=startBlock
+ while i <= endBlock:
+ if mode.v == 1:
+ print 'Erasing block %i '%(i)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ don.erase_block(i)
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ i=i+1
+ if mode.v == 0: # add CRTL return to dots
+ print ""
+ #Do marching one test on data and address
+ mode.length= 0 #make word length
+ don.write_command(0x00FF) # put flash to data read mode
+ buf2=don.read_data(1,0) #read first byte
+ if ord(buf2[0]) != 0xFF:
+ print "Can't run FLASH TEST on unerased flash first byte is 0x%02x"%(ord(buf2[0]))
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ try:
+ #Marching one test
+ print "Single bit high test on addr and data"
+ #---------------------------------------------------------------------------
+ address = 0x100000 # set word address
+ data = 0x100000
+ while mode.length<20: # last address to test 0x20 0000
+ buf1=pack('BBBB', (0x000000FF&data),(0x0000FF00&data)>>8 ,(0x00FF0000&data)>>16 ,(0xFF0000&data)>>24 )
+ don.buffer_write(2,address,buf1)
+ don.parse_status() #do this after programming all but uneaven ending
+ don.write_command(0x00FF) # put flash to data read mode
+ buf2=don.read_data(2,address) # word count and byte address read 64 words to speed up
+ if buf1 != buf2:
+ print 'IN %02x %02x %02x %02x '%(ord(buf1[3]), ord(buf1[2]),ord(buf1[1]), ord(buf1[0]))
+ print 'OUT %02x %02x %02x %02x '%(ord(buf2[3]), ord(buf2[2]),ord(buf2[1]), ord(buf2[0]))
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Data written = 0x%08x"%(data&0xFFFF)
+ print "Test FAIL!!!!!"
+ test_status = 0
+ buf2=don.read_data(1,0) #read first byte
+ if ord(buf2[0]) != 0xFF:
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Test FAIL (Used address line probably const. 0)!"
+ test_status = 0
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ address = address >> 1
+ if address == 0x2:
+ address = address >> 1 # 0x2 is written and will return zero on read as write new write will fail
+ data = data >> 1
+ mode.length = mode.length + 1
+
+ #-----------------------------------------------------------------------
+ #Marching zero test
+ print "Single bit low test on addr and data"
+ address = 0xFFEFFFFF # set word address
+ data = 0xFFEFFFFF
+ while mode.length<18: # last address to test 0x20 0000
+ buf1=pack('BBBB', (0x000000FF&data),(0x0000FF00&data)>>8 ,(0x00FF0000&data)>>16 ,(0xFF0000&data)>>24 )
+ don.buffer_write(2,address,buf1)
+ don.parse_status() #do this after programming all but uneaven ending
+ don.write_command(0x00FF) # put flash to data read mode
+ buf2=don.read_data(2,address&0x1FFFFF) # word count and byte address read 64 words to speed up
+ if buf1 != buf2:
+ print 'IN %02x %02x %02x %02x '%(ord(buf1[3]), ord(buf1[2]),ord(buf1[1]), ord(buf1[0]))
+ print 'OUT %02x %02x %02x %02x '%(ord(buf2[3]), ord(buf2[2]),ord(buf2[1]), ord(buf2[0]))
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Data written = 0x%08x"%(data&0xFFFF)
+ print "Test FAIL!!!!!"
+ print "Test FAIL!!!!!"
+ test_status = 0
+ buf2=don.read_data(1,0x1FFFFF) #read first byte
+ if ord(buf2[0]) != 0xFF:
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Test FAIL (At used address line const. 1 or lines bonded)!"
+ test_status = 0
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ address = (address >> 1)|0xFF000000
+ data = data >> 1
+ mode.length = mode.length + 1
+ if mode.b == 1:
+ #Erase Dongle
+ print "Erasing"
+ don.write_command(0x0060) # 0x0098
+ don.write_command(0x00D0) # 0x0098
+ don.wait_on_busy()
+ don.parse_status()
+ endBlock = 31
+ startBlock = 0
+ i=startBlock
+ while i <= endBlock:
+ if mode.v == 1:
+ print 'Blanking block %i '%(i)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ don.erase_block(i)
+ if mode.version < 5:
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ i=i+1
+ if mode.v == 0:
+ print " "
+ if test_status == 1:
+ print "Test SUCCESSFUL!"
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ except IOError:
+ print "IO Error on file open"
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+
+def psram_test(mode,don):
+ print "PSRAM TEST"
+ test_status = 1
+ #Do marching one test on data and address
+ mode.length= 0 #make word length
+ try:
+ print "Single bit high test on addr and data"
+ #---------------------------------------------------------------------------
+ address = 0x100000 # set word address
+ data = 0x100000
+ don.buffer_write_ram(0,"\xFF\xFF") #init PSRAM
+ while mode.length<20: # last address to test 0x20 0000
+ buf1=pack('BBBB', (0x000000FF&data),(0x0000FF00&data)>>8 ,(0x00FF0000&data)>>16 ,(0xFF0000&data)>>24 )
+ don.buffer_write_ram(address,buf1)
+ buf2=don.read_data(2,address) # word count and byte address read 64 words to speed up
+ if buf1 != buf2:
+ print 'IN %02x %02x %02x %02x '%(ord(buf1[3]), ord(buf1[2]),ord(buf1[1]), ord(buf1[0]))
+ print 'OUT %02x %02x %02x %02x '%(ord(buf2[3]), ord(buf2[2]),ord(buf2[1]), ord(buf2[0]))
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Data written = 0x%08x"%(data&0xFFFF)
+ print "Test due to data FAIL!!!!!"
+ test_status=0
+ buf2=don.read_data(1,0) #read first byte
+ if ord(buf2[0]) != 0xFF:
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Test FAIL (At least one address line const. 0)!!!!!"
+ test_status=0
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ address = address >> 1
+ if address == 0x2:
+ address = address >> 1 # 0x2 is written and will return zero on read as write new write will fail
+ data = data >> 1
+ mode.length = mode.length + 1
+
+ #-----------------------------------------------------------------------
+ #Marching zero test
+ print "Single bit low test on addr and data"
+ address = 0xFFEFFFFF # set word address
+ data = 0xFFEFFFFF
+ while mode.length<18: # last address to test 0x20 0000
+ buf1=pack('BBBB', (0x000000FF&data),(0x0000FF00&data)>>8 ,(0x00FF0000&data)>>16 ,(0xFF0000&data)>>24 )
+ don.buffer_write_ram(address&0x1FFFFF,buf1)
+ buf2=don.read_data(2,address&0x1FFFFF) # word count and byte address read 64 words to speed up
+ if buf1 != buf2:
+ print 'IN %02x %02x %02x %02x '%(ord(buf1[3]), ord(buf1[2]),ord(buf1[1]), ord(buf1[0]))
+ print 'OUT %02x %02x %02x %02x '%(ord(buf2[3]), ord(buf2[2]),ord(buf2[1]), ord(buf2[0]))
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Data written = 0x%08x"%(data&0xFFFF)
+ print "Test FAIL!!!!!"
+ test_status=0
+ buf2=don.read_data(1,0x1FFFFF) #read first byte
+ if ord(buf2[0]) != 0xFF:
+ print "Address used = 0x%08x"%(address&0x1FFFFF)
+ print "Test FAIL (At used address least two address lines bonded or const. 1)!"
+ test_status=0
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ address = (address >> 1)|0xFF000000
+ data = data >> 1
+ mode.length = mode.length + 1
+ if test_status==1:
+ print "Test SUCCESSFUL!"
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+ except IOError:
+ print "IO Error on file open"
+ don.write_command(0xC6C5) #clear lock bit
+ ret_buf=don.getReturn(2) #two bytes expected to this command
+ sys.exit()
+
+def flash_erase(mode,don):
+ #Erase Dongle
+ print "Erasing all"
+ don.write_command(0x0060) # 0x0098
+ don.write_command(0x00D0) # 0x0098
+ if mode.version < 5:
+ don.wait_on_busy()
+ don.parse_status()
+ endBlock = 31
+ startBlock = 0
+ i=startBlock
+ while i <= endBlock:
+ if mode.v == 1:
+ print 'Erasing block %i '%(i)
+ else:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ don.erase_block(i)
+ if mode.version < 5:
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ i=i+1
+ if mode.v == 0: # add CRTL return to dots
+ print ""
+ if mode.version >= 5:
+ print "Waiting for buffers to empty"
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ print "Erase done."
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+def flash_looptest(mode,don):
+ print "Status Loop test"
+ i=1024
+ startTime = time.clock()
+ while i > 0:
+ if i%128==0:
+ sys.stdout.write(".")
+ sys.stdout.flush()
+ don.wait_on_busy()
+ don.parse_status() #do this after programming all but uneaven ending
+ i=i-1
+ #if sys.platform=='win32':
+ endTime = (time.clock()-startTime)/1024.0
+ print "\nSystem round delay is %4f ms"%(endTime*1000.0)
+ sys.stdout.flush()
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+
+################## Main program #########################
+
+
+last_ops = 0
+mode = DongleMode()
+# PARSE ARGUMENTS
+for arg in sys.argv:
+ if len(sys.argv) == 1: # if no arguments display help
+ #usage(sys.argv[0])
+ usage("dongle.py")
+ sys.exit()
+ if arg in ("-h","--help","/help","/h"):
+ #usage(sys.argv[0])
+ usage("dongle.py")
+ sys.exit()
+ if arg in ("-c"):
+ last_ops = sys.argv.index(arg) + 1 #if remains last set of options from here start ordered strings
+ i = sys.argv.index(arg)
+ print "Opening port: "+sys.argv[i+1]
+ mode.portname = sys.argv[i+1] # next element after -c open port for usage
+ if arg[0]=="-" and arg[1]!="c": # if other opptions
+ # parse all options in this
+ last_ops = sys.argv.index(arg) #if remains last set of options from here start ordered strings
+ ops = arg[1:]# get all besides the - sign
+ for op in ops:
+ if op=="q":
+ mode.q = 1
+ if op=="v":
+ mode.v = 1
+ if op=="f":
+ mode.f = 1
+ if op=="d":
+ mode.d = 1
+ if op=="r":
+ mode.r = 1
+ if op=="t":
+ mode.t = 1
+ if op=="e":
+ mode.e = 1
+ if op=="b":
+ mode.b = 1
+ if op=="l":
+ mode.l = 1
+ if op=="p":
+ mode.p = 0
+ if op=="P":
+ mode.p = 1
+ if op=="u":
+ mode.u = 1
+ else:
+ i = sys.argv.index(arg)
+ if i == last_ops + 1:
+ if mode.r==1:
+ mode.offset=mode.convParamStr(arg)
+ else:
+ mode.filename=arg
+ if i == last_ops + 2:
+ if mode.r==1:
+ mode.length=mode.convParamStr(arg)
+ else:
+ if arg.find("EOF")>-1:
+ print "Found EOF marker"
+ mode.eof = 1 #the file is to be written to the end of 4M area
+ mode.address = 0
+ else:
+ mode.address=mode.convParamStr(arg)
+
+ if i == last_ops + 3:
+ if mode.r==1:
+ mode.filename=arg
+ else:
+ print "Too many parameters provided"
+ sys.exit()
+ if i > last_ops + 3:
+ print "Too many parameters provided"
+ sys.exit()
+
+# END PARSE ARGUMENTS
+
+if mode.portname=="":
+ print "No port name given see -h for help"
+ sys.exit()
+else:
+ # test PC speed to find sutable delay for linux driver
+ # to get 250 us
+ mytime = time.clock()
+ n = 0
+ while (n < 100000):
+ n += 1;
+ k10Time = time.clock() - mytime # time per 10000 while cycles
+ wait = k10Time/100000.0 # time per while cycle
+ wait = (0.00025/wait) * 1.20 # count for 250us + safe margin
+ # ok done
+ reopened = 0
+
+
+ if sys.platform=='win32':
+ don = Dongle(mode.portname,256000,6000)
+ elif sys.platform=='linux2':
+ don = Dongle(mode.portname,230400,6000)
+ #don.tty.cts()
+ elif sys.platform=='darwin':
+ don = Dongle(mode.portname,230400,6000)
+ #don.tty.cts()
+ else:
+ sys.exit('Sorry, no implementation for this platform yet')
+
+
+ don.tty.wait = wait
+ while 1:
+ #don.write_command(0x0050) #FLASH command clear status register
+ don.write_command(0x00C5) #send dongle check internal command
+ don_ret=don.testReturn(2)
+ if don_ret==2:
+ break
+ if reopened == 3:
+ print 'Dongle connected, but does not communicate'
+ sys.exit()
+ reopened = reopened + 1
+ # reopen and do new cycle
+ if sys.platform=='win32':
+ don = Dongle(mode.portname,256000,6000)
+ elif sys.platform=='linux2':
+ don = Dongle(mode.portname,230400,6000)
+ #self.tty.cts()
+ elif sys.platform=='darwin':
+ don = Dongle(mode.portname,230400,6000)
+ #self.tty.cts()
+ else:
+ sys.exit('Sorry, no implementation for this platform yet')
+ don.tty.wait = wait
+
+ buf=don.getReturn(2) # two bytes expected to this command
+ if ord(buf[1])==0x32 and ord(buf[0])==0x10:
+ print "Dongle OK"
+ else:
+ print 'Dongle returned on open: %02x %02x '%(ord(buf[1]), ord(buf[0]))
+ don.write_command(0x01C5) #try getting dongle HW ver (works since 05 before that returns 0x3210)
+ buf=don.getReturn(2) # two bytes expected to this command
+ if ord(buf[1])==0x86 and ord(buf[0])>0x04:
+ mode.version = ord(buf[0])
+ don.mode = mode
+ print 'Dongle HW version code is %02x %02x'%(ord(buf[1]), ord(buf[0]))
+
+ print 'Dongle version is %x'%(mode.version)
+ else:
+ don.mode = mode
+ print 'Dongle HW version code is smaller than 05 some features have been improved on'
+ print 'HW code and Quartus FPGA binary file are available at:'
+ print 'http://www.opencores.org/projects.cgi/web/usb_dongle_fpga/overview'
+ print 'Programming is possible with Altera Quartus WE and BYTEBLASTER II cable or'
+ print 'compatible clone like X-Blaster http://www.customcircuitsolutions.com/cable.html'
+
+ if mode.version>0x19: # Dongle II versions
+ print 'Other status info:'
+ if mode.p == 0:
+ don.write_command(0xC3C5) # ldev_present_n set to 0 (is active low for thincan)
+ buf_dc = don.getReturn(2) # two bytes expected to this command
+ else:
+ don.write_command(0xC4C5) # ldev_present_n set to 1 (is active low for thincan)
+ buf_dc = don.getReturn(2) # two bytes expected to this command
+ if mode.u == 1:
+ don.write_command(0xC2C5) # force USB prog mode signals to conf memory
+ #buf_dc = don.getReturn(2) # two bytes expected to this command
+ sys.exit()
+ don.write_command(0x02C5) #try getting PCB ver (works since 06 before that returns 0x3210)
+ buf=don.getReturn(2) # two bytes expected to this command
+ i_temp = 0
+ i_temp = (ord(buf[1])<<8)|ord(buf[0])
+ print 'Dongle PCB version code is AD 67075%05i'%( i_temp )
+ don.write_command(0x03C5) #try getting mode switch setting (works since 06 before that returns 0x3210)
+ buf=don.getReturn(2) # two bytes expected to this command
+ mode_reg = ord(buf[0])
+ print 'Dongle memory region %02x'%(mode_reg)
+ if ord(buf[1])==0x00:
+ if ord(buf[0]) > 3:
+ print 'PSRAM region selected'
+ else:
+ print 'FLASH region selected'
+ mode.region = mode_reg #set the region for PSRAM support
+ if mode.region>3:
+ pass
+ #print 'Initialize psram on region %i'%(mode.region)
+ #PSRAM mode init
+ else:
+ #print 'Initialize flash on region %i'%(mode.region)
+ don.write_command(0x0050) #FLASH command clear status register
+ don.write_command(0x00FF) # 0x0098 --set flash to read array mode
+ #Flash mode init
+
+#Lock LPC out from memory interface
+don.write_command(0xC5C5) #set lock bit up
+ret_buf=don.getReturn(2) #two bytes expected to this command
+
+if mode.q == 1: # perform a query from dongle
+ if mode.region<4:
+ flash_qry(mode,don)
+ else:
+ print "Query only supported on flash regions (to change region turn the Mode switch):"
+ print "FLASH regions are regions from 0 to 3"
+
+
+if mode.filename!="" and mode.address!=-1: #Dongle write command given
+ if mode.region<4:
+ print "Flash write called"
+ flash_write(mode,don)
+ else:
+ print "PSRAM write called"
+ psram_write(mode,don)
+
+if mode.r == 1: # perform a readback
+ if mode.region<4:
+ print "Flash read called"
+ flash_read(mode,don)
+ else:
+ print "PSRAM read called"
+ psram_read(mode,don)
+
+if mode.t == 1: # perform dongle test
+ if mode.region<4:
+ flash_test(mode,don)
+ else:
+ psram_test(mode,don)
+if mode.e == 1: # perform dongle erase
+ if mode.region<4:
+ flash_erase(mode,don)
+ else:
+ print "Erase is supported on flash regions (to change region turn the Mode switch):"
+ print "FLASH regions are regions from 0 to 3"
+
+if mode.l == 1: # perform dongle test
+ if mode.region<4:
+ flash_looptest(mode,don)
+ else:
+ print "Looptest is supported on flash regions (to change region turn the Mode switch):"
+ print "FLASH regions are regions from 0 to 3"
+
+##########################################################
+
+#Unlock memory interface
+don.write_command(0xC6C5) #clear lock bit
+ret_buf=don.getReturn(2) #two bytes expected to this command
+sys.exit()
+
+
Index: tags/google_release_of_0x20_firmware/sw/AUTHORS
===================================================================
--- tags/google_release_of_0x20_firmware/sw/AUTHORS (nonexistent)
+++ tags/google_release_of_0x20_firmware/sw/AUTHORS (revision 3)
@@ -0,0 +1,9 @@
+LPC dongle script
+ Jüri Toomessoo
+
+Uspp inlined library
+ Isaac Barona Martínez Madrid (SPAIN)
+ Damien Géranton
+ Douglas Jones
+ J.Grauheding
+ Stefan Reinauer (MAC OS X support)
\ No newline at end of file
Index: tags/google_release_of_0x20_firmware/sw/Copyright
===================================================================
--- tags/google_release_of_0x20_firmware/sw/Copyright (nonexistent)
+++ tags/google_release_of_0x20_firmware/sw/Copyright (revision 3)
@@ -0,0 +1,44 @@
+LPC Dongle script dongle.py
+
+Copyright (C) 2008 Artec Design
+
+This library is free software; you can redistribute it and/or
+modify it under the terms of the GNU Lesser General Public
+License as published by the Free Software Foundation; either
+version 2.1 of the License, or (at your option) any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public
+License along with this library; if not, write to the Free Software
+Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+The complete text of the GNU Lesser General Public License can be found in
+the file 'lesser.txt'.
+
+
+Inlined USPP Library (Universal Serial Port Python Library)
+
+Copyright (C) 2006 Isaac Barona Martínez
+
+This library is free software; you can redistribute it and/or
+modify it under the terms of the GNU Lesser General Public
+License as published by the Free Software Foundation; either
+version 2.1 of the License, or (at your option) any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public
+License along with this library; if not, write to the Free Software
+Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+The complete text of the GNU Lesser General Public License can be found in
+the file 'lesser.txt'.
Index: tags/google_release_of_0x20_firmware/sw/lesser.txt
===================================================================
--- tags/google_release_of_0x20_firmware/sw/lesser.txt (nonexistent)
+++ tags/google_release_of_0x20_firmware/sw/lesser.txt (revision 3)
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
+ordinary GNU General Public License. This license, the GNU Lesser
+General Public License, applies to certain designated libraries, and
+is quite different from the ordinary General Public License. We use
+this license for certain libraries in order to permit linking those
+libraries into non-free programs.
+
+ When a program is linked with a library, whether statically or using
+a shared library, the combination of the two is legally speaking a
+combined work, a derivative of the original library. The ordinary
+General Public License therefore permits such linking only if the
+entire combination fits its criteria of freedom. The Lesser General
+Public License permits more lax criteria for linking other code with
+the library.
+
+ We call this license the "Lesser" General Public License because it
+does Less to protect the user's freedom than the ordinary General
+Public License. It also provides other free software developers Less
+of an advantage over competing non-free programs. These disadvantages
+are the reason we use the ordinary General Public License for many
+libraries. However, the Lesser license provides advantages in certain
+special circumstances.
+
+ For example, on rare occasions, there may be a special need to
+encourage the widest possible use of a certain library, so that it becomes
+a de-facto standard. To achieve this, non-free programs must be
+allowed to use the library. A more frequent case is that a free
+library does the same job as widely used non-free libraries. In this
+case, there is little to gain by limiting the free library to free
+software only, so we use the Lesser General Public License.
+
+ In other cases, permission to use a particular library in non-free
+programs enables a greater number of people to use a large body of
+free software. For example, permission to use the GNU C Library in
+non-free programs enables many more people to use the whole GNU
+operating system, as well as its variant, the GNU/Linux operating
+system.
+
+ Although the Lesser General Public License is Less protective of the
+users' freedom, it does ensure that the user of a program that is
+linked with the Library has the freedom and the wherewithal to run
+that program using a modified version of the Library.
+
+ The precise terms and conditions for copying, distribution and
+modification follow. Pay close attention to the difference between a
+"work based on the library" and a "work that uses the library". The
+former contains code derived from the library, whereas the latter must
+be combined with the library in order to run.
+
+ GNU LESSER GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License Agreement applies to any software library or other
+program which contains a notice placed by the copyright holder or
+other authorized party saying it may be distributed under the terms of
+this Lesser General Public License (also called "this License").
+Each licensee is addressed as "you".
+
+ A "library" means a collection of software functions and/or data
+prepared so as to be conveniently linked with application programs
+(which use some of those functions and data) to form executables.
+
+ The "Library", below, refers to any such software library or work
+which has been distributed under these terms. A "work based on the
+Library" means either the Library or any derivative work under
+copyright law: that is to say, a work containing the Library or a
+portion of it, either verbatim or with modifications and/or translated
+straightforwardly into another language. (Hereinafter, translation is
+included without limitation in the term "modification".)
+
+ "Source code" for a work means the preferred form of the work for
+making modifications to it. For a library, complete source code means
+all the source code for all modules it contains, plus any associated
+interface definition files, plus the scripts used to control compilation
+and installation of the library.
+
+ Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running a program using the Library is not restricted, and output from
+such a program is covered only if its contents constitute a work based
+on the Library (independent of the use of the Library in a tool for
+writing it). Whether that is true depends on what the Library does
+and what the program that uses the Library does.
+
+ 1. You may copy and distribute verbatim copies of the Library's
+complete source code as you receive it, in any medium, provided that
+you conspicuously and appropriately publish on each copy an
+appropriate copyright notice and disclaimer of warranty; keep intact
+all the notices that refer to this License and to the absence of any
+warranty; and distribute a copy of this License along with the
+Library.
+
+ You may charge a fee for the physical act of transferring a copy,
+and you may at your option offer warranty protection in exchange for a
+fee.
+
+ 2. You may modify your copy or copies of the Library or any portion
+of it, thus forming a work based on the Library, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) The modified work must itself be a software library.
+
+ b) You must cause the files modified to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ c) You must cause the whole of the work to be licensed at no
+ charge to all third parties under the terms of this License.
+
+ d) If a facility in the modified Library refers to a function or a
+ table of data to be supplied by an application program that uses
+ the facility, other than as an argument passed when the facility
+ is invoked, then you must make a good faith effort to ensure that,
+ in the event an application does not supply such function or
+ table, the facility still operates, and performs whatever part of
+ its purpose remains meaningful.
+
+ (For example, a function in a library to compute square roots has
+ a purpose that is entirely well-defined independent of the
+ application. Therefore, Subsection 2d requires that any
+ application-supplied function or table used by this function must
+ be optional: if the application does not supply it, the square
+ root function must still compute square roots.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Library,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Library, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Library.
+
+In addition, mere aggregation of another work not based on the Library
+with the Library (or with a work based on the Library) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may opt to apply the terms of the ordinary GNU General Public
+License instead of this License to a given copy of the Library. To do
+this, you must alter all the notices that refer to this License, so
+that they refer to the ordinary GNU General Public License, version 2,
+instead of to this License. (If a newer version than version 2 of the
+ordinary GNU General Public License has appeared, then you can specify
+that version instead if you wish.) Do not make any other change in
+these notices.
+
+ Once this change is made in a given copy, it is irreversible for
+that copy, so the ordinary GNU General Public License applies to all
+subsequent copies and derivative works made from that copy.
+
+ This option is useful when you wish to copy part of the code of
+the Library into a program that is not a library.
+
+ 4. You may copy and distribute the Library (or a portion or
+derivative of it, under Section 2) in object code or executable form
+under the terms of Sections 1 and 2 above provided that you accompany
+it with the complete corresponding machine-readable source code, which
+must be distributed under the terms of Sections 1 and 2 above on a
+medium customarily used for software interchange.
+
+ If distribution of object code is made by offering access to copy
+from a designated place, then offering equivalent access to copy the
+source code from the same place satisfies the requirement to
+distribute the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 5. A program that contains no derivative of any portion of the
+Library, but is designed to work with the Library by being compiled or
+linked with it, is called a "work that uses the Library". Such a
+work, in isolation, is not a derivative work of the Library, and
+therefore falls outside the scope of this License.
+
+ However, linking a "work that uses the Library" with the Library
+creates an executable that is a derivative of the Library (because it
+contains portions of the Library), rather than a "work that uses the
+library". The executable is therefore covered by this License.
+Section 6 states terms for distribution of such executables.
+
+ When a "work that uses the Library" uses material from a header file
+that is part of the Library, the object code for the work may be a
+derivative work of the Library even though the source code is not.
+Whether this is true is especially significant if the work can be
+linked without the Library, or if the work is itself a library. The
+threshold for this to be true is not precisely defined by law.
+
+ If such an object file uses only numerical parameters, data
+structure layouts and accessors, and small macros and small inline
+functions (ten lines or less in length), then the use of the object
+file is unrestricted, regardless of whether it is legally a derivative
+work. (Executables containing this object code plus portions of the
+Library will still fall under Section 6.)
+
+ Otherwise, if the work is a derivative of the Library, you may
+distribute the object code for the work under the terms of Section 6.
+Any executables containing that work also fall under Section 6,
+whether or not they are linked directly with the Library itself.
+
+ 6. As an exception to the Sections above, you may also combine or
+link a "work that uses the Library" with the Library to produce a
+work containing portions of the Library, and distribute that work
+under terms of your choice, provided that the terms permit
+modification of the work for the customer's own use and reverse
+engineering for debugging such modifications.
+
+ You must give prominent notice with each copy of the work that the
+Library is used in it and that the Library and its use are covered by
+this License. You must supply a copy of this License. If the work
+during execution displays copyright notices, you must include the
+copyright notice for the Library among them, as well as a reference
+directing the user to the copy of this License. Also, you must do one
+of these things:
+
+ a) Accompany the work with the complete corresponding
+ machine-readable source code for the Library including whatever
+ changes were used in the work (which must be distributed under
+ Sections 1 and 2 above); and, if the work is an executable linked
+ with the Library, with the complete machine-readable "work that
+ uses the Library", as object code and/or source code, so that the
+ user can modify the Library and then relink to produce a modified
+ executable containing the modified Library. (It is understood
+ that the user who changes the contents of definitions files in the
+ Library will not necessarily be able to recompile the application
+ to use the modified definitions.)
+
+ b) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (1) uses at run time a
+ copy of the library already present on the user's computer system,
+ rather than copying library functions into the executable, and (2)
+ will operate properly with a modified version of the library, if
+ the user installs one, as long as the modified version is
+ interface-compatible with the version that the work was made with.
+
+ c) Accompany the work with a written offer, valid for at
+ least three years, to give the same user the materials
+ specified in Subsection 6a, above, for a charge no more
+ than the cost of performing this distribution.
+
+ d) If distribution of the work is made by offering access to copy
+ from a designated place, offer equivalent access to copy the above
+ specified materials from the same place.
+
+ e) Verify that the user has already received a copy of these
+ materials or that you have already sent this user a copy.
+
+ For an executable, the required form of the "work that uses the
+Library" must include any data and utility programs needed for
+reproducing the executable from it. However, as a special exception,
+the materials to be distributed need not include anything that is
+normally distributed (in either source or binary form) with the major
+components (compiler, kernel, and so on) of the operating system on
+which the executable runs, unless that component itself accompanies
+the executable.
+
+ It may happen that this requirement contradicts the license
+restrictions of other proprietary libraries that do not normally
+accompany the operating system. Such a contradiction means you cannot
+use both them and the Library together in an executable that you
+distribute.
+
+ 7. You may place library facilities that are a work based on the
+Library side-by-side in a single library together with other library
+facilities not covered by this License, and distribute such a combined
+library, provided that the separate distribution of the work based on
+the Library and of the other library facilities is otherwise
+permitted, and provided that you do these two things:
+
+ a) Accompany the combined library with a copy of the same work
+ based on the Library, uncombined with any other library
+ facilities. This must be distributed under the terms of the
+ Sections above.
+
+ b) Give prominent notice with the combined library of the fact
+ that part of it is a work based on the Library, and explaining
+ where to find the accompanying uncombined form of the same work.
+
+ 8. You may not copy, modify, sublicense, link with, or distribute
+the Library except as expressly provided under this License. Any
+attempt otherwise to copy, modify, sublicense, link with, or
+distribute the Library is void, and will automatically terminate your
+rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses
+terminated so long as such parties remain in full compliance.
+
+ 9. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Library or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Library (or any work based on the
+Library), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Library or works based on it.
+
+ 10. Each time you redistribute the Library (or any work based on the
+Library), the recipient automatically receives a license from the
+original licensor to copy, distribute, link with or modify the Library
+subject to these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties with
+this License.
+
+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Library at all. For example, if a patent
+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ , 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
+
+
Index: tags/google_release_of_0x20_firmware/sw/readme.txt
===================================================================
--- tags/google_release_of_0x20_firmware/sw/readme.txt (nonexistent)
+++ tags/google_release_of_0x20_firmware/sw/readme.txt (revision 3)
@@ -0,0 +1,15 @@
+Linux:
+On linux only python installation is needed
+and usually python is included.
+
+
+Windows:
+To use the python script on windows
+Python for Windows extensions have to be installed
+
+http://sourceforge.net/projects/pywin32
+
+
+The software also needs FT245B windows VCP driver
+http://www.ftdichip.com/Drivers/VCP.htm
+
Index: tags/google_release_of_0x20_firmware/beh/lpc_byte_test.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/beh/lpc_byte_test.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/beh/lpc_byte_test.vhd (revision 3)
@@ -0,0 +1,207 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:35:11 10/09/2006
+-- Design Name: lpc_iow
+-- Module Name: C:/projects/USB_dongle/beh/lpc_byte_test.vhd
+-- Project Name: simulation
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: lpc_iow
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY lpc_byte_test_vhd IS
+END lpc_byte_test_vhd;
+
+ARCHITECTURE behavior OF lpc_byte_test_vhd IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT lpc_iow
+ PORT(
+ lreset_n : IN std_logic;
+ lclk : IN std_logic;
+ lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ lena_reads : in std_logic; --enable read capabilities
+ lad_i : IN std_logic_vector(3 downto 0);
+ lframe_n : IN std_logic;
+ lpc_data_i : IN std_logic_vector(7 downto 0);
+ lpc_ack : IN std_logic;
+ lad_o : OUT std_logic_vector(3 downto 0);
+ lad_oe : OUT std_logic;
+ lpc_addr : OUT std_logic_vector(23 downto 0);
+ lpc_wr : OUT std_logic;
+ lpc_data_o : OUT std_logic_vector(7 downto 0);
+ lpc_val : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ SIGNAL lreset_n : std_logic := '0';
+ SIGNAL lclk : std_logic := '0';
+
+ SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
+
+ SIGNAL lframe_n : std_logic := '1';
+ SIGNAL lpc_ack : std_logic := '0';
+ SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
+ SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
+
+ --Outputs
+ SIGNAL lad_o : std_logic_vector(3 downto 0);
+ SIGNAL lad_oe : std_logic;
+ SIGNAL lpc_addr : std_logic_vector(23 downto 0);
+ SIGNAL lpc_wr : std_logic;
+ SIGNAL lpc_data_o : std_logic_vector(7 downto 0);
+ SIGNAL lpc_val : std_logic;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: lpc_iow PORT MAP(
+ lreset_n => lreset_n,
+ lclk => lclk,
+ lena_mem_r=> lena_mem_r,
+ lena_reads => lena_reads,
+ lad_i => lad_i,
+ lad_o => lad_o,
+ lad_oe => lad_oe,
+ lframe_n => lframe_n,
+ lpc_addr => lpc_addr,
+ lpc_wr => lpc_wr,
+ lpc_data_i => lpc_data_i,
+ lpc_data_o => lpc_data_o,
+ lpc_val => lpc_val,
+ lpc_ack => lpc_ack
+ );
+
+
+ clocker : process is
+ begin
+ wait for 15 ns;
+ lclk <=not (lclk);
+ end process clocker;
+
+
+ VCI_ACK : process is
+ begin
+ wait until lpc_val='1';
+ wait for 100 ns;
+ lpc_ack <='1';
+ wait until lpc_val='0';
+ lpc_ack <='0';
+ end process VCI_ACK;
+
+
+ tb : PROCESS
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 500 ns;
+ lreset_n <='1';
+ -- Place stimulus here
+ wait until lclk='0'; --cycle 1
+ wait until lclk='1';
+ lad_i <="0000";
+ lframe_n <='0';
+ wait until lclk='0'; --cycle 2
+ wait until lclk='1';
+ lad_i <="0010"; --LPC IO write
+ lframe_n <='1';
+ wait until lclk='0'; --cycle 3
+ wait until lclk='1';
+ lad_i <=x"0"; --address nibble 1
+ wait until lclk='0'; --cycle 4
+ wait until lclk='1';
+ lad_i <=x"0"; --address nibble 2
+ wait until lclk='0'; --cycle 5
+ wait until lclk='1';
+ lad_i <=x"8"; --address nibble 3
+ wait until lclk='0'; --cycle 6
+ wait until lclk='1';
+ lad_i <=x"0"; --address nibble 4
+ wait until lclk='0'; --cycle 7
+ wait until lclk='1';
+ lad_i <=x"A"; --data nibble 1
+ wait until lclk='0'; --cycle 8
+ wait until lclk='1';
+ lad_i <=x"5"; --data nibble 2
+ wait until lclk='0'; --cycle 9
+ wait until lclk='1';
+ lad_i <=x"F"; --TAR 1
+ wait until lclk='0'; --cycle 10
+ wait until lclk='1';
+ if lad_oe='0' then --TAR 2
+ else
+ report "LPC error found on TAR cycle no 0xF on lad_o";
+ lframe_n <='0';
+ end if;
+ wait until lclk='0'; --cycle 11
+ wait until lclk='1';
+ wait until lad_o=x"6";
+ while(lad_o=x"6") loop
+ wait until lclk='0'; --cycle 11
+ wait until lclk='1';
+ end loop;
+ if (lad_o=x"0") and lad_oe='1' then --SYNC
+ else
+ report "LPC error found on SYNC cycle no 0x0 on lad_o";
+ lframe_n <='0';
+ end if;
+ wait until lclk='0'; --cycle 12
+ wait until lclk='1';
+ if (lad_o=x"F") and lad_oe='1' then --TARL 1
+ else
+ report "LPC error found on TAR_L cycle no 0xF on lad_o";
+ lframe_n <='0';
+ end if;
+ wait until lclk='0'; --cycle 13
+ wait until lclk='1';
+ lad_i <=x"F"; --TARL 2
+ lframe_n <='1';
+ wait; -- will wait forever
+ END PROCESS;
+
+END;
Index: tags/google_release_of_0x20_firmware/beh/toplevel_usb_test.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/beh/toplevel_usb_test.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/beh/toplevel_usb_test.vhd (revision 3)
@@ -0,0 +1,316 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:17:32 09/28/2006
+-- Design Name: design_top
+-- Module Name: C:/projects/USB_dongle/beh/toplevel_usb_test.vhd
+-- Project Name: simulation
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: design_top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY toplevel_usb_test_vhd IS
+END toplevel_usb_test_vhd;
+
+ARCHITECTURE behavior OF toplevel_usb_test_vhd IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT design_top
+ PORT(
+ sys_clk : IN std_logic;
+ resetn : IN std_logic;
+ hdr : OUT std_logic_vector(10 downto 0);
+ alt_clk : IN std_logic;
+ mode : IN std_logic_vector(1 downto 0);
+ lreset_n : IN std_logic;
+ lclk : IN std_logic;
+ fl_sts : IN std_logic;
+ usb_txe_n : IN std_logic;
+ usb_rxf_n : IN std_logic;
+ lad : INOUT std_logic_vector(3 downto 0);
+ lframe_n : INOUT std_logic;
+ fl_data : INOUT std_logic_vector(15 downto 0);
+ usb_bd : INOUT std_logic_vector(7 downto 0);
+ seg_out : OUT std_logic_vector(7 downto 0);
+ scn_seg : OUT std_logic_vector(3 downto 0);
+ led_green : OUT std_logic;
+ led_red : OUT std_logic;
+ fl_addr : OUT std_logic_vector(23 downto 0);
+ fl_ce_n : OUT std_logic;
+ fl_oe_n : OUT std_logic;
+ fl_we_n : OUT std_logic;
+ fl_rp_n : OUT std_logic;
+ usb_rd_n : OUT std_logic;
+ usb_wr : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ SIGNAL sys_clk : std_logic := '0';
+ SIGNAL resetn : std_logic := '0';
+ SIGNAL alt_clk : std_logic := '0';
+ SIGNAL lreset_n : std_logic := '0';
+ SIGNAL lclk : std_logic := '0';
+ SIGNAL fl_sts : std_logic := '0';
+ SIGNAL usb_txe_n : std_logic := '0';
+ SIGNAL usb_rxf_n : std_logic := '0';
+ SIGNAL hdr : std_logic_vector(10 downto 0);
+ SIGNAL mode : std_logic_vector(1 downto 0) := (others=>'0');
+
+ --BiDirs
+ SIGNAL lad : std_logic_vector(3 downto 0);
+ SIGNAL lframe_n : std_logic;
+ SIGNAL fl_data : std_logic_vector(15 downto 0);
+ SIGNAL usb_bd : std_logic_vector(7 downto 0);
+
+ --Outputs
+ SIGNAL seg_out : std_logic_vector(7 downto 0);
+ SIGNAL scn_seg : std_logic_vector(3 downto 0);
+ SIGNAL led_green : std_logic;
+ SIGNAL led_red : std_logic;
+ SIGNAL fl_addr : std_logic_vector(23 downto 0);
+ SIGNAL fl_ce_n : std_logic;
+ SIGNAL fl_oe_n : std_logic;
+ SIGNAL fl_we_n : std_logic;
+ SIGNAL fl_rp_n : std_logic;
+ SIGNAL usb_rd_n : std_logic;
+ SIGNAL usb_wr : std_logic;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: design_top PORT MAP(
+ sys_clk => sys_clk,
+ resetn => resetn,
+ hdr => hdr,
+ alt_clk => alt_clk,
+ mode => mode,
+ lad => lad,
+ lframe_n => lframe_n,
+ lreset_n => lreset_n,
+ lclk => lclk,
+ seg_out => seg_out,
+ scn_seg => scn_seg,
+ led_green => led_green,
+ led_red => led_red,
+ fl_addr => fl_addr,
+ fl_ce_n => fl_ce_n,
+ fl_oe_n => fl_oe_n,
+ fl_we_n => fl_we_n,
+ fl_data => fl_data,
+ fl_rp_n => fl_rp_n,
+ fl_sts => fl_sts,
+ usb_rd_n => usb_rd_n,
+ usb_wr => usb_wr,
+ usb_txe_n => usb_txe_n,
+ usb_rxf_n => usb_rxf_n,
+ usb_bd => usb_bd
+ );
+
+ clocker : process is
+ begin
+ wait for 17 ns;
+ lclk <=not (lclk);
+ end process clocker;
+
+ clocker2 : process is
+ begin
+ wait for 20 ns;
+ sys_clk <=not (sys_clk);
+ end process clocker2;
+
+
+ tb : PROCESS
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 100 ns;
+ resetn <='1';
+ lreset_n <='1';
+ -- Status check COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"C5";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A1 COMMAND
+ wait for 800 ns;
+
+ -- A0 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"02";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A0";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A0 COMMAND
+ wait for 800 ns;
+
+ -- A1 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A1";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A1 COMMAND
+ wait for 800 ns;
+
+ -- A2 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A2";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A2 COMMAND
+ wait for 800 ns;
+
+ -- 98 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"98";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A2 COMMAND
+ wait for 800 ns;
+
+ -- CD COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"CD";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END CD COMMAND
+ wait for 800 ns;
+
+ -- E8 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01"; --this should mean 2 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"E8";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END E8 COMMAND
+ wait for 2000 ns;
+
+ -- SEND Data count to flash COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01"; --this should mean 2 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"00"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END COMMAND
+ wait for 800 ns;
+
+ -- SEND raw Data
+ usb_rxf_n <='0';
+ usb_bd <=x"CA"; --this should mean 1 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"FE"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END send data
+ wait for 800 ns;
+
+ -- SEND raw Data
+ usb_rxf_n <='0';
+ usb_bd <=x"BE"; --this should mean 1 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"CD"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END send data
+ wait for 800 ns;
+
+ wait; -- will wait forever
+ END PROCESS;
+
+END;
Index: tags/google_release_of_0x20_firmware/beh/usb_mem_test.vhd
===================================================================
--- tags/google_release_of_0x20_firmware/beh/usb_mem_test.vhd (nonexistent)
+++ tags/google_release_of_0x20_firmware/beh/usb_mem_test.vhd (revision 3)
@@ -0,0 +1,271 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:19:29 09/28/2006
+-- Design Name: usb2mem
+-- Module Name: C:/projects/USB_dongle/beh/usb_mem_test.vhd
+-- Project Name: simulation
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: usb2mem
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY usb_mem_test_vhd IS
+END usb_mem_test_vhd;
+
+ARCHITECTURE behavior OF usb_mem_test_vhd IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT usb2mem
+ PORT(
+ clk25 : IN std_logic;
+ reset_n : IN std_logic;
+ mem_di : IN std_logic_vector(15 downto 0);
+ mem_ack : IN std_logic;
+ usb_txe_n : IN std_logic;
+ usb_rxf_n : IN std_logic;
+ usb_bd : INOUT std_logic_vector(7 downto 0);
+ mem_addr : OUT std_logic_vector(23 downto 0);
+ mem_do : OUT std_logic_vector(15 downto 0);
+ mem_wr : OUT std_logic;
+ mem_val : OUT std_logic;
+ mem_cmd : OUT std_logic;
+ usb_rd_n : OUT std_logic;
+ usb_wr : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ SIGNAL clk25 : std_logic := '0';
+ SIGNAL reset_n : std_logic := '0';
+ SIGNAL mem_ack : std_logic := '0';
+ SIGNAL usb_txe_n : std_logic := '0';
+ SIGNAL usb_rxf_n : std_logic := '1';
+ SIGNAL mem_di : std_logic_vector(15 downto 0) := x"3210";
+
+ --BiDirs
+ SIGNAL usb_bd : std_logic_vector(7 downto 0);
+
+ --Outputs
+ SIGNAL mem_addr : std_logic_vector(23 downto 0);
+ SIGNAL mem_do : std_logic_vector(15 downto 0);
+ SIGNAL mem_wr : std_logic;
+ SIGNAL mem_val : std_logic;
+ SIGNAL mem_cmd : std_logic;
+ SIGNAL usb_rd_n : std_logic;
+ SIGNAL usb_wr : std_logic;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: usb2mem PORT MAP(
+ clk25 => clk25,
+ reset_n => reset_n,
+ mem_addr => mem_addr,
+ mem_do => mem_do,
+ mem_di => mem_di,
+ mem_wr => mem_wr,
+ mem_val => mem_val,
+ mem_ack => mem_ack,
+ mem_cmd => mem_cmd,
+ usb_rd_n => usb_rd_n,
+ usb_wr => usb_wr,
+ usb_txe_n => usb_txe_n,
+ usb_rxf_n => usb_rxf_n,
+ usb_bd => usb_bd
+ );
+
+ clocker : process is
+ begin
+ wait for 20 ns;
+ clk25 <=not (clk25);
+ end process clocker;
+
+
+ VCI_ACK : process is
+ begin
+ wait until mem_val='1';
+ wait for 100 ns;
+ mem_ack <='1';
+ wait until mem_val='0';
+ mem_ack <='0';
+ end process VCI_ACK;
+
+
+ tb : PROCESS
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 100 ns;
+ reset_n <='1';
+
+ -- STATUS CHECK COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"C5";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END STATUS CHECK COMMAND
+ wait for 800 ns;
+
+ -- A0 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"02";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A0";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A0 COMMAND
+ wait for 800 ns;
+
+ -- A1 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A1";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A1 COMMAND
+ wait for 800 ns;
+
+ -- A2 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"00";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"A2";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END A2 COMMAND
+ wait for 800 ns;
+
+ -- CD COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01";
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"CD";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END CD COMMAND
+ wait for 800 ns;
+
+ -- E8 COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01"; --this should mean 2 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"E8";
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END E8 COMMAND
+ wait for 2000 ns;
+
+ -- SEND Data count to flash COMMAND
+ usb_rxf_n <='0';
+ usb_bd <=x"01"; --this should mean 2 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"00"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END COMMAND
+ wait for 800 ns;
+
+ -- SEND raw Data
+ usb_rxf_n <='0';
+ usb_bd <=x"CA"; --this should mean 1 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"FE"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END send data
+ wait for 800 ns;
+
+ -- SEND raw Data
+ usb_rxf_n <='0';
+ usb_bd <=x"BE"; --this should mean 1 word to write
+ wait until usb_rd_n='0'; --wait to go low --first read
+ wait until usb_rd_n='1'; --wait to go low
+ wait for 20 ns;
+ usb_bd <=x"CD"; --count 00 means 1 word
+ wait until usb_rd_n='0'; --wait to go low --second read
+ wait until usb_rd_n='1'; --wait to go low
+ usb_bd <=(others=>'Z');
+ usb_rxf_n <='1';
+ -- END send data
+ wait for 800 ns;
+
+ wait; -- will wait forever
+ END PROCESS;
+
+END;