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/tags/INIT/code/cores/HEC/generator/tb/PCK_CRC8_D8.vhd
0,0 → 1,83
-----------------------------------------------------------------------
-- File: PCK_CRC8_D8.vhd
-- Date: Sun Dec 31 07:41:19 2000
--
-- Copyright (C) 1999 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose: VHDL package containing a synthesizable CRC function
-- * polynomial: (0 1 2 5 7 8)
-- * data width: 8
--
-- Info: jand@easics.be (Jan Decaluwe)
-- http://www.easics.com
-----------------------------------------------------------------------
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package PCK_CRC8_D8 is
 
-- polynomial: (0 1 2 5 7 8)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC8_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(7 downto 0) )
return std_logic_vector;
 
end PCK_CRC8_D8;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package body PCK_CRC8_D8 is
 
-- polynomial: (0 1 2 5 7 8)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC8_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(7 downto 0) )
return std_logic_vector is
 
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(7 downto 0);
variable NewCRC: std_logic_vector(7 downto 0);
 
begin
 
D := Data;
C := CRC;
 
NewCRC(0) := D(6) xor D(4) xor D(2) xor D(1) xor D(0) xor C(0) xor
C(1) xor C(2) xor C(4) xor C(6);
NewCRC(1) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(0) xor
C(0) xor C(3) xor C(4) xor C(5) xor C(6) xor C(7);
NewCRC(2) := D(7) xor D(5) xor D(2) xor D(0) xor C(0) xor C(2) xor
C(5) xor C(7);
NewCRC(3) := D(6) xor D(3) xor D(1) xor C(1) xor C(3) xor C(6);
NewCRC(4) := D(7) xor D(4) xor D(2) xor C(2) xor C(4) xor C(7);
NewCRC(5) := D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor D(1) xor
D(0) xor C(0) xor C(1) xor C(2) xor C(3) xor C(4) xor
C(5) xor C(6);
NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor
D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor C(5) xor
C(6) xor C(7);
NewCRC(7) := D(7) xor D(5) xor D(3) xor D(1) xor D(0) xor C(0) xor
C(1) xor C(3) xor C(5) xor C(7);
 
return NewCRC;
 
end nextCRC8_D8;
 
end PCK_CRC8_D8;
 
/tags/INIT/code/cores/HEC/generator/tb/hec_gen.vhd
0,0 → 1,109
-------------------------------------------------------------------------------
-- Title : HEC generator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : hec_gen.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update : 2000/12/28
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: HEC generator core
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.PCK_CRC8_D8.all;
 
entity HECgen_ent is
 
port (
clk : in std_logic; -- system clock
rst : in std_logic; -- system reset
header : in std_logic_vector(9 downto 0); -- header data
hec : out std_logic_vector(7 downto 0); -- HEC 8 bit value
init : in std_logic_vector(7 downto 0); -- init value
load : in std_logic); -- load header
 
end HECgen_ent;
 
architecture HECgen_beh of HECgen_ent is
 
signal tsthec : std_logic_vector(7 downto 0);
 
begin -- HECgen_beh
 
tsthec <= nextCRC8_D8(header(9 downto 2), (others=> '1'));
 
 
-- purpose: Generate HEC
-- type : sequential
-- inputs : clk, rst
-- outputs:
generate_proc : process (clk, rst)
 
variable lfsr : std_logic_vector(7 downto 0); -- LFSR (HEC register)
variable feedback_var : std_logic; -- feed back variable
 
begin -- process generate_proc
if rst = '0' then -- asynchronous reset (active low)
 
lfsr := (others => '0');
HEC <= (others => '0');
 
elsif clk'event and clk = '1' then -- rising clock edge
 
if load = '1' then
 
lfsr := init;
 
else
 
for i in 9 downto 0 loop
 
feedback_var := header(i) xor lfsr(7);
 
lfsr(7) := feedback_var xor lfsr(6);
lfsr(6) := lfsr(5);
lfsr(5) := feedback_var xor lfsr(4);
lfsr(4) := lfsr(3);
lfsr(3) := lfsr(2);
lfsr(2) := feedback_var xor lfsr(1);
lfsr(1) := feedback_var xor lfsr(0);
lfsr(0) := feedback_var;
 
end loop; -- i
 
 
end if;
 
HEC <= lfsr;
 
end if;
 
end process generate_proc;
 
end HECgen_beh;
/tags/INIT/code/cores/HEC/generator/core/HEC_gen.vhd
0,0 → 1,104
-------------------------------------------------------------------------------
-- Title : HEC generator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : hec_gen.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update : 2000/12/28
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: HEC generator core
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity HECgen_ent is
 
port (
clk : in std_logic; -- system clock
rst : in std_logic; -- system reset
header : in std_logic_vector(9 downto 0); -- header data
hec : out std_logic_vector(7 downto 0); -- HEC 8 bit value
init : in std_logic_vector(7 downto 0); -- init value
load : in std_logic); -- load header
 
end HECgen_ent;
 
architecture HECgen_beh of HECgen_ent is
 
begin -- HECgen_beh
 
 
 
-- purpose: Generate HEC
-- type : sequential
-- inputs : clk, rst
-- outputs:
generate_proc : process (clk, rst)
 
variable lfsr : std_logic_vector(7 downto 0); -- LFSR (HEC register)
variable feedback_var : std_logic; -- feed back variable
 
begin -- process generate_proc
if rst = '0' then -- asynchronous reset (active low)
 
lfsr := (others => '0');
HEC <= (others => '0');
 
elsif clk'event and clk = '1' then -- rising clock edge
 
if load = '1' then
 
lfsr := init;
 
else
 
for i in 9 downto 0 loop
 
feedback_var := header(i) xor lfsr(7);
 
lfsr(7) := feedback_var xor lfsr(6);
lfsr(6) := lfsr(5);
lfsr(5) := feedback_var xor lfsr(4);
lfsr(4) := lfsr(3);
lfsr(3) := lfsr(2);
lfsr(2) := feedback_var xor lfsr(1);
lfsr(1) := feedback_var xor lfsr(0);
lfsr(0) := feedback_var;
 
end loop; -- i
 
 
end if;
 
HEC <= lfsr;
 
end if;
 
end process generate_proc;
 
end HECgen_beh;
/tags/INIT/code/cores/scrambler/core/scrambler.vhd
0,0 → 1,84
-------------------------------------------------------------------------------
-- Title : Data scrambler
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : scrambler.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/18
-- Last update : 2000/12/18
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: Data scrambler core (data whitening)
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 18 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze : Needs one clock cycle to load new init value before it
-- accepts new data
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity scrambler_ent is
port (
clk : in std_logic; -- system clock
rst_n : in std_logic; -- system reset
Din : in std_logic; -- Data in
Dout : out std_logic; -- Data out
init : in std_logic_vector(6 downto 0); -- LFSR init value
load : in std_logic); -- Load new packet and init LFSR
 
end scrambler_ent;
 
architecture scrambler_beh of scrambler_ent is
signal lfsr : std_logic_vector(6 downto 0); -- LFSR register
begin -- scrambler_beh
 
-- purpose: Scrmbler core
-- type : sequential
-- inputs : clk, rst_n
-- outputs:
scrambler_proc: process (clk, rst_n)
begin -- process scrambler_proc
if rst_n = '0' then -- asynchronous reset (active low)
Dout <= '0';
lfsr <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if load = '1' then
lfsr <= init;
Dout <= '0';
else
Dout <= Din xor lfsr(6);
lfsr(6 downto 5) <= lfsr(5 downto 4);
lfsr(4) <= lfsr(3) xor lfsr(6);
lfsr(3 downto 0) <= lfsr(2 downto 0) & lfsr(6);
end if;
end if;
end process scrambler_proc;
 
end scrambler_beh;
/tags/INIT/code/cores/correlator/core/corrtop.vhd
0,0 → 1,136
-------------------------------------------------------------------------------
-- Title : Correlator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : corrtop.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/24
-- Last update : 2000/12/24
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164, ieee.std_logic_signed
-------------------------------------------------------------------------------
-- Description: correlator top
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 24 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze : Threshold Detection must be optimized
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
 
entity corrtop_ent is
generic (
THRESHOLD_LIMIT : integer := 64;
REG_WIDTH : integer := 72); -- Register width
port (
rst : in std_logic; -- system reset
clk : in std_logic; -- system clock
enable : in std_logic; -- enable
din : in std_logic; -- Data in bit
dout : out std_logic; -- Data out
StartOfFrame : out std_logic; -- Start Of Frame
ThresholdLimit : in integer range 0 to REG_WIDTH-1; -- Threshold limit
AccessCode : in std_logic_vector(REG_WIDTH-1 downto 0)); -- Access code
 
end corrtop_ent;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture corrtop_beh of corrtop_ent is
component correlator_core_ent
generic (
REG_WIDTH : integer);
port (
clk : in std_logic;
rst : in std_logic;
Din : in std_logic;
Dout : out std_logic;
enable : in std_logic;
pattern : in std_logic_vector(REG_WIDTH-1 downto 0);
Threshold : out std_logic_vector(REG_WIDTH-1 downto 0));
end component;
 
-------------------------------------------------------------------------------
 
signal threshold : std_logic_vector(REG_WIDTH-1 downto 0); -- threshold signal
signal Dout_reg : std_logic; -- Output register
 
begin -- corrtop_beh
-------------------------------------------------------------------------------
correlator_core : correlator_core_ent
generic map (
REG_WIDTH => REG_WIDTH)
port map (
clk => clk,
rst => rst,
Din => Din,
Dout => Dout_reg,
enable => enable,
pattern => AccessCode,
Threshold => Threshold);
-------------------------------------------------------------------------------
-- purpose: threshold detection
-- type : sequential
-- inputs : clk, rst
-- outputs:
process (clk, rst)
 
variable count_ones : integer range 0 to REG_WIDTH; ---1; -- Ones counter
 
begin -- process
if rst = '0' then -- asynchronous reset (active low)
 
StartOfFrame <= '0';
 
elsif clk'event and clk = '1' then -- rising clock edge
 
count_ones := 0;
 
for i in 0 to REG_WIDTH-1 loop
if Threshold(i) = '1' then
count_ones := count_ones + 1;
end if;
-- count_ones := count_ones + slv_2_int(threshold(i));
end loop; -- i
 
if count_ones > ThresholdLimit then
StartOfFrame <= '1';
else
StartOfFrame <= '0';
end if;
 
end if;
end process;
-------------------------------------------------------------------------------
-- purpose: Register output data
-- type : sequential
-- inputs : clk, rst
-- outputs:
register_out : process (clk, rst)
begin -- process register_out
if rst = '0' then -- asynchronous reset (active low)
Dout <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
Dout <= Dout_reg;
end if;
end process register_out;
-------------------------------------------------------------------------------
end corrtop_beh;
/tags/INIT/code/cores/correlator/core/correlator.vhd
0,0 → 1,91
-------------------------------------------------------------------------------
-- Title : Correlator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : correlator.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/18
-- Last update : 2000/12/18
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: correlator core
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 18 Nov 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity correlator_core_ent is
generic (
REG_WIDTH : integer := 72); -- Register width
port (
clk : in std_logic; -- system clock
rst : in std_logic; -- system reset
Din : in std_logic; -- Input Data
Dout : out std_logic; -- Output Data
enable : in std_logic; -- correlator enable
pattern : in std_logic_vector(REG_WIDTH-1 downto 0); -- Match pattern
Threshold : out std_logic_vector(REG_WIDTH-1 downto 0)); -- Threshold
 
end correlator_core_ent;
 
 
architecture correlator_core_beh of correlator_core_ent is
signal data_reg : std_logic_vector(REG_WIDTH-1 downto 0); -- data register
signal pattern_reg : std_logic_vector(REG_WIDTH-1 downto 0); -- pattern register
begin -- correlator_core_beh
 
-- purpose: Correlator core
-- type : sequential
-- inputs : clk, rst
-- outputs:
correlate_proc : process (clk, rst)
 
 
 
begin -- process correlate_proc
if rst = '0' then -- asynchronous reset (active low)
 
data_reg <= (others => '0');
pattern_reg <= (others => '0');
Dout <= '0';
Threshold <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
 
if enable = '1' then
 
pattern_reg <= pattern;
 
else
 
data_reg <= Din & data_reg(REG_WIDTH-1 downto 1);
Threshold <= data_reg xor pattern_reg;
 
end if;
 
Dout <= data_reg(0);
 
end if;
end process correlate_proc;
 
end correlator_core_beh;

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