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Rev 2 → Rev 3

/generic_booth_multipler/trunk/rtl/benches/TB_ALU.vhd
0,0 → 1,41
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_ALU IS
END TB_ALU;
ARCHITECTURE behavior OF TB_ALU IS
COMPONENT Alu
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
op : IN std_logic;
S : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal op : std_logic := '0';
 
--Outputs
signal S : std_logic_vector(7 downto 0);
BEGIN
 
uut: Alu PORT MAP (
A => A,
B => B,
op => op,
S => S
);
A <= X"05" after 10 ns , X"0F" after 30 ns;
B <= X"0A" after 10 ns , X"08" after 30 ns;
op <= '1' after 20 ns , '0' after 40 ns;
 
END;
/generic_booth_multipler/trunk/rtl/benches/TB_Adder.vhd
0,0 → 1,47
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Adder IS
END TB_Adder;
ARCHITECTURE behavior OF TB_Adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(7 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal A : std_logic_vector(7 downto 0) := (others =>'0');
signal B : std_logic_vector(7 downto 0) := (others =>'0');
signal Cin : std_logic := '0';
 
--Outputs
signal S : std_logic_vector(7 downto 0);
signal Cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
cin <= '1' after 20 ns , '0' after 40 ns;
A <= X"05" after 10 ns , X"06" after 20 ns , X"F8" after 30 ns ;
B <= X"0F" after 10 ns , X"0A" after 20 ns , X"F3" after 30 ns ;
END;
/generic_booth_multipler/trunk/rtl/benches/TB_Ander.vhd
0,0 → 1,40
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Ander IS
END TB_Ander;
ARCHITECTURE behavior OF TB_Ander IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Ander
PORT(
input1 : IN std_logic;
input2 : IN std_logic_vector(7 downto 0);
result : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal input1 : std_logic := '0';
signal input2 : std_logic_vector(7 downto 0) := (others=>'0');
 
--Outputs
signal result : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Ander PORT MAP (
input1 => input1,
input2 => input2,
result => result
);
input2 <= X"58";
input1 <= '1' after 20 ns;
END;
/generic_booth_multipler/trunk/rtl/benches/TB_BoothDatapath.vhd
0,0 → 1,68
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity TB_BoothDatapath is
end TB_BoothDatapath;
 
architecture Behavioral of TB_BoothDatapath is
 
component BoothDatapath is
port(
clock :in std_logic;
reset :in std_logic;
load :in std_logic;
shift :in std_logic;
X :in std_logic_vector;
Y :in std_logic_vector;
P :out std_logic_vector);
end component;
 
signal clock: std_logic := '0';
signal load: std_logic := '0';
signal reset: std_logic := '0';
signal shift: std_logic := '0';
signal X4: std_logic_vector(3 downto 0);
signal Y4: std_logic_vector(3 downto 0);
signal P8: std_logic_vector(7 downto 0);
signal X8: std_logic_vector(7 downto 0);
signal Y8: std_logic_vector(7 downto 0);
signal P16: std_logic_vector(15 downto 0);
begin
uut4: BoothDatapath
port map(
clock => clock,
reset => reset,
load => load,
shift => shift,
X => X4,
Y => Y4,
P => P8);
 
uut8: BoothDatapath
port map(
clock => clock,
reset => reset,
load => load,
shift => shift,
X => X8,
Y => Y8,
P => P16);
 
clock <= not clock after 5 ns;
reset<= '1' after 10 ns, '0' after 20 ns;
load <= '1' after 30 ns, '0' after 40 ns;
shift <= '1' after 40 ns;
Y4 <= X"B";
X4 <= X"A";
Y8 <= X"BA";
X8 <= X"A7";
 
end Behavioral;
/generic_booth_multipler/trunk/rtl/benches/TB_BoothMultiplier.vhd
0,0 → 1,90
-- TestBench Template
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY TB_BoothMultiplier IS
END TB_BoothMultiplier;
 
ARCHITECTURE behavior OF TB_BoothMultiplier IS
 
-- Component Declaration
component BoothMultiplier is
generic(COUNTER_SIZE : positive := 2);
port(
clock : in std_logic;
clear : in std_logic;
start : in std_logic;
X_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0);
Y_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0);
ready : out std_logic;
Result: out std_logic_vector(2*(2**COUNTER_SIZE)-1 downto 0));
end component;
 
signal clock :std_logic := '0';
signal reset :std_logic := '0';
signal start :std_logic := '0';
signal ready4 :std_logic := '0';
signal ready8 :std_logic := '0';
signal X_data4 :std_logic_vector(3 downto 0);
signal Y_data4 :std_logic_vector(3 downto 0);
signal Result8 :std_logic_vector(7 downto 0);
signal X_data8 :std_logic_vector(7 downto 0);
signal Y_data8 :std_logic_vector(7 downto 0);
signal Result16 :std_logic_vector(15 downto 0);
begin
desing_under_test4bit: BoothMultiplier
generic map(
COUNTER_SIZE => 2)
port map(
clock => clock,
clear => reset,
start => start,
X_data => X_data4,
Y_data => Y_data4,
ready => ready4,
Result => Result8);
desing_under_test8bit: BoothMultiplier
generic map(
COUNTER_SIZE => 3)
port map(
clock => clock,
clear => reset,
start => start,
X_data => X_data8,
Y_data => Y_data8,
ready => ready8,
Result => Result16);
 
clock <= not clock after 5 ns;
start <= '1' after 10 ns ;
reset <= '1' after 0010 ns ,'0' after 0020 ns;
-- '1' after 0410 ns, '0' after 0420 ns,
-- '1' after 0810 ns, '0' after 0820 ns,
-- '1' after 1210 ns, '0' after 1220 ns;
--
X_data8 <= X"23" , -- 35
X"03" after 0400 ns, -- 3
X"FA" after 0800 ns, -- -8
X"F5" after 1200 ns; -- -10
 
Y_data8 <= X"03" , -- 3
X"23" after 0400 ns, -- 35
X"F5" after 0800 ns, -- -10
X"FA" after 1200 ns; -- -8
X_data4 <= X"3" , -- 35
X"3" after 0400 ns, -- 3
X"A" after 0800 ns, -- -8
X"5" after 1200 ns; -- -10
Y_data4 <= X"3" , -- 3
X"3" after 0400 ns, -- 35
X"5" after 0800 ns, -- -10
X"A" after 1200 ns; -- -8
 
end;
/generic_booth_multipler/trunk/rtl/benches/TB_Register.vhd
0,0 → 1,59
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Register IS
END TB_Register;
ARCHITECTURE behavior OF TB_Register IS
COMPONENT Regeister
PORT(
clock : IN std_logic;
enable : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(7 downto 0);
dout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
signal clock : std_logic := '0';
signal enable : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(7 downto 0) ;
 
signal dout : std_logic_vector(7 downto 0);
 
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Regeister PORT MAP (
clock => clock,
enable => enable,
reset => reset,
din => din,
dout => dout
);
 
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
reset <= '1' after clock_period/2 ,'0' after clock_period*3/2;
enable<= '1' after clock_period*2 ,'0' after clock_period*7;
din <= X"05" after clock_period ,
X"0A" after clock_period*2,
X"1A" after clock_period*3,
X"2A" after clock_period*4,
X"3A" after clock_period*5,
X"4A" after clock_period*6,
X"5A" after clock_period*7,
X"6B" after clock_period*8;
END;
/generic_booth_multipler/trunk/rtl/benches/TB_RightShiftReg.vhd
0,0 → 1,59
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY TB_RightShiftReg IS
END TB_RightShiftReg;
ARCHITECTURE behavior OF TB_RightShiftReg IS
 
COMPONENT RightShiftReg
PORT(
clock : IN std_logic;
enable : IN std_logic;
shift : IN std_logic;
din : IN std_logic_vector(8 downto 0);
dout : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
 
--Inputs
signal clock : std_logic := '0';
signal enable : std_logic := '0';
signal shift : std_logic := '0';
signal din : std_logic_vector(8 downto 0) := (others => '0');
 
--Outputs
signal dout : std_logic_vector(1 downto 0);
 
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RightShiftReg PORT MAP (
clock => clock,
enable => enable,
shift => shift,
din => din,
dout => dout
);
 
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
enable <= '1' after clock_period*2 ,'0' after clock_period*3;
shift <= '1' after clock_period*3 ,'0' after clock_period*7;
din <= "011001101" after clock_period/2;
END;

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