URL
https://opencores.org/ocsvn/hd44780_driver/hd44780_driver/trunk
Subversion Repositories hd44780_driver
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- This comparison shows the changes necessary to convert path
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- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/hd44780_driver/trunk/lcd_driver_hd44780_module.vhd
25,7 → 25,7
-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396 |
-- for more info. The display used has only two lines. |
-- |
-- The VHDL description can both be simulated and synthesized. |
-- This VHDL description can both be simulated and synthesized. |
-- |
-- This driver has a User Side and a LCD Side. The user is to interface at the User Side |
-- and has a number of "routines" at her disposal. The User Side implements the following |
/hd44780_driver/trunk/readme.txt
36,7 → 36,7
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396 |
for more info. The display used has only two lines. |
|
The VHDL description can both be simulated and synthesized. |
The VHDL descriptions can both be simulated and synthesized. |
|
This driver has a User Side and a LCD Side. The user is to interface at the User Side |
and has a number of "routines" at her disposal. The User Side implements the following |
97,8 → 97,8
A note about timing: |
Some of the timing parameters are very small, e.g. the RW and RS setup time with |
respect to rising edge of E. If the clock frequency is too low, the delay calculated |
will be zero, which result in at least a delay with the period time of the clock. |
will be zero, which result in at least a delay with the period time of the clock. |
|
A note about implementing: |
If the driver doesn't work or you get clobbered strings, please use non-BF |
reading at first. Next, increase the Cycle E time and PWeh time. |
reading at first. Next, increase the Cycle E time and PWeh time. |