OpenCores

/trunk/testbench/hssrdc_driver_cbs_class.sv File deleted

trunk/testbench/hssrdc_driver_cbs_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/hssrdc_scoreboard_class.sv =================================================================== --- trunk/testbench/hssrdc_scoreboard_class.sv (revision 2) +++ trunk/testbench/hssrdc_scoreboard_class.sv (nonexistent) @@ -1,142 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : hssrdc_scoreboard_class.sv -// -// Description : scoreboard for test read transaction -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "tb_define.svh" - -`include "message_class.sv" -`include "hssrdc_driver_cbs_class.sv" - -class hssdrc_scoreboard_class extends hssrdc_driver_cbs_class; - - sdram_tr_mbx out_mbx; - message_class msg; - - event done; - - function new (message_class msg, ref event done); - - this.msg = msg; - - this.done = done; - - endfunction - - int checked_tr_num; - int check_err_num; - - // - // - // - - task start (); - checked_tr_num = 0; - check_err_num = 0; - endtask - - // - // - // - - virtual task post_ReadData (input realtime t, sdram_transaction_class tr); - tb_data_t golden_data2cmp; - tb_data_t data2cmp; - - tb_chid_t golden_chid2cmp; - tb_chid_t chid2cmp; - - tb_datam_t datam; - - int burst; - - string str; - begin - - burst = tr.burst + 1; - - golden_chid2cmp = tr.chid; - - for (int i = 0; i < burst; i++) begin - - datam = tr.wdatam [i]; - - data2cmp = MaskData(tr.rdata [i], datam); - golden_data2cmp = MaskData(tr.wdata [i], datam); - - chid2cmp = tr.rchid [i]; - - if (data2cmp !== golden_data2cmp) begin - str = $psprintf("data compare error at ba = %0d, rowa = %0d, cola = %0d : ", tr.ba, tr.rowa, tr.cola); - str = {str, ($psprintf("write data %h : read data %h", golden_data2cmp, data2cmp))}; - msg.err(str); - - check_err_num++; - end - - if (chid2cmp !== golden_chid2cmp) begin - str = $psprintf("chid compare error at ba = %0d, rowa = %0d, cola = %0d : ", tr.ba, tr.rowa, tr.cola); - str = {str, ($psprintf("write chid %h : read chid %h", golden_chid2cmp, chid2cmp))}; - msg.err(str); - - check_err_num++; - end - - end - - checked_tr_num++; - -> done; - end - endtask - - // - // - // - - function data_t MaskData (input tb_data_t data, tb_datam_t datam); - if (datam == 0) - MaskData = data; - else begin - for (int m = 0; m < $size(datam); m++) begin - for (int b = 0; b < 8; b++) begin - MaskData[8*m + b] = data [8*m + b] & ~datam[m]; - end - end - end - endfunction - -endclass

trunk/testbench/hssrdc_scoreboard_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/sdram_transaction_class.sv =================================================================== --- trunk/testbench/sdram_transaction_class.sv (revision 2) +++ trunk/testbench/sdram_transaction_class.sv (nonexistent) @@ -1,220 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : sdram_transaction_class.sv -// -// Description : sdram transaction structure -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_define.vh" -`include "tb_define.svh" - -`ifndef __SDRAM_TRANSACTION_CLASS_SV__ - -`define __SDRAM_TRANSACTION_CLASS_SV__ - - class sdram_transaction_class; - - // transaction id - int id; - // transacton type for driver - tr_type_e_t tr_type ; - // input sdram path - rand tb_ba_t ba ; - rand tb_rowa_t rowa ; - rand tb_cola_t cola ; - rand tb_burst_t burst ; - rand tb_chid_t chid ; - // input data path - rand tb_data_t wdata [0:cBurstMaxValue-1]; - tb_datam_t wdatam [0:cBurstMaxValue-1]; - // output data path - tb_data_t rdata [0:cBurstMaxValue-1]; - tb_chid_t rchid [0:cBurstMaxValue-1]; - - // random generate controls - int burst_random_mode = 0; - int address_random_mode = 0; - // used in random generate variables - tb_ba_t last_used_ba; - tb_rowa_t last_used_rowa; - - - function new (int id = 0, tr_type_e_t tr_type = cTR_WRITE, int ba = 0, rowa = 0, cola = 0, burst = 1, chid = 0); - - this.id = id; - this.tr_type = tr_type; - this.ba = ba; - this.rowa = rowa; - this.cola = cola; - this.burst = burst - 1; - this.chid = chid; - - endfunction - - // - // function to generate linear data packet - // - - function void GetLinearPacket; - data_t tmp_data; - begin - - tmp_data = {ba, rowa, this.cola}; - - for (int i = 0; i <= burst; i++) - wdata [i] = tmp_data + i + 1; - - wdatam = '{default : 0}; - end - endfunction - - // - // - // - - function void GetRandomPacket; - data_t tmp_data; - begin - - assert ( std::randomize(wdata)) else $error ("random packet generate"); - - wdatam = '{default : 0}; - - end - endfunction - - // - // randomize callback function to store transaction addres's - // - function void post_randomize(); - last_used_ba = ba; - last_used_rowa = rowa; - endfunction - - // - // constraint for use for performance measuring - // - - // burst constraint - - // mode 0 : any birst, no cola allign - - // mode 1 : fixed burst = 1, cola allign - constraint burst_constraint_1 { (burst_random_mode == 1) -> burst == 0; } - // mode 2 : fixed burst = 2, cola allign - constraint burst_constraint_2 { (burst_random_mode == 2) -> burst == 1; } - // mode 3 : fixed burst = 4, cola allign - constraint burst_constraint_3 { (burst_random_mode == 3) -> burst == 3; } - // mode 4 : fixed burst == 8, cola allign - constraint burst_constraint_4 { (burst_random_mode == 4) -> burst == 7; } - // mode 5 : fixed burst == 16, cola allign - constraint burst_constraint_5 { (burst_random_mode == 5) -> burst == 15; } - // mode 6 : max performance burst, cola allign - constraint burst_constraint_6 { (burst_random_mode == 6) -> burst inside {0, 1, 3, 7, 15}; } - - // cola constraint - constraint cola_constraint { (burst_random_mode != 0) -> - (burst == 1) -> (cola[0] == 0); - (burst == 3) -> (cola[1:0] == 0); - (burst == 7) -> (cola[2:0] == 0); - (burst == 15) -> (cola[3:0] == 0); - } - - constraint burst_order {solve burst before cola; } - - // address constraint - - // mode 0 : same bank same row - constraint address_constraint_0 { (address_random_mode == 0) -> { - (ba == last_used_ba); - (rowa == last_used_rowa); - } - } - // mode 1 : same bank - constraint address_constraint_1 { (address_random_mode == 1) -> { - (ba == last_used_ba); - (rowa != last_used_rowa); - } - } - // mode 2 : any bank same row - constraint address_constraint_2 { (address_random_mode == 2) -> { - (ba != last_used_ba); - (rowa == last_used_rowa); - } - } - // mode 3 : linear bank same row - constraint address_constraint_3 { (address_random_mode == 3) -> { - (last_used_ba == 0) -> (ba == 1); - (last_used_ba == 1) -> (ba == 2); - (last_used_ba == 2) -> (ba == 3); - (last_used_ba == 3) -> (ba == 0); - (rowa == last_used_rowa); - } - } - // mode 4 : any bank any row - constraint address_constraint_4 { (address_random_mode == 4) -> { - (ba != last_used_ba); - (rowa != last_used_rowa); - } - } - // mode 5 : linear bank any row - constraint address_constraint_5 { (address_random_mode == 5) -> { - (last_used_ba == 0) -> (ba == 1); - (last_used_ba == 1) -> (ba == 2); - (last_used_ba == 2) -> (ba == 3); - (last_used_ba == 3) -> (ba == 0); - (rowa != last_used_rowa); - } - } - // mode 6 : ba varies more often than rowa - constraint address_constraint_6 { (address_random_mode == 6) -> { - ba dist { (ba == last_used_ba) := 1, (ba != last_used_ba) :/5}; // 1/6 const ba - rowa dist { (rowa == last_used_rowa) := 5, (rowa != last_used_rowa) :/1}; // 5/6 const rowa - } - } - // mode 7 : ba varies less often than rowa - constraint address_constraint_7 { (address_random_mode == 7) -> { - ba dist { (ba == last_used_ba) := 3, (ba != last_used_ba) :/1}; // 75% const ba - rowa dist { (rowa == last_used_rowa) := 1, (rowa != last_used_rowa) :/3}; // 25% const rowa - } - } - - endclass - // - // mailbox for connet agent with driver - // - typedef mailbox #(sdram_transaction_class) sdram_tr_mbx; - -`endif

trunk/testbench/sdram_transaction_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/hssdrc_driver_class.sv =================================================================== --- trunk/testbench/hssdrc_driver_class.sv (revision 2) +++ trunk/testbench/hssdrc_driver_class.sv (nonexistent) @@ -1,351 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : hssdrc_driver_class.sv -// -// Description : low level API driver for hssdrc_controller -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_tb_sys_if.vh" - -`include "hssdrc_define.vh" - -`include "tb_define.svh" - -`include "hssrdc_driver_cbs_class.sv" - -`ifndef __HSSDRC_DRIVER_SV__ - - `define __HSSDRC_DRIVER_SV__ - - class hssrdc_driver_class; - - // callback quene - hssrdc_driver_cbs_class cbs[$]; - - // mailboxes to connect with transaction agent - sdram_tr_mbx in_mbx; - - // mailbox for connect command path with data path of this driver - sdram_tr_mbx wdata_mbx; - sdram_tr_mbx rdata_mbx; - - // - virtual hssdrc_tb_sys_if sys_if; - - // acknowledge mailbox for agent. used in locked transaction only - sdram_tr_ack_mbx done_mbx; - - // feedback to tb for waiting event - event write_done; - event read_done; - - // driver work modes - bit random_delay_mode = 0; - bit debug = 0; - - // - // - // - - function new (virtual hssdrc_tb_sys_if sys_if, sdram_tr_mbx in_mbx, sdram_tr_ack_mbx done_mbx); - - this.sys_if = sys_if; - - this.in_mbx = in_mbx; - - this.done_mbx = done_mbx; - - // internal not sized mailboxes : all must be controlled via in_mbx, out_mbx size - wdata_mbx = new; - rdata_mbx = new; - - endfunction - - // - // init interface task - // - - task init; - sys_if.cb.write <= 1'b0; - sys_if.cb.read <= 1'b0; - sys_if.cb.refr <= 1'b0; - sys_if.cb.cola <= '0; - sys_if.cb.rowa <= '0; - sys_if.cb.ba <= '0; - sys_if.cb.chid_i <= '0; - sys_if.cb.burst <= '0; - sys_if.cb.wdata <= '0; - sys_if.cb.wdatam <= '0; - endtask - - // - // start driver task - // - - task run; - init (); - fork - CommandDriver (); - WriteDataDriver (); - ReadDataDriver (); - join_none; - endtask - - // - // stop driver task - // - - task stop (); - disable this.CommandDriver; - disable this.WriteDataDriver; - disable this.ReadDataDriver; - endtask - - //----------------------------------------------------------------------- - // command driver - //----------------------------------------------------------------------- - - task CommandDriver; - sdram_transaction_class tr; - - bit [4:0] delay; // max delay is 32 bit - - begin - - @(sys_if.cb); - forever begin - - // syncronize mailbox to clock - if ( !in_mbx.try_get(tr) ) begin - @(sys_if.cb); - continue; - end - - if (debug) begin - if ((tr.tr_type == cTR_READ) || (tr.tr_type == cTR_READ_LOCKED)) - $display("%0t cmd get READ transaction id = %0d", $time, tr.id); - else if ((tr.tr_type == cTR_WRITE) || (tr.tr_type == cTR_WRITE_LOCKED)) - $display("%0t cmd get WRITE transaction id = %0d", $time, tr.id); - end - - if (random_delay_mode) begin - assert (std::randomize(delay) with {delay dist {0 := 1, !0 :/ 2};}) else - $error ("random delay generate error"); - - repeat (delay) @(sys_if.cb); - end - - - // set command on interface - SetCommand(tr); - - // if need callbacks - foreach ( cbs [i] ) cbs[i].post_Command ($realtime); - - // set command for write/read drivers - case (tr.tr_type) - cTR_WRITE, cTR_WRITE_LOCKED : wdata_mbx.put (tr); - cTR_READ , cTR_READ_LOCKED : rdata_mbx.put (tr); - endcase - - // for locked transactions wait done and set acknowledge - case (tr.tr_type) - cTR_WRITE_LOCKED : begin - @(write_done); - done_mbx.put (cTR_WRITE_LOCKED); - end - cTR_READ_LOCKED : begin - @(read_done); - done_mbx.put(cTR_READ_LOCKED); - end - cTR_REFR_LOCKED : begin - done_mbx.put (cTR_WRITE_LOCKED); - end - endcase - - end - end - endtask - - // - // - // - - task SetCommand (sdram_transaction_class tr); - - case (tr.tr_type) - cTR_WRITE, cTR_WRITE_LOCKED : begin - sys_if.cb.write <= 1'b1; - sys_if.cb.read <= 1'b0; - sys_if.cb.refr <= 1'b0; - end - cTR_READ, cTR_READ_LOCKED : begin - sys_if.cb.write <= 1'b0; - sys_if.cb.read <= 1'b1; - sys_if.cb.refr <= 1'b0; - end - cTR_REFR, cTR_REFR_LOCKED : begin - sys_if.cb.write <= 1'b0; - sys_if.cb.read <= 1'b0; - sys_if.cb.refr <= 1'b1; - end - endcase - - sys_if.cb.rowa <= tr.rowa; - sys_if.cb.cola <= tr.cola; - sys_if.cb.ba <= tr.ba; - sys_if.cb.burst <= tr.burst; - sys_if.cb.chid_i <= tr.chid; - - do - @(sys_if.cb); - while (sys_if.cb.ready != 1'b1); - - sys_if.cb.write <= 1'b0; - sys_if.cb.read <= 1'b0; - sys_if.cb.refr <= 1'b0; - - endtask - - //----------------------------------------------------------------------- - // write data driver - //----------------------------------------------------------------------- - - task WriteDataDriver; - - sdram_transaction_class tr; - int num; - - begin - - forever begin - wdata_mbx.get (tr); - - if (debug) - $display("%0t write driver get transaction id = %0d", $time, tr.id); - - num = tr.burst + 1; - - // set data - for (int i = 0; i < num; i++) - SetWrData (tr.wdata [i] , tr.wdatam [i]); - - -> write_done; - - if (debug) - $display("%0t write driver done transaction id = %0d", $time, tr.id); - - foreach ( cbs[i] ) cbs[i].post_WriteData($realtime, tr); - - end - end - endtask - - // - // - // -`ifndef HSSDRC_COMBINATIVE_USE_WDATA - task SetWrData ( input data_t data, datam_t datam); - sys_if.cb.wdata <= data; - sys_if.cb.wdatam <= datam; - - do - @(sys_if.cb); - while (sys_if.cb.use_wdata != 1'b1); - endtask -`else - task SetWrData ( input data_t data, datam_t datam); - do - @(sys_if.cb); - while (sys_if.cb.use_wdata != 1'b1); - - sys_if.cb.wdata <= data; - sys_if.cb.wdatam <= datam; - endtask -`endif - //----------------------------------------------------------------------- - // read part of driver - //----------------------------------------------------------------------- - - task ReadDataDriver; - - sdram_transaction_class tr; - int num; - - begin - forever begin - rdata_mbx.get (tr); - - if (debug) - $display("%0t read driver get transaction id = %0d", $time, tr.id); - - num = tr.burst + 1; - - for (int i = 0; i < num; i++) - GetRdData (tr.rdata [i], tr.rchid [i]); - - -> read_done; - - if (debug) - $display("%0t read driver done transaction id = %0d", $time, tr.id); - - foreach ( cbs[i] ) cbs[i].post_ReadData($realtime, tr); - - end - end - endtask - - // - // - // - - task GetRdData (output data_t data, chid_t chid); - - do - @(sys_if.cb); - while (sys_if.cb.vld_rdata != 1'b1); - - data = sys_if.cb.rdata; - chid = sys_if.cb.chid_o; - - endtask - - // - // - // - - endclass - -`endif

trunk/testbench/hssdrc_driver_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/hssrdc_bandwidth_monitor_class.sv =================================================================== --- trunk/testbench/hssrdc_bandwidth_monitor_class.sv (revision 2) +++ trunk/testbench/hssrdc_bandwidth_monitor_class.sv (nonexistent) @@ -1,257 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : hssrdc_bandwidth_monitor_class.sv -// -// Description : bandwidth monitor measurement class -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_define.vh" -`include "hssdrc_timing.vh" -`include "hssdrc_tb_sys_if.vh" - -`include "sdram_transaction_class.sv" -`include "hssrdc_driver_cbs_class.sv" - - -`ifndef __HSSDRC_BANDWIDTH_MONITOR_CLASS__ - - `define __HSSDRC_BANDWIDTH_MONITOR_CLASS__ - - class hssdrc_bandwidth_monitor_class extends hssrdc_driver_cbs_class; - - virtual hssdrc_tb_sys_if sys_if; - - // bandwidth measurement FSM - enum {idle, wait_start, work} state = idle; - - // timestamps - realtime end_time; - realtime start_time; - - // word transfer counters - int unsigned wr_word_num; - int unsigned rd_word_num; - - // bandwidth measurement itself - real write_bandwidth ; - real read_bandwidth ; - real bandwidth ; - - real write_bandwidth_percent ; - real read_bandwidth_percent ; - real bandwidth_percent ; - - // semaphore to controll access to variables - semaphore sem; - - // bandwidth measurement parameters - real mbps_mfactor; - real max_bandwidth; - - // tb syncronization - int measured_tr_num = 0; - event done; - - function new (virtual hssdrc_tb_sys_if sys_if, ref event done); - sem = new (1); - - this.sys_if = sys_if; - - this.done = done; - endfunction - - - // - // function to start measurement process - // - - task start(); - - sem.get (1) ; - - // set begin - state = wait_start; - - // clear all counters - end_time = 0ns; - start_time = 0ns; - - wr_word_num = 0; - rd_word_num = 0; - - measured_tr_num = 0; - - sem.put (1) ; - endtask - - // - // function to stop measurement process - // - - task stop(); - sem.get (1); - - state = idle; - count_bandwidth(); - - sem.put (1); - - endtask - - // - // callback for command part of hssdrc_driver_class - // - - task post_Command (input realtime t); - endtask - - // - // callback for write part of hssdrc_driver_class - // - - task post_WriteData (input realtime t, sdram_transaction_class tr); - int burst; - begin - - burst = tr.burst + 1; - - sem.get (1); - - if (state == wait_start) begin - start_time = t; - state = work; - end - else if (state == work) begin - wr_word_num += burst; - end_time = t; - end - - measured_tr_num++; - -> done; - - sem.put (1); - end - endtask - - // - // callback for read part of hssdrc_driver_class - // - - task post_ReadData ( input realtime t, sdram_transaction_class tr); - int burst; - begin - - burst = tr.burst + 1; - - sem.get (1); - - if (state == wait_start) begin - start_time = t; - state = work; - end - else if (state == work) begin - rd_word_num += burst; - end_time = t; - end - - measured_tr_num++; - - -> done; - - sem.put (1); - end - endtask - - // - // measurement count function bwth = mbps_mfactor*num/(end_time - start_time); - // - - function void count_bandwidth(); - realtime delta; - int unsigned wrrd_word_num; - begin - - delta = (end_time - start_time); - - wrrd_word_num = wr_word_num + rd_word_num; - - write_bandwidth = (wr_word_num/delta)*mbps_mfactor; - read_bandwidth = (rd_word_num/delta)*mbps_mfactor; - bandwidth = (wrrd_word_num/delta)*mbps_mfactor; - - write_bandwidth_percent = write_bandwidth*100.0/max_bandwidth ; - read_bandwidth_percent = read_bandwidth *100.0/max_bandwidth ; - bandwidth_percent = bandwidth *100.0/max_bandwidth ; - - end - endfunction - - // - // task to get multiplicatin factor for counters - // - - task count_mbps_mfactor (int bytes_in_kilobytes) ; - realtime delta; - realtime scale; - begin - // define current timeunit value - delta = $realtime; - #1; - delta = $realtime - delta; - - // define time scale factor - scale = 1s/delta; - - // kilobytes - mbps_mfactor = real'(scale)/(bytes_in_kilobytes); - - // megabytes - mbps_mfactor = mbps_mfactor/(bytes_in_kilobytes); - - mbps_mfactor = mbps_mfactor*pDatamBits; - - // define max bandwwidth : 1 world per cycle period - @(sys_if.cb); - delta = $realtime; - @(sys_if.cb); - delta = $realtime - delta; - - max_bandwidth = (1/delta)*mbps_mfactor; - - end - endtask - - endclass - -`endif

trunk/testbench/hssrdc_bandwidth_monitor_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/tb_top.sv =================================================================== --- trunk/testbench/tb_top.sv (revision 2) +++ trunk/testbench/tb_top.sv (nonexistent) @@ -1,182 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : tb_top.sv -// -// Description : testbench top level -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_timescale.vh" -`include "hssdrc_define.vh" -`include "hssdrc_timing.vh" -`include "hssdrc_tb_sys_if.vh" - -module tb_top; - - parameter cPeriod = 1000.0/pClkMHz; - parameter cHalfPeriod = cPeriod/2.0; - - wire [pDataBits-1:0] dq; - wire [pDatamBits-1:0] dqm; - wire [pSdramAddrBits-1 :0] addr; - wire [pBaBits-1 :0] ba; - wire cke ; - wire cs_n ; - wire ras_n ; - wire cas_n ; - wire we_n ; - - logic sys_write; - logic sys_read ; - logic sys_refr ; - rowa_t sys_rowa ; - cola_t sys_cola ; - ba_t sys_ba ; - burst_t sys_burst ; - chid_t sys_chid_i; - data_t sys_wdata ; - datam_t sys_wdatam; - logic sys_ready ; - logic sys_use_wdata ; - logic sys_vld_rdata ; - chid_t sys_chid_o ; - data_t sys_rdata ; - - - bit clk_main ; - bit clk; - bit nclk; - - bit reset ; - bit sclr ; - - hssdrc_tb_sys_if sys_if (clk, reset, sclr); - - assign sys_write = sys_if.write ; - assign sys_read = sys_if.read ; - assign sys_refr = sys_if.refr ; - assign sys_rowa = sys_if.rowa ; - assign sys_cola = sys_if.cola ; - assign sys_ba = sys_if.ba ; - assign sys_burst = sys_if.burst ; - assign sys_chid_i = sys_if.chid_i; - assign sys_wdata = sys_if.wdata ; - assign sys_wdatam = sys_if.wdatam; - - assign sys_if.ready = sys_ready ; - assign sys_if.use_wdata = sys_use_wdata ; - assign sys_if.vld_rdata = sys_vld_rdata ; - assign sys_if.chid_o = sys_chid_o ; - assign sys_if.rdata = sys_rdata ; - - - mt48lc2m32b2 sdram_chip ( - .Dq (dq ), - .Addr (addr ), - .Ba (ba ), - .Clk (nclk ), - .Cke (cke ), - .Cs_n (cs_n ), - .Ras_n (ras_n), - .Cas_n (cas_n), - .We_n (we_n ), - .Dqm (dqm ) - ); - - sdram_interpretator inter ( - .ba (ba), - .cs_n (cs_n ), - .ras_n(ras_n), - .cas_n(cas_n), - .we_n (we_n ), - .a10 (addr [10] ) - ); - - hssdrc_top top( - .clk (clk ), - .reset (reset), - .sclr (sclr ), - // - .sys_write (sys_write ), - .sys_read (sys_read ), - .sys_refr (sys_refr ), - .sys_rowa (sys_rowa ), - .sys_cola (sys_cola ), - .sys_ba (sys_ba ), - .sys_burst (sys_burst ), - .sys_chid_i (sys_chid_i ), - .sys_wdata (sys_wdata ), - .sys_wdatam (sys_wdatam ), - .sys_ready (sys_ready ), - .sys_use_wdata (sys_use_wdata), - .sys_vld_rdata (sys_vld_rdata), - .sys_chid_o (sys_chid_o ), - .sys_rdata (sys_rdata ), - // - .dq (dq ), - .dqm (dqm ), - .addr (addr ), - .ba (ba ), - .cke (cke ), - .cs_n (cs_n ), - .ras_n (ras_n), - .cas_n (cas_n), - .we_n (we_n ) - ); - - initial begin : clock_generator - clk_main = 1'b0; - #(cHalfPeriod); - forever clk_main = #(cHalfPeriod) ~clk_main; - end - - always_comb begin - clk <= clk_main; - nclk <= #2 ~clk_main; // model output buffer delay - end - - assign sclr = 1'b0; - - initial begin : reset_generator - reset = 1'b1; - - repeat (4) @(posedge clk); - @(negedge clk); - - reset = 1'b0; - end - - tb_prog prog (sys_if.tb); - -endmodule

trunk/testbench/tb_top.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/sdram_interpretator.sv =================================================================== --- trunk/testbench/sdram_interpretator.sv (revision 2) +++ trunk/testbench/sdram_interpretator.sv (nonexistent) @@ -1,115 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : sdram_interpretator.sv -// -// Description : testbench only sdram command decoder -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_timescale.vh" - -module sdram_interpretator (ba, cs_n, ras_n, cas_n, we_n, a10); - - input wire [1:0] ba; - input wire cs_n; - input wire ras_n; - input wire cas_n; - input wire we_n; - input wire a10; - - enum { - nop, - act0, act1, act2, act3, - rd0, rd1, rd2, rd3, - wr0, wr1, wr2, wr3, - bt, - pre0, pre1, pre2, pre3, - prea, arefr, lmr, inop, unknown - } cmd_e; - - - always_comb begin - logic [3:0] tmp; - - tmp = {cs_n, ras_n, cas_n, we_n}; - - cmd_e = unknown; - - if (cs_n) - cmd_e = inop; - else - case (tmp) - 4'b0111 : cmd_e = nop; - 4'b0011 : begin - case (ba) - 2'd1 : cmd_e = act1; - 2'd2 : cmd_e = act2; - 2'd3 : cmd_e = act3; - default : cmd_e = act0; - endcase - end - 4'b0101 : begin - case (ba) - 2'd1 : cmd_e = rd1; - 2'd2 : cmd_e = rd2; - 2'd3 : cmd_e = rd3; - default : cmd_e = rd0; - endcase - end - 4'b0100 : begin - case (ba) - 2'd1 : cmd_e = wr1; - 2'd2 : cmd_e = wr2; - 2'd3 : cmd_e = wr3; - default : cmd_e = wr0; - endcase - end - 4'b0110 : cmd_e = bt; - 4'b0010 : - if (a10) cmd_e = prea; - else begin - case (ba) - 2'd1 : cmd_e = pre1; - 2'd2 : cmd_e = pre2; - 2'd3 : cmd_e = pre3; - default : cmd_e = pre0; - endcase - end - 4'b0001 : cmd_e = arefr; - 4'b0000 : cmd_e = lmr; - default : cmd_e = unknown; - endcase - end - -endmodule

trunk/testbench/sdram_interpretator.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/sdram_agent_class.sv =================================================================== --- trunk/testbench/sdram_agent_class.sv (revision 2) +++ trunk/testbench/sdram_agent_class.sv (nonexistent) @@ -1,173 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : sdram_agent_class.sv -// -// Description : agent for connect with hssdrc controller via driver -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "tb_define.svh" -`include "sdram_transaction_class.sv" - -class sdram_agent_class; - - // to hssdrc_driver - sdram_tr_mbx in_mbx; - - // input transaction - sdram_tr_mbx write_tr_mbx; - sdram_tr_mbx read_tr_mbx; - - // tb syncronization : transaction done numbers - int write_tr_done_num; - int read_tr_done_num; - - // acknowledge from driver - sdram_tr_ack_mbx done_mbx; - - // - // - // - - function new (sdram_tr_mbx in_mbx, sdram_tr_ack_mbx done_mbx, sdram_tr_mbx write_tr_mbx, read_tr_mbx); - - this.in_mbx = in_mbx; - - this.done_mbx = done_mbx; - - this.write_tr_mbx = write_tr_mbx; - this.read_tr_mbx = read_tr_mbx; - - endfunction - - // - // - // - - task SetTransaction (sdram_transaction_class tr); - tr_type_e_t ret_code; - - in_mbx.put (tr); - - case (tr.tr_type) - cTR_WRITE_LOCKED, cTR_READ_LOCKED, cTR_REFR_LOCKED : done_mbx.get (ret_code); - default : begin end - endcase - - endtask - - // - // - // - - task run_write_read (); - - fork - write_read(); - join_none - - endtask - - // - // - // - - task stop_write_read (); - disable this.run_write_read; - endtask - - // - // - // - - task write_read (); - const int sequental_tr_max_num = 6; - - int tr_num; - - int write_tr_max_num; - int read_tr_max_num; - - int avail_read_tr_num; - - sdram_transaction_class write_tr; - sdram_transaction_class read_tr; - - write_tr_done_num = 0; - read_tr_done_num = 0; - - forever begin - - // - // if there is something to write - // - assert ( std::randomize(write_tr_max_num) with {write_tr_max_num inside {[1:sequental_tr_max_num]};} ) - - for (tr_num = 0; tr_num < write_tr_max_num; tr_num++) begin : write_state - - if (!write_tr_mbx.try_get (write_tr)) - break; - - SetTransaction (write_tr); - - write_tr_done_num++; - end : write_state - - // - // read - // - - assert ( std::randomize(read_tr_max_num) with {read_tr_max_num inside {[1:sequental_tr_max_num]};} ); - - avail_read_tr_num = write_tr_done_num - read_tr_done_num; - - if (read_tr_max_num > avail_read_tr_num) - read_tr_max_num = avail_read_tr_num; - - for (tr_num = 0; tr_num < read_tr_max_num; tr_num++) begin : read_state - - if (!read_tr_mbx.try_get(read_tr)) - break; - - SetTransaction (read_tr); - - read_tr_done_num++; - end : read_state - - #10; - end - - endtask - -endclass

trunk/testbench/sdram_agent_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/message_class.sv =================================================================== --- trunk/testbench/message_class.sv (revision 2) +++ trunk/testbench/message_class.sv (nonexistent) @@ -1,106 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : message_class.sv -// -// Description : simple message service class -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`ifndef __MESSAGE_CLASS__ - - `define __MESSAGE_CLASS__ - - class message_class; - - static int fp; - - static int err_cnt; - - // - // - // - - function new (string file_name = ""); - if (file_name.len() != 0) - fp = $fopen(file_name, "w"); - else - fp = 0; - endfunction - - // - // - // - - function void stop(); - $fclose(fp); - endfunction - - // - // - // - - function void note (string str); - string io_str; - - io_str = $psprintf("**NOTE** at %0t : ", $time); - - io_str = {io_str, str}; - - $display (io_str); - if (fp) - $fdisplay (fp, io_str); - endfunction - - // - // - // - - function void err (string str); - string io_str; - - err_cnt++; - - io_str = $psprintf("**ERROR** at %0t : ", $time); - - io_str = {io_str, str}; - - $display (io_str); - if (fp) - $fdisplay (fp, io_str); - - endfunction - - endclass - -`endif

trunk/testbench/message_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/sdram_tread_class.sv =================================================================== --- trunk/testbench/sdram_tread_class.sv (revision 2) +++ trunk/testbench/sdram_tread_class.sv (nonexistent) @@ -1,105 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : sdram_tread_class.sv -// -// Description : virtual sdram treads using for sdram chip testing -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - - -`include "tb_define.svh" - -`ifndef __SDRAM_TREAD_CLASS_SV__ - - `define __SDRAM_TREAD_CLASS_SV__ - - class sdram_tread_class; - - sdram_tread_state_s_t active_tread_state [sdram_tread_ptr_t]; - - rand sdram_tread_ptr_t curr_tread_num; // no need to constrant - - sdram_tread_ptr_t disable_tread_num [$]; - - constraint select_tread { !(curr_tread_num inside {disable_tread_num}); } - - // - // - // - - function void Init () ; - int tread_num = 0; - const int shift = clogb2(cBaMaxValue); - sdram_tread_state_s_t tread_state; - - if (active_tread_state.num != 0) - active_tread_state.delete; - - if (disable_tread_num.size != 0) - disable_tread_num = {}; - - for (int rowa = 0; rowa < cRowaMaxValue; rowa++) begin - for (int ba = 0; ba < cBaMaxValue; ba++) begin - - tread_num = (rowa << shift) + ba; - - tread_state = '{ba : ba, rowa : rowa, cola : 0}; - - active_tread_state[tread_num] = tread_state; - - end - end - - endfunction - - // - // - // - - function burst_t GetBurst (input sdram_tread_state_s_t tread_state); - - int max_burst; - - max_burst = cColaMaxValue - tread_state.cola; - - if (max_burst > cBurstMaxValue) max_burst = 16; - - assert (std::randomize(GetBurst) with {GetBurst inside {[1:max_burst]};}) - else $error ("burst generate error : max burst = %0d burst = %0d", max_burst, GetBurst ); - - endfunction - - endclass - -`endif

trunk/testbench/sdram_tread_class.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/testbench/tb_prog.sv =================================================================== --- trunk/testbench/tb_prog.sv (revision 2) +++ trunk/testbench/tb_prog.sv (nonexistent) @@ -1,538 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:54:00 $ -// -// Workfile : tb_prog.sv -// -// Description : testbench program for all cases -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_timescale.vh" -`include "hssdrc_define.vh" -`include "hssdrc_timing.vh" -`include "tb_define.svh" - -`include "message_class.sv" - -`include "hssdrc_driver_class.sv" -`include "hssrdc_bandwidth_monitor_class.sv" -`include "hssrdc_scoreboard_class.sv" - -`include "sdram_transaction_class.sv" - -`include "sdram_tread_class.sv" -`include "sdram_agent_class.sv" - -program tb_prog (interface sys_if); - - // agent <-> driver mailbox - sdram_tr_mbx agent2drv_mbx; - sdram_tr_ack_mbx drv2agent_mbx; - - // message service - message_class msg; - - // test program -> agent mailbox - sdram_tr_mbx agent_write_mbx; - sdram_tr_mbx agent_read_mbx; - - // transaction agent class - sdram_agent_class agent; - - // virtual sdram treads - sdram_tread_class tread; - - // driver to uut - hssrdc_driver_class driver; - - // driver callbacks - hssdrc_bandwidth_monitor_class bandwidth_mon; - hssdrc_scoreboard_class scoreboard; - - event scoreboard_event; - event bandwidth_mon_event; - - initial begin - - agent2drv_mbx = new (8); - drv2agent_mbx = new (8); - - agent_write_mbx = new (8); - agent_read_mbx = new (8); - - // init objects - msg = new ("tb_hssdrc.log"); - - driver = new (sys_if, agent2drv_mbx, drv2agent_mbx); - - agent = new (agent2drv_mbx, drv2agent_mbx, agent_write_mbx, agent_read_mbx); - - tread = new ; - - bandwidth_mon = new (sys_if, bandwidth_mon_event); - - scoreboard = new (msg, scoreboard_event); - - driver.run(); - - agent.run_write_read (); - - // calibrate bandwidth monitor - - bandwidth_mon.count_mbps_mfactor(1000); - - // disable debug process inside sdram model - - force tb_top.sdram_chip.Debug = 0; - - wait (sys_if.reset == 1'b0); - - wait (sys_if.cb.ready == 1'b1); - - msg.note ("Program start"); - -`ifdef HSSDRC_NOT_SHARE_ACT_COMMAND - msg.note ("Controller use HSSDRC_NOT_SHARE_ACT_COMMAND macros"); -`endif - -`ifdef HSSDRC_SHARE_ONE_DECODER - msg.note ("Controller use HSSDRC_SHARE_ONE_DECODER macros"); -`endif - -`ifdef HSSDRC_SHARE_NONE_DECODER - msg.note ("Controller use HSSDRC_SHARE_NONE_DECODER macros"); -`endif - - //test(-1,-1); // simple_debug_test - //test(0,0); // linear_test - test(1,1); // random_test - //test(2,2); // bandwidth_measurement - - agent.stop_write_read(); - - driver.stop(); - - msg.stop(); - - $stop; - $finish (2); - - end - - // - // - // - - task test (input int start_task, end_task); - int task_num; - - sdram_transaction_class write_tr; - sdram_transaction_class read_tr; - - sdram_transaction_class rand_tr; - sdram_transaction_class tr; - - int err; - - int tr_burst; - tr_type_e_t tr_type; - int tr_id; - int tr_chid; - int tr_num; - - bit tread_end; - int next_cola; - - sdram_tread_state_s_t tread_state; // selected tread state - int tread_num; // selected tread num - - string log_str; - begin - - for (task_num = start_task; task_num <= end_task; task_num++) - begin - // - // Task -1 : manualy checking write/read transactions - // - if (task_num == -1) begin : simple_debug_test - - msg.note ($psprintf("test %0d : simple debug test", task_num)); - - // - // test for debug only - // - - tr = new (0, cTR_WRITE_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(3)); - tr.GetLinearPacket(); - agent.SetTransaction(tr); - - tr = new (0, cTR_WRITE_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(4)); - tr.GetLinearPacket(); - agent.SetTransaction(tr); - - tr = new (0, cTR_READ_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(4), .chid(1)); - tr.GetLinearPacket(); - agent.SetTransaction(tr); - -// tr = new (0, cTR_READ, .ba(0), .rowa(1), .cola(0), .burst(2)); -// tr.GetLinearPacket(); -// agent.SetTransaction(tr); - - tr = new (0, cTR_REFR_LOCKED, .ba(0), .rowa(0)); - agent.SetTransaction(tr); - - repeat (10) @(sys_if.cb); - end : simple_debug_test - - // - // Task 0 : linear write -> read with linear data (random burst only) - // - - else if (task_num == 0) begin : linear_test - - msg.note ($psprintf("test %0d : linear write -> read with linear data", task_num)); - - // - // test for correctness. set scoreboard callbacks - // - - driver.cbs = {}; - scoreboard.start(); - driver.cbs.push_back(scoreboard); - - driver.random_delay_mode = 1; - // - // transaction generator - // - - tread.Init(); - - msg.note ($psprintf("test %0d start_task with number of treads is %0d", task_num, tread.active_tread_state.num())); - - for (tread_num = 0; tread_num < tread.active_tread_state.num(); tread_num++) begin - - // - // get tread state - // - - tread_state = tread.active_tread_state [tread_num]; - - msg.note ($psprintf("start tread %0d" , tread_num)); - - // - // full tread transaction - // - - tr_num = 0; - - do begin - // - // generate transaction - // - tr_id = tread_num; - tr_type = cTR_WRITE; - tr_burst = tread.GetBurst (tread_state); - tr_chid = tread_state.ba; - - write_tr = new (tr_id, tr_type, tread_state.ba, tread_state.rowa, tread_state.cola, tr_burst, tr_chid); - write_tr.GetLinearPacket(); - - read_tr = new write_tr; - read_tr.tr_type = cTR_READ; - // - // set transaction - // - #10; - agent_write_mbx.put (write_tr); - #10; - agent_read_mbx.put (read_tr); - // - // update tread state - // - tr_num++; - - next_cola = tread_state.cola + tr_burst; - - tread_end = (next_cola >= cColaMaxValue); - - tread_state.cola = next_cola; - - end - while (tread_end != 1); - - msg.note ($psprintf("done tread %0d. number of tread transactions %0d", tread_num, tr_num)); - - end - - // - // wait compare done - // - - do - @(scoreboard_event); - while (agent.read_tr_done_num != scoreboard.checked_tr_num); - - msg.note ($psprintf("test%0d done. Number of errors = %0d", task_num, scoreboard.check_err_num)); - - end : linear_test - - // - // Task 1 : random write -> read with random data, rowa, ba, burst, linear cola - // - - else if (task_num == 1) begin : random_test - - msg.note ($psprintf("test %0d : random write -> read with random data", task_num)); - - // - // test for correctness. set scoreboard callbacks - // - - driver.cbs = {}; - scoreboard.start(); - driver.cbs.push_back(scoreboard); - - driver.random_delay_mode = 1; - - // - // transaction generator - // - - tread.Init(); - - msg.note ($psprintf("test %0d start_task with number of treads is %0d", task_num, tread.active_tread_state.num())); - - tr_num = 0; - - do begin - - // - // select tread - // - - assert (tread.randomize()) else $error ("generate tread selection error"); - - tread_num = tread.curr_tread_num; - - tread_state = tread.active_tread_state [tread_num]; - - // - // generate transaction - // - - tr_burst = tread.GetBurst (tread_state); - tr_type = cTR_WRITE; - tr_id = tread_num; - tr_chid = tread_state.ba; - - write_tr = new (tr_id, tr_type, tread_state.ba, tread_state.rowa, tread_state.cola, tr_burst, tr_chid); - //write_tr.GetLinearPacket(); - write_tr.GetRandomPacket(); - - read_tr = new write_tr; - read_tr.tr_type = cTR_READ; - // - // set transaction - // - #10; - agent_write_mbx.put (write_tr); - #10; - agent_read_mbx.put (read_tr); - // - // update tread state - // - tr_num++; - - next_cola = tread_state.cola + tr_burst; - - tread_end = (next_cola >= cColaMaxValue); - - tread_state.cola = next_cola; - - tread.active_tread_state [tread_num] = tread_state; - // - // if tread end kill it - // - if (tread_end) begin - tread.active_tread_state.delete (tread_num); - tread.disable_tread_num.push_back (tread_num); // random pointer constrain update - msg.note ($psprintf("done tread %0d", tread_num)); - end - - if (tr_num > cTransactionMaxValue) break; - - if (tr_num % cTransactionLogPeriod == 0) - msg.note($psprintf("transaction done %0d", tr_num)); - - end - while (tread.active_tread_state.num() != 0); - - // - // wait compare done - // - - do - @(scoreboard_event); - while (agent.read_tr_done_num != scoreboard.checked_tr_num); - - msg.note ($psprintf("test%0d done. Number of errors = %0d", task_num, scoreboard.check_err_num)); - - end : random_test - - // - // Task 2 : bandwidth measurement - // - - else if (task_num == 2) begin : bandwidth_measurement - - msg.note ($psprintf("test %0d : access bandwidth measurement", task_num)); - - // - // test for perfromance. set bandwidth monitor callbacks, no random delay mode - // - - driver.cbs = {}; - driver.cbs.push_back(bandwidth_mon); - - driver.random_delay_mode = 0; - - // - // generate transactions - // - foreach ( test_mode [t] ) begin : test_mode_cycle - - msg.note ($psprintf("test %0d start %0s test mode", task_num, test_mode_name[test_mode[t]])); - - foreach (burst_mode [b]) begin : burst_cycle - - foreach (address_mode [a] ) begin : address_cycle - - time start_time; - string str; - - tr_num = 0; - start_time = $time; - - // - // init tr.generator - // - - rand_tr = new; - rand_tr.burst_random_mode = burst_mode [b]; - rand_tr.address_random_mode = address_mode [a]; - - bandwidth_mon.start(); - - do begin - - assert ( rand_tr.randomize() ) else begin - $error("test %0d : random transaction generate error", task_num); - $stop; - end - - if ( test_mode[t].write_mode) begin - write_tr = new rand_tr; - write_tr.id = tr_num++; - write_tr.tr_type = cTR_WRITE; - - agent.SetTransaction(write_tr); - end - - if ( test_mode[t].read_mode) begin - read_tr = new rand_tr; - read_tr.id = tr_num++; - read_tr.tr_type = cTR_READ; - - agent.SetTransaction(read_tr); - end - - if (tr_num % cTransactionLogPeriod == 0) - msg.note($psprintf("task %0d transaction done %0d", task_num, tr_num)); - - end - while (($time - start_time) < cPerfomanceInterval); - - // - // syncronize output for measure - // - do - @(bandwidth_mon_event); - while (tr_num != bandwidth_mon.measured_tr_num); - - // - // stop measure - // - bandwidth_mon.stop(); - - // - // logs - // - - str = $psprintf("task %0d done. %0s mode bandwith : %0s and %0s is :\n", task_num, - test_mode_name[test_mode[t]], address_mode_name [address_mode[a]], burst_mode_name [burst_mode[b]]); - - if (test_mode [t].write_mode) - str = {str, $psprintf("\t\twrite bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", - bandwidth_mon.write_bandwidth, bandwidth_mon.write_bandwidth_percent)}; - - if (test_mode [t].read_mode) - str = {str, $psprintf("\t\t read bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", - bandwidth_mon.read_bandwidth, bandwidth_mon.read_bandwidth_percent)}; - - if (test_mode [t].read_mode & test_mode [t].write_mode) - str = {str, $psprintf("\t\tram bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", - bandwidth_mon.bandwidth, bandwidth_mon.bandwidth_percent)}; - - msg.note(str); - - end : address_cycle - - end : burst_cycle - - end : test_mode_cycle - - - end : bandwidth_measurement - - end - - msg.note ("all test done"); - - repeat (100) @(sys_if.cb); - end - - endtask - - - -endprogram

trunk/testbench/tb_prog.sv Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_top.v =================================================================== --- trunk/rtl/hssdrc_top.v (revision 2) +++ trunk/rtl/hssdrc_top.v (nonexistent) @@ -1,758 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_top.v -// -// Description : top level of memory controller -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_top ( - clk , - reset , - sclr , - sys_write , - sys_read , - sys_refr , - sys_rowa , - sys_cola , - sys_ba , - sys_burst , - sys_chid_i , - sys_wdata , - sys_wdatam , - sys_ready , - sys_use_wdata , - sys_vld_rdata , - sys_chid_o , - sys_rdata , - dq , - dqm , - addr , - ba , - cke , - cs_n , - ras_n , - cas_n , - we_n - ); - - input wire clk ; - input wire reset; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // system interface - //-------------------------------------------------------------------------------------------------- - - input wire sys_write ; - input wire sys_read ; - input wire sys_refr ; - input rowa_t sys_rowa ; - input cola_t sys_cola ; - input ba_t sys_ba ; - input burst_t sys_burst ; - input chid_t sys_chid_i ; - input data_t sys_wdata ; - input datam_t sys_wdatam ; - - output logic sys_ready ; - output logic sys_use_wdata ; - output logic sys_vld_rdata ; - output chid_t sys_chid_o ; - output data_t sys_rdata ; - - //-------------------------------------------------------------------------------------------------- - // sdram interface - //-------------------------------------------------------------------------------------------------- - - inout wire [pDataBits-1:0] dq; - output datam_t dqm; - output sdram_addr_t addr; - output ba_t ba; - output logic cke; - output logic cs_n; - output logic ras_n; - output logic cas_n; - output logic we_n; - - //-------------------------------------------------------------------------------------------------- - // internal signals - //-------------------------------------------------------------------------------------------------- - - wire init_done; - wire hssdrc_sclr; - - //-------------------------------------------------------------------------------------------------- - // refr_cnt <-> arbiter_in - //-------------------------------------------------------------------------------------------------- - - wire refr_cnt___ack ; - wire refr_cnt___hi_req ; - wire refr_cnt___low_req ; - - //-------------------------------------------------------------------------------------------------- - // arbiter_in <-> decoder's - //-------------------------------------------------------------------------------------------------- - - wire arbiter_in0___write ; - wire arbiter_in0___read ; - wire arbiter_in0___refr ; - rowa_t arbiter_in0___rowa ; - cola_t arbiter_in0___cola ; - ba_t arbiter_in0___ba ; - burst_t arbiter_in0___burst ; - chid_t arbiter_in0___chid ; - wire arbiter_in0___ready ; - // - wire arbiter_in1___write ; - wire arbiter_in1___read ; - wire arbiter_in1___refr ; - rowa_t arbiter_in1___rowa ; - cola_t arbiter_in1___cola ; - ba_t arbiter_in1___ba ; - burst_t arbiter_in1___burst ; - chid_t arbiter_in1___chid ; - wire arbiter_in1___ready ; - // - wire arbiter_in2___write ; - wire arbiter_in2___read ; - wire arbiter_in2___refr ; - rowa_t arbiter_in2___rowa ; - cola_t arbiter_in2___cola ; - ba_t arbiter_in2___ba ; - burst_t arbiter_in2___burst ; - chid_t arbiter_in2___chid ; - wire arbiter_in2___ready ; - - //-------------------------------------------------------------------------------------------------- - // ba_map <-> decoder's - //-------------------------------------------------------------------------------------------------- - - wire ba_map___update ; - wire ba_map___clear ; - ba_t ba_map___ba ; - rowa_t ba_map___rowa ; - wire ba_map___pre_act_rw ; - wire ba_map___act_rw ; - wire ba_map___rw ; - wire ba_map___all_close ; - - //-------------------------------------------------------------------------------------------------- - // decoder's <-> arbiter_out - //-------------------------------------------------------------------------------------------------- - - wire dec0___pre_all ; - wire dec0___refr ; - wire dec0___pre ; - wire dec0___act ; - wire dec0___read ; - wire dec0___write ; - wire dec0___pre_all_enable ; - wire dec0___refr_enable ; - wire dec0___pre_enable ; - wire dec0___act_enable ; - wire dec0___read_enable ; - wire dec0___write_enable ; - wire dec0___locked ; - wire dec0___last ; - rowa_t dec0___rowa ; - cola_t dec0___cola ; - ba_t dec0___ba ; - chid_t dec0___chid ; - sdram_burst_t dec0___burst ; - // - wire dec1___pre_all ; - wire dec1___refr ; - wire dec1___pre ; - wire dec1___act ; - wire dec1___read ; - wire dec1___write ; - wire dec1___pre_all_enable ; - wire dec1___refr_enable ; - wire dec1___pre_enable ; - wire dec1___act_enable ; - wire dec1___read_enable ; - wire dec1___write_enable ; - wire dec1___locked ; - wire dec1___last ; - rowa_t dec1___rowa ; - cola_t dec1___cola ; - ba_t dec1___ba ; - chid_t dec1___chid ; - sdram_burst_t dec1___burst ; - // - wire dec2___pre_all ; - wire dec2___refr ; - wire dec2___pre ; - wire dec2___act ; - wire dec2___read ; - wire dec2___write ; - wire dec2___pre_all_enable ; - wire dec2___refr_enable ; - wire dec2___pre_enable ; - wire dec2___act_enable ; - wire dec2___read_enable ; - wire dec2___write_enable ; - wire dec2___locked ; - wire dec2___last ; - rowa_t dec2___rowa ; - cola_t dec2___cola ; - ba_t dec2___ba ; - chid_t dec2___chid ; - sdram_burst_t dec2___burst ; - - //-------------------------------------------------------------------------------------------------- - // access_manager -> arbiter_out - //-------------------------------------------------------------------------------------------------- - - wire access_manager___pre_all_enable ; - wire access_manager___refr_enable ; - wire [0:3] access_manager___pre_enable ; - wire [0:3] access_manager___act_enable ; - wire [0:3] access_manager___read_enable ; - wire [0:3] access_manager___write_enable ; - - //-------------------------------------------------------------------------------------------------- - // arbiter_out -> multiplexer/access_manager - //-------------------------------------------------------------------------------------------------- - - wire arbiter_out___pre_all ; - wire arbiter_out___refr ; - wire arbiter_out___pre ; - wire arbiter_out___act ; - wire arbiter_out___read ; - wire arbiter_out___write ; - rowa_t arbiter_out___rowa ; - cola_t arbiter_out___cola ; - ba_t arbiter_out___ba ; - chid_t arbiter_out___chid ; - sdram_burst_t arbiter_out___burst ; - - //-------------------------------------------------------------------------------------------------- - // init_state -> multiplexer - //-------------------------------------------------------------------------------------------------- - - wire init_state___pre_all ; - wire init_state___refr ; - wire init_state___lmr ; - rowa_t init_state___rowa ; - - //-------------------------------------------------------------------------------------------------- - // multiplexer -> sdram_addr_path/sdram_data_path - //-------------------------------------------------------------------------------------------------- - - wire mux___pre_all ; - wire mux___refr ; - wire mux___pre ; - wire mux___act ; - wire mux___read ; - wire mux___write ; - wire mux___lmr ; - rowa_t mux___rowa ; - cola_t mux___cola ; - ba_t mux___ba ; - chid_t mux___chid ; - sdram_burst_t mux___burst ; - - // - // this clear use to disable fsm that must be off when sdram chip is not configured - // - - assign hssdrc_sclr = sclr | ~init_done; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - hssdrc_refr_counter refr_cnt( - .clk (clk ), - .reset (reset), - .sclr (hssdrc_sclr ), // use internal sclr becouse there is refresh "fsm" - .ack (refr_cnt___ack ), - .hi_req (refr_cnt___hi_req ), - .low_req (refr_cnt___low_req) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_arbiter_in arbiter_in ( - .clk (clk ), - .reset (reset), - .sclr (hssdrc_sclr ), // use internal sclr becouse there is arbiter fsm - // - .sys_write (sys_write ) , - .sys_read (sys_read ) , - .sys_refr (sys_refr ) , - .sys_rowa (sys_rowa ) , - .sys_cola (sys_cola ) , - .sys_ba (sys_ba ) , - .sys_burst (sys_burst ) , - .sys_chid_i (sys_chid_i) , - .sys_ready (sys_ready ) , - // - .refr_cnt_ack (refr_cnt___ack ), - .refr_cnt_hi_req (refr_cnt___hi_req ), - .refr_cnt_low_req (refr_cnt___low_req), - // - .dec0_write (arbiter_in0___write), - .dec0_read (arbiter_in0___read ), - .dec0_refr (arbiter_in0___refr ), - .dec0_rowa (arbiter_in0___rowa ), - .dec0_cola (arbiter_in0___cola ), - .dec0_ba (arbiter_in0___ba ), - .dec0_burst (arbiter_in0___burst), - .dec0_chid (arbiter_in0___chid ), - .dec0_ready (arbiter_in0___ready), - // - .dec1_write (arbiter_in1___write), - .dec1_read (arbiter_in1___read ), - .dec1_refr (arbiter_in1___refr ), - .dec1_rowa (arbiter_in1___rowa ), - .dec1_cola (arbiter_in1___cola ), - .dec1_ba (arbiter_in1___ba ), - .dec1_burst (arbiter_in1___burst), - .dec1_chid (arbiter_in1___chid ), - .dec1_ready (arbiter_in1___ready), - // - .dec2_write (arbiter_in2___write), - .dec2_read (arbiter_in2___read ), - .dec2_refr (arbiter_in2___refr ), - .dec2_rowa (arbiter_in2___rowa ), - .dec2_cola (arbiter_in2___cola ), - .dec2_ba (arbiter_in2___ba ), - .dec2_burst (arbiter_in2___burst), - .dec2_chid (arbiter_in2___chid ), - .dec2_ready (arbiter_in2___ready) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_ba_map ba_map ( - .clk (clk ), - .reset (reset), - .sclr (hssdrc_sclr), // use internal sclr becouse there is bank access map - // - .update (ba_map___update), - .clear (ba_map___clear ), - .ba (ba_map___ba ), - .rowa (ba_map___rowa ), - // - .pre_act_rw (ba_map___pre_act_rw), - .act_rw (ba_map___act_rw ), - .rw (ba_map___rw ), - .all_close (ba_map___all_close ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_decoder decoder ( - .clk (clk ), - .reset (reset), - .sclr (hssdrc_sclr), // use internal sclr becouse there is decoders fsm - // - .ba_map_update (ba_map___update ), - .ba_map_clear (ba_map___clear ), - .ba_map_ba (ba_map___ba ), - .ba_map_rowa (ba_map___rowa ), - // - .ba_map_pre_act_rw (ba_map___pre_act_rw), - .ba_map_act_rw (ba_map___act_rw ), - .ba_map_rw (ba_map___rw ), - .ba_map_all_close (ba_map___all_close ), - // - .arb0_write (arbiter_in0___write), - .arb0_read (arbiter_in0___read ), - .arb0_refr (arbiter_in0___refr ), - .arb0_rowa (arbiter_in0___rowa ), - .arb0_cola (arbiter_in0___cola ), - .arb0_ba (arbiter_in0___ba ), - .arb0_burst (arbiter_in0___burst), - .arb0_chid (arbiter_in0___chid ), - .arb0_ready (arbiter_in0___ready), - // - .arb1_write (arbiter_in1___write), - .arb1_read (arbiter_in1___read ), - .arb1_refr (arbiter_in1___refr ), - .arb1_rowa (arbiter_in1___rowa ), - .arb1_cola (arbiter_in1___cola ), - .arb1_ba (arbiter_in1___ba ), - .arb1_burst (arbiter_in1___burst), - .arb1_chid (arbiter_in1___chid ), - .arb1_ready (arbiter_in1___ready), - // - .arb2_write (arbiter_in2___write), - .arb2_read (arbiter_in2___read ), - .arb2_refr (arbiter_in2___refr ), - .arb2_rowa (arbiter_in2___rowa ), - .arb2_cola (arbiter_in2___cola ), - .arb2_ba (arbiter_in2___ba ), - .arb2_burst (arbiter_in2___burst), - .arb2_chid (arbiter_in2___chid ), - .arb2_ready (arbiter_in2___ready), - // - .dec0_pre_all (dec0___pre_all ), - .dec0_refr (dec0___refr ), - .dec0_pre (dec0___pre ), - .dec0_act (dec0___act ), - .dec0_read (dec0___read ), - .dec0_write (dec0___write ), - .dec0_pre_all_enable(dec0___pre_all_enable), - .dec0_refr_enable (dec0___refr_enable ), - .dec0_pre_enable (dec0___pre_enable ), - .dec0_act_enable (dec0___act_enable ), - .dec0_read_enable (dec0___read_enable ), - .dec0_write_enable (dec0___write_enable ), - .dec0_locked (dec0___locked ), - .dec0_last (dec0___last ), - .dec0_rowa (dec0___rowa ), - .dec0_cola (dec0___cola ), - .dec0_ba (dec0___ba ), - .dec0_chid (dec0___chid ), - .dec0_burst (dec0___burst ), - // - .dec1_pre_all (dec1___pre_all ), - .dec1_refr (dec1___refr ), - .dec1_pre (dec1___pre ), - .dec1_act (dec1___act ), - .dec1_read (dec1___read ), - .dec1_write (dec1___write ), - .dec1_pre_all_enable(dec1___pre_all_enable), - .dec1_refr_enable (dec1___refr_enable ), - .dec1_pre_enable (dec1___pre_enable ), - .dec1_act_enable (dec1___act_enable ), - .dec1_read_enable (dec1___read_enable ), - .dec1_write_enable (dec1___write_enable ), - .dec1_locked (dec1___locked ), - .dec1_last (dec1___last ), - .dec1_rowa (dec1___rowa ), - .dec1_cola (dec1___cola ), - .dec1_ba (dec1___ba ), - .dec1_chid (dec1___chid ), - .dec1_burst (dec1___burst ), - // - .dec2_pre_all (dec2___pre_all ), - .dec2_refr (dec2___refr ), - .dec2_pre (dec2___pre ), - .dec2_act (dec2___act ), - .dec2_read (dec2___read ), - .dec2_write (dec2___write ), - .dec2_pre_all_enable(dec2___pre_all_enable), - .dec2_refr_enable (dec2___refr_enable ), - .dec2_pre_enable (dec2___pre_enable ), - .dec2_act_enable (dec2___act_enable ), - .dec2_read_enable (dec2___read_enable ), - .dec2_write_enable (dec2___write_enable ), - .dec2_locked (dec2___locked ), - .dec2_last (dec2___last ), - .dec2_rowa (dec2___rowa ), - .dec2_cola (dec2___cola ), - .dec2_ba (dec2___ba ), - .dec2_chid (dec2___chid ), - .dec2_burst (dec2___burst ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_arbiter_out arbiter_out( - .clk (clk), - .reset (reset), - .sclr (hssdrc_sclr), // use internal sclr becouse there is arbiter fsm - // - .dec0_pre_all (dec0___pre_all ), - .dec0_refr (dec0___refr ), - .dec0_pre (dec0___pre ), - .dec0_act (dec0___act ), - .dec0_read (dec0___read ), - .dec0_write (dec0___write ), - .dec0_pre_all_enable(dec0___pre_all_enable), - .dec0_refr_enable (dec0___refr_enable ), - .dec0_pre_enable (dec0___pre_enable ), - .dec0_act_enable (dec0___act_enable ), - .dec0_read_enable (dec0___read_enable ), - .dec0_write_enable (dec0___write_enable ), - .dec0_locked (dec0___locked ), - .dec0_last (dec0___last ), - .dec0_rowa (dec0___rowa ), - .dec0_cola (dec0___cola ), - .dec0_ba (dec0___ba ), - .dec0_chid (dec0___chid ), - .dec0_burst (dec0___burst ), - // - .dec1_pre_all (dec1___pre_all ), - .dec1_refr (dec1___refr ), - .dec1_pre (dec1___pre ), - .dec1_act (dec1___act ), - .dec1_read (dec1___read ), - .dec1_write (dec1___write ), - .dec1_pre_all_enable(dec1___pre_all_enable), - .dec1_refr_enable (dec1___refr_enable ), - .dec1_pre_enable (dec1___pre_enable ), - .dec1_act_enable (dec1___act_enable ), - .dec1_read_enable (dec1___read_enable ), - .dec1_write_enable (dec1___write_enable ), - .dec1_locked (dec1___locked ), - .dec1_last (dec1___last ), - .dec1_rowa (dec1___rowa ), - .dec1_cola (dec1___cola ), - .dec1_ba (dec1___ba ), - .dec1_chid (dec1___chid ), - .dec1_burst (dec1___burst ), - // - .dec2_pre_all (dec2___pre_all ), - .dec2_refr (dec2___refr ), - .dec2_pre (dec2___pre ), - .dec2_act (dec2___act ), - .dec2_read (dec2___read ), - .dec2_write (dec2___write ), - .dec2_pre_all_enable(dec2___pre_all_enable), - .dec2_refr_enable (dec2___refr_enable ), - .dec2_pre_enable (dec2___pre_enable ), - .dec2_act_enable (dec2___act_enable ), - .dec2_read_enable (dec2___read_enable ), - .dec2_write_enable (dec2___write_enable ), - .dec2_locked (dec2___locked ), - .dec2_last (dec2___last ), - .dec2_rowa (dec2___rowa ), - .dec2_cola (dec2___cola ), - .dec2_ba (dec2___ba ), - .dec2_chid (dec2___chid ), - .dec2_burst (dec2___burst ), - // - .am_pre_all_enable (access_manager___pre_all_enable), - .am_refr_enable (access_manager___refr_enable ), - .am_pre_enable (access_manager___pre_enable ), - .am_act_enable (access_manager___act_enable ), - .am_read_enable (access_manager___read_enable ), - .am_write_enable (access_manager___write_enable ), - // - .arb_pre_all (arbiter_out___pre_all), - .arb_refr (arbiter_out___refr ), - .arb_pre (arbiter_out___pre ), - .arb_act (arbiter_out___act ), - .arb_read (arbiter_out___read ), - .arb_write (arbiter_out___write ), - .arb_rowa (arbiter_out___rowa ), - .arb_cola (arbiter_out___cola ), - .arb_ba (arbiter_out___ba ), - .arb_chid (arbiter_out___chid ), - .arb_burst (arbiter_out___burst ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_access_manager access_manager ( - .clk (clk ), - .reset (reset), - .sclr (hssdrc_sclr), // use internal sclr becouse there is access "fsm's" - // - .arb_pre_all (arbiter_out___pre_all), - .arb_refr (arbiter_out___refr ), - .arb_pre (arbiter_out___pre ), - .arb_act (arbiter_out___act ), - .arb_read (arbiter_out___read ), - .arb_write (arbiter_out___write ), - .arb_ba (arbiter_out___ba ), - .arb_burst (arbiter_out___burst ), - // - .am_pre_all_enable (access_manager___pre_all_enable), - .am_refr_enable (access_manager___refr_enable ), - .am_pre_enable (access_manager___pre_enable ), - .am_act_enable (access_manager___act_enable ), - .am_read_enable (access_manager___read_enable ), - .am_write_enable (access_manager___write_enable ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_init_state init_state( - .clk (clk ), - .reset (reset), - .sclr (sclr ), // use external sclr becouse this is initial start fsm - .init_done (init_done), - .pre_all (init_state___pre_all), - .refr (init_state___refr ), - .lmr (init_state___lmr ), - .rowa (init_state___rowa ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_mux mux ( - .init_done (init_done), - // - .init_state_pre_all (init_state___pre_all), - .init_state_refr (init_state___refr ), - .init_state_lmr (init_state___lmr ), - .init_state_rowa (init_state___rowa ), - // - .arb_pre_all (arbiter_out___pre_all), - .arb_refr (arbiter_out___refr ), - .arb_pre (arbiter_out___pre ), - .arb_act (arbiter_out___act ), - .arb_read (arbiter_out___read ), - .arb_write (arbiter_out___write ), - .arb_rowa (arbiter_out___rowa ), - .arb_cola (arbiter_out___cola ), - .arb_ba (arbiter_out___ba ), - .arb_chid (arbiter_out___chid ), - .arb_burst (arbiter_out___burst ), - // - .mux_pre_all (mux___pre_all), - .mux_refr (mux___refr ), - .mux_pre (mux___pre ), - .mux_act (mux___act ), - .mux_read (mux___read ), - .mux_write (mux___write ), - .mux_lmr (mux___lmr ), - .mux_rowa (mux___rowa ), - .mux_cola (mux___cola ), - .mux_ba (mux___ba ), - .mux_chid (mux___chid ), - .mux_burst (mux___burst ) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - `ifndef HSSDRC_DQ_PIPELINE - - hssdrc_data_path data_path ( - .clk (clk ), - .reset (reset), - .sclr (sclr ), // use external sclr becouse there is no any fsm - // - .sys_wdata (sys_wdata ), - .sys_wdatam (sys_wdatam ), - .sys_use_wdata (sys_use_wdata), - .sys_vld_rdata (sys_vld_rdata), - .sys_chid_o (sys_chid_o ), - .sys_rdata (sys_rdata ), - // - .arb_read (mux___read ), - .arb_write (mux___write ), - .arb_chid (mux___chid ), - .arb_burst (mux___burst ), - // - .dq (dq ), - .dqm (dqm ) - ); - - `else - - hssdrc_data_path_p1 data_path_p1 ( - .clk (clk ), - .reset (reset), - .sclr (sclr ), // use external sclr becouse there is no any fsm - // - .sys_wdata (sys_wdata ), - .sys_wdatam (sys_wdatam ), - .sys_use_wdata (sys_use_wdata), - .sys_vld_rdata (sys_vld_rdata), - .sys_chid_o (sys_chid_o ), - .sys_rdata (sys_rdata ), - // - .arb_read (mux___read ), - .arb_write (mux___write ), - .arb_chid (mux___chid ), - .arb_burst (mux___burst ), - // - .dq (dq ), - .dqm (dqm ) - ); - - `endif - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - `ifndef HSSDRC_DQ_PIPELINE - - hssdrc_addr_path addr_path( - .clk (clk ), - .reset (reset), - .sclr (sclr ), // use external sclr becouse there is no any fsm - // - .arb_pre_all (mux___pre_all), - .arb_refr (mux___refr ), - .arb_pre (mux___pre ), - .arb_act (mux___act ), - .arb_read (mux___read ), - .arb_write (mux___write ), - .arb_lmr (mux___lmr ), - .arb_rowa (mux___rowa ), - .arb_cola (mux___cola ), - .arb_ba (mux___ba ), - // - .addr (addr ), - .ba (ba ), - .cke (cke ), - .cs_n (cs_n ), - .ras_n (ras_n), - .cas_n (cas_n), - .we_n (we_n ) - ); - - `else - - hssdrc_addr_path_p1 addr_path_p1( - .clk (clk ), - .reset (reset), - .sclr (sclr ), // use external sclr becouse there is no any fsm - // - .arb_pre_all (mux___pre_all), - .arb_refr (mux___refr ), - .arb_pre (mux___pre ), - .arb_act (mux___act ), - .arb_read (mux___read ), - .arb_write (mux___write ), - .arb_lmr (mux___lmr ), - .arb_rowa (mux___rowa ), - .arb_cola (mux___cola ), - .arb_ba (mux___ba ), - // - .addr (addr ), - .ba (ba ), - .cke (cke ), - .cs_n (cs_n ), - .ras_n (ras_n), - .cas_n (cas_n), - .we_n (we_n ) - ); - - `endif - -endmodule - -

trunk/rtl/hssdrc_top.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_init_state.v =================================================================== --- trunk/rtl/hssdrc_init_state.v (revision 2) +++ trunk/rtl/hssdrc_init_state.v (nonexistent) @@ -1,154 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_init_state.v -// -// Description : sdram chip initialization unit -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_timing.vh" -`include "hssdrc_define.vh" - -module hssdrc_init_state ( - clk , - reset , - sclr , - init_done , - pre_all , - refr , - lmr , - rowa - ); - - input wire clk ; - input wire reset; - input wire sclr ; - - output logic init_done; - output logic pre_all ; - output logic refr ; - output logic lmr ; - output rowa_t rowa ; - - assign rowa = cInitLmrValue; - - //--------------------------------------------------------------------------------------------------- - // counter based FSM - // fsm has 1 counter divided by 2 part : - // cnt_high - decode for wait init interval - // cnt_low - execute command sequence when wait done. - // true init time is ~= (1.1 - 1.2) pInit_time for less logic resource using - //--------------------------------------------------------------------------------------------------- - - localparam int unsigned cInitPre = 1; - localparam int unsigned cInitRefr0 = cInitPre + cTrp; - localparam int unsigned cInitRefr1 = cInitRefr0 + cTrfc; - localparam int unsigned cInitLmr = cInitRefr1 + cTrfc; - localparam int unsigned cInitDone = cInitLmr + cTmrd + 1; - - // - // counter parameters - // - - localparam int unsigned cInitCntLowWidth = clogb2(cInitDone); - localparam int unsigned cInitCntHighMax = (cInitTime >> cInitCntLowWidth) + 1; - localparam int unsigned cInitCntWidth = clogb2(cInitCntHighMax) + cInitCntLowWidth; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - logic [cInitCntWidth-1 : 0] cnt; - logic [cInitCntLowWidth-1 : 0] cnt_low; - logic [cInitCntWidth-1 : cInitCntLowWidth] cnt_high; - - logic cnt_high_is_max; - - assign cnt_low = cnt [cInitCntLowWidth-1 : 0]; - assign cnt_high = cnt [cInitCntWidth-1 : cInitCntLowWidth]; - - - always_ff @(posedge clk or posedge reset) begin : cnt_fsm - if (reset) - cnt <= '0; - else if (sclr) - cnt <= '0; - else if (~init_done) - cnt <= cnt + 1'b1; - end - - - always_ff @(posedge clk or posedge reset) begin : cnt_fsm_comparator - if (reset) - cnt_high_is_max <= 1'b0; - else if (sclr) - cnt_high_is_max <= 1'b0; - else - cnt_high_is_max <= (cnt_high == cInitCntHighMax); - end - - - always_ff @(posedge clk or posedge reset) begin : cnt_fsm_decode - if (reset) begin - init_done <= 1'b0; - pre_all <= 1'b0; - refr <= 1'b0; - lmr <= 1'b0; - end - else if (sclr) begin - init_done <= 1'b0; - pre_all <= 1'b0; - refr <= 1'b0; - lmr <= 1'b0; - end - else begin - - pre_all <= 1'b0; - refr <= 1'b0; - lmr <= 1'b0; - - unique case (cnt_low) - cInitPre : pre_all <= cnt_high_is_max; - cInitRefr0 : refr <= cnt_high_is_max; - cInitRefr1 : refr <= cnt_high_is_max; - cInitLmr : lmr <= cnt_high_is_max; - cInitDone : init_done <= cnt_high_is_max; - default : begin end - endcase - - end - end - -endmodule

trunk/rtl/hssdrc_init_state.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_data_path.v =================================================================== --- trunk/rtl/hssdrc_data_path.v (revision 2) +++ trunk/rtl/hssdrc_data_path.v (nonexistent) @@ -1,405 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_data_path.v -// -// Description : sdram data (data & mask) path unit -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_timing.vh" -`include "hssdrc_define.vh" - -module hssdrc_data_path ( - clk , - reset , - sclr , - // - sys_wdata , - sys_wdatam , - sys_use_wdata , - sys_vld_rdata , - sys_chid_o , - sys_rdata , - // - arb_read , - arb_write , - arb_chid , - arb_burst , - // - dq , - dqm - ); - - input wire clk; - input wire reset; - input wire sclr; - - //-------------------------------------------------------------------------------------------------- - // system data interface - //-------------------------------------------------------------------------------------------------- - - input data_t sys_wdata ; - input datam_t sys_wdatam ; - output logic sys_use_wdata ; - output logic sys_vld_rdata ; - output chid_t sys_chid_o ; - output data_t sys_rdata ; - - //-------------------------------------------------------------------------------------------------- - // interface from arbiter throw multiplexer - //-------------------------------------------------------------------------------------------------- - - input wire arb_read ; - input wire arb_write ; - input chid_t arb_chid ; - input sdram_burst_t arb_burst ; - - //-------------------------------------------------------------------------------------------------- - // interface sdram chip - //-------------------------------------------------------------------------------------------------- - - inout wire [pDataBits-1 :0] dq; - output logic [pDatamBits-1 :0] dqm; - - //-------------------------------------------------------------------------------------------------- - // Mask paramters count via pBL, pCL parameters only for clarify. - // unit has been designed to use fixed lengh mask patterns - //-------------------------------------------------------------------------------------------------- - localparam cWDataMask = cSdramBL - 1; // - 1 cycle for write command itself - - localparam cRDataMask = cSdramBL - 1 + pCL - 2; // - 1 cycle for read command itself, - // - 2 cycle for read dqm latency - - localparam cDataMask = max(cWDataMask, cRDataMask); - - localparam cReadAllign = pCL + 1; // + 1 is capture register cycle - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - logic [3:0] use_wdata_srl; - wire use_wdata; - wire use_wdatam; - - logic [cDataMask-1 : 0] datam_srl; - logic datam; - - - - logic [3:0] vld_rdata_srl; - logic vld_rdata; - logic vld_rdata_allign_srl [cReadAllign-1 : 0]; - - chid_t chid_srl [3:0]; - chid_t chid; - chid_t chid_allign_srl [cReadAllign-1 : 0]; - - //-------------------------------------------------------------------------------------------------- - // use write data & mask - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : use_wdata_generate - if (reset) - use_wdata_srl <= 4'b0000; - else if (sclr) - use_wdata_srl <= 4'b0000; - else if (arb_write) - unique case (arb_burst) - 2'h0 : use_wdata_srl <= 4'b1000; - 2'h1 : use_wdata_srl <= 4'b1100; - 2'h2 : use_wdata_srl <= 4'b1110; - 2'h3 : use_wdata_srl <= 4'b1111; - endcase - else - use_wdata_srl <= (use_wdata_srl << 1); - end - - assign use_wdata = use_wdata_srl[3]; - assign use_wdatam = use_wdata_srl[3]; - - //-------------------------------------------------------------------------------------------------- - // read/write data mask for command terminate - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : data_burst_mask_generate - if (reset) - datam_srl <= '0; - else if (sclr) - datam_srl <= '0; - else begin - if (arb_write) - datam_srl <= WriteMaskBits(arb_burst); - else if (arb_read) - datam_srl <= ReadMaskBits(arb_burst); - else - datam_srl <= (datam_srl << 1); - end - end - - always_ff @(posedge clk or posedge reset) begin : data_mask_generate - if (reset) - datam <= 1'b0; - else if (sclr) - datam <= 1'b0; - else begin - if (arb_write) - datam <= 1'b0; - else if (arb_read) - datam <= FirstReadMaskBit(arb_burst); - else - datam <= datam_srl [cDataMask-1]; - end - end - - // - // dqm - // - - assign dqm = use_wdatam ? sys_wdatam : {pDatamBits{datam}}; - - //-------------------------------------------------------------------------------------------------- - // write data request - //-------------------------------------------------------------------------------------------------- - -`ifndef HSSDRC_COMBINATORY_USE_WDATA - - assign sys_use_wdata = use_wdata; - -`else - - logic [2:0] use_wdata_srl_small; - - always_ff @(posedge clk or posedge reset) begin : use_wdata_small_generate - if (reset) - use_wdata_srl_small <= 3'b000; - else if (sclr) - use_wdata_srl_small <= 3'b000; - else if (arb_write) - unique case (arb_burst) - 2'h0 : use_wdata_srl_small <= 3'b000; - 2'h1 : use_wdata_srl_small <= 3'b100; - 2'h2 : use_wdata_srl_small <= 3'b110; - 2'h3 : use_wdata_srl_small <= 3'b111; - endcase - else - use_wdata_srl_small <= (use_wdata_srl_small << 1); - end - - assign sys_use_wdata = arb_write | use_wdata_srl_small[2]; - -`endif - // - // dq - // - - assign dq = use_wdata ? sys_wdata : {pDataBits{1'bz}}; - - //-------------------------------------------------------------------------------------------------- - // read data - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : vld_rdata_generate - if (reset) - vld_rdata_srl <= 4'b0000; - else if (sclr) - vld_rdata_srl <= 4'b0000; - else if (arb_read) - unique case (arb_burst) - 2'h0 : vld_rdata_srl <= 4'b1000; - 2'h1 : vld_rdata_srl <= 4'b1100; - 2'h2 : vld_rdata_srl <= 4'b1110; - 2'h3 : vld_rdata_srl <= 4'b1111; - endcase - else - vld_rdata_srl <= (vld_rdata_srl << 1); - end - - assign vld_rdata = vld_rdata_srl [3]; - - // - // - // - - always_ff @(posedge clk) begin : chid_rdata_generate - int i; - - if (arb_read) begin - for (i = 0; i < 4; i++) - chid_srl[i] <= arb_chid; // load all with chid - end - else begin - for (i = 1; i < 4; i++) - chid_srl[i] <= chid_srl[i-1]; // shift left - end - end - - assign chid = chid_srl [3]; - - // - // - // - - always_ff @(posedge clk or posedge reset) begin : vld_rdata_allign_generate - int i; - - if (reset) begin - for (i = 0; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= 1'b0; - end - else if (sclr) begin - for (i = 0; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= 1'b0; - end - else begin - vld_rdata_allign_srl[0] <= vld_rdata; // shift left - - for (i = 1; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= vld_rdata_allign_srl [i-1]; - end - end - - - assign sys_vld_rdata = vld_rdata_allign_srl [cReadAllign-1]; - - // - // - // - - always_ff @(posedge clk) begin : chid_allign_generate - int i; - - chid_allign_srl[0] <= chid; // shift left - - for (i = 1; i < cReadAllign; i++) - chid_allign_srl[i] <= chid_allign_srl[i-1]; - end - - - assign sys_chid_o = chid_allign_srl [cReadAllign-1]; - - // - // - // - - always_ff @(posedge clk) begin : rdata_reclock - sys_rdata <= dq; - end - - //-------------------------------------------------------------------------------------------------- - // function to count write bit mask pattern for different burst value and - // for different Cas Latency paramter value - // full burst == 2'h3 no need to be masked - //-------------------------------------------------------------------------------------------------- - - function automatic bit [cDataMask-1:0] WriteMaskBits (input bit [1:0] burst); - if (pCL == 3) begin - WriteMaskBits = 4'b0000; - case (burst) - 2'h0 : WriteMaskBits = 4'b1110; - 2'h1 : WriteMaskBits = 4'b0110; - 2'h2 : WriteMaskBits = 4'b0010; - endcase - end - else if (pCL == 2) begin - WriteMaskBits = 3'b000; - case (burst) - 2'h0 : WriteMaskBits = 3'b111; - 2'h1 : WriteMaskBits = 3'b011; - 2'h2 : WriteMaskBits = 3'b001; - endcase - end - else if (pCL == 1) begin - WriteMaskBits = 3'b000; - case (burst) - 2'h0 : WriteMaskBits = 3'b111; - 2'h1 : WriteMaskBits = 3'b011; - 2'h2 : WriteMaskBits = 3'b001; - endcase - end - else begin - WriteMaskBits = '0; - end - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to count first read bit mask pattern for different burst value and - // for different Cas Latency paramter value - //-------------------------------------------------------------------------------------------------- - - function automatic bit FirstReadMaskBit (input bit [1:0] burst); - if ((pCL == 1) && (burst == 0)) - FirstReadMaskBit = 1'b1; - else - FirstReadMaskBit = 1'b0; - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to count read bit mask pattern for different burst value and - // for different Cas Latency paramter value - // full burst == 2'h3 no need to be masked - //-------------------------------------------------------------------------------------------------- - - function automatic bit [cDataMask-1:0] ReadMaskBits (input bit [1:0] burst); - if (pCL == 3) begin - ReadMaskBits = 4'b0000; - case (burst) - 2'h0 : ReadMaskBits = 4'b0111; - 2'h1 : ReadMaskBits = 4'b0011; - 2'h2 : ReadMaskBits = 4'b0001; - endcase - end - else if (pCL == 2) begin - ReadMaskBits = 3'b000; - case (burst) - 2'h0 : ReadMaskBits = 3'b111; - 2'h1 : ReadMaskBits = 3'b011; - 2'h2 : ReadMaskBits = 3'b001; - endcase - end - else if (pCL == 1) begin - ReadMaskBits = 3'b000; - case (burst) - 2'h0 : ReadMaskBits = 3'b110; - 2'h1 : ReadMaskBits = 3'b110; - 2'h2 : ReadMaskBits = 3'b010; - endcase - end - else begin - ReadMaskBits = '0; - end - endfunction - -endmodule

trunk/rtl/hssdrc_data_path.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_decoder_state.v =================================================================== --- trunk/rtl/hssdrc_decoder_state.v (revision 2) +++ trunk/rtl/hssdrc_decoder_state.v (nonexistent) @@ -1,534 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_decoder_state.v -// -// Description : sdram command sequence decoder -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_timing.vh" -`include "hssdrc_define.vh" - - -module hssdrc_decoder_state ( - clk , - reset , - sclr , - // - ba_map_update , - ba_map_clear , - ba_map_pre_act_rw , - ba_map_act_rw , - ba_map_rw , - ba_map_all_close , - // - arb_write , - arb_read , - arb_refr , - arb_rowa , - arb_cola , - arb_ba , - arb_burst , - arb_chid , - arb_ready , - // - dec_pre_all , - dec_refr , - dec_pre , - dec_act , - dec_read , - dec_write , - // - dec_pre_all_enable, - dec_refr_enable , - dec_pre_enable , - dec_act_enable , - dec_read_enable , - dec_write_enable , - // - dec_locked , - dec_last , - // - dec_rowa , - dec_cola , - dec_ba , - dec_chid , - // - dec_burst - ); - - input wire clk ; - input wire reset; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // bank map interface - //-------------------------------------------------------------------------------------------------- - - output logic ba_map_update ; - output logic ba_map_clear ; - input wire ba_map_pre_act_rw ; - input wire ba_map_act_rw ; - input wire ba_map_rw ; - input wire ba_map_all_close ; - - //-------------------------------------------------------------------------------------------------- - // interface from input arbiter - //-------------------------------------------------------------------------------------------------- - - input wire arb_write ; - input wire arb_read ; - input wire arb_refr ; - input rowa_t arb_rowa ; - input cola_t arb_cola ; - input ba_t arb_ba ; - input burst_t arb_burst ; - input chid_t arb_chid ; - output logic arb_ready ; - - //-------------------------------------------------------------------------------------------------- - // inteface to output arbiter - //-------------------------------------------------------------------------------------------------- - - // logical commands - output logic dec_pre_all ; - output logic dec_refr ; - output logic dec_pre ; - output logic dec_act ; - output logic dec_read ; - output logic dec_write ; - // logical commands en - input wire dec_pre_all_enable ; - input wire dec_refr_enable ; - input wire dec_pre_enable ; - input wire dec_act_enable ; - input wire dec_read_enable ; - input wire dec_write_enable ; - // addititional signal - output logic dec_locked ; - output logic dec_last ; - // control path - output rowa_t dec_rowa ; - output cola_t dec_cola ; - output ba_t dec_ba ; - output chid_t dec_chid ; - // - output sdram_burst_t dec_burst ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - localparam int cTrp_m1 = cTrp - 1; - localparam int cTrcd_m1 = cTrcd - 1; - - typedef enum { - STATE_RESET_BIT , // need for create simple true ready condition - STATE_IDLE_BIT , - STATE_DECODE_BIT , - STATE_PRE_BIT , - STATE_TRP_BIT , - STATE_ACT_BIT , - STATE_TRCD_BIT , - STATE_RW_BIT , - STATE_ADDR_INC_BIT, - STATE_PRE_ALL_BIT , - STATE_REFR_BIT - } state_bits_e; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - enum bit [10:0] { - STATE_RESET = (11'h1 << STATE_RESET_BIT) , - STATE_IDLE = (11'h1 << STATE_IDLE_BIT) , - STATE_DECODE = (11'h1 << STATE_DECODE_BIT) , - STATE_PRE = (11'h1 << STATE_PRE_BIT) , - STATE_TRP = (11'h1 << STATE_TRP_BIT) , - STATE_ACT = (11'h1 << STATE_ACT_BIT) , - STATE_TRCD = (11'h1 << STATE_TRCD_BIT) , - STATE_RW = (11'h1 << STATE_RW_BIT) , - STATE_ADDR_INC = (11'h1 << STATE_ADDR_INC_BIT) , - STATE_PRE_ALL = (11'h1 << STATE_PRE_ALL_BIT) , - STATE_REFR = (11'h1 << STATE_REFR_BIT) - } state, next_state; - - logic refr_mode ; - logic write_mode ; - - logic burst_done ; - logic early_burst_done; - - cola_t cola_latched ; - rowa_t rowa_latched ; - ba_t ba_latched ; - chid_t chid_latched ; - - logic [3:0] burst_latched ; - logic [3:0] burst_shift_cnt ; - - logic [3:0] available_burst ; - - logic [3:0] remained_burst ; - logic [1:0] remained_burst_high ; - logic [1:0] remained_burst_low ; - logic [1:0] remained_burst_low_latched; - - logic [3:0] last_used_burst; - - wire trp_cnt_done; - wire trcd_cnt_done; - - //-------------------------------------------------------------------------------------------------- - // use shift register instead of counter for trp time count - //-------------------------------------------------------------------------------------------------- - - generate - if (cTrp_m1 <= 1) begin : no_trp_cnt_generate - - assign trp_cnt_done = 1'b1; - - end - else begin : trp_cnt_generate - - logic [cTrp_m1-2:0] trp_cnt; - - always_ff @(posedge clk) begin - if (state [STATE_TRP_BIT]) - trp_cnt <= (trp_cnt << 1) | 1'b1; - else - trp_cnt <= '0; - end - - assign trp_cnt_done = trp_cnt [cTrp_m1-2]; - - end - endgenerate - - //-------------------------------------------------------------------------------------------------- - // use shift register instead of counter for trcd time count - //-------------------------------------------------------------------------------------------------- - - generate - if (cTrcd_m1 <= 1) begin : no_trcd_cnt_generate - - assign trcd_cnt_done = 1'b1; - - end - else begin : trcd_cnt_generate - - logic [cTrcd_m1-2:0] trcd_cnt; - - always_ff @(posedge clk) begin - if (state [STATE_TRCD_BIT]) - trcd_cnt <= (trcd_cnt << 1) | 1'b1; - else - trcd_cnt <= '0; - end - - assign trcd_cnt_done = trcd_cnt [cTrcd_m1-2]; - - end - endgenerate - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - always_comb begin : fsm_jump_decode - - next_state = STATE_RESET; - - unique case (1'b1) - - state [STATE_RESET_BIT] : begin - next_state = STATE_IDLE; - end - - state [STATE_IDLE_BIT] : begin - if (arb_write | arb_read | arb_refr) - next_state = STATE_DECODE; - else - next_state = STATE_IDLE; - end - // - // decode branch - // - state [STATE_DECODE_BIT] : begin - if (refr_mode) begin : shorten_refresh_decode - - if (ba_map_all_close) - next_state = STATE_REFR; - else - next_state = STATE_PRE_ALL; - - end - else begin : mode_of_rw_decode - - if (ba_map_pre_act_rw) - next_state = STATE_PRE; - else if (ba_map_rw) - next_state = STATE_RW; - else // if (ba_map_act_rw) - next_state = STATE_ACT; - - end - end - // - // pre branch - // - state [STATE_PRE_BIT] : begin - if (dec_pre_enable) - - if (cTrp_m1 == 0) - next_state = STATE_ACT; - else - next_state = STATE_TRP; - - else - next_state = STATE_PRE; - end - - state [STATE_TRP_BIT] : begin - if (trp_cnt_done) - next_state = STATE_ACT; - else - next_state = STATE_TRP; - end - // - // act branch - // - state [STATE_ACT_BIT] : begin - if (dec_act_enable) - - if (cTrcd_m1 == 0) - next_state = STATE_RW; - else - next_state = STATE_TRCD; - - else - next_state = STATE_ACT; - end - - state [STATE_TRCD_BIT] : begin - if (trcd_cnt_done) - next_state = STATE_RW; - else - next_state = STATE_TRCD; - end - // - // data branch - // - state [STATE_RW_BIT] : begin - if ((dec_write_enable & write_mode) | (dec_read_enable & ~write_mode)) begin : burst_done_decode - - if (burst_done) - next_state = STATE_IDLE; - else - next_state = STATE_ADDR_INC; - - end - else begin - next_state = STATE_RW; - end - end - - state [STATE_ADDR_INC_BIT] : begin - next_state = STATE_RW; - end - // - // refresh breanch - // - state [STATE_PRE_ALL_BIT] : begin - if (dec_pre_all_enable) - next_state = STATE_REFR; - else - next_state = STATE_PRE_ALL; - end - - state [STATE_REFR_BIT] : begin - if (dec_refr_enable) - next_state = STATE_IDLE; - else - next_state = STATE_REFR; - end - - endcase - end - - //--------------------------------------------------------------------------------------------------- - // - //--------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : fsm_register_process - if (reset) state <= STATE_RESET; - else if (sclr) state <= STATE_RESET; - else state <= next_state; - end - - //--------------------------------------------------------------------------------------------------- - // - //--------------------------------------------------------------------------------------------------- - - assign arb_ready = state[STATE_IDLE_BIT]; - - assign dec_pre_all = state[STATE_PRE_ALL_BIT]; - assign dec_refr = state[STATE_REFR_BIT]; - assign dec_pre = state[STATE_PRE_BIT]; - assign dec_act = state[STATE_ACT_BIT]; - assign dec_read = state[STATE_RW_BIT] & ~write_mode; - assign dec_write = state[STATE_RW_BIT] & write_mode; - assign dec_last = state[STATE_RW_BIT] & burst_done ; - - // - // instead of decode state_refr_bit & state_pre_all_bit we can use refresh mode register - // - - assign dec_locked = refr_mode; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - assign ba_map_update = state[STATE_DECODE_BIT] & ~refr_mode; - assign ba_map_clear = state[STATE_DECODE_BIT] & refr_mode; - - always_ff @(posedge clk) begin : mode_logic - if (state [STATE_IDLE_BIT]) begin - refr_mode <= arb_refr; - write_mode <= arb_write; - end - end - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk) begin : addr_chid_logic - - if (state[STATE_IDLE_BIT]) begin - rowa_latched <= arb_rowa; - ba_latched <= arb_ba; - chid_latched <= arb_chid; - end - - if (state[STATE_IDLE_BIT]) - cola_latched <= arb_cola; - else if (state[STATE_ADDR_INC_BIT]) - cola_latched <= cola_latched + last_used_burst; - - end - - assign dec_cola = cola_latched; - assign dec_rowa = rowa_latched; - assign dec_ba = ba_latched; - assign dec_chid = chid_latched; - - - //-------------------------------------------------------------------------------------------------- - // alligned burst max cycles is 4 - // burst [3:2] == 0 & burst[1:0] <= available_burst. 1 cycle is burst - // burst [3:2] != 0 & burst[1:0] <= available_burst. 1 cycle is burst shift_cnt burst_done - // burst [ 1.. 4] : encoded with [ 4'd0 : 4'd3] : cycle is 1 : burst_shift_cnt = 4'b0000 1 - // burst [ 5.. 8] : encoded with [ 4'd4 : 4'd7] : cycle is 2 : burst_shift_cnt = 4'b0001 0 - // burst [ 9..12] : encoded with [ 4'd8 : 4'd11] : cycle is 3 : burst_shift_cnt = 4'b0010 0 - // burst [13..16] : encoded with [4'd12 : 4'd15] : cycle is 4 : burst_shift_cnt = 4'b0100 0 - // - - // not alligned burst max cycles is 5 shift_cnt burst_done - // burst [ 1.. 4] : encoded with [ 4'd0 : 4'd3] : cycle is 2 : burst_shift_cnt = 4'b0001 0 - // burst [ 5.. 8] : encoded with [ 4'd4 : 4'd7] : cycle is 3 : burst_shift_cnt = 4'b0010 0 - // burst [ 9..12] : encoded with [ 4'd8 : 4'd11] : cycle is 4 : burst_shift_cnt = 4'b0100 0 - // burst [13..16] : encoded with [4'd12 : 4'd15] : cycle is 5 : burst_shift_cnt = 4'b1000 0 - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk) begin : burst_latch_logic - if (state[STATE_IDLE_BIT]) - burst_latched = arb_burst; - end - - // remember that burst has -1 offset - // available burst has -1 offset too - - assign available_burst = 4'b0011 - {2'b00, cola_latched[1:0]}; - - assign remained_burst = burst_latched - available_burst - 1'b1; - assign remained_burst_high = remained_burst[3:2]; - assign remained_burst_low = remained_burst[1:0]; - - assign early_burst_done = burst_shift_cnt[0]; - - always_ff @(posedge clk) begin : burst_logic - if (state[STATE_DECODE_BIT]) begin - - if (burst_latched <= available_burst) begin - - burst_shift_cnt <= '0; - - burst_done <= 1'b1; // only 1 transaction will be - dec_burst <= burst_latched[1:0]; - - end - else begin - - burst_shift_cnt <= '0; - burst_shift_cnt[remained_burst_high] <= 1'b1; - - remained_burst_low_latched <= remained_burst_low; - - burst_done <= 1'b0; // more then 2 transaction will be - - dec_burst <= available_burst[1:0]; - last_used_burst <= {2'b00, available_burst[1:0]} + 1'b1; // + 1 is compensation of -1 offset - - end - end - else if (state[STATE_ADDR_INC_BIT]) begin - - burst_shift_cnt <= burst_shift_cnt >> 1; - - burst_done <= early_burst_done; - // - if (early_burst_done) - dec_burst <= remained_burst_low_latched; // no transaction any more - else - dec_burst <= 2'b11; - // - last_used_burst <= 4'b0011 + 1'b1; - end - end - -endmodule

trunk/rtl/hssdrc_decoder_state.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_data_path_p1.v =================================================================== --- trunk/rtl/hssdrc_data_path_p1.v (revision 2) +++ trunk/rtl/hssdrc_data_path_p1.v (nonexistent) @@ -1,429 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_data_path_p1.v -// -// Description : sdram data (data & mask) path unit -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_timing.vh" -`include "hssdrc_define.vh" - -module hssdrc_data_path_p1 ( - clk , - reset , - sclr , - // - sys_wdata , - sys_wdatam , - sys_use_wdata , - sys_vld_rdata , - sys_chid_o , - sys_rdata , - // - arb_read , - arb_write , - arb_chid , - arb_burst , - // - dq , - dqm - ); - - input wire clk; - input wire reset; - input wire sclr; - - //-------------------------------------------------------------------------------------------------- - // system data interface - //-------------------------------------------------------------------------------------------------- - - input data_t sys_wdata ; - input datam_t sys_wdatam ; - output logic sys_use_wdata ; - output logic sys_vld_rdata ; - output chid_t sys_chid_o ; - output data_t sys_rdata ; - - //-------------------------------------------------------------------------------------------------- - // interface from arbiter throw multiplexer - //-------------------------------------------------------------------------------------------------- - - input wire arb_read ; - input wire arb_write ; - input chid_t arb_chid ; - input sdram_burst_t arb_burst ; - - //-------------------------------------------------------------------------------------------------- - // interface sdram chip - //-------------------------------------------------------------------------------------------------- - - inout wire [pDataBits-1 :0] dq; - output logic [pDatamBits-1 :0] dqm; - - //-------------------------------------------------------------------------------------------------- - // Mask paramters count via pBL, pCL parameters only for clarify. - // unit has been designed to use fixed lengh mask patterns - //-------------------------------------------------------------------------------------------------- - localparam cWDataMask = cSdramBL - 1; // - 1 cycle for write command itself - - localparam cRDataMask = cSdramBL - 1 + pCL - 2; // - 1 cycle for read command itself, - // - 2 cycle for read dqm latency - - localparam cDataMask = max(cWDataMask, cRDataMask); - - localparam cReadAllign = pCL + 1 + 1; // + 1 is capture register cycle - // + 1 is additition command latency - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - data_t wdata_delayed; - logic use_wdata_delayed; - - logic [3:0] use_wdata_srl; - wire use_wdata; - wire use_wdatam; - - logic [cDataMask-1 : 0] datam_srl; - logic datam; - - - logic [3:0] vld_rdata_srl; - logic vld_rdata; - logic vld_rdata_allign_srl [cReadAllign-1 : 0]; - - chid_t chid_srl [3:0]; - chid_t chid; - chid_t chid_allign_srl [cReadAllign-1 : 0]; - - //-------------------------------------------------------------------------------------------------- - // use write data & mask - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : use_wdata_generate - if (reset) - use_wdata_srl <= 4'b0000; - else if (sclr) - use_wdata_srl <= 4'b0000; - else if (arb_write) - unique case (arb_burst) - 2'h0 : use_wdata_srl <= 4'b1000; - 2'h1 : use_wdata_srl <= 4'b1100; - 2'h2 : use_wdata_srl <= 4'b1110; - 2'h3 : use_wdata_srl <= 4'b1111; - endcase - else - use_wdata_srl <= (use_wdata_srl << 1); - end - - assign use_wdata = use_wdata_srl[3]; - assign use_wdatam = use_wdata_srl[3]; - - // - // read/write data mask for command terminate - // - - always_ff @(posedge clk or posedge reset) begin : data_burst_mask_generate - if (reset) - datam_srl <= '0; - else if (sclr) - datam_srl <= '0; - else begin - if (arb_write) - datam_srl <= WriteMaskBits(arb_burst); - else if (arb_read) - datam_srl <= ReadMaskBits(arb_burst); - else - datam_srl <= (datam_srl << 1); - end - end - - always_ff @(posedge clk or posedge reset) begin : data_mask_generate - if (reset) - datam <= 1'b0; - else if (sclr) - datam <= 1'b0; - else begin - if (arb_write) - datam <= 1'b0; - else if (arb_read) - datam <= FirstReadMaskBit(arb_burst); - else - datam <= datam_srl [cDataMask-1]; - end - end - - // - // dqm - // - - - always_ff @(posedge clk or posedge reset) begin - if (reset) - dqm <= '0; - else if (sclr) - dqm <= '0; - else - dqm <= use_wdatam ? sys_wdatam : {pDatamBits{datam}}; - end - - - //-------------------------------------------------------------------------------------------------- - // write data request - //-------------------------------------------------------------------------------------------------- - -`ifndef HSSDRC_COMBINATORY_USE_WDATA - - assign sys_use_wdata = use_wdata; - -`else - - logic [2:0] use_wdata_srl_small; - - always_ff @(posedge clk or posedge reset) begin : use_wdata_small_generate - if (reset) - use_wdata_srl_small <= 3'b000; - else if (sclr) - use_wdata_srl_small <= 3'b000; - else if (arb_write) - unique case (arb_burst) - 2'h0 : use_wdata_srl_small <= 3'b000; - 2'h1 : use_wdata_srl_small <= 3'b100; - 2'h2 : use_wdata_srl_small <= 3'b110; - 2'h3 : use_wdata_srl_small <= 3'b111; - endcase - else - use_wdata_srl_small <= (use_wdata_srl_small << 1); - end - - assign sys_use_wdata = arb_write | use_wdata_srl_small[2]; - -`endif - // - // dq - // - - - always_ff @(posedge clk) begin : wdata_reclock - wdata_delayed <= sys_wdata; - end - - always_ff @(posedge clk or posedge reset) begin : use_wdata_reclock - if (reset) - use_wdata_delayed <= 1'b0; - else - use_wdata_delayed <= use_wdata; - end - - - assign dq = use_wdata_delayed ? wdata_delayed : {pDataBits{1'bz}}; - - //-------------------------------------------------------------------------------------------------- - // read data - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : vld_rdata_generate - if (reset) - vld_rdata_srl <= 4'b0000; - else if (sclr) - vld_rdata_srl <= 4'b0000; - else if (arb_read) - unique case (arb_burst) - 2'h0 : vld_rdata_srl <= 4'b1000; - 2'h1 : vld_rdata_srl <= 4'b1100; - 2'h2 : vld_rdata_srl <= 4'b1110; - 2'h3 : vld_rdata_srl <= 4'b1111; - endcase - else - vld_rdata_srl <= (vld_rdata_srl << 1); - end - - assign vld_rdata = vld_rdata_srl [3]; - - // - // - // - - always_ff @(posedge clk) begin : chid_rdata_generate - int i; - - if (arb_read) begin - for (i = 0; i < 4; i++) - chid_srl[i] <= arb_chid; // load all with chid - end - else begin - for (i = 1; i < 4; i++) - chid_srl[i] <= chid_srl[i-1]; // shift left with last data stable - end - end - - assign chid = chid_srl [3]; - - // - // - // - - always_ff @(posedge clk or posedge reset) begin : vld_rdata_allign_generate - int i; - - if (reset) begin - for (i = 0; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= 1'b0; - end - else if (sclr) begin - for (i = 0; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= 1'b0; - end - else begin - vld_rdata_allign_srl[0] <= vld_rdata; // shift left - - for (i = 1; i < cReadAllign; i++) - vld_rdata_allign_srl[i] <= vld_rdata_allign_srl [i-1]; - end - end - - - assign sys_vld_rdata = vld_rdata_allign_srl [cReadAllign-1]; - - // - // - // - - always_ff @(posedge clk) begin : chid_allign_generate - int i; - - chid_allign_srl[0] <= chid; // shift left - - for (i = 1; i < cReadAllign; i++) - chid_allign_srl[i] <= chid_allign_srl[i-1]; - end - - - assign sys_chid_o = chid_allign_srl [cReadAllign-1]; - - // - // - // - - always_ff @(posedge clk) begin : rdata_reclock - sys_rdata <= dq; - end - - //-------------------------------------------------------------------------------------------------- - // function to count write bit mask pattern for different burst value and - // for different Cas Latency paramter value - // full burst == 2'h3 no need to be masked - //-------------------------------------------------------------------------------------------------- - - function automatic bit [cDataMask-1:0] WriteMaskBits (input bit [1:0] burst); - if (pCL == 3) begin - WriteMaskBits = 4'b0000; - case (burst) - 2'h0 : WriteMaskBits = 4'b1110; - 2'h1 : WriteMaskBits = 4'b0110; - 2'h2 : WriteMaskBits = 4'b0010; - endcase - end - else if (pCL == 2) begin - WriteMaskBits = 3'b000; - case (burst) - 2'h0 : WriteMaskBits = 3'b111; - 2'h1 : WriteMaskBits = 3'b011; - 2'h2 : WriteMaskBits = 3'b001; - endcase - end - else if (pCL == 1) begin - WriteMaskBits = 3'b000; - case (burst) - 2'h0 : WriteMaskBits = 3'b111; - 2'h1 : WriteMaskBits = 3'b011; - 2'h2 : WriteMaskBits = 3'b001; - endcase - end - else begin - WriteMaskBits = '0; - end - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to count first read bit mask pattern for different burst value and - // for different Cas Latency paramter value - //-------------------------------------------------------------------------------------------------- - - function automatic bit FirstReadMaskBit (input bit [1:0] burst); - if ((pCL == 1) && (burst == 0)) - FirstReadMaskBit = 1'b1; - else - FirstReadMaskBit = 1'b0; - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to count read bit mask pattern for different burst value and - // for different Cas Latency paramter value - // full burst == 2'h3 no need to be masked - //-------------------------------------------------------------------------------------------------- - - function automatic bit [cDataMask-1:0] ReadMaskBits (input bit [1:0] burst); - if (pCL == 3) begin - ReadMaskBits = 4'b0000; - case (burst) - 2'h0 : ReadMaskBits = 4'b0111; - 2'h1 : ReadMaskBits = 4'b0011; - 2'h2 : ReadMaskBits = 4'b0001; - endcase - end - else if (pCL == 2) begin - ReadMaskBits = 3'b000; - case (burst) - 2'h0 : ReadMaskBits = 3'b111; - 2'h1 : ReadMaskBits = 3'b011; - 2'h2 : ReadMaskBits = 3'b001; - endcase - end - else if (pCL == 1) begin - ReadMaskBits = 3'b000; - case (burst) - 2'h0 : ReadMaskBits = 3'b110; - 2'h1 : ReadMaskBits = 3'b110; - 2'h2 : ReadMaskBits = 3'b010; - endcase - end - else begin - ReadMaskBits = '0; - end - endfunction - -endmodule

trunk/rtl/hssdrc_data_path_p1.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_decoder.v =================================================================== --- trunk/rtl/hssdrc_decoder.v (revision 2) +++ trunk/rtl/hssdrc_decoder.v (nonexistent) @@ -1,477 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_decoder.v -// -// Description : sdram command sequence decoder's array -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_decoder ( - clk , - reset , - sclr , - // - ba_map_update , - ba_map_clear , - ba_map_ba , - ba_map_rowa , - ba_map_pre_act_rw , - ba_map_act_rw , - ba_map_rw , - ba_map_all_close , - // - arb0_write , - arb0_read , - arb0_refr , - arb0_rowa , - arb0_cola , - arb0_ba , - arb0_burst , - arb0_chid , - arb0_ready , - // - arb1_write , - arb1_read , - arb1_refr , - arb1_rowa , - arb1_cola , - arb1_ba , - arb1_burst , - arb1_chid , - arb1_ready , - // - arb2_write , - arb2_read , - arb2_refr , - arb2_rowa , - arb2_cola , - arb2_ba , - arb2_burst , - arb2_chid , - arb2_ready , - // - dec0_pre_all , - dec0_refr , - dec0_pre , - dec0_act , - dec0_read , - dec0_write , - dec0_pre_all_enable , - dec0_refr_enable , - dec0_pre_enable , - dec0_act_enable , - dec0_read_enable , - dec0_write_enable , - dec0_locked , - dec0_last , - dec0_rowa , - dec0_cola , - dec0_ba , - dec0_chid , - dec0_burst , - // - dec1_pre_all , - dec1_refr , - dec1_pre , - dec1_act , - dec1_read , - dec1_write , - dec1_pre_all_enable , - dec1_refr_enable , - dec1_pre_enable , - dec1_act_enable , - dec1_read_enable , - dec1_write_enable , - dec1_locked , - dec1_last , - dec1_rowa , - dec1_cola , - dec1_ba , - dec1_chid , - dec1_burst , - // - dec2_pre_all , - dec2_refr , - dec2_pre , - dec2_act , - dec2_read , - dec2_write , - dec2_pre_all_enable , - dec2_refr_enable , - dec2_pre_enable , - dec2_act_enable , - dec2_read_enable , - dec2_write_enable , - dec2_locked , - dec2_last , - dec2_rowa , - dec2_cola , - dec2_ba , - dec2_chid , - dec2_burst - ); - - input wire clk ; - input wire reset; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // bank map interface - //-------------------------------------------------------------------------------------------------- - - output wire ba_map_update ; - output wire ba_map_clear ; - output ba_t ba_map_ba ; - output rowa_t ba_map_rowa ; - input wire ba_map_pre_act_rw; - input wire ba_map_act_rw ; - input wire ba_map_rw ; - input wire ba_map_all_close ; - - //-------------------------------------------------------------------------------------------------- - // interface from input arbiter - //-------------------------------------------------------------------------------------------------- - - input logic arb0_write ; - input logic arb0_read ; - input logic arb0_refr ; - input rowa_t arb0_rowa ; - input cola_t arb0_cola ; - input ba_t arb0_ba ; - input burst_t arb0_burst ; - input chid_t arb0_chid ; - output wire arb0_ready ; - // - input logic arb1_write ; - input logic arb1_read ; - input logic arb1_refr ; - input rowa_t arb1_rowa ; - input cola_t arb1_cola ; - input ba_t arb1_ba ; - input burst_t arb1_burst ; - input chid_t arb1_chid ; - output wire arb1_ready ; - // - input logic arb2_write ; - input logic arb2_read ; - input logic arb2_refr ; - input rowa_t arb2_rowa ; - input cola_t arb2_cola ; - input ba_t arb2_ba ; - input burst_t arb2_burst ; - input chid_t arb2_chid ; - output wire arb2_ready ; - - //-------------------------------------------------------------------------------------------------- - // inteface to output arbiter - //-------------------------------------------------------------------------------------------------- - - output logic dec0_pre_all ; - output logic dec0_refr ; - output logic dec0_pre ; - output logic dec0_act ; - output logic dec0_read ; - output logic dec0_write ; - input wire dec0_pre_all_enable; - input wire dec0_refr_enable ; - input wire dec0_pre_enable ; - input wire dec0_act_enable ; - input wire dec0_read_enable ; - input wire dec0_write_enable ; - output logic dec0_locked ; - output logic dec0_last ; - output rowa_t dec0_rowa ; - output cola_t dec0_cola ; - output ba_t dec0_ba ; - output chid_t dec0_chid ; - output sdram_burst_t dec0_burst ; - // - output logic dec1_pre_all ; - output logic dec1_refr ; - output logic dec1_pre ; - output logic dec1_act ; - output logic dec1_read ; - output logic dec1_write ; - input wire dec1_pre_all_enable; - input wire dec1_refr_enable ; - input wire dec1_pre_enable ; - input wire dec1_act_enable ; - input wire dec1_read_enable ; - input wire dec1_write_enable ; - output logic dec1_locked ; - output logic dec1_last ; - output rowa_t dec1_rowa ; - output cola_t dec1_cola ; - output ba_t dec1_ba ; - output chid_t dec1_chid ; - output sdram_burst_t dec1_burst ; - // - output logic dec2_pre_all ; - output logic dec2_refr ; - output logic dec2_pre ; - output logic dec2_act ; - output logic dec2_read ; - output logic dec2_write ; - input wire dec2_pre_all_enable; - input wire dec2_refr_enable ; - input wire dec2_pre_enable ; - input wire dec2_act_enable ; - input wire dec2_read_enable ; - input wire dec2_write_enable ; - output logic dec2_locked ; - output logic dec2_last ; - output rowa_t dec2_rowa ; - output cola_t dec2_cola ; - output ba_t dec2_ba ; - output chid_t dec2_chid ; - output sdram_burst_t dec2_burst ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - ba_t ba_latched ; - rowa_t rowa_latched; - - // - // local state ba_map signals - // - - wire state0__ba_map_update ; - wire state0__ba_map_clear ; - wire state0__ba_map_pre_act_rw ; - wire state0__ba_map_act_rw ; - wire state0__ba_map_rw ; - wire state0__ba_map_all_close ; - - wire state1__ba_map_update ; - wire state1__ba_map_clear ; - wire state1__ba_map_pre_act_rw ; - wire state1__ba_map_act_rw ; - wire state1__ba_map_rw ; - wire state1__ba_map_all_close ; - - wire state2__ba_map_update ; - wire state2__ba_map_clear ; - wire state2__ba_map_pre_act_rw ; - wire state2__ba_map_act_rw ; - wire state2__ba_map_rw ; - wire state2__ba_map_all_close ; - - //-------------------------------------------------------------------------------------------------- - // we can capture bank map data into register, becouse we have +1 tick in FSM - // for bank map decoding we can take data from any arbiter channel - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk) begin : ba_map_data_register - ba_latched <= arb0_ba; - rowa_latched <= arb0_rowa; - end - - // - // - // - - assign ba_map_ba = ba_latched; - assign ba_map_rowa = rowa_latched; - assign ba_map_update = state0__ba_map_update | state1__ba_map_update | state2__ba_map_update ; - assign ba_map_clear = state0__ba_map_clear | state1__ba_map_clear | state2__ba_map_clear ; - - assign state0__ba_map_pre_act_rw = ba_map_pre_act_rw ; - assign state0__ba_map_act_rw = ba_map_act_rw ; - assign state0__ba_map_rw = ba_map_rw ; - assign state0__ba_map_all_close = ba_map_all_close ; - - assign state1__ba_map_pre_act_rw = ba_map_pre_act_rw ; - assign state1__ba_map_act_rw = ba_map_act_rw ; - assign state1__ba_map_rw = ba_map_rw ; - assign state1__ba_map_all_close = ba_map_all_close ; - - assign state2__ba_map_pre_act_rw = ba_map_pre_act_rw ; - assign state2__ba_map_act_rw = ba_map_act_rw ; - assign state2__ba_map_rw = ba_map_rw ; - assign state2__ba_map_all_close = ba_map_all_close ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_decoder_state state0 ( - .clk (clk ), - .reset (reset), - .sclr (sclr ), - // - .ba_map_update (state0__ba_map_update ), - .ba_map_clear (state0__ba_map_clear ), - .ba_map_pre_act_rw (state0__ba_map_pre_act_rw), - .ba_map_act_rw (state0__ba_map_act_rw ), - .ba_map_rw (state0__ba_map_rw ), - .ba_map_all_close (state0__ba_map_all_close ), - // - .arb_write (arb0_write), - .arb_read (arb0_read ), - .arb_refr (arb0_refr ), - .arb_rowa (arb0_rowa ), - .arb_cola (arb0_cola ), - .arb_ba (arb0_ba ), - .arb_burst (arb0_burst), - .arb_chid (arb0_chid ), - .arb_ready (arb0_ready), - // - .dec_pre_all (dec0_pre_all), - .dec_refr (dec0_refr ), - .dec_pre (dec0_pre ), - .dec_act (dec0_act ), - .dec_read (dec0_read ), - .dec_write (dec0_write ), - // - .dec_pre_all_enable(dec0_pre_all_enable), - .dec_refr_enable (dec0_refr_enable ), - .dec_pre_enable (dec0_pre_enable ), - .dec_act_enable (dec0_act_enable ), - .dec_read_enable (dec0_read_enable ), - .dec_write_enable (dec0_write_enable ), - // - .dec_locked (dec0_locked), - .dec_last (dec0_last ), - // - .dec_rowa (dec0_rowa ), - .dec_cola (dec0_cola ), - .dec_ba (dec0_ba ), - .dec_chid (dec0_chid ), - // - .dec_burst (dec0_burst) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_decoder_state state1 ( - .clk (clk ), - .reset (reset), - .sclr (sclr ), - // - .ba_map_update (state1__ba_map_update ), - .ba_map_clear (state1__ba_map_clear ), - .ba_map_pre_act_rw (state1__ba_map_pre_act_rw), - .ba_map_act_rw (state1__ba_map_act_rw ), - .ba_map_rw (state1__ba_map_rw ), - .ba_map_all_close (state1__ba_map_all_close ), - // - .arb_write (arb1_write), - .arb_read (arb1_read ), - .arb_refr (arb1_refr ), - .arb_rowa (arb1_rowa ), - .arb_cola (arb1_cola ), - .arb_ba (arb1_ba ), - .arb_burst (arb1_burst), - .arb_chid (arb1_chid ), - .arb_ready (arb1_ready), - // - .dec_pre_all (dec1_pre_all), - .dec_refr (dec1_refr ), - .dec_pre (dec1_pre ), - .dec_act (dec1_act ), - .dec_read (dec1_read ), - .dec_write (dec1_write ), - // - .dec_pre_all_enable(dec1_pre_all_enable), - .dec_refr_enable (dec1_refr_enable ), - .dec_pre_enable (dec1_pre_enable ), - .dec_act_enable (dec1_act_enable ), - .dec_read_enable (dec1_read_enable ), - .dec_write_enable (dec1_write_enable ), - // - .dec_locked (dec1_locked), - .dec_last (dec1_last ), - // - .dec_rowa (dec1_rowa ), - .dec_cola (dec1_cola ), - .dec_ba (dec1_ba ), - .dec_chid (dec1_chid ), - // - .dec_burst (dec1_burst) - ); - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - hssdrc_decoder_state state2 ( - .clk (clk ), - .reset (reset), - .sclr (sclr ), - // - .ba_map_update (state2__ba_map_update ), - .ba_map_clear (state2__ba_map_clear ), - .ba_map_pre_act_rw (state2__ba_map_pre_act_rw), - .ba_map_act_rw (state2__ba_map_act_rw ), - .ba_map_rw (state2__ba_map_rw ), - .ba_map_all_close (state2__ba_map_all_close ), - // - .arb_write (arb2_write), - .arb_read (arb2_read ), - .arb_refr (arb2_refr ), - .arb_rowa (arb2_rowa ), - .arb_cola (arb2_cola ), - .arb_ba (arb2_ba ), - .arb_burst (arb2_burst), - .arb_chid (arb2_chid ), - .arb_ready (arb2_ready), - // - .dec_pre_all (dec2_pre_all), - .dec_refr (dec2_refr ), - .dec_pre (dec2_pre ), - .dec_act (dec2_act ), - .dec_read (dec2_read ), - .dec_write (dec2_write ), - // - .dec_pre_all_enable(dec2_pre_all_enable), - .dec_refr_enable (dec2_refr_enable ), - .dec_pre_enable (dec2_pre_enable ), - .dec_act_enable (dec2_act_enable ), - .dec_read_enable (dec2_read_enable ), - .dec_write_enable (dec2_write_enable ), - // - .dec_locked (dec2_locked), - .dec_last (dec2_last ), - // - .dec_rowa (dec2_rowa ), - .dec_cola (dec2_cola ), - .dec_ba (dec2_ba ), - .dec_chid (dec2_chid ), - // - .dec_burst (dec2_burst) - ); - -endmodule

trunk/rtl/hssdrc_decoder.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_addr_path_p1.v =================================================================== --- trunk/rtl/hssdrc_addr_path_p1.v (revision 2) +++ trunk/rtl/hssdrc_addr_path_p1.v (nonexistent) @@ -1,216 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_addr_path_p1.v -// -// Description : coder for translate logical onehot command to sdram command -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - - -module hssdrc_addr_path_p1( - clk , - reset , - sclr , - // - arb_pre_all , - arb_refr , - arb_pre , - arb_act , - arb_read , - arb_write , - arb_lmr , - arb_rowa , - arb_cola , - arb_ba , - // - addr , - ba , - cke , - cs_n , - ras_n , - cas_n , - we_n - ); - - input wire clk; - input wire reset; - input wire sclr; - - //-------------------------------------------------------------------------------------------------- - // interface from output arbiter - //-------------------------------------------------------------------------------------------------- - - input wire arb_pre_all ; - input wire arb_refr ; - input wire arb_pre ; - input wire arb_act ; - input wire arb_read ; - input wire arb_write ; - input wire arb_lmr ; - input rowa_t arb_rowa ; - input cola_t arb_cola ; - input ba_t arb_ba ; - - //-------------------------------------------------------------------------------------------------- - // interface to sdram - //-------------------------------------------------------------------------------------------------- - - output sdram_addr_t addr; - output ba_t ba; - output logic cke; - output logic cs_n; - output logic ras_n; - output logic cas_n; - output logic we_n; - - // - // - // - - logic [3:0] cs_n__ras_n__cas_n__we_n; - - sdram_addr_t addr_latched; - ba_t ba_latched; - - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : logical_command_decode - if (reset) - cs_n__ras_n__cas_n__we_n <= 4'b1111; // inheribit nop - else if (sclr) - cs_n__ras_n__cas_n__we_n <= 4'b1111; // inheribit nop - else begin - unique case (1'b1) - arb_pre_all : cs_n__ras_n__cas_n__we_n <= 4'b0010; // Pre - arb_refr : cs_n__ras_n__cas_n__we_n <= 4'b0001; // Refr - arb_pre : cs_n__ras_n__cas_n__we_n <= 4'b0010; // Pre - arb_act : cs_n__ras_n__cas_n__we_n <= 4'b0011; // Act - arb_write : cs_n__ras_n__cas_n__we_n <= 4'b0100; // Write - arb_read : cs_n__ras_n__cas_n__we_n <= 4'b0101; // Read - arb_lmr : cs_n__ras_n__cas_n__we_n <= 4'b0000; // Lmr (data == address) - default : cs_n__ras_n__cas_n__we_n <= 4'b0111; - endcase - end - end - - // - // don't use clocking disable - // - - assign cke = 1'b1; - - // synthesis translate_off - initial begin - {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // only to disable mt48lc2m warnings - end - // synthesis translate_on - - always_ff @(posedge clk or posedge reset) begin : sdram_control_register - if (reset) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop - else if (sclr) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop - else {cs_n, ras_n, cas_n, we_n} <= cs_n__ras_n__cas_n__we_n; - end - - always_ff @(posedge clk) begin : sdram_mux_addr_path - - ba_latched <= arb_ba; - ba <= ba_latched; - - - if (arb_act | arb_lmr) - addr_latched <= ResizeRowa(arb_rowa); - else - addr_latched <= ResizeCola(arb_cola, arb_pre_all); - - addr <= addr_latched; - end - - //-------------------------------------------------------------------------------------------------- - // function to get sdram address from row address. row address is transfered during - // act/lmr sdram command and is directly mapped to row address. - //-------------------------------------------------------------------------------------------------- - - function sdram_addr_t ResizeRowa (input rowa_t rowa); - int i; - sdram_addr_t addr_resized; - - for (i = 0; i < pSdramAddrBits; i++) begin - if (pRowaBits > i) - addr_resized[i] = rowa[i]; - else - addr_resized[i] = 1'b0; - end - - return addr_resized; - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to get sdram address from column address. column address is transfered during : - // 1. read/write sdram command and A10 is autoprecharge bit and if pColaBits > 10 then - // cola [$:10] is mapped to addr [$:11]. - // 2. pre sdram command and A10 is select all banks bit - //-------------------------------------------------------------------------------------------------- - - function sdram_addr_t ResizeCola (input cola_t cola, input bit pre_all); - int i; - sdram_addr_t addr_resized; - - for (i = 0; i < pSdramAddrBits; i++) begin - if (i < 10) begin - if (pColaBits > i) - addr_resized[i] = cola[i]; - else - addr_resized[i] = 1'b0; - end - else if (i == 10) begin - addr_resized[i] = pre_all; // Autoprecharge is not used -> A10 is always 1'b0 then read/write active - end - else begin - if (pColaBits > i) - addr_resized[i] = cola[i-1]; - else - addr_resized[i] = 1'b0; - end - end - - return addr_resized; - endfunction - -endmodule

trunk/rtl/hssdrc_addr_path_p1.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_addr_path.v =================================================================== --- trunk/rtl/hssdrc_addr_path.v (revision 2) +++ trunk/rtl/hssdrc_addr_path.v (nonexistent) @@ -1,207 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_addr_path.v -// -// Description : coder for translate logical onehot command to sdram command -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - - -module hssdrc_addr_path( - clk , - reset , - sclr , - // - arb_pre_all , - arb_refr , - arb_pre , - arb_act , - arb_read , - arb_write , - arb_lmr , - arb_rowa , - arb_cola , - arb_ba , - // - addr , - ba , - cke , - cs_n , - ras_n , - cas_n , - we_n - ); - - input wire clk; - input wire reset; - input wire sclr; - - //-------------------------------------------------------------------------------------------------- - // interface from output arbiter - //-------------------------------------------------------------------------------------------------- - - input wire arb_pre_all ; - input wire arb_refr ; - input wire arb_pre ; - input wire arb_act ; - input wire arb_read ; - input wire arb_write ; - input wire arb_lmr ; - input rowa_t arb_rowa ; - input cola_t arb_cola ; - input ba_t arb_ba ; - - //-------------------------------------------------------------------------------------------------- - // interface to sdram - //-------------------------------------------------------------------------------------------------- - - output sdram_addr_t addr; - output ba_t ba; - output logic cke; - output logic cs_n; - output logic ras_n; - output logic cas_n; - output logic we_n; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - logic [3:0] cs_n__ras_n__cas_n__we_n; - - // synthesis translate_off - wire [6:0] arb_cmd = {arb_pre_all, arb_refr, arb_pre, arb_act, arb_write, arb_read, arb_lmr}; - arb_cmd_assert : assert property (@(posedge clk) disable iff (reset) (arb_cmd !== 0) |-> $onehot(arb_cmd)); - // synthesis translate_on - - always_comb begin : logical_command_decode - - cs_n__ras_n__cas_n__we_n = 4'b0111; // nop - - unique case (1'b1) - arb_pre_all : cs_n__ras_n__cas_n__we_n = 4'b0010; // Pre - arb_refr : cs_n__ras_n__cas_n__we_n = 4'b0001; // Refr - arb_pre : cs_n__ras_n__cas_n__we_n = 4'b0010; // Pre - arb_act : cs_n__ras_n__cas_n__we_n = 4'b0011; // Act - arb_write : cs_n__ras_n__cas_n__we_n = 4'b0100; // Write - arb_read : cs_n__ras_n__cas_n__we_n = 4'b0101; // Read - arb_lmr : cs_n__ras_n__cas_n__we_n = 4'b0000; // Lmr (data == address) - default : begin end - endcase - end - - // - // don't use clocking disable - // - - assign cke = 1'b1; - - // synthesis translate_off - initial begin - {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // only to disable mt48lc2m warnings - end - // synthesis translate_on - - always_ff @(posedge clk or posedge reset) begin : sdram_control_register - if (reset) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop - else if (sclr) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop - else {cs_n, ras_n, cas_n, we_n} <= cs_n__ras_n__cas_n__we_n; - end - - always_ff @(posedge clk) begin : sdram_mux_addr_path - - ba <= arb_ba; - - if (arb_act | arb_lmr) - addr <= ResizeRowa(arb_rowa); - else - addr <= ResizeCola(arb_cola, arb_pre_all); - - end - - //-------------------------------------------------------------------------------------------------- - // function to get sdram address from row address. row address is transfered during - // act/lmr sdram command and is directly mapped to row address. - //-------------------------------------------------------------------------------------------------- - - function sdram_addr_t ResizeRowa (input rowa_t rowa); - int i; - sdram_addr_t addr_resized; - - for (i = 0; i < pSdramAddrBits; i++) begin - if (pRowaBits > i) - addr_resized[i] = rowa[i]; - else - addr_resized[i] = 1'b0; - end - - return addr_resized; - endfunction - - //-------------------------------------------------------------------------------------------------- - // function to get sdram address from column address. column address is transfered during : - // 1. read/write sdram command and A10 is autoprecharge bit and if pColaBits > 10 then - // cola [$:10] is mapped to addr [$:11]. - // 2. pre sdram command and A10 is select all banks bit - //-------------------------------------------------------------------------------------------------- - - function sdram_addr_t ResizeCola (input cola_t cola, input bit pre_all); - int i; - sdram_addr_t addr_resized; - - for (i = 0; i < pSdramAddrBits; i++) begin - if (i < 10) begin - if (pColaBits > i) - addr_resized[i] = cola[i]; - else - addr_resized[i] = 1'b0; - end - else if (i == 10) begin - addr_resized[i] = pre_all; // Autoprecharge is not used -> A10 is always 1'b0 then read/write active - end - else begin - if (pColaBits > i) - addr_resized[i] = cola[i-1]; - else - addr_resized[i] = 1'b0; - end - end - - return addr_resized; - endfunction - -endmodule

trunk/rtl/hssdrc_addr_path.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_mux.v =================================================================== --- trunk/rtl/hssdrc_mux.v (revision 2) +++ trunk/rtl/hssdrc_mux.v (nonexistent) @@ -1,153 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_mux.v -// -// Description : multiplexer for sdram signals -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_mux - ( - init_done , - // - init_state_pre_all , - init_state_refr , - init_state_lmr , - init_state_rowa , - // - arb_pre_all , - arb_refr , - arb_pre , - arb_act , - arb_read , - arb_write , - arb_rowa , - arb_cola , - arb_ba , - arb_chid , - arb_burst , - // - mux_pre_all , - mux_refr , - mux_pre , - mux_act , - mux_read , - mux_write , - mux_lmr , - mux_rowa , - mux_cola , - mux_ba , - mux_chid , - mux_burst - ); - - input wire init_done; - - //-------------------------------------------------------------------------------------------------- - // interface from inis state controller - //-------------------------------------------------------------------------------------------------- - - input wire init_state_pre_all ; - input wire init_state_refr ; - input wire init_state_lmr ; - input rowa_t init_state_rowa ; - - //-------------------------------------------------------------------------------------------------- - // interface from output arbiter - //-------------------------------------------------------------------------------------------------- - - input wire arb_pre_all ; - input wire arb_refr ; - input wire arb_pre ; - input wire arb_act ; - input wire arb_read ; - input wire arb_write ; - input rowa_t arb_rowa ; - input cola_t arb_cola ; - input ba_t arb_ba ; - input chid_t arb_chid ; - input sdram_burst_t arb_burst ; - - //-------------------------------------------------------------------------------------------------- - // interface to data/addr path units - //-------------------------------------------------------------------------------------------------- - - output logic mux_pre_all ; - output logic mux_refr ; - output logic mux_pre ; - output logic mux_act ; - output logic mux_read ; - output logic mux_write ; - output logic mux_lmr ; - output rowa_t mux_rowa ; - output cola_t mux_cola ; - output ba_t mux_ba ; - output chid_t mux_chid ; - output sdram_burst_t mux_burst ; - - //------------------------------------------------------------------------------------------------- - // there is no reason to mask or mux arbiter_if signals, becouse during init state phase - // init_done == 0 and this signals is cleared inside decoders and after init state phase - // init_done == 1 and init_state_if signals will be cleared also - //------------------------------------------------------------------------------------------------- - - assign mux_pre_all = arb_pre_all | init_state_pre_all; - assign mux_refr = arb_refr | init_state_refr ; - - // this will be synthesis as simple logic, becouse init_state_rowa is constant - assign mux_rowa = init_done ? arb_rowa : init_state_rowa ; - - assign mux_pre = arb_pre ; - assign mux_act = arb_act ; - assign mux_read = arb_read ; - assign mux_write = arb_write ; - - assign mux_lmr = init_state_lmr; - - // - // no mux becouse init state phase not use this sdram ports - // - - assign mux_cola = arb_cola ; - assign mux_ba = arb_ba ; - assign mux_burst = arb_burst; - assign mux_chid = arb_chid ; - -endmodule - - -

trunk/rtl/hssdrc_mux.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_access_manager.v =================================================================== --- trunk/rtl/hssdrc_access_manager.v (revision 2) +++ trunk/rtl/hssdrc_access_manager.v (nonexistent) @@ -1,538 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_access_manager.v -// -// Description : sdram bank access manager -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -// used command sequenceces -// 1. {pre a -> act a -> rw a} -> {pre a -> act a -> rw a } -// -> {rw a } -// -> {pre_all -> refr} -// 2. {pre a -> act a -> rw a} -> {pre b -> act b -> rw b } -// -> {act b -> rw b} -// -> {rw b } -// -> {pre_all -> refr} -// 3. {pre_all -> refr} -> refr -// -> act -// -// just need to control : -// +-------------------+-------------------------+--------------------------+ -// | command | sequental decoder part | concurent/pipeline part | -// +===================+=========================+==========================+ -// | pre [0] -> | act [0] | act [1,2,3] | -// | pre [0] -> | | pre [1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | pre [1] -> | act [1] | act [0,2,3] | -// | pre [1] -> | | pre [0,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | pre [2] -> | act [2] | act [0,1,3] | -// | pre [2] -> | | pre [0,1,3] | -// +-------------------+-------------------------+--------------------------+ -// | pre [3] -> | act [3] | act [0,1,2] | -// | pre [3] -> | | pre [0,1,2] | -// +-------------------+-------------------------+--------------------------+ -// | act [0] -> | write [0] | | -// | act [0] -> | | act [1,2,3] | -// | act [0] -> | | pre [0,1,2,3] | -// | act [0] -> | read [0] | | -// +-------------------+-------------------------+--------------------------+ -// | act [1] -> | write [1] | | -// | act [1] -> | | act [0,2,3] | -// | act [1] -> | | pre [0,1,2,3] | -// | act [1] -> | read [1] | | -// +-------------------+-------------------------+--------------------------+ -// | act [2] -> | write [2] | | -// | act [2] -> | | act [0,1,3] | -// | act [2] -> | | pre [0,1,2,3] | -// | act [2] -> | read [2] | | -// +-------------------+-------------------------+--------------------------+ -// | act [3] -> | write [3] | | -// | act [3] -> | | act [0,1,2] | -// | act [3] -> | | pre [0,1,2,3] | -// | act [3] -> | read [3] | | -// +-------------------+-------------------------+--------------------------+ -// | write/read [0] -> | | pre [0,1,2,3] | -// | write/read [0] -> | | act [1,2,3] | -// | write/read [0] -> | | write[0,1,2,3] | -// | write/read [0] -> | | read [0,1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | write/read [1] -> | | pre [0,1,2,3] | -// | write/read [1] -> | | act [0,2,3] | -// | write/read [1] -> | | write[0,1,2,3] | -// | write/read [1] -> | | read [0,1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | write/read [2] -> | | pre [0,1,2,3] | -// | write/read [2] -> | | act [0,1,3] | -// | write/read [2] -> | | write[0,1,2,3] | -// | write/read [2] -> | | read [0,1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | write/read [3] -> | | pre [0,1,2,3] | -// | write/read [3] -> | | act [0,1,2] | -// | write/read [3] -> | | write[0,1,2,3] | -// | write/read [3] -> | | read [0,1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// | pre_all -> | refr | | -// | | | | -// +-------------------+-------------------------+--------------------------+ -// | refr -> | | refr | -// | refr -> | | act[0,1,2,3] | -// +-------------------+-------------------------+--------------------------+ -// -// -// -// +-----------------+---------------+-----------------+---------------------+-----------+ -// | past command | control tread | current command | contol time value | note | -// +=================+===============+=================+=====================+===========+ -// | act [0] | 0 | pre [0] | Tras | | -// | write [0] | 1 | | Twr + Burst | 1,2,3 | -// | read [0] | 2 | | Burst | bank | -// | pre [1,2,3] | | | 0 | is | -// | act [1,2,3] | | | 0 | same | -// | write [1,2,3] | | | 0 | | -// | read [1,2,3] | | | 0 | | -// +-----------------+---------------+-----------------+---------------------+-----------+ -// | pre [0] | 3 [1]_ | act [0] | Trp | | -// | refr | 4 | | Trfc | 1,2,3 | -// | act [0] | 5 | | Trc | | -// | act [1,2,3] | 6 | | Trrd | bank | -// | pre [1,2,3] | | | 0 | is | -// | write [1,2,3] | | | 0 | same | -// | read [1,2,3] | | | 0 | | -// +-----------------+---------------+-----------------+---------------------+-----------+ -// | act [0] | 7 [1]_ | write [0] | Trcd | 1,2,3 | -// | write [0,1,2,3] | 8 | | Burst | bank | -// | read [0,1,2,3] | 9 | | Burst + CL + 1(?bta)| is | -// | | | | | same | -// +-----------------+---------------+-----------------+---------------------+-----------+ -// | act [0] | 10 [1]_ | read [0] | Trcd | 1,2,3 | -// | write [0,1,2,3] | 11 | | Burst + 1(?bta) | bank | -// | read [0,1,2,3] | 12 | | Burst | is | -// | | | | | same | -// +-----------------+---------------+-----------------+---------------------+-----------+ -// | pre_all | 13 | refr | Trp | | -// | refr | 14 | | Trfc | | -// +-----------------+---------------+-----------------+---------------------+-----------+ -// -// ..[1] Trp (pre -> act) & Trcd (act -> read/write) contolled internal in decoder FSM -// - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" -`include "hssdrc_timing.vh" - -module hssdrc_access_manager ( - clk , - reset , - sclr , - // - arb_pre_all , - arb_refr , - arb_pre , - arb_act , - arb_read , - arb_write , - arb_ba , - arb_burst , - // - am_pre_all_enable , - am_refr_enable , - am_pre_enable , - am_act_enable , - am_read_enable , - am_write_enable - ); - - input wire clk; - input wire reset; - input wire sclr; - - //-------------------------------------------------------------------------------------------------- - // interface from output arbiter - //-------------------------------------------------------------------------------------------------- - - input logic arb_pre_all ; - input logic arb_refr ; - input logic arb_pre ; - input logic arb_act ; - input logic arb_read ; - input logic arb_write ; - input ba_t arb_ba ; - input sdram_burst_t arb_burst ; - - //-------------------------------------------------------------------------------------------------- - // outputs - //-------------------------------------------------------------------------------------------------- - - output logic am_pre_all_enable ; - output logic am_refr_enable ; - output logic [0:3] am_pre_enable ; - output logic [0:3] am_act_enable ; - output logic [0:3] am_read_enable ; - output logic [0:3] am_write_enable ; - - - //-------------------------------------------------------------------------------------------------- - // all timings is select using shift register techique. - // enable is 1'b1 level on output. - // all shift is shift rigth. - // shift register command load pattern is 'b{{x{1'b0}}, {y{1'b1}}} - //-------------------------------------------------------------------------------------------------- - - //-------------------------------------------------------------------------------------------------- - // take into acount load shift register cycle - //-------------------------------------------------------------------------------------------------- - - localparam int cTras_m1 = cTras - 1; - localparam int cTrfc_m1 = cTrfc - 1; -// localparam int cTrc_m1 = cTrc - 1; tras + trp contolled -// localparam int cTrcd_m1 = cTrcd - 1; fsm contolled - localparam int cTwr_m1 = cTwr - 1; - localparam int cTrp_m1 = cTrp - 1; - localparam int cTrrd_m1 = cTrrd - 1; - localparam int cSdramBL_m1 = cSdramBL - 1; - - //-------------------------------------------------------------------------------------------------- - // tread 0/1/2 : Tras (act -> pre) & Twr + Burst (write -> pre) & Burst (read -> write) - // Twr + Burst & Burst control via one register becouse write/read has atomic access - //-------------------------------------------------------------------------------------------------- - - localparam int cPreActEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1); - localparam int cPreRwEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1); - - typedef logic [cPreActEnableLength-1:0] pre_act_enable_srl_t; - typedef logic [cPreRwEnableLength-1 :0] pre_rw_enable_srl_t; - - // to pre load patterns - localparam pre_act_enable_srl_t cPreActEnableInitValue = {cPreActEnableLength{1'b1}}; - localparam pre_act_enable_srl_t cPreActEnableActValue = PercentRelation(cTras_m1, cPreActEnableLength); - - // to pre load patterns - localparam pre_rw_enable_srl_t cPreRwEnableInitValue = {cPreRwEnableLength{1'b1}}; - - // Remember : burst already has -1 offset (!!!!) - function automatic pre_rw_enable_srl_t PreRwEnableWriteValue (input sdram_burst_t burst); - PreRwEnableWriteValue = PercentRelation (cTwr_m1 + burst, cPreRwEnableLength); - endfunction - - function automatic pre_rw_enable_srl_t PreRwEnableReadValue (input sdram_burst_t burst); - PreRwEnableReadValue = PercentRelation (burst, cPreRwEnableLength); - endfunction - - // each bank has own control registers - pre_act_enable_srl_t pre_act_enable_srl [0:3]; - pre_rw_enable_srl_t pre_rw_enable_srl [0:3]; - - wire [0:3] pre_enable ; - - genvar p; - - generate - - for (p = 0; p < 4; p++) begin : pre_enable_generate - - always_ff @(posedge clk or posedge reset) begin : pre_enable_shift_register - - if (reset) - pre_act_enable_srl [p] <= cPreActEnableInitValue; - else if (sclr) - pre_act_enable_srl [p] <= cPreActEnableInitValue; - else begin - if (arb_act && (arb_ba == p)) - pre_act_enable_srl [p] <= cPreActEnableActValue; - else - pre_act_enable_srl [p] <= (pre_act_enable_srl [p] << 1) | 1'b1; - end - - - if (reset) - pre_rw_enable_srl [p] <= cPreRwEnableInitValue; - else if (sclr) - pre_rw_enable_srl [p] <= cPreRwEnableInitValue; - else begin - if (arb_write && (arb_ba == p)) - pre_rw_enable_srl [p] <= PreRwEnableWriteValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1); - else if (arb_read && (arb_ba == p)) - pre_rw_enable_srl [p] <= PreRwEnableReadValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1); - else - pre_rw_enable_srl [p] <= (pre_rw_enable_srl [p] << 1) | 1'b1; - end - - end - - assign pre_enable [p] = pre_rw_enable_srl [p] [cPreRwEnableLength-1] ; - - end - - endgenerate - - //-------------------------------------------------------------------------------------------------- - // pre_all_enable has same logic as pre enable. - // pre_all_enable == &(pre_enable), but for increase performance it have own control registers - //-------------------------------------------------------------------------------------------------- - - pre_act_enable_srl_t pre_all_act_enable_srl ; - pre_rw_enable_srl_t pre_all_rw_enable_srl ; - - wire pre_all_enable; - - always_ff @(posedge clk or posedge reset) begin : pre_all_enable_shift_register - - if (reset) - pre_all_act_enable_srl <= cPreActEnableInitValue; - else if (sclr) - pre_all_act_enable_srl <= cPreActEnableInitValue; - else begin - if (arb_act) - pre_all_act_enable_srl <= cPreActEnableActValue; - else - pre_all_act_enable_srl <= (pre_all_act_enable_srl << 1) | 1'b1; - end - - - if (reset) - pre_all_rw_enable_srl <= cPreRwEnableInitValue; - else if (sclr) - pre_all_rw_enable_srl <= cPreRwEnableInitValue; - else begin - if (arb_write) - pre_all_rw_enable_srl <= PreRwEnableWriteValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1); - else if (arb_read) - pre_all_rw_enable_srl <= PreRwEnableReadValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1); - else - pre_all_rw_enable_srl <= (pre_all_rw_enable_srl << 1) | 1'b1; - end - - end - - assign pre_all_enable = pre_all_rw_enable_srl [cPreRwEnableLength-1]; - - //-------------------------------------------------------------------------------------------------- - // tread 4/5/6 : Trfc (refr -> act) & Trc (act -> act) & Trrd (act a -> act b) - // Trc don't need to be contolled, becouse Trc = Tras + Trcd - // Trfc & Trrd control via one register becouse refr -> any act has locked & sequental access. - // for Trc we can use 1 register, becouse act a -> act a is imposible sequence - //-------------------------------------------------------------------------------------------------- - - localparam int cActEnableLength = max (cTrfc_m1, cTrrd_m1); - - typedef logic [cActEnableLength-1:0] act_enable_srl_t; - - // to act load patterns - localparam act_enable_srl_t cActEnableInitValue = {cActEnableLength{1'b1}}; - localparam act_enable_srl_t cActEnableRefrValue = PercentRelation(cTrfc_m1, cActEnableLength); - localparam act_enable_srl_t cActEnableActValue = PercentRelation(cTrrd_m1, cActEnableLength); - - act_enable_srl_t act_enable_srl ; - - wire [0:3] act_enable ; - - always_ff @(posedge clk or posedge reset) begin : act_enable_shift_register - - if (reset) - act_enable_srl <= cActEnableInitValue; - else if (sclr) - act_enable_srl <= cActEnableInitValue; - else begin - - if (arb_refr) - act_enable_srl <= cActEnableRefrValue; - else if (arb_act) - act_enable_srl <= cActEnableActValue; - else - act_enable_srl <= (act_enable_srl << 1) | 1'b1; - - end - end - - assign act_enable = {4{act_enable_srl [cActEnableLength-1]}} ; - - //-------------------------------------------------------------------------------------------------- - // tread 8/9 : Burst (write -> write) & Burst + CL + BTA (read -> write). - // control via one register becouse write/read -> write is atomic sequental access. - //-------------------------------------------------------------------------------------------------- - - localparam int cWriteEnableLength = max (cSdramBL_m1, cSdramBL_m1 + pCL + pBTA); - - typedef logic [cWriteEnableLength-1:0] write_enable_srl_t; - - // to write load patterns - localparam write_enable_srl_t cWriteEnableInitValue = {cWriteEnableLength{1'b1}}; - - // Remember : burst already has -1 offset (!!!!) - function automatic write_enable_srl_t WriteEnableWriteValue (input sdram_burst_t burst); - WriteEnableWriteValue = PercentRelation(burst, cWriteEnableLength); - endfunction - - function automatic write_enable_srl_t WriteEnableReadValue (input sdram_burst_t burst); - WriteEnableReadValue = PercentRelation(burst + pCL + pBTA, cWriteEnableLength); - endfunction - - write_enable_srl_t write_enable_srl; - - wire [0:3] write_enable ; - - always_ff @(posedge clk or posedge reset) begin : write_enable_shift_register - - if (reset) - write_enable_srl <= cWriteEnableInitValue; - else if (sclr) - write_enable_srl <= cWriteEnableInitValue; - else begin - if (arb_write) - write_enable_srl <= WriteEnableWriteValue (arb_burst); - else if (arb_read) - write_enable_srl <= WriteEnableReadValue (arb_burst); - else - write_enable_srl <= (write_enable_srl << 1) | 1'b1; - end - end - - assign write_enable = {4{write_enable_srl [cWriteEnableLength-1]}}; - - //-------------------------------------------------------------------------------------------------- - // tread 11/12 : Burst + BTA (write -> read) & Burst (read -> read). - // contorl via one register becouse write/read -> read is atomic sequental access - // BTA from write -> read is not need !!! becouse read have read latency !!!! - //-------------------------------------------------------------------------------------------------- - - localparam int cReadEnableLength = max(cSdramBL_m1, cSdramBL_m1); - - typedef logic [cReadEnableLength-1:0] read_enable_srl_t; - - // to read load patterns - localparam read_enable_srl_t cReadEnableInitValue = {cReadEnableLength{1'b1}}; - // Remember : burst already has -1 offset (!!!!) - function automatic read_enable_srl_t ReadEnableWriteValue (input sdram_burst_t burst); - ReadEnableWriteValue = PercentRelation(burst, cReadEnableLength); - endfunction - - function automatic read_enable_srl_t ReadEnableReadValue (input sdram_burst_t burst); - ReadEnableReadValue = PercentRelation(burst, cReadEnableLength); - endfunction - - read_enable_srl_t read_enable_srl; - - wire [0:3] read_enable ; - - always_ff @(posedge clk or posedge reset) begin : read_enable_shift_register - - if (reset) - read_enable_srl <= cReadEnableInitValue; - else if (sclr) - read_enable_srl <= cReadEnableInitValue; - else begin - if (arb_write) - read_enable_srl <= ReadEnableWriteValue (arb_burst); - else if (arb_read) - read_enable_srl <= ReadEnableReadValue (arb_burst); - else - read_enable_srl <= (read_enable_srl << 1) | 1'b1; - end - - end - - assign read_enable = {4{read_enable_srl [cReadEnableLength-1]}}; - - //-------------------------------------------------------------------------------------------------- - // tread 13/14 : Trp (pre_all -> refr) & Trfc (refr -> refr). - // contol via one register becouse pre_all/refr has locked access & (pre_all -> refr) has sequental access - //-------------------------------------------------------------------------------------------------- - - localparam int cRefrEnableLength = max (cTrp_m1, cTrfc_m1); - - typedef logic [cRefrEnableLength-1:0] refr_enable_srl_t; - - // to refr load patterns - localparam refr_enable_srl_t cRefrEnableInitValue = {cRefrEnableLength{1'b1}}; - localparam refr_enable_srl_t cRefrEnablePreAllValue = PercentRelation( cTrp_m1, cRefrEnableLength); - localparam refr_enable_srl_t cRefrEnableRefrValue = PercentRelation(cTrfc_m1, cRefrEnableLength); - - refr_enable_srl_t refr_enable_srl; - - wire refr_enable; - - always_ff @(posedge clk or posedge reset) begin : refr_enable_shift_register - - if (reset) - refr_enable_srl <= cRefrEnableInitValue; - else if (sclr) - refr_enable_srl <= cRefrEnableInitValue; - else begin - if (arb_pre_all) - refr_enable_srl <= cRefrEnablePreAllValue; - else if (arb_refr) - refr_enable_srl <= cRefrEnableRefrValue; - else - refr_enable_srl <= (refr_enable_srl << 1) | 1'b1; - end - - end - - assign refr_enable = refr_enable_srl [cRefrEnableLength-1]; - - //-------------------------------------------------------------------------------------------------- - // output mapping - //-------------------------------------------------------------------------------------------------- - - assign am_pre_all_enable = pre_all_enable; - assign am_refr_enable = refr_enable; - assign am_act_enable = act_enable; - assign am_pre_enable = pre_enable; - assign am_write_enable = write_enable; - assign am_read_enable = read_enable; - - //-------------------------------------------------------------------------------------------------- - // function to generate 'b{{{data}1'b0}, {{length-data}{1'b1}}} shift register load pattern - //-------------------------------------------------------------------------------------------------- - - function automatic int unsigned PercentRelation (input int unsigned data, length); - int unsigned value; - int i; - int ones_num; - - value = 0; - ones_num = length - data; // number of ones from lsb in constant vector - for ( i = 0; i < length; i++) begin - if (i < ones_num) value[i] = 1'b1; - else value[i] = 1'b0; - end - - return value; - endfunction - - -endmodule -

trunk/rtl/hssdrc_access_manager.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_refr_counter.v =================================================================== --- trunk/rtl/hssdrc_refr_counter.v (revision 2) +++ trunk/rtl/hssdrc_refr_counter.v (nonexistent) @@ -1,131 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_refr_counter.v -// -// Description : refresh time decode, counter based fsm -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_timing.vh" -`include "hssdrc_define.vh" - -module hssdrc_refr_counter ( - clk , - reset , - sclr , - ack , - hi_req , - low_req - ); - - input wire clk ; - input wire reset ; - input wire sclr ; - - input wire ack ; - output logic hi_req ; - output logic low_req ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - localparam cCntWidth = clogb2(cRefCounterMaxTime); - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - logic [cCntWidth-1 : 0] cnt; - - // - // - // - - always_ff @(posedge clk or posedge reset) begin : refresh_interval_counter - if (reset) - cnt <= '0; - else if (sclr | ack) - cnt <= '0; - else - cnt <= cnt + 1'b1; - end - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - -`ifdef HSSDRC_REFR_LOW_DISABLE - - assign low_req = 1'b0; - -`else - - always_ff @(posedge clk or posedge reset) begin : low_priopity_refresh_request_set - if (reset) - low_req <= 1'b0; - else if (sclr | ack) - low_req <= 1'b0; - else if (cnt > cRefrWindowLowPriorityTime) - low_req <= 1'b1; - end - -`endif - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - -`ifdef HSSDRC_REFR_HI_DISABLE - - assign hi_req = 1'b0; - -`else - - always_ff @(posedge clk or posedge reset) begin : high_priority_refresh_request_set - if (reset) - hi_req <= 1'b0; - else if (sclr | ack) - hi_req <= 1'b0; - else if (cnt > cRefrWindowHighPriorityTime) - hi_req <= 1'b1; - end - -`endif - - // - // - // -endmodule

trunk/rtl/hssdrc_refr_counter.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_arbiter_in.v =================================================================== --- trunk/rtl/hssdrc_arbiter_in.v (revision 2) +++ trunk/rtl/hssdrc_arbiter_in.v (nonexistent) @@ -1,255 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_arbiter_in.v -// -// Description : input 3 way decode arbiter -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_arbiter_in ( - clk , - reset , - sclr , - // - sys_write , - sys_read , - sys_refr , - sys_rowa , - sys_cola , - sys_ba , - sys_burst , - sys_chid_i , - sys_ready , - // - refr_cnt_ack , - refr_cnt_hi_req , - refr_cnt_low_req , - // - dec0_write , - dec0_read , - dec0_refr , - dec0_rowa , - dec0_cola , - dec0_ba , - dec0_burst , - dec0_chid , - dec0_ready , - // - dec1_write , - dec1_read , - dec1_refr , - dec1_rowa , - dec1_cola , - dec1_ba , - dec1_burst , - dec1_chid , - dec1_ready , - // - dec2_write , - dec2_read , - dec2_refr , - dec2_rowa , - dec2_cola , - dec2_ba , - dec2_burst , - dec2_chid , - dec2_ready - ); - - input wire clk ; - input wire reset ; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // interface from refresh cycle generator - //-------------------------------------------------------------------------------------------------- - - output logic refr_cnt_ack ; - input wire refr_cnt_hi_req ; - input wire refr_cnt_low_req ; - - //-------------------------------------------------------------------------------------------------- - // interface from system - //-------------------------------------------------------------------------------------------------- - - input wire sys_write ; - input wire sys_read ; - input wire sys_refr ; - input rowa_t sys_rowa ; - input cola_t sys_cola ; - input ba_t sys_ba ; - input burst_t sys_burst ; - input chid_t sys_chid_i ; - output logic sys_ready ; - - //-------------------------------------------------------------------------------------------------- - // interface to sdram sequence decoders - //-------------------------------------------------------------------------------------------------- - - output logic dec0_write ; - output logic dec0_read ; - output logic dec0_refr ; - output rowa_t dec0_rowa ; - output cola_t dec0_cola ; - output ba_t dec0_ba ; - output burst_t dec0_burst ; - output chid_t dec0_chid ; - input wire dec0_ready ; - // - output logic dec1_write ; - output logic dec1_read ; - output logic dec1_refr ; - output rowa_t dec1_rowa ; - output cola_t dec1_cola ; - output ba_t dec1_ba ; - output burst_t dec1_burst ; - output chid_t dec1_chid ; - input wire dec1_ready ; - // - output logic dec2_write ; - output logic dec2_read ; - output logic dec2_refr ; - output rowa_t dec2_rowa ; - output cola_t dec2_cola ; - output ba_t dec2_ba ; - output burst_t dec2_burst ; - output chid_t dec2_chid ; - input wire dec2_ready ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - wire sys_lock ; - wire low_req_lock ; - wire arb_write ; - wire arb_read ; - wire arb_refr ; - wire arb_ready ; - wire arb_ack ; - wire arb_refr_ack ; - logic [2:0] arb; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - assign sys_lock = refr_cnt_hi_req; - assign low_req_lock = sys_write | sys_read | sys_refr; - - // - // - // - - assign arb_write = sys_write & ~sys_lock; - assign arb_read = sys_read & ~sys_lock; - assign arb_refr = sys_refr | refr_cnt_hi_req | (refr_cnt_low_req & ~low_req_lock); - assign arb_ready = dec0_ready | dec1_ready | dec2_ready; - - // - // - // - - assign arb_ack = arb_ready & (arb_write | arb_read | arb_refr); - assign arb_refr_ack = arb_ready & arb_refr ; - - // - // - // - - assign refr_cnt_ack = arb_refr_ack; - - // - // - // - - assign sys_ready = arb_ready & ~sys_lock; - - // - // - // - - always_ff @(posedge clk or posedge reset) begin : arbiter_logic - if (reset) - arb <= 3'b001; - else if (sclr) - arb <= 3'b001; - else if (arb_ack) - arb <= {arb[1:0], arb[2]}; - end - - // - // - // - - assign dec0_write = arb_write & arb[0]; - assign dec0_read = arb_read & arb[0]; - assign dec0_refr = arb_refr & arb[0]; - assign dec0_rowa = sys_rowa ; - assign dec0_cola = sys_cola ; - assign dec0_ba = sys_ba ; - assign dec0_burst = sys_burst ; - assign dec0_chid = sys_chid_i; - - // - // - // - - assign dec1_write = arb_write & arb[1]; - assign dec1_read = arb_read & arb[1]; - assign dec1_refr = arb_refr & arb[1]; - assign dec1_rowa = sys_rowa ; - assign dec1_cola = sys_cola ; - assign dec1_ba = sys_ba ; - assign dec1_burst = sys_burst ; - assign dec1_chid = sys_chid_i; - - // - // - // - - assign dec2_write = arb_write & arb[2]; - assign dec2_read = arb_read & arb[2]; - assign dec2_refr = arb_refr & arb[2]; - assign dec2_rowa = sys_rowa ; - assign dec2_cola = sys_cola ; - assign dec2_ba = sys_ba ; - assign dec2_burst = sys_burst ; - assign dec2_chid = sys_chid_i; - -endmodule

trunk/rtl/hssdrc_arbiter_in.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_arbiter_out.v =================================================================== --- trunk/rtl/hssdrc_arbiter_out.v (revision 2) +++ trunk/rtl/hssdrc_arbiter_out.v (nonexistent) @@ -1,631 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_arbiter_out.v -// -// Description : output 3 way decode arbiter -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_arbiter_out ( - clk , - reset , - sclr , - // - dec0_pre_all , - dec0_refr , - dec0_pre , - dec0_act , - dec0_read , - dec0_write , - dec0_pre_all_enable, - dec0_refr_enable , - dec0_pre_enable , - dec0_act_enable , - dec0_read_enable , - dec0_write_enable , - dec0_locked , - dec0_last , - dec0_rowa , - dec0_cola , - dec0_ba , - dec0_chid , - dec0_burst , - // - dec1_pre_all , - dec1_refr , - dec1_pre , - dec1_act , - dec1_read , - dec1_write , - dec1_pre_all_enable, - dec1_refr_enable , - dec1_pre_enable , - dec1_act_enable , - dec1_read_enable , - dec1_write_enable , - dec1_locked , - dec1_last , - dec1_rowa , - dec1_cola , - dec1_ba , - dec1_chid , - dec1_burst , - // - dec2_pre_all , - dec2_refr , - dec2_pre , - dec2_act , - dec2_read , - dec2_write , - dec2_pre_all_enable, - dec2_refr_enable , - dec2_pre_enable , - dec2_act_enable , - dec2_read_enable , - dec2_write_enable , - dec2_locked , - dec2_last , - dec2_rowa , - dec2_cola , - dec2_ba , - dec2_chid , - dec2_burst , - // - am_pre_all_enable , - am_refr_enable , - am_pre_enable , - am_act_enable , - am_read_enable , - am_write_enable , - // - arb_pre_all , - arb_refr , - arb_pre , - arb_act , - arb_read , - arb_write , - arb_rowa , - arb_cola , - arb_ba , - arb_chid , - arb_burst - ); - - input wire clk ; - input wire reset; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // interface from sequence decoders - //-------------------------------------------------------------------------------------------------- - - input wire dec0_pre_all ; - input wire dec0_refr ; - input wire dec0_pre ; - input wire dec0_act ; - input wire dec0_read ; - input wire dec0_write ; - output logic dec0_pre_all_enable; - output logic dec0_refr_enable ; - output logic dec0_pre_enable ; - output logic dec0_act_enable ; - output logic dec0_read_enable ; - output logic dec0_write_enable ; - input wire dec0_locked ; - input wire dec0_last ; - input rowa_t dec0_rowa ; - input cola_t dec0_cola ; - input ba_t dec0_ba ; - input chid_t dec0_chid ; - input sdram_burst_t dec0_burst ; - // - input wire dec1_pre_all ; - input wire dec1_refr ; - input wire dec1_pre ; - input wire dec1_act ; - input wire dec1_read ; - input wire dec1_write ; - output logic dec1_pre_all_enable; - output logic dec1_refr_enable ; - output logic dec1_pre_enable ; - output logic dec1_act_enable ; - output logic dec1_read_enable ; - output logic dec1_write_enable ; - input wire dec1_locked ; - input wire dec1_last ; - input rowa_t dec1_rowa ; - input cola_t dec1_cola ; - input ba_t dec1_ba ; - input chid_t dec1_chid ; - input sdram_burst_t dec1_burst ; - // - input wire dec2_pre_all ; - input wire dec2_refr ; - input wire dec2_pre ; - input wire dec2_act ; - input wire dec2_read ; - input wire dec2_write ; - output logic dec2_pre_all_enable; - output logic dec2_refr_enable ; - output logic dec2_pre_enable ; - output logic dec2_act_enable ; - output logic dec2_read_enable ; - output logic dec2_write_enable ; - input wire dec2_locked ; - input wire dec2_last ; - input rowa_t dec2_rowa ; - input cola_t dec2_cola ; - input ba_t dec2_ba ; - input chid_t dec2_chid ; - input sdram_burst_t dec2_burst ; - - //-------------------------------------------------------------------------------------------------- - // interface from access manager - //-------------------------------------------------------------------------------------------------- - - input wire am_pre_all_enable ; - input wire am_refr_enable ; - input wire [0:3] am_pre_enable ; - input wire [0:3] am_act_enable ; - input wire [0:3] am_read_enable ; - input wire [0:3] am_write_enable ; - - //-------------------------------------------------------------------------------------------------- - // interface to multiplexer - //-------------------------------------------------------------------------------------------------- - - output logic arb_pre_all ; - output logic arb_refr ; - output logic arb_pre ; - output logic arb_act ; - output logic arb_read ; - output logic arb_write ; - output rowa_t arb_rowa ; - output cola_t arb_cola ; - output ba_t arb_ba ; - output chid_t arb_chid ; - output sdram_burst_t arb_burst ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - enum bit [1:0] {ARB0, ARB1, ARB2} arb, ba_rowa_mux; - - logic arb_ack; - - logic dec0_access_enable; - logic dec1_access_enable; - logic dec2_access_enable; - - logic dec0_bank_access_enable; - logic dec1_bank_access_enable; - logic dec2_bank_access_enable; - - logic dec1_can_have_access_when_arb_is_0 ; - logic dec2_can_have_access_when_arb_is_0 ; - - logic dec2_can_have_access_when_arb_is_1 ; - logic dec0_can_have_access_when_arb_is_1 ; - - logic dec0_can_have_access_when_arb_is_2 ; - logic dec1_can_have_access_when_arb_is_2 ; - - logic dec0_access_done; - logic dec1_access_done; - logic dec2_access_done; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : arbiter_logic - if (reset) - arb <= ARB0; - else if (sclr) - arb <= ARB0; - else if (arb_ack) - unique case (arb) - ARB0 : arb <= ARB1; - ARB1 : arb <= ARB2; - ARB2 : arb <= ARB0; - endcase - end - - // - // - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - // use act command sharing - assign dec0_bank_access_enable = (dec0_pre & am_pre_enable [dec0_ba] ) | - (dec0_act & am_act_enable [dec0_ba] ) ; - - assign dec1_bank_access_enable = (dec1_pre & am_pre_enable [dec1_ba] ) | - (dec1_act & am_act_enable [dec1_ba] ) ; - - assign dec2_bank_access_enable = (dec2_pre & am_pre_enable [dec2_ba] ) | - (dec2_act & am_act_enable [dec2_ba] ) ; - `else - // not use act command sharing - assign dec0_bank_access_enable = (dec0_pre & am_pre_enable [dec0_ba] ) ; - - assign dec1_bank_access_enable = (dec1_pre & am_pre_enable [dec1_ba] ) ; - - assign dec2_bank_access_enable = (dec2_pre & am_pre_enable [dec2_ba] ) ; - `endif - // - // - // - assign dec0_access_enable = (dec0_read & am_read_enable [dec0_ba] ) | - (dec0_write & am_write_enable [dec0_ba] ) | - (dec0_pre & am_pre_enable [dec0_ba] ) | - (dec0_act & am_act_enable [dec0_ba] ) ; - - assign dec1_access_enable = (dec1_read & am_read_enable [dec1_ba] ) | - (dec1_write & am_write_enable [dec1_ba] ) | - (dec1_pre & am_pre_enable [dec1_ba] ) | - (dec1_act & am_act_enable [dec1_ba] ) ; - - - assign dec2_access_enable = (dec2_read & am_read_enable [dec2_ba] ) | - (dec2_write & am_write_enable [dec2_ba] ) | - (dec2_pre & am_pre_enable [dec2_ba] ) | - (dec2_act & am_act_enable [dec2_ba] ) ; - // - // - // - assign dec0_access_done = (dec0_refr & dec0_refr_enable) | - (dec0_last & - ((dec0_read & dec0_read_enable ) | - ( dec0_write & dec0_write_enable )) - ); - - assign dec1_access_done = (dec1_refr & dec1_refr_enable) | - (dec1_last & - ((dec1_read & dec1_read_enable ) | - ( dec1_write & dec1_write_enable )) - ); - - assign dec2_access_done = (dec2_refr & dec2_refr_enable) | - (dec2_last & - ((dec2_read & dec2_read_enable ) | - ( dec2_write & dec2_write_enable )) - ); - // - // - // - assign arb_ack = (dec0_access_done && (arb == ARB0)) | - (dec1_access_done && (arb == ARB1)) | - (dec2_access_done && (arb == ARB2)); - //-------------------------------------------------------------------------------------------------- - // decoder roundabout : dec0 -> dec1 -> dec2 -> dec0 -> dec1 - // - // arbiter for command pipeline need in folow comparators : - // 0 : dec0 - dec1 -> select dec1 - // : dec0 - dec2 & dec1 - dec2 -> select dec2 - // 1 : dec1 - dec2 -> select dec2 - // : dec1 - dec2 & dec2 - dec0 -> select dec0 - // 2 : dec2 - dec0 -> select dec0 - // : dec2 - dec1 & dec0 - dec1 -> select dec1 - // we can reclock it. becouse "ba" and "locked" is valid 1 tick before command - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk) begin : locked_and_bank_access_comparator - dec1_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec1_ba != dec0_ba); - dec2_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec2_ba != dec0_ba) & ~dec1_locked & (dec2_ba != dec1_ba); - - dec2_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec2_ba != dec1_ba); - dec0_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec0_ba != dec1_ba) & ~dec2_locked & (dec0_ba != dec2_ba); - - dec0_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec0_ba != dec2_ba); - dec1_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec1_ba != dec2_ba) & ~dec0_locked & (dec1_ba != dec0_ba); - end - - // - // - // - - always_comb begin : control_path_arbiter - - dec0_pre_all_enable = 1'b0; - dec0_refr_enable = 1'b0; - dec0_pre_enable = 1'b0; - dec0_act_enable = 1'b0; - dec0_read_enable = 1'b0; - dec0_write_enable = 1'b0; - - dec1_pre_all_enable = 1'b0; - dec1_refr_enable = 1'b0; - dec1_pre_enable = 1'b0; - dec1_act_enable = 1'b0; - dec1_read_enable = 1'b0; - dec1_write_enable = 1'b0; - - dec2_pre_all_enable = 1'b0; - dec2_refr_enable = 1'b0; - dec2_pre_enable = 1'b0; - dec2_act_enable = 1'b0; - dec2_read_enable = 1'b0; - dec2_write_enable = 1'b0; - - arb_pre_all = 1'b0; - arb_refr = 1'b0; - arb_pre = 1'b0; - arb_act = 1'b0; - arb_read = 1'b0; - arb_write = 1'b0; - - ba_rowa_mux = arb; - - unique case (arb) - ARB0 : begin : dec0_is_master - - dec0_pre_all_enable = am_pre_all_enable ; - dec0_refr_enable = am_refr_enable ; - dec0_pre_enable = am_pre_enable [dec0_ba]; - dec0_act_enable = am_act_enable [dec0_ba]; - dec0_read_enable = am_read_enable [dec0_ba]; - dec0_write_enable = am_write_enable [dec0_ba]; - - arb_pre_all = dec0_pre_all & dec0_pre_all_enable ; - arb_refr = dec0_refr & dec0_refr_enable ; - arb_pre = dec0_pre & dec0_pre_enable ; - arb_act = dec0_act & dec0_act_enable ; - arb_read = dec0_read & dec0_read_enable ; - arb_write = dec0_write & dec0_write_enable ; - -`ifndef HSSDRC_SHARE_NONE_DECODER - - if (~dec0_access_enable) begin - - if (dec1_can_have_access_when_arb_is_0) begin - - ba_rowa_mux = ARB1; - // - dec1_pre_enable = am_pre_enable [dec1_ba]; - - arb_pre = dec1_pre & dec1_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec1_act_enable = am_act_enable [dec1_ba]; - - arb_act = dec1_act & dec1_act_enable ; - `endif - - end - - `ifndef HSSDRC_SHARE_ONE_DECODER - if (~dec1_bank_access_enable & dec2_can_have_access_when_arb_is_0) begin - `else - else if (dec2_can_have_access_when_arb_is_0) begin - `endif - ba_rowa_mux = ARB2; - // - dec2_pre_enable = am_pre_enable [dec2_ba]; - - arb_pre = dec2_pre & dec2_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec2_act_enable = am_act_enable [dec2_ba]; - - arb_act = dec2_act & dec2_act_enable ; - `endif - - end - end -`endif // HSSDRC_SHARE_NONE_DECODER - end - - ARB1 : begin : dec1_is_master - - dec1_pre_all_enable = am_pre_all_enable ; - dec1_refr_enable = am_refr_enable ; - dec1_pre_enable = am_pre_enable [dec1_ba]; - dec1_act_enable = am_act_enable [dec1_ba]; - dec1_read_enable = am_read_enable [dec1_ba]; - dec1_write_enable = am_write_enable [dec1_ba]; - - arb_pre_all = dec1_pre_all & dec1_pre_all_enable ; - arb_refr = dec1_refr & dec1_refr_enable ; - arb_pre = dec1_pre & dec1_pre_enable ; - arb_act = dec1_act & dec1_act_enable ; - arb_read = dec1_read & dec1_read_enable ; - arb_write = dec1_write & dec1_write_enable ; - -`ifndef HSSDRC_SHARE_NONE_DECODER - - if (~dec1_access_enable) begin - - if (dec2_can_have_access_when_arb_is_1) begin - - ba_rowa_mux = ARB2; - // - dec2_pre_enable = am_pre_enable [dec2_ba]; - - arb_pre = dec2_pre & dec2_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec2_act_enable = am_act_enable [dec2_ba]; - - arb_act = dec2_act & dec2_act_enable ; - `endif - - end - - `ifndef HSSDRC_SHARE_ONE_DECODER - if (~dec2_bank_access_enable & dec0_can_have_access_when_arb_is_1) begin - `else - else if (dec0_can_have_access_when_arb_is_1) begin - `endif - ba_rowa_mux = ARB0; - // - dec0_pre_enable = am_pre_enable [dec0_ba]; - - arb_pre = dec0_pre & dec0_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec0_act_enable = am_act_enable [dec0_ba]; - - arb_act = dec0_act & dec0_act_enable ; - `endif - - end - end -`endif // HSSDRC_SHARE_NONE_DECODER - end - - ARB2 : begin : dec2_is_master - - dec2_pre_all_enable = am_pre_all_enable ; - dec2_refr_enable = am_refr_enable ; - dec2_pre_enable = am_pre_enable [dec2_ba] ; - dec2_act_enable = am_act_enable [dec2_ba] ; - dec2_read_enable = am_read_enable [dec2_ba] ; - dec2_write_enable = am_write_enable [dec2_ba] ; - - arb_pre_all = dec2_pre_all & dec2_pre_all_enable ; - arb_refr = dec2_refr & dec2_refr_enable ; - arb_pre = dec2_pre & dec2_pre_enable ; - arb_act = dec2_act & dec2_act_enable ; - arb_read = dec2_read & dec2_read_enable ; - arb_write = dec2_write & dec2_write_enable ; - -`ifndef HSSDRC_SHARE_NONE_DECODER - - if (~dec2_access_enable) begin - - if (dec0_can_have_access_when_arb_is_2) begin - - ba_rowa_mux = ARB0; - // - dec0_pre_enable = am_pre_enable [dec0_ba]; - - arb_pre = dec0_pre & dec0_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec0_act_enable = am_act_enable [dec0_ba]; - - arb_act = dec0_act & dec0_act_enable ; - `endif - - end - - `ifndef HSSDRC_SHARE_ONE_DECODER - if (~dec0_bank_access_enable & dec1_can_have_access_when_arb_is_2) begin - `else - else if (dec1_can_have_access_when_arb_is_2) begin - `endif - ba_rowa_mux = ARB1; - // - dec1_pre_enable = am_pre_enable [dec1_ba]; - - arb_pre = dec1_pre & dec1_pre_enable ; - // - `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - dec1_act_enable = am_act_enable [dec1_ba]; - - arb_act = dec1_act & dec1_act_enable ; - `endif - - end - end -`endif // HSSDRC_SHARE_NONE_DECODER - end - endcase - end - - - - always_comb begin : mux_addr_path2arbiter - - // - // no complex mux : used in read/write command - // - - arb_cola = dec0_cola; - arb_chid = dec0_chid; - arb_burst = dec0_burst; - - unique case (arb) - ARB0 : begin - arb_cola = dec0_cola; - arb_chid = dec0_chid; - arb_burst = dec0_burst; - end - ARB1 : begin - arb_cola = dec1_cola; - arb_chid = dec1_chid; - arb_burst = dec1_burst; - end - ARB2 : begin - arb_cola = dec2_cola; - arb_chid = dec2_chid; - arb_burst = dec2_burst; - end - default : begin end - endcase - - // - // complex mux used in pre command - // - - arb_ba = dec0_ba; - - unique case (ba_rowa_mux) - ARB0 : arb_ba = dec0_ba; - ARB1 : arb_ba = dec1_ba; - ARB2 : arb_ba = dec2_ba; - endcase - - // - // complex mux used in act command - // - - arb_rowa = dec0_rowa; - -`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND - unique case (ba_rowa_mux) -`else - unique case (arb) -`endif - ARB0 : arb_rowa = dec0_rowa; - ARB1 : arb_rowa = dec1_rowa; - ARB2 : arb_rowa = dec2_rowa; - endcase - - end - -endmodule

trunk/rtl/hssdrc_arbiter_out.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/hssdrc_ba_map.v =================================================================== --- trunk/rtl/hssdrc_ba_map.v (revision 2) +++ trunk/rtl/hssdrc_ba_map.v (nonexistent) @@ -1,136 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:52:43 $ -// -// Workfile : hssdrc_ba_map.v -// -// Description : bank & row map unit -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - - -`include "hssdrc_timescale.vh" - -`include "hssdrc_define.vh" - -module hssdrc_ba_map ( - clk , - reset , - sclr , - // - update , - clear , - ba , - rowa , - // - pre_act_rw , - act_rw , - rw , - all_close - - ); - - input wire clk ; - input wire reset ; - input wire sclr ; - - //-------------------------------------------------------------------------------------------------- - // interface from sequence decoders - //-------------------------------------------------------------------------------------------------- - - input wire update ; - input wire clear ; - input ba_t ba ; - input rowa_t rowa ; - - //-------------------------------------------------------------------------------------------------- - // interface to sequence decoders - //-------------------------------------------------------------------------------------------------- - - output logic pre_act_rw ; - output logic act_rw ; - output logic rw ; - output logic all_close ; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - logic [3:0] bank_open; - rowa_t row_open [0:3]; - wire bank_is_open; - wire row_is_open; - - //-------------------------------------------------------------------------------------------------- - // - //-------------------------------------------------------------------------------------------------- - - always_ff @(posedge clk or posedge reset) begin : bank_open_map_process - if (reset) - bank_open <= '0; - else if (sclr) - bank_open <= '0; - else begin - if (clear) - bank_open <= '0; - else if (update) - bank_open [ba] <= 1'b1; - else begin - end - end - end - - // - // - // - - always_ff @(posedge clk) begin : row_open_map_process - if (update) - row_open[ba] <= rowa; - end - - // - // - // - - assign bank_is_open = bank_open [ba]; - assign row_is_open = (row_open [ba] == rowa); - - // - // - // - - assign rw = bank_is_open & row_is_open; - assign pre_act_rw = bank_is_open & ~row_is_open; - assign act_rw = ~bank_is_open; - assign all_close = (bank_open == 0); - -endmodule

trunk/rtl/hssdrc_ba_map.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/include/hssdrc_timescale.vh =================================================================== --- trunk/include/hssdrc_timescale.vh (revision 2) +++ trunk/include/hssdrc_timescale.vh (nonexistent) @@ -1,44 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:51:55 $ -// -// Workfile : hssdrc_timescale.vh -// -// Description : simulation time settings -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -// synthesis translate_off - - timeunit 1ns; - timeprecision 10ps; - -// synthesis translate_on

trunk/include/hssdrc_timescale.vh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/include/hssdrc_timing.vh =================================================================== --- trunk/include/hssdrc_timing.vh (revision 2) +++ trunk/include/hssdrc_timing.vh (nonexistent) @@ -1,93 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:51:55 $ -// -// Workfile : hssdrc_timing.vh -// -// Description : controller sdram timing paramters -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`ifndef __HSSDRC_TIMING_VH__ - - `define __HSSDRC_TIMING_VH__ - - //`define HSSDRC_SIMULATE_TIMING // uncomment for easy debug arefr sequence - - //------------------------------------------------- - // sdram controller clock settings in MHz - //------------------------------------------------- - parameter real pClkMHz = 133.0; - //------------------------------------------------- - // sdram chip timing paramters in "ns" for -6 CL3 - //------------------------------------------------- - parameter real pTras_time = 42.0; // act a -> prech a - parameter real pTrfc_time = 60.0; // refr -> !nop - parameter real pTrc_time = 60.0; // act a -> act a (Tras + Trcd) - parameter real pTrcd_time = 18.0; // act a -> write/read a - parameter real pTrp_time = 18.0; // prech a -> !nop - parameter real pTrrd_time = 12.0; // act a -> act b - parameter real pTwr_time = 12.0; // write a -> prech a - - `ifndef HSSDRC_SIMULATE_TIMING - parameter real pRefr_time = 15625.0; // refr -> refr - parameter real pInit_time = 100000.0; // power up -> refr - `else - parameter real pRefr_time = 500.0; // simulate only refr -> refr - parameter real pInit_time = 500.0; // simulate only power up -> refr - `endif - //------------------------------------------------- - // sdram chip normalaize to clock parameters - //------------------------------------------------- - parameter int cTras = 0.5 + (pTras_time * pClkMHz)/1000.0; // act a -> prech a - parameter int cTrfc = 0.5 + (pTrfc_time * pClkMHz)/1000.0; // refr -> !nop - parameter int cTrc = 0.5 + ( pTrc_time * pClkMHz)/1000.0; // act a -> act a - parameter int cTrcd = 0.5 + (pTrcd_time * pClkMHz)/1000.0; // act a -> write/read a - parameter int cTrp = 0.5 + ( pTrp_time * pClkMHz)/1000.0; // prech a -> !nop - parameter int cTrrd = 0.5 + (pTrrd_time * pClkMHz)/1000.0; // act a -> act b - parameter int cTwr = 0.5 + ( pTwr_time * pClkMHz)/1000.0; // write a -> prech a - parameter int cTmrd = 2; // lmr -> !nop (not used) - parameter int cInitTime = 0.5 + (pInit_time * pClkMHz)/1000.0; - //------------------------------------------------- - // refresh parameters - //------------------------------------------------- - parameter real pRefrWindowLowPriority = 0.85; - parameter real pRefrWindowHighPriority = 0.95; - parameter int cRefCounterMaxTime = 0.5 + (pRefr_time * pClkMHz)/1000.0; - parameter int cRefrWindowLowPriorityTime = 0.5 + (pRefrWindowLowPriority * pRefr_time * pClkMHz)/1000.0; - parameter int cRefrWindowHighPriorityTime = 0.5 + (pRefrWindowHighPriority * pRefr_time * pClkMHz)/1000.0; - //------------------------------------------------- - // sdram controller use 0/1 cycle bus turnaround - //------------------------------------------------- - parameter int pBTA = 1; // set 0 if not need - - // -`endif

trunk/include/hssdrc_timing.vh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/include/hssdrc_define.vh =================================================================== --- trunk/include/hssdrc_define.vh (revision 2) +++ trunk/include/hssdrc_define.vh (nonexistent) @@ -1,139 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:51:55 $ -// -// Workfile : hssdrc_define.vh -// -// Description : controller hardware paramters & settings -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`ifndef __HSSDRC_DEFINE_VH__ - - `define __HSSDRC_DEFINE_VH__ - - //`define HSSDRC_DQ_PIPELINE // uncomment when need dq data register output - //`define HSSDRC_REFR_HI_DISABLE // uncomment when not need high priority refresh logic - //`define HSSDRC_REFR_LOW_DISABLE // uncomment when not need low priority refresh logic - //---------------------------------------------------------------------------------- - // default : controller used use_wdata signal with register output type - // optionaly : controller can use combinative use_wdata signal which set 1 cycle early - //---------------------------------------------------------------------------------- - //`define HSSDRC_COMBINATORY_USE_WDATA // uncomment when need to use non register use_wdata signal - //---------------------------------------------------------------------------------- - // default : decoders sharing PRE & ACT command inside sdram command pipeline waiting - //---------------------------------------------------------------------------------- - //`define HSSDRC_NOT_SHARE_ACT_COMMAND // uncomment for not generate logic for share ACT command - //---------------------------------------------------------------------------------- - // default : 2 decoders sharing sdram command pipeline inside PRE & ACT command waiting - //---------------------------------------------------------------------------------- - //`define HSSDRC_SHARE_ONE_DECODER // uncoment for only 1 decoder share - //`define HSSDRC_SHARE_NONE_DECODER // uncoment for none decoder share - //---------------------------------------------------------------------------------- - // sdram controller command interface parameters - //---------------------------------------------------------------------------------- - parameter int pRowaBits = 11; // >= 11 (0..10) - parameter int pColaBits = 8; // <= pRowBits - parameter int pBaBits = 2; // fixed == 2 (don't change !!!) - parameter int pBurstBits = 4; // <= 4 - parameter int pChIdBits = 2; // >= 1 - //---------------------------------------------------------------------------------- - // sdram controller data interface & sdram chip data interface parameters - //---------------------------------------------------------------------------------- - parameter int pDataBits = 32; // >= 8 - parameter int pDatamBits = byte_lanes(pDataBits); - //---------------------------------------------------------------------------------- - // sdram controller command interface parameters - //---------------------------------------------------------------------------------- - parameter int pSdramAddrBits = 11; // (>= pRowaBits & >= 11) - parameter int pSdramBurstBits = 2; // fixed == 2 (don't change !!!) - parameter int cSdramBL = 2**pSdramBurstBits; - //---------------------------------------------------------------------------------- - // sdram controller mode parameters (don't change except CL !!!!) - //---------------------------------------------------------------------------------- - parameter bit pInitWBM = 1'b0; // write burst mode = programed burst - parameter bit [1:0] pInitOM = 1'b0; // operation mode = standart - parameter bit [2:0] pCL = 3'b011; // cas latency = 3 - parameter bit pInitBT = 1'b0; // burst type = sequental - parameter bit [2:0] pInitBL = 3'b010; // burst = 4 - - parameter bit [pSdramAddrBits-1:10] pReserved = '0; - parameter bit [pSdramAddrBits-1: 0] cInitLmrValue = {pReserved, pInitWBM, pInitOM, pCL, pInitBT, pInitBL}; - //---------------------------------------------------------------------------------- - // used types - //---------------------------------------------------------------------------------- - typedef logic [pColaBits - 1 : 0] cola_t; - typedef logic [pRowaBits - 1 : 0] rowa_t; - typedef logic [pBaBits - 1 : 0] ba_t; - typedef logic [pBurstBits - 1 : 0] burst_t; - typedef logic [pChIdBits - 1 : 0] chid_t; - typedef logic [pDataBits - 1 : 0] data_t; - typedef logic [pDatamBits - 1 : 0] datam_t; - - typedef logic [pSdramAddrBits-1 :0] sdram_addr_t; - typedef logic [pSdramBurstBits-1:0] sdram_burst_t; - //---------------------------------------------------------------------------------- - // - //---------------------------------------------------------------------------------- - function automatic int clogb2 (input int data); - int i; - - for (i = 0; 2**i < data; i++) - clogb2 = i + 1; - endfunction - //---------------------------------------------------------------------------------- - // - //---------------------------------------------------------------------------------- - function automatic int byte_lanes (input int data); - int num; - - byte_lanes = 0; - - num = data; - // synthesis translate_off - assert (num != 0) else $error ("wrong data parameter"); - // synthesis translate_on - while (num > 0) begin - byte_lanes++; - num = num - 8; - end - - endfunction - //---------------------------------------------------------------------------------- - // - //---------------------------------------------------------------------------------- - function automatic int unsigned max(input int unsigned a, b); - if (a >= b) max = a; - else max = b; - endfunction - -`endif -

trunk/include/hssdrc_define.vh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/include/tb_define.svh =================================================================== --- trunk/include/tb_define.svh (revision 2) +++ trunk/include/tb_define.svh (nonexistent) @@ -1,157 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:51:55 $ -// -// Workfile : tb_define.svh -// -// Description : testbench types, values, parameters -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_define.vh" - -`ifndef __TB_DEFINE_SVH__ - - `define __TB_DEFINE_SVH__ - - // - // tb types without Z, X states - // - typedef bit [pColaBits - 1 : 0] tb_cola_t; - typedef bit [pRowaBits - 1 : 0] tb_rowa_t; - typedef bit [pBaBits - 1 : 0] tb_ba_t; - typedef bit [pBurstBits - 1 : 0] tb_burst_t; - typedef bit [pChIdBits - 1 : 0] tb_chid_t; - typedef bit [pDataBits - 1 : 0] tb_data_t; - typedef bit [pDatamBits - 1 : 0] tb_datam_t; - - // - // ram test parameters for correctness test - // - - localparam int cColaMaxValue = 2**pColaBits; - localparam int cRowaMaxValue = 2**pRowaBits; - localparam int cBaMaxValue = 2**pBaBits; - localparam int cBurstMaxValue = 2**pBurstBits; - - // - // number of transactions in random correctness test - // - - localparam int cTransactionMaxValue = cColaMaxValue*cBaMaxValue*cRowaMaxValue; - - // - // time interval for bandwidth measure for each bandwidth measure mode - // - - const time cPerfomanceInterval = 200us;//10ms; - - // - // number of transaction for done log message - // - - const int cTransactionLogPeriod = 1024; - - // - // bandwidth measure modes - // - - typedef struct packed { - bit read_mode; - bit write_mode; - } test_mode_t; // used tests : 1 - write, 2 - read, 3 write -> read; - - int burst_mode [$] = '{1, 2, 3, 4, 5}; - int address_mode [$] = '{0, 1, 2, 3, 4, 5}; - test_mode_t test_mode [$] = '{1, 2, 3} ; - - const string test_mode_name [4] = '{ - 0 : "error mode", - 1 : "sequental write", - 2 : "sequental read", - 3 : "sequental write -> read" - }; - - const string burst_mode_name [7] = '{ - 0 : "burst mode : {any, no cola allign}", - 1 : "burst mode : {fixed == 1, cola allign}", - 2 : "burst mode : {fixed == 2, cola allign}", - 3 : "burst mode : {fixed == 4, cola allign}", - 4 : "burst mode : {fixed == 8, cola allign}", - 5 : "burst mode : {fixed == 16, cola allign}", - 6 : "burst mode : {any inside [1,2, 4,8,16], cola allign}" - }; - - const string address_mode_name [8] = '{ - 0 : "address mode : {same bank : same row}", - 1 : "address mode : {same bank : any row}", - 2 : "address mode : {any bank : same row}", - 3 : "address mode : {linear bank : same row}", - 4 : "address mode : {any bank : any row}", - 5 : "address mode : {linear bank : any row}", - 6 : "address mode : {any bank : any row : ba varies more often than rowa}", - 7 : "address mode : {any bank : any row : ba varies less often than rowa}" - }; - - // - // virtual transaction tread types & parameters - // - - localparam int cTreadMaxNumber = cBaMaxValue*cRowaMaxValue; - localparam int cTreadPointerWidth = clogb2(cTreadMaxNumber); - - typedef bit [cTreadPointerWidth-1:0] sdram_tread_ptr_t; - - typedef struct { - ba_t ba; - rowa_t rowa; - cola_t cola; - } sdram_tread_state_s_t; - - // - // sdram transaction types - // - - typedef enum {cTR_WRITE, cTR_READ, cTR_REFR, - cTR_WRITE_LOCKED, cTR_READ_LOCKED, cTR_REFR_LOCKED - } tr_type_e_t; - - // - // transaction acknowledge mailbox. use only for locked transaction - // - - typedef mailbox #(tr_type_e_t) sdram_tr_ack_mbx; - - // - // - // - -`endif

trunk/include/tb_define.svh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/include/hssdrc_tb_sys_if.vh =================================================================== --- trunk/include/hssdrc_tb_sys_if.vh (revision 2) +++ trunk/include/hssdrc_tb_sys_if.vh (nonexistent) @@ -1,99 +0,0 @@ -// -// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline -// -// Project Nick : HSSDRC -// -// Version : 1.0-beta -// -// Revision : $Revision: 1.1 $ -// -// Date : $Date: 2008-03-06 13:51:55 $ -// -// Workfile : hssdrc_tb_sys_if.vh -// -// Description : system interface to memory controller -// -// HSSDRC is licensed under MIT License -// -// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of -// this software and associated documentation files (the "Software"), to deal in -// the Software without restriction, including without limitation the rights to -// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -// the Software, and to permit persons to whom the Software is furnished to do so, -// subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all -// copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -// - - -`include "hssdrc_define.vh" - -`ifndef __HSSDRC_TB_SYS_IF_VH__ - - `define __HSSDRC_TB_SYS_IF_VH__ - - interface hssdrc_tb_sys_if (clk, reset, sclr); - input wire clk ; - input wire reset; - input wire sclr ; - // - logic write; - logic read; - logic refr; - rowa_t rowa; - cola_t cola; - ba_t ba; - burst_t burst; - chid_t chid_i; - data_t wdata; - datam_t wdatam; - // - logic ready; - logic use_wdata; - logic vld_rdata; - chid_t chid_o; - data_t rdata; - // - modport master ( output rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam, - input ready, use_wdata, vld_rdata, chid_o, rdata); - modport slave ( input rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam, - output ready, use_wdata, vld_rdata, chid_o, rdata); - // synthesis translate_off - clocking cb @(posedge clk); - default input #1ns output #1ns; - output rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam; - input ready, use_wdata, vld_rdata, chid_o, rdata; - endclocking - // - modport tb (input clk, reset, sclr, clocking cb); - // - wire [2:0] cmd_vect = {write, read, refr}; - wire sys_reset = reset | sclr; - // - property cmd_onehot; - @(cb) disable iff (sys_reset) (cmd_vect != 0) |-> $onehot(cmd_vect); - endproperty - // - property rst_output(logic signal); - @(cb) (sys_reset) |-> not (signal); - endproperty - // - assert property (cmd_onehot) else $error ("command overlaped violation error"); - assert property (rst_output(ready)) else $error ("hssdc reaady output reset violation error"); - assert property (rst_output(use_wdata)) else $error ("hssdc use_wdata output reset violation error"); - assert property (rst_output(vld_rdata)) else $error ("hssdc vld_rdata output reset violation error"); - // synthesis translate_on - - endinterface - -`endif

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trunk/doc/hssdrc_design_document_rev10.odt Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/doc/hssdrc_design_document.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/hssdrc_design_document.pdf =================================================================== --- trunk/doc/hssdrc_design_document.pdf (revision 2) +++ trunk/doc/hssdrc_design_document.pdf (nonexistent)

trunk/doc/hssdrc_design_document.pdf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sim/compile.do =================================================================== --- trunk/sim/compile.do (revision 2) +++ trunk/sim/compile.do (nonexistent) @@ -1,59 +0,0 @@ - -set need_quit 1 -set need_del 1 - -set debug 1 - -if {$debug} { - set opt novopt -} else { - set opt O4 -} -# -#set used project dir -# -set prjdir E:/work_des00/Project/prj_10_hssdrc - -set coredir $prjdir/core -set rtldir $prjdir/rtl -set tbdir $prjdir/testbench -set incdir $prjdir/include - -if {$need_del} { - vdel -all work -} - -vlib work -# core codes -vlog $coredir/mt48lc2m32b2.v -# headers codes -# rtl codes -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_data_path.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_data_path_p1.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_addr_path.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_addr_path_p1.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_mux.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_init_state.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_arbiter_out.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_access_manager.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_decoder_state.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_decoder.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_ba_map.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_arbiter_in.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_refr_counter.v -vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_top.v - -# tb codes -vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/sdram_interpretator.sv - -vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/tb_prog.sv -vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/tb_top.sv - -if {$need_quit} { - quit -} - - - - -

trunk/sim/compile.do Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/sim.do =================================================================== --- trunk/sim/sim.do (revision 2) +++ trunk/sim/sim.do (nonexistent) @@ -1,133 +0,0 @@ - -onbreak {resume} - -proc r {} { - restart -force -all -} - -transcript file "" - -set debug 1 - -if {$debug} { - set seed [clock seconds] -} else { - set seed [clock seconds] -} - -#transcript file transcript - -if {$debug} { -vsim -novopt -sv_seed $seed -wlf hssdrc_work.wlf work.tb_top - -onerror {resume} -quietly WaveActivateNextPane {} 0 - -radix hexadecimal - -add wave -noupdate -divider system -add wave -noupdate -format Logic /tb_top/clk -add wave -noupdate -format Logic /tb_top/reset -add wave -noupdate -format Logic /tb_top/sclr - -add wave -noupdate -divider sys_if_req_resp -add wave -noupdate -format Logic /tb_top/sys_write -add wave -noupdate -format Logic /tb_top/sys_read -add wave -noupdate -format Logic /tb_top/sys_refr -add wave -noupdate -format Logic /tb_top/sys_ready - -add wave -noupdate -divider sys_if_req_data -add wave -noupdate -format Literal /tb_top/sys_rowa -add wave -noupdate -format Literal /tb_top/sys_cola -add wave -noupdate -format Literal /tb_top/sys_ba -add wave -noupdate -format Literal /tb_top/sys_burst -add wave -noupdate -format Literal /tb_top/sys_chid_i - -add wave -noupdate -divider sys_if_data -add wave -noupdate -format Literal /tb_top/sys_wdata -add wave -noupdate -format Literal /tb_top/sys_wdatam -add wave -noupdate -format Logic /tb_top/sys_use_wdata - -add wave -noupdate -format Logic /tb_top/sys_chid_o -add wave -noupdate -format Literal /tb_top/sys_rdata -add wave -noupdate -format Logic /tb_top/sys_vld_rdata - -add wave -noupdate -divider sdram_if -add wave -noupdate -format Logic /tb_top/nclk -add wave -noupdate -format Literal /tb_top/inter/cmd_e -add wave -noupdate -format Literal /tb_top/dq -add wave -noupdate -format Literal /tb_top/dqm -add wave -noupdate -format Literal /tb_top/addr -add wave -noupdate -format Literal /tb_top/ba -add wave -noupdate -format Logic /tb_top/cs_n -add wave -noupdate -format Logic /tb_top/ras_n -add wave -noupdate -format Logic /tb_top/cas_n -add wave -noupdate -format Logic /tb_top/we_n - -add wave -noupdate -divider am -add wave -noupdate -format Logic /tb_top/top/access_manager/am_pre_all_enable -add wave -noupdate -format Logic /tb_top/top/access_manager/am_refr_enable -add wave -noupdate -format Literal /tb_top/top/access_manager/am_pre_enable -add wave -noupdate -format Literal /tb_top/top/access_manager/am_act_enable -add wave -noupdate -format Literal /tb_top/top/access_manager/am_read_enable -add wave -noupdate -format Literal /tb_top/top/access_manager/am_write_enable - -add wave -noupdate -divider mux -add wave -noupdate -format Logic /tb_top/top/mux/mux_pre_all -add wave -noupdate -format Logic /tb_top/top/mux/mux_refr -add wave -noupdate -format Logic /tb_top/top/mux/mux_pre -add wave -noupdate -format Logic /tb_top/top/mux/mux_act -add wave -noupdate -format Logic /tb_top/top/mux/mux_read -add wave -noupdate -format Logic /tb_top/top/mux/mux_write -add wave -noupdate -format Logic /tb_top/top/mux/mux_lmr -add wave -noupdate -format Literal /tb_top/top/mux/mux_burst - -add wave -noupdate -divider state -add wave -noupdate -format Literal /tb_top/top/decoder/state0/state -add wave -noupdate -format Literal /tb_top/top/decoder/state1/state -add wave -noupdate -format Literal /tb_top/top/decoder/state2/state - -add wave -noupdate -divider ba_map -add wave -noupdate -format Logic /tb_top/top/ba_map/update -add wave -noupdate -format Logic /tb_top/top/ba_map/clear -add wave -noupdate -format Literal /tb_top/top/ba_map/ba -add wave -noupdate -format Literal /tb_top/top/ba_map/rowa -add wave -noupdate -format Logic /tb_top/top/ba_map/pre_act_rw -add wave -noupdate -format Logic /tb_top/top/ba_map/act_rw -add wave -noupdate -format Logic /tb_top/top/ba_map/rw -add wave -noupdate -format Logic /tb_top/top/ba_map/all_close - -add wave -noupdate -divider init_state -add wave -noupdate -format Logic /tb_top/top/init_state/init_done - -add wave -noupdate -divider refr_cnt -add wave -noupdate -format Logic /tb_top/top/refr_cnt/ack -add wave -noupdate -format Logic /tb_top/top/refr_cnt/hi_req -add wave -noupdate -format Logic /tb_top/top/refr_cnt/low_req - - - -TreeUpdate [SetDefaultTree] -configure wave -namecolwidth 203 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {1000 ps} - -log -r /* - -} else { - vsim -sv_seed $seed work.tb_top - run -all - quit -} -

trunk/sim/sim.do Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/core/test.v =================================================================== --- trunk/core/test.v (revision 2) +++ trunk/core/test.v (nonexistent) @@ -1,367 +0,0 @@ -// Testbench for Micron SDR SDRAM Verilog models - -`timescale 1ns / 1ps - -module test; - -reg [31 : 0] dq; // SDRAM I/O -reg [10 : 0] addr; // SDRAM Address -reg [1 : 0] ba; // Bank Address -reg clk; // Clock -reg cke; // Synchronous Clock Enable -reg cs_n; // CS# -reg ras_n; // RAS# -reg cas_n; // CAS# -reg we_n; // WE# -reg [3 : 0] dqm; // I/O Mask - -wire [31 : 0] DQ = dq; - -parameter hi_z = 32'bz; // Hi-Z - -parameter tCK = 10; // Clock Period - -mt48lc2m32b2 sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm); - -initial begin - clk = 1'b0; - cke = 1'b0; - cs_n = 1'b1; - dq = hi_z; -end - -always #5 clk = ~clk; - -/* -always @ (posedge clk) begin - $strobe("at time %t clk=%b cke=%b CS#=%b RAS#=%b CAS#=%b WE#=%b dqm=%b addr=%b ba=%b DQ=%d", - $time, clk, cke, cs_n, ras_n, cas_n, we_n, dqm, addr, ba, DQ); -end -*/ - -task active; - input [1 : 0] bank; - input [10 : 0] row; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 1; - dqm = 0; - ba = bank; - addr = row; - dq = dq_in; - end -endtask - -task auto_refresh; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 0; - we_n = 1; - dqm = 0; - //ba = 0; - //addr = 0; - dq = hi_z; - end -endtask - -task burst_term; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 1; - cas_n = 1; - we_n = 0; - dqm = 0; - //ba = 0; - //addr = 0; - dq = dq_in; - end -endtask - -task load_mode_reg; - input [10 : 0] op_code; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 0; - we_n = 0; - dqm = 0; - ba = 0; - addr = op_code; - dq = hi_z; - end -endtask - -task nop; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 1; - cas_n = 1; - we_n = 1; - dqm = dqm_in; - //ba = 0; - //addr = 0; - dq = dq_in; - end -endtask - -task precharge_bank_0; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 0; - dqm = dqm_in; - ba = 0; - addr = 0; - dq = dq_in; - end -endtask - -task precharge_bank_1; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 0; - dqm = dqm_in; - ba = 1; - addr = 0; - dq = dq_in; - end -endtask - -task precharge_bank_2; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 0; - dqm = dqm_in; - ba = 2; - addr = 0; - dq = dq_in; - end -endtask - -task precharge_bank_3; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 0; - dqm = dqm_in; - ba = 3; - addr = 0; - dq = dq_in; - end -endtask - -task precharge_all_bank; - input [3 : 0] dqm_in; - input [31 : 0] dq_in; - begin - cke = 1; - cs_n = 0; - ras_n = 0; - cas_n = 1; - we_n = 0; - dqm = dqm_in; - ba = 0; - addr = 1024; // A10 = 1 - dq = dq_in; - end -endtask - -task read; - input [1 : 0] bank; - input [10 : 0] column; - input [31 : 0] dq_in; - input [3 : 0] dqm_in; - begin - cke = 1; - cs_n = 0; - ras_n = 1; - cas_n = 0; - we_n = 1; - dqm = dqm_in; - ba = bank; - addr = column; - dq = dq_in; - end -endtask - -task write; - input [1 : 0] bank; - input [10 : 0] column; - input [31 : 0] dq_in; - input [3 : 0] dqm_in; - begin - cke = 1; - cs_n = 0; - ras_n = 1; - cas_n = 0; - we_n = 0; - dqm = dqm_in; - ba = bank; - addr = column; - dq = dq_in; - end -endtask - -initial begin - begin - // Initialize - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; precharge_all_bank(0, hi_z); // Precharge ALL Bank - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; auto_refresh; // Auto Refresh - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; auto_refresh; // Auto Refresh - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; load_mode_reg (50); // Load Mode: Lat = 3, BL = 4, Seq - #tCK; nop (0, hi_z); // Nop - - // Write with auto precharge to bank 0 (non-interrupt) - #tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; write (0, 1024, 100, 0); // Write : Bank = 0, Col = 0, Dqm = 0, Auto Precharge - #tCK; nop (0, 101); // Nop - #tCK; nop (0, 102); // Nop - #tCK; nop (0, 103); // Nop - #tCK; nop (0, hi_z); // Nop - - // Write with auto precharge to bank 1 (non-interrupt) - #tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; write (1, 1024, 200, 0); // Write : Bank = 1, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, 201); // Nop - #tCK; nop (0, 202); // Nop - #tCK; nop (0, 203); // Nop - #tCK; nop (0, hi_z); // Nop - - // Write with auto precharge to bank 2 (non-interrupt) - #tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; write (2, 1024, 300, 0); // Write : Bank = 2, Col = 0, Dqm = 0, Auto Precharge - #tCK; nop (0, 301); // Nop - #tCK; nop (0, 302); // Nop - #tCK; nop (0, 303); // Nop - #tCK; nop (0, hi_z); // Nop - - // Write with auto precharge to bank 3 (non-interrupt) - #tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; write (3, 1024, 400, 0); // Write : Bank = 3, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, 401); // Nop - #tCK; nop (0, 402); // Nop - #tCK; nop (0, 403); // Nop - #tCK; nop (0, hi_z); // Nop - - // Read with auto precharge to bank 0 (non-interrupt) - #tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; read (0, 1024, hi_z, 0); // Read : Bank = 0, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - - // Read with auto precharge to bank 1 (non-interrupt) - #tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; read (1, 1024, hi_z, 0); // Read : Bank = 1, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - - // Read with auto precharge to bank 2 (non-interrupt) - #tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; read (2, 1024, hi_z, 0); // Read : Bank = 2, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - - // Read with auto precharge to bank 3 (non-interrupt) - #tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0 - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; read (3, 1024, hi_z, 0); // Read : Bank = 3, Col = 0, Dqm = 0, Auto precharge - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; nop (0, hi_z); // Nop - #tCK; - end -$stop; -$finish; -end - -endmodule - -

trunk/core/test.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/core/mt48lc2m32b2.v =================================================================== --- trunk/core/mt48lc2m32b2.v (revision 2) +++ trunk/core/mt48lc2m32b2.v (nonexistent) @@ -1,1096 +0,0 @@ -/************************************************************************** -* -* File Name: MT48LC2M32B2.V -* Version: 2.1 -* Date: June 6th, 2002 -* Model: BUS Functional -* Simulator: Model Technology -* -* Dependencies: None -* -* Email: modelsupport@micron.com -* Company: Micron Technology, Inc. -* Model: MT48LC2M32B2 (512K x 32 x 4 Banks) -* -* Description: Micron 64Mb SDRAM Verilog model -* -* Limitation: - Doesn't check for 4096 cycle refresh -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* -* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY -* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY -* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR -* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. -* -* Copyright � 2001 Micron Semiconductor Products, Inc. -* All rights researved -* -* Rev Author Date Changes -* --- -------------------------- --------------------------------------- -* 2.1 SH 06/06/2002 - Typo in bank multiplex -* Micron Technology Inc. -* -* 2.0 SH 04/30/2002 - Second release -* Micron Technology Inc. -* -**************************************************************************/ - -`timescale 1ns / 1ps - -module mt48lc2m32b2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); - - parameter addr_bits = 11; - parameter data_bits = 32; - parameter col_bits = 8; - parameter mem_sizes = 524287; - - inout [data_bits - 1 : 0] Dq; - input [addr_bits - 1 : 0] Addr; - input [1 : 0] Ba; - input Clk; - input Cke; - input Cs_n; - input Ras_n; - input Cas_n; - input We_n; - input [3 : 0] Dqm; - - reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; - - reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline - reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline - reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline - reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline - reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; - - reg [addr_bits - 1 : 0] Mode_reg; - reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; - reg [col_bits - 1 : 0] Col_temp, Burst_counter; - - reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate - reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge - - reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command - reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) - reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank) - reg Read_precharge [0 : 3]; // R Auto Precharge - reg Write_precharge [0 : 3]; // W Auto Precharge - reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge - reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge - reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank - integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter - integer Count_precharge [0 : 3]; // RW Auto Precharge Counter - - reg Data_in_enable; - reg Data_out_enable; - - reg [1 : 0] Bank, Prev_bank; - reg [addr_bits - 1 : 0] Row; - reg [col_bits - 1 : 0] Col, Col_brst; - - // Internal system clock - reg CkeZ, Sys_clk; - - // Commands Decode - wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; - wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; - wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; - wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; - wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; - wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; - wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; - - // Burst Length Decode - wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; - wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; - wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; - wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; - wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; - - // CAS Latency Decode - wire Cas_latency_1 = ~Mode_reg[6] & ~Mode_reg[5] & Mode_reg[4]; - wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; - wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; - - // Write Burst Mode - wire Write_burst_mode = Mode_reg[9]; - - wire Debug = 1'b1; // Debug messages : 1 = On - wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ - - assign Dq = Dq_reg; // DQ buffer - - // Commands Operation - `define ACT 0 - `define NOP 1 - `define READ 2 - `define WRITE 3 - `define PRECH 4 - `define A_REF 5 - `define BST 6 - `define LMR 7 - - // Timing Parameters for -6 CL3 - parameter tAC = 5.5; - parameter tHZ = 5.5; - parameter tOH = 2.5; - parameter tMRD = 2.0; // 2 Clk Cycles - parameter tRAS = 42.0; - parameter tRC = 60.0; - parameter tRCD = 18.0; - parameter tRFC = 60.0; - parameter tRP = 18.0; - parameter tRRD = 12.0; - parameter tWRa = 6.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns) - parameter tWRm = 12.0; // A2 Version - Manual precharge mode (14 ns) - - // Timing Check variable - time MRD_chk; - time WR_chkm [0 : 3]; - time RFC_chk, RRD_chk; - time RC_chk0, RC_chk1, RC_chk2, RC_chk3; - time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; - time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; - time RP_chk0, RP_chk1, RP_chk2, RP_chk3; - - initial begin - Dq_reg = {data_bits{1'bz}}; - Data_in_enable = 0; Data_out_enable = 0; - Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1; - Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0; - WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0; - RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0; - RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0; - MRD_chk = 0; RFC_chk = 0; RRD_chk = 0; - RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0; - RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0; - RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; - RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; - $timeformat (-9, 1, " ns", 12); - end - - // System clock generator - always begin - @ (posedge Clk) begin - Sys_clk = CkeZ; - CkeZ = Cke; - end - @ (negedge Clk) begin - Sys_clk = 1'b0; - end - end - - always @ (posedge Sys_clk) begin - // Internal Commamd Pipelined - Command[0] = Command[1]; - Command[1] = Command[2]; - Command[2] = Command[3]; - Command[3] = `NOP; - - Col_addr[0] = Col_addr[1]; - Col_addr[1] = Col_addr[2]; - Col_addr[2] = Col_addr[3]; - Col_addr[3] = {col_bits{1'b0}}; - - Bank_addr[0] = Bank_addr[1]; - Bank_addr[1] = Bank_addr[2]; - Bank_addr[2] = Bank_addr[3]; - Bank_addr[3] = 2'b0; - - Bank_precharge[0] = Bank_precharge[1]; - Bank_precharge[1] = Bank_precharge[2]; - Bank_precharge[2] = Bank_precharge[3]; - Bank_precharge[3] = 2'b0; - - A10_precharge[0] = A10_precharge[1]; - A10_precharge[1] = A10_precharge[2]; - A10_precharge[2] = A10_precharge[3]; - A10_precharge[3] = 1'b0; - - // Dqm pipeline for Read - Dqm_reg0 = Dqm_reg1; - Dqm_reg1 = Dqm; - - // Read or Write with Auto Precharge Counter - if (Auto_precharge[0] === 1'b1) begin - Count_precharge[0] = Count_precharge[0] + 1; - end - if (Auto_precharge[1] === 1'b1) begin - Count_precharge[1] = Count_precharge[1] + 1; - end - if (Auto_precharge[2] === 1'b1) begin - Count_precharge[2] = Count_precharge[2] + 1; - end - if (Auto_precharge[3] === 1'b1) begin - Count_precharge[3] = Count_precharge[3] + 1; - end - - // Read or Write Interrupt Counter - if (RW_interrupt_write[0] === 1'b1) begin - RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1; - end - if (RW_interrupt_write[1] === 1'b1) begin - RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1; - end - if (RW_interrupt_write[2] === 1'b1) begin - RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1; - end - if (RW_interrupt_write[3] === 1'b1) begin - RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1; - end - - // tMRD Counter - MRD_chk = MRD_chk + 1; - - // Auto Refresh - if (Aref_enable === 1'b1) begin - if (Debug) begin - $display ("%m : at time %t AREF : Auto Refresh", $time); - end - - // Auto Refresh to Auto Refresh - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time); - end - - // Precharge to Auto Refresh - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time); - end - - // Precharge to Refresh - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); - end - - // Load Mode Register to Auto Refresh - if (MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time); - end - - // Record Current tRFC time - RFC_chk = $time; - end - - // Load Mode Register - if (Mode_reg_enable === 1'b1) begin - // Register Mode - Mode_reg = Addr; - - // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode - if (Debug) begin - $display ("%m : at time %t LMR : Load Mode Register", $time); - // CAS Latency - case (Addr[6 : 4]) - 3'b001 : $display ("%m : CAS Latency = 1"); - 3'b010 : $display ("%m : CAS Latency = 2"); - 3'b011 : $display ("%m : CAS Latency = 3"); - default : $display ("%m : CAS Latency = Reserved"); - endcase - - // Burst Length - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Burst Length = 1"); - 3'b001 : $display ("%m : Burst Length = 2"); - 3'b010 : $display ("%m : Burst Length = 4"); - 3'b011 : $display ("%m : Burst Length = 8"); - 3'b111 : $display ("%m : Burst Length = Full"); - default : $display ("%m : Burst Length = Reserved"); - endcase - - // Burst Type - if (Addr[3] === 1'b0) begin - $display ("%m : Burst Type = Sequential"); - end else if (Addr[3] === 1'b1) begin - $display ("%m : Burst Type = Interleaved"); - end else begin - $display ("%m : Burst Type = Reserved"); - end - - // Write Burst Mode - if (Addr[9] === 1'b0) begin - $display ("%m : Write Burst Mode = Programmed Burst Length"); - end else if (Addr[9] === 1'b1) begin - $display ("%m : Write Burst Mode = Single Location Access"); - end else begin - $display ("%m : Write Burst Mode = Reserved"); - end - end - - // Precharge to Load Mode Register - if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin - $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); - end - - // Precharge to Load Mode Register - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time); - end - - // Auto Refresh to Load Mode Register - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time); - end - - // Load Mode Register to Load Mode Register - if (MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time); - end - - // Reset MRD Counter - MRD_chk = 0; - end - - // Active Block (Latch Bank Address and Row Address) - if (Active_enable === 1'b1) begin - // Activate an open bank can corrupt data - if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) || - (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin - $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time); - end - - // Activate Bank 0 - if (Ba === 2'b00 && Pc_b0 === 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk0 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time); - end - - // Precharge to Activate Bank 0 - if ($time - RP_chk0 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time); - end - - // Record variables - Act_b0 = 1'b1; - Pc_b0 = 1'b0; - B0_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk0 = $time; - RC_chk0 = $time; - RCD_chk0 = $time; - end - - if (Ba == 2'b01 && Pc_b1 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk1 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time); - end - - // Precharge to Activate Bank 1 - if ($time - RP_chk1 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time); - end - - // Record variables - Act_b1 = 1'b1; - Pc_b1 = 1'b0; - B1_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk1 = $time; - RC_chk1 = $time; - RCD_chk1 = $time; - end - - if (Ba == 2'b10 && Pc_b2 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk2 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time); - end - - // Precharge to Activate Bank 2 - if ($time - RP_chk2 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time); - end - - // Record variables - Act_b2 = 1'b1; - Pc_b2 = 1'b0; - B2_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk2 = $time; - RC_chk2 = $time; - RCD_chk2 = $time; - end - - if (Ba == 2'b11 && Pc_b3 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk3 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time); - end - - // Precharge to Activate Bank 3 - if ($time - RP_chk3 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time); - end - - // Record variables - Act_b3 = 1'b1; - Pc_b3 = 1'b0; - B3_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk3 = $time; - RC_chk3 = $time; - RCD_chk3 = $time; - end - - // Active Bank A to Active Bank B - if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin - $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); - end - - // Auto Refresh to Activate - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba); - end - - // Load Mode Register to Active - if (MRD_chk < tMRD ) begin - $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); - end - - // Record variables for checking violation - RRD_chk = $time; - Prev_bank = Ba; - end - - // Precharge Block - if (Prech_enable == 1'b1) begin - // Load Mode Register to Precharge - if ($time - MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time); - end - - // Precharge Bank 0 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin - Act_b0 = 1'b0; - Pc_b0 = 1'b1; - RP_chk0 = $time; - - // Activate to Precharge - if ($time - RAS_chk0 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[0] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 1 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin - Act_b1 = 1'b0; - Pc_b1 = 1'b1; - RP_chk1 = $time; - - // Activate to Precharge - if ($time - RAS_chk1 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[1] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 2 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin - Act_b2 = 1'b0; - Pc_b2 = 1'b1; - RP_chk2 = $time; - - // Activate to Precharge - if ($time - RAS_chk2 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[2] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 3 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin - Act_b3 = 1'b0; - Pc_b3 = 1'b1; - RP_chk3 = $time; - - // Activate to Precharge - if ($time - RAS_chk3 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[3] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Terminate a Write Immediately (if same bank or all banks) - if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin - Data_in_enable = 1'b0; - end - - // Precharge Command Pipeline for Read - if (Cas_latency_3 === 1'b1) begin - Command[2] = `PRECH; - Bank_precharge[2] = Ba; - A10_precharge[2] = Addr[10]; - end else if (Cas_latency_2 === 1'b1) begin - Command[1] = `PRECH; - Bank_precharge[1] = Ba; - A10_precharge[1] = Addr[10]; - end else if (Cas_latency_1 === 1'b1) begin - Command[0] = `PRECH; - Bank_precharge[0] = Ba; - A10_precharge[0] = Addr[10]; - end - end - - // Burst terminate - if (Burst_term === 1'b1) begin - // Terminate a Write Immediately - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - end - - // Terminate a Read Depend on CAS Latency - if (Cas_latency_3 === 1'b1) begin - Command[2] = `BST; - end else if (Cas_latency_2 == 1'b1) begin - Command[1] = `BST; - end else if (Cas_latency_1 == 1'b1) begin - Command[0] = `BST; - end - - // Display debug message - if (Debug) begin - $display ("%m : at time %t BST : Burst Terminate",$time); - end - end - - // Read, Write, Column Latch - if (Read_enable === 1'b1) begin - // Check to see if bank is open (ACT) - if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || - (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin - $display("%m : at time %t ERROR: Bank is not Activated for Read", $time); - end - - // Activate to Read or Write - if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || - (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || - (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || - (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin - $display("%m : at time %t ERROR: tRCD violation during Read", $time); - end - - // CAS Latency pipeline - if (Cas_latency_3 == 1'b1) begin - Command[2] = `READ; - Col_addr[2] = Addr; - Bank_addr[2] = Ba; - end else if (Cas_latency_2 == 1'b1) begin - Command[1] = `READ; - Col_addr[1] = Addr; - Bank_addr[1] = Ba; - end else if (Cas_latency_1 == 1'b1) begin - Command[0] = `READ; - Col_addr[0] = Addr; - Bank_addr[0] = Ba; - end - - // Read interrupt Write (terminate Write immediately) - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - - // Interrupting a Write with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_write[RW_interrupt_bank] = 1'b1; - RW_interrupt_counter[RW_interrupt_bank] = 0; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time); - end - end - end - - // Read with Auto Precharge - if (Addr[10] == 1'b1) begin - Auto_precharge[Ba] = 1'b1; - Count_precharge[Ba] = 0; - RW_interrupt_bank = Ba; - Read_precharge[Ba] = 1'b1; - end - end - - // Write Command - if (Write_enable == 1'b1) begin - // Activate to Write - if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || - (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin - $display("%m : at time %t ERROR: Bank is not Activated for Write", $time); - end - - // Activate to Read or Write - if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || - (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || - (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || - (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin - $display("%m : at time %t ERROR: tRCD violation during Read", $time); - end - - // Latch Write command, Bank, and Column - Command[0] = `WRITE; - Col_addr[0] = Addr; - Bank_addr[0] = Ba; - - // Write interrupt Write (terminate Write immediately) - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - - // Interrupting a Write with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_write[RW_interrupt_bank] = 1'b1; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); - end - end - end - - // Write interrupt Read (terminate Read immediately) - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - - // Interrupting a Read with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_read[RW_interrupt_bank] = 1'b1; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); - end - end - end - - // Write with Auto Precharge - if (Addr[10] == 1'b1) begin - Auto_precharge[Ba] = 1'b1; - Count_precharge[Ba] = 0; - RW_interrupt_bank = Ba; - Write_precharge[Ba] = 1'b1; - end - end - - /* - Write with Auto Precharge Calculation - The device start internal precharge when: - 1. Meet minimum tRAS requirement - and 2. tWR cycle(s) after last valid data - or 3. Interrupt by a Read or Write (with or without Auto Precharge) - - Note: Model is starting the internal precharge 1 cycle after they meet all the - requirement but tRP will be compensate for the time after the 1 cycle. - */ - if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin - if ((($time - RAS_chk0 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || - (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3 - Auto_precharge[0] = 1'b0; - Write_precharge[0] = 1'b0; - RW_interrupt_write[0] = 1'b0; - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); - end - end - end - if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin - if ((($time - RAS_chk1 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || - (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3 - Auto_precharge[1] = 1'b0; - Write_precharge[1] = 1'b0; - RW_interrupt_write[1] = 1'b0; - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); - end - end - end - if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin - if ((($time - RAS_chk2 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || - (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3 - Auto_precharge[2] = 1'b0; - Write_precharge[2] = 1'b0; - RW_interrupt_write[2] = 1'b0; - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); - end - end - end - if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin - if ((($time - RAS_chk3 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || - (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3 - Auto_precharge[3] = 1'b0; - Write_precharge[3] = 1'b0; - RW_interrupt_write[3] = 1'b0; - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); - end - end - end - - // Read with Auto Precharge Calculation - // The device start internal precharge: - // 1. Meet minimum tRAS requirement - // and 2. CAS Latency - 1 cycles before last burst - // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) - if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin - if ((($time - RAS_chk0 >= tRAS) && // Case 1 - ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || - (RW_interrupt_read[0] == 1'b1)) begin // Case 3 - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $time; - Auto_precharge[0] = 1'b0; - Read_precharge[0] = 1'b0; - RW_interrupt_read[0] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); - end - end - end - if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin - if ((($time - RAS_chk1 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || - (RW_interrupt_read[1] == 1'b1)) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time; - Auto_precharge[1] = 1'b0; - Read_precharge[1] = 1'b0; - RW_interrupt_read[1] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); - end - end - end - if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin - if ((($time - RAS_chk2 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || - (RW_interrupt_read[2] == 1'b1)) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time; - Auto_precharge[2] = 1'b0; - Read_precharge[2] = 1'b0; - RW_interrupt_read[2] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); - end - end - end - if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin - if ((($time - RAS_chk3 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || - (RW_interrupt_read[3] == 1'b1)) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time; - Auto_precharge[3] = 1'b0; - Read_precharge[3] = 1'b0; - RW_interrupt_read[3] = 1'b0; - if (Debug) begin - $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); - end - end - end - - // Internal Precharge or Bst - if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks - if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - end - end - end else if (Command[0] == `BST) begin // BST terminate a read to current bank - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - end - end - - if (Data_out_enable == 1'b0) begin - Dq_reg <= #tOH {data_bits{1'bz}}; - end - - // Detect Read or Write command - if (Command[0] == `READ) begin - Bank = Bank_addr[0]; - Col = Col_addr[0]; - Col_brst = Col_addr[0]; - case (Bank_addr[0]) - 2'b00 : Row = B0_row_addr; - 2'b01 : Row = B1_row_addr; - 2'b10 : Row = B2_row_addr; - 2'b11 : Row = B3_row_addr; - endcase - Burst_counter = 0; - Data_in_enable = 1'b0; - Data_out_enable = 1'b1; - end else if (Command[0] == `WRITE) begin - Bank = Bank_addr[0]; - Col = Col_addr[0]; - Col_brst = Col_addr[0]; - case (Bank_addr[0]) - 2'b00 : Row = B0_row_addr; - 2'b01 : Row = B1_row_addr; - 2'b10 : Row = B2_row_addr; - 2'b11 : Row = B3_row_addr; - endcase - Burst_counter = 0; - Data_in_enable = 1'b1; - Data_out_enable = 1'b0; - end - - // DQ buffer (Driver/Receiver) - if (Data_in_enable == 1'b1) begin // Writing Data to Memory - // Array buffer - case (Bank) - 2'b00 : Dq_dqm = Bank0 [{Row, Col}]; - 2'b01 : Dq_dqm = Bank1 [{Row, Col}]; - 2'b10 : Dq_dqm = Bank2 [{Row, Col}]; - 2'b11 : Dq_dqm = Bank3 [{Row, Col}]; - endcase - - // Dqm operation - if (Dqm[0] == 1'b0) begin - Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; - end - if (Dqm[1] == 1'b0) begin - Dq_dqm [15 : 8] = Dq [15 : 8]; - end - if (Dqm[2] == 1'b0) begin - Dq_dqm [23 : 16] = Dq [23 : 16]; - end - if (Dqm[3] == 1'b0) begin - Dq_dqm [31 : 24] = Dq [31 : 24]; - end - - // Write to memory - case (Bank) - 2'b00 : Bank0 [{Row, Col}] = Dq_dqm; - 2'b01 : Bank1 [{Row, Col}] = Dq_dqm; - 2'b10 : Bank2 [{Row, Col}] = Dq_dqm; - 2'b11 : Bank3 [{Row, Col}] = Dq_dqm; - endcase - - // Display debug message - if (Dqm !== 4'b1111) begin - // Record tWR for manual precharge - WR_chkm [Bank] = $time; - - if (Debug) begin - $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %h", $time, Bank, Row, Col, Dq_dqm); - end - end else begin - if (Debug) begin - $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); - end - end - - // Advance burst counter subroutine - #tHZ Burst_decode; - - end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory - // Array buffer - case (Bank) - 2'b00 : Dq_dqm = Bank0[{Row, Col}]; - 2'b01 : Dq_dqm = Bank1[{Row, Col}]; - 2'b10 : Dq_dqm = Bank2[{Row, Col}]; - 2'b11 : Dq_dqm = Bank3[{Row, Col}]; - endcase - - // Dqm operation - if (Dqm_reg0 [0] == 1'b1) begin - Dq_dqm [ 7 : 0] = 8'bz; - end - if (Dqm_reg0 [1] == 1'b1) begin - Dq_dqm [15 : 8] = 8'bz; - end - if (Dqm_reg0 [2] == 1'b1) begin - Dq_dqm [23 : 16] = 8'bz; - end - if (Dqm_reg0 [3] == 1'b1) begin - Dq_dqm [31 : 24] = 8'bz; - end - - // Display debug message - if (Dqm_reg0 !== 4'b1111) begin - Dq_reg = #tAC Dq_dqm; - if (Debug) begin - $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %h", $time, Bank, Row, Col, Dq_reg); - end - end else begin - Dq_reg = #tHZ {data_bits{1'bz}}; - if (Debug) begin - $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); - end - end - - // Advance burst counter subroutine - Burst_decode; - end - end - - // Burst counter decode - task Burst_decode; - begin - // Advance Burst Counter - Burst_counter = Burst_counter + 1; - - // Burst Type - if (Mode_reg[3] == 1'b0) begin // Sequential Burst - Col_temp = Col + 1; - end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst - Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; - Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; - Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; - end - - // Burst Length - if (Burst_length_2) begin // Burst Length = 2 - Col [0] = Col_temp [0]; - end else if (Burst_length_4) begin // Burst Length = 4 - Col [1 : 0] = Col_temp [1 : 0]; - end else if (Burst_length_8) begin // Burst Length = 8 - Col [2 : 0] = Col_temp [2 : 0]; - end else begin // Burst Length = FULL - Col = Col_temp; - end - - // Burst Read Single Write - if (Write_burst_mode == 1'b1) begin - Data_in_enable = 1'b0; - end - - // Data Counter - if (Burst_length_1 == 1'b1) begin - if (Burst_counter >= 1) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_2 == 1'b1) begin - if (Burst_counter >= 2) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_4 == 1'b1) begin - if (Burst_counter >= 4) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_8 == 1'b1) begin - if (Burst_counter >= 8) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end - end - endtask - - // Timing Parameters for -6 CL3 - specify - specparam - tAH = 1.0, // Addr, Ba Hold Time - tAS = 1.5, // Addr, Ba Setup Time - tCH = 2.5, // Clock High-Level Width - tCL = 2.5, // Clock Low-Level Width - tCK = 6.0, // Clock Cycle Time - tDH = 1.0, // Data-in Hold Time - tDS = 1.5, // Data-in Setup Time - tCKH = 1.0, // CKE Hold Time - tCKS = 1.5, // CKE Setup Time - tCMH = 1.0, // CS#, RAS#, CAS#, WE#, DQM# Hold Time - tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time - $width (posedge Clk, tCH); - $width (negedge Clk, tCL); - $period (negedge Clk, tCK); - $period (posedge Clk, tCK); - $setuphold(posedge Clk, Cke, tCKS, tCKH); - $setuphold(posedge Clk, Cs_n, tCMS, tCMH); - $setuphold(posedge Clk, Cas_n, tCMS, tCMH); - $setuphold(posedge Clk, Ras_n, tCMS, tCMH); - $setuphold(posedge Clk, We_n, tCMS, tCMH); - $setuphold(posedge Clk, Addr, tAS, tAH); - $setuphold(posedge Clk, Ba, tAS, tAH); - $setuphold(posedge Clk, Dqm, tCMS, tCMH); - $setuphold(posedge Dq_chk, Dq, tDS, tDH); - endspecify - -endmodule

trunk/core/mt48lc2m32b2.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/readme.txt =================================================================== --- trunk/readme.txt (revision 2) +++ trunk/readme.txt (nonexistent) @@ -1,8 +0,0 @@ -Logical project decsription - -core - external not under development IP cores -doc - project documentation -include - common rtl, testbench header files -rtl - rtl models of project units -sim - simulation scripts for verivication -testbench - verification enviroment for project

trunk/readme.txt Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: hssdrc/trunk/testbench/sdram_interpretator.sv =================================================================== --- hssdrc/trunk/testbench/sdram_interpretator.sv (nonexistent) +++ hssdrc/trunk/testbench/sdram_interpretator.sv (revision 3) @@ -0,0 +1,115 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : sdram_interpretator.sv +// +// Description : testbench only sdram command decoder +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_timescale.vh" + +module sdram_interpretator (ba, cs_n, ras_n, cas_n, we_n, a10); + + input wire [1:0] ba; + input wire cs_n; + input wire ras_n; + input wire cas_n; + input wire we_n; + input wire a10; + + enum { + nop, + act0, act1, act2, act3, + rd0, rd1, rd2, rd3, + wr0, wr1, wr2, wr3, + bt, + pre0, pre1, pre2, pre3, + prea, arefr, lmr, inop, unknown + } cmd_e; + + + always_comb begin + logic [3:0] tmp; + + tmp = {cs_n, ras_n, cas_n, we_n}; + + cmd_e = unknown; + + if (cs_n) + cmd_e = inop; + else + case (tmp) + 4'b0111 : cmd_e = nop; + 4'b0011 : begin + case (ba) + 2'd1 : cmd_e = act1; + 2'd2 : cmd_e = act2; + 2'd3 : cmd_e = act3; + default : cmd_e = act0; + endcase + end + 4'b0101 : begin + case (ba) + 2'd1 : cmd_e = rd1; + 2'd2 : cmd_e = rd2; + 2'd3 : cmd_e = rd3; + default : cmd_e = rd0; + endcase + end + 4'b0100 : begin + case (ba) + 2'd1 : cmd_e = wr1; + 2'd2 : cmd_e = wr2; + 2'd3 : cmd_e = wr3; + default : cmd_e = wr0; + endcase + end + 4'b0110 : cmd_e = bt; + 4'b0010 : + if (a10) cmd_e = prea; + else begin + case (ba) + 2'd1 : cmd_e = pre1; + 2'd2 : cmd_e = pre2; + 2'd3 : cmd_e = pre3; + default : cmd_e = pre0; + endcase + end + 4'b0001 : cmd_e = arefr; + 4'b0000 : cmd_e = lmr; + default : cmd_e = unknown; + endcase + end + +endmodule

hssdrc/trunk/testbench/sdram_interpretator.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/message_class.sv =================================================================== --- hssdrc/trunk/testbench/message_class.sv (nonexistent) +++ hssdrc/trunk/testbench/message_class.sv (revision 3) @@ -0,0 +1,106 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : message_class.sv +// +// Description : simple message service class +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`ifndef __MESSAGE_CLASS__ + + `define __MESSAGE_CLASS__ + + class message_class; + + static int fp; + + static int err_cnt; + + // + // + // + + function new (string file_name = ""); + if (file_name.len() != 0) + fp = $fopen(file_name, "w"); + else + fp = 0; + endfunction + + // + // + // + + function void stop(); + $fclose(fp); + endfunction + + // + // + // + + function void note (string str); + string io_str; + + io_str = $psprintf("**NOTE** at %0t : ", $time); + + io_str = {io_str, str}; + + $display (io_str); + if (fp) + $fdisplay (fp, io_str); + endfunction + + // + // + // + + function void err (string str); + string io_str; + + err_cnt++; + + io_str = $psprintf("**ERROR** at %0t : ", $time); + + io_str = {io_str, str}; + + $display (io_str); + if (fp) + $fdisplay (fp, io_str); + + endfunction + + endclass + +`endif

hssdrc/trunk/testbench/message_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/sdram_agent_class.sv =================================================================== --- hssdrc/trunk/testbench/sdram_agent_class.sv (nonexistent) +++ hssdrc/trunk/testbench/sdram_agent_class.sv (revision 3) @@ -0,0 +1,173 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : sdram_agent_class.sv +// +// Description : agent for connect with hssdrc controller via driver +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "tb_define.svh" +`include "sdram_transaction_class.sv" + +class sdram_agent_class; + + // to hssdrc_driver + sdram_tr_mbx in_mbx; + + // input transaction + sdram_tr_mbx write_tr_mbx; + sdram_tr_mbx read_tr_mbx; + + // tb syncronization : transaction done numbers + int write_tr_done_num; + int read_tr_done_num; + + // acknowledge from driver + sdram_tr_ack_mbx done_mbx; + + // + // + // + + function new (sdram_tr_mbx in_mbx, sdram_tr_ack_mbx done_mbx, sdram_tr_mbx write_tr_mbx, read_tr_mbx); + + this.in_mbx = in_mbx; + + this.done_mbx = done_mbx; + + this.write_tr_mbx = write_tr_mbx; + this.read_tr_mbx = read_tr_mbx; + + endfunction + + // + // + // + + task SetTransaction (sdram_transaction_class tr); + tr_type_e_t ret_code; + + in_mbx.put (tr); + + case (tr.tr_type) + cTR_WRITE_LOCKED, cTR_READ_LOCKED, cTR_REFR_LOCKED : done_mbx.get (ret_code); + default : begin end + endcase + + endtask + + // + // + // + + task run_write_read (); + + fork + write_read(); + join_none + + endtask + + // + // + // + + task stop_write_read (); + disable this.run_write_read; + endtask + + // + // + // + + task write_read (); + const int sequental_tr_max_num = 6; + + int tr_num; + + int write_tr_max_num; + int read_tr_max_num; + + int avail_read_tr_num; + + sdram_transaction_class write_tr; + sdram_transaction_class read_tr; + + write_tr_done_num = 0; + read_tr_done_num = 0; + + forever begin + + // + // if there is something to write + // + assert ( std::randomize(write_tr_max_num) with {write_tr_max_num inside {[1:sequental_tr_max_num]};} ) + + for (tr_num = 0; tr_num < write_tr_max_num; tr_num++) begin : write_state + + if (!write_tr_mbx.try_get (write_tr)) + break; + + SetTransaction (write_tr); + + write_tr_done_num++; + end : write_state + + // + // read + // + + assert ( std::randomize(read_tr_max_num) with {read_tr_max_num inside {[1:sequental_tr_max_num]};} ); + + avail_read_tr_num = write_tr_done_num - read_tr_done_num; + + if (read_tr_max_num > avail_read_tr_num) + read_tr_max_num = avail_read_tr_num; + + for (tr_num = 0; tr_num < read_tr_max_num; tr_num++) begin : read_state + + if (!read_tr_mbx.try_get(read_tr)) + break; + + SetTransaction (read_tr); + + read_tr_done_num++; + end : read_state + + #10; + end + + endtask + +endclass

hssdrc/trunk/testbench/sdram_agent_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/sdram_tread_class.sv =================================================================== --- hssdrc/trunk/testbench/sdram_tread_class.sv (nonexistent) +++ hssdrc/trunk/testbench/sdram_tread_class.sv (revision 3) @@ -0,0 +1,105 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : sdram_tread_class.sv +// +// Description : virtual sdram treads using for sdram chip testing +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + + +`include "tb_define.svh" + +`ifndef __SDRAM_TREAD_CLASS_SV__ + + `define __SDRAM_TREAD_CLASS_SV__ + + class sdram_tread_class; + + sdram_tread_state_s_t active_tread_state [sdram_tread_ptr_t]; + + rand sdram_tread_ptr_t curr_tread_num; // no need to constrant + + sdram_tread_ptr_t disable_tread_num [$]; + + constraint select_tread { !(curr_tread_num inside {disable_tread_num}); } + + // + // + // + + function void Init () ; + int tread_num = 0; + const int shift = clogb2(cBaMaxValue); + sdram_tread_state_s_t tread_state; + + if (active_tread_state.num != 0) + active_tread_state.delete; + + if (disable_tread_num.size != 0) + disable_tread_num = {}; + + for (int rowa = 0; rowa < cRowaMaxValue; rowa++) begin + for (int ba = 0; ba < cBaMaxValue; ba++) begin + + tread_num = (rowa << shift) + ba; + + tread_state = '{ba : ba, rowa : rowa, cola : 0}; + + active_tread_state[tread_num] = tread_state; + + end + end + + endfunction + + // + // + // + + function burst_t GetBurst (input sdram_tread_state_s_t tread_state); + + int max_burst; + + max_burst = cColaMaxValue - tread_state.cola; + + if (max_burst > cBurstMaxValue) max_burst = 16; + + assert (std::randomize(GetBurst) with {GetBurst inside {[1:max_burst]};}) + else $error ("burst generate error : max burst = %0d burst = %0d", max_burst, GetBurst ); + + endfunction + + endclass + +`endif

hssdrc/trunk/testbench/sdram_tread_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/tb_prog.sv =================================================================== --- hssdrc/trunk/testbench/tb_prog.sv (nonexistent) +++ hssdrc/trunk/testbench/tb_prog.sv (revision 3) @@ -0,0 +1,538 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : tb_prog.sv +// +// Description : testbench program for all cases +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_timescale.vh" +`include "hssdrc_define.vh" +`include "hssdrc_timing.vh" +`include "tb_define.svh" + +`include "message_class.sv" + +`include "hssdrc_driver_class.sv" +`include "hssrdc_bandwidth_monitor_class.sv" +`include "hssrdc_scoreboard_class.sv" + +`include "sdram_transaction_class.sv" + +`include "sdram_tread_class.sv" +`include "sdram_agent_class.sv" + +program tb_prog (interface sys_if); + + // agent <-> driver mailbox + sdram_tr_mbx agent2drv_mbx; + sdram_tr_ack_mbx drv2agent_mbx; + + // message service + message_class msg; + + // test program -> agent mailbox + sdram_tr_mbx agent_write_mbx; + sdram_tr_mbx agent_read_mbx; + + // transaction agent class + sdram_agent_class agent; + + // virtual sdram treads + sdram_tread_class tread; + + // driver to uut + hssrdc_driver_class driver; + + // driver callbacks + hssdrc_bandwidth_monitor_class bandwidth_mon; + hssdrc_scoreboard_class scoreboard; + + event scoreboard_event; + event bandwidth_mon_event; + + initial begin + + agent2drv_mbx = new (8); + drv2agent_mbx = new (8); + + agent_write_mbx = new (8); + agent_read_mbx = new (8); + + // init objects + msg = new ("tb_hssdrc.log"); + + driver = new (sys_if, agent2drv_mbx, drv2agent_mbx); + + agent = new (agent2drv_mbx, drv2agent_mbx, agent_write_mbx, agent_read_mbx); + + tread = new ; + + bandwidth_mon = new (sys_if, bandwidth_mon_event); + + scoreboard = new (msg, scoreboard_event); + + driver.run(); + + agent.run_write_read (); + + // calibrate bandwidth monitor + + bandwidth_mon.count_mbps_mfactor(1000); + + // disable debug process inside sdram model + + force tb_top.sdram_chip.Debug = 0; + + wait (sys_if.reset == 1'b0); + + wait (sys_if.cb.ready == 1'b1); + + msg.note ("Program start"); + +`ifdef HSSDRC_NOT_SHARE_ACT_COMMAND + msg.note ("Controller use HSSDRC_NOT_SHARE_ACT_COMMAND macros"); +`endif + +`ifdef HSSDRC_SHARE_ONE_DECODER + msg.note ("Controller use HSSDRC_SHARE_ONE_DECODER macros"); +`endif + +`ifdef HSSDRC_SHARE_NONE_DECODER + msg.note ("Controller use HSSDRC_SHARE_NONE_DECODER macros"); +`endif + + //test(-1,-1); // simple_debug_test + //test(0,0); // linear_test + test(1,1); // random_test + //test(2,2); // bandwidth_measurement + + agent.stop_write_read(); + + driver.stop(); + + msg.stop(); + + $stop; + $finish (2); + + end + + // + // + // + + task test (input int start_task, end_task); + int task_num; + + sdram_transaction_class write_tr; + sdram_transaction_class read_tr; + + sdram_transaction_class rand_tr; + sdram_transaction_class tr; + + int err; + + int tr_burst; + tr_type_e_t tr_type; + int tr_id; + int tr_chid; + int tr_num; + + bit tread_end; + int next_cola; + + sdram_tread_state_s_t tread_state; // selected tread state + int tread_num; // selected tread num + + string log_str; + begin + + for (task_num = start_task; task_num <= end_task; task_num++) + begin + // + // Task -1 : manualy checking write/read transactions + // + if (task_num == -1) begin : simple_debug_test + + msg.note ($psprintf("test %0d : simple debug test", task_num)); + + // + // test for debug only + // + + tr = new (0, cTR_WRITE_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(3)); + tr.GetLinearPacket(); + agent.SetTransaction(tr); + + tr = new (0, cTR_WRITE_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(4)); + tr.GetLinearPacket(); + agent.SetTransaction(tr); + + tr = new (0, cTR_READ_LOCKED, .ba(0), .rowa(0), .cola(0), .burst(4), .chid(1)); + tr.GetLinearPacket(); + agent.SetTransaction(tr); + +// tr = new (0, cTR_READ, .ba(0), .rowa(1), .cola(0), .burst(2)); +// tr.GetLinearPacket(); +// agent.SetTransaction(tr); + + tr = new (0, cTR_REFR_LOCKED, .ba(0), .rowa(0)); + agent.SetTransaction(tr); + + repeat (10) @(sys_if.cb); + end : simple_debug_test + + // + // Task 0 : linear write -> read with linear data (random burst only) + // + + else if (task_num == 0) begin : linear_test + + msg.note ($psprintf("test %0d : linear write -> read with linear data", task_num)); + + // + // test for correctness. set scoreboard callbacks + // + + driver.cbs = {}; + scoreboard.start(); + driver.cbs.push_back(scoreboard); + + driver.random_delay_mode = 1; + // + // transaction generator + // + + tread.Init(); + + msg.note ($psprintf("test %0d start_task with number of treads is %0d", task_num, tread.active_tread_state.num())); + + for (tread_num = 0; tread_num < tread.active_tread_state.num(); tread_num++) begin + + // + // get tread state + // + + tread_state = tread.active_tread_state [tread_num]; + + msg.note ($psprintf("start tread %0d" , tread_num)); + + // + // full tread transaction + // + + tr_num = 0; + + do begin + // + // generate transaction + // + tr_id = tread_num; + tr_type = cTR_WRITE; + tr_burst = tread.GetBurst (tread_state); + tr_chid = tread_state.ba; + + write_tr = new (tr_id, tr_type, tread_state.ba, tread_state.rowa, tread_state.cola, tr_burst, tr_chid); + write_tr.GetLinearPacket(); + + read_tr = new write_tr; + read_tr.tr_type = cTR_READ; + // + // set transaction + // + #10; + agent_write_mbx.put (write_tr); + #10; + agent_read_mbx.put (read_tr); + // + // update tread state + // + tr_num++; + + next_cola = tread_state.cola + tr_burst; + + tread_end = (next_cola >= cColaMaxValue); + + tread_state.cola = next_cola; + + end + while (tread_end != 1); + + msg.note ($psprintf("done tread %0d. number of tread transactions %0d", tread_num, tr_num)); + + end + + // + // wait compare done + // + + do + @(scoreboard_event); + while (agent.read_tr_done_num != scoreboard.checked_tr_num); + + msg.note ($psprintf("test%0d done. Number of errors = %0d", task_num, scoreboard.check_err_num)); + + end : linear_test + + // + // Task 1 : random write -> read with random data, rowa, ba, burst, linear cola + // + + else if (task_num == 1) begin : random_test + + msg.note ($psprintf("test %0d : random write -> read with random data", task_num)); + + // + // test for correctness. set scoreboard callbacks + // + + driver.cbs = {}; + scoreboard.start(); + driver.cbs.push_back(scoreboard); + + driver.random_delay_mode = 1; + + // + // transaction generator + // + + tread.Init(); + + msg.note ($psprintf("test %0d start_task with number of treads is %0d", task_num, tread.active_tread_state.num())); + + tr_num = 0; + + do begin + + // + // select tread + // + + assert (tread.randomize()) else $error ("generate tread selection error"); + + tread_num = tread.curr_tread_num; + + tread_state = tread.active_tread_state [tread_num]; + + // + // generate transaction + // + + tr_burst = tread.GetBurst (tread_state); + tr_type = cTR_WRITE; + tr_id = tread_num; + tr_chid = tread_state.ba; + + write_tr = new (tr_id, tr_type, tread_state.ba, tread_state.rowa, tread_state.cola, tr_burst, tr_chid); + //write_tr.GetLinearPacket(); + write_tr.GetRandomPacket(); + + read_tr = new write_tr; + read_tr.tr_type = cTR_READ; + // + // set transaction + // + #10; + agent_write_mbx.put (write_tr); + #10; + agent_read_mbx.put (read_tr); + // + // update tread state + // + tr_num++; + + next_cola = tread_state.cola + tr_burst; + + tread_end = (next_cola >= cColaMaxValue); + + tread_state.cola = next_cola; + + tread.active_tread_state [tread_num] = tread_state; + // + // if tread end kill it + // + if (tread_end) begin + tread.active_tread_state.delete (tread_num); + tread.disable_tread_num.push_back (tread_num); // random pointer constrain update + msg.note ($psprintf("done tread %0d", tread_num)); + end + + if (tr_num > cTransactionMaxValue) break; + + if (tr_num % cTransactionLogPeriod == 0) + msg.note($psprintf("transaction done %0d", tr_num)); + + end + while (tread.active_tread_state.num() != 0); + + // + // wait compare done + // + + do + @(scoreboard_event); + while (agent.read_tr_done_num != scoreboard.checked_tr_num); + + msg.note ($psprintf("test%0d done. Number of errors = %0d", task_num, scoreboard.check_err_num)); + + end : random_test + + // + // Task 2 : bandwidth measurement + // + + else if (task_num == 2) begin : bandwidth_measurement + + msg.note ($psprintf("test %0d : access bandwidth measurement", task_num)); + + // + // test for perfromance. set bandwidth monitor callbacks, no random delay mode + // + + driver.cbs = {}; + driver.cbs.push_back(bandwidth_mon); + + driver.random_delay_mode = 0; + + // + // generate transactions + // + foreach ( test_mode [t] ) begin : test_mode_cycle + + msg.note ($psprintf("test %0d start %0s test mode", task_num, test_mode_name[test_mode[t]])); + + foreach (burst_mode [b]) begin : burst_cycle + + foreach (address_mode [a] ) begin : address_cycle + + time start_time; + string str; + + tr_num = 0; + start_time = $time; + + // + // init tr.generator + // + + rand_tr = new; + rand_tr.burst_random_mode = burst_mode [b]; + rand_tr.address_random_mode = address_mode [a]; + + bandwidth_mon.start(); + + do begin + + assert ( rand_tr.randomize() ) else begin + $error("test %0d : random transaction generate error", task_num); + $stop; + end + + if ( test_mode[t].write_mode) begin + write_tr = new rand_tr; + write_tr.id = tr_num++; + write_tr.tr_type = cTR_WRITE; + + agent.SetTransaction(write_tr); + end + + if ( test_mode[t].read_mode) begin + read_tr = new rand_tr; + read_tr.id = tr_num++; + read_tr.tr_type = cTR_READ; + + agent.SetTransaction(read_tr); + end + + if (tr_num % cTransactionLogPeriod == 0) + msg.note($psprintf("task %0d transaction done %0d", task_num, tr_num)); + + end + while (($time - start_time) < cPerfomanceInterval); + + // + // syncronize output for measure + // + do + @(bandwidth_mon_event); + while (tr_num != bandwidth_mon.measured_tr_num); + + // + // stop measure + // + bandwidth_mon.stop(); + + // + // logs + // + + str = $psprintf("task %0d done. %0s mode bandwith : %0s and %0s is :\n", task_num, + test_mode_name[test_mode[t]], address_mode_name [address_mode[a]], burst_mode_name [burst_mode[b]]); + + if (test_mode [t].write_mode) + str = {str, $psprintf("\t\twrite bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", + bandwidth_mon.write_bandwidth, bandwidth_mon.write_bandwidth_percent)}; + + if (test_mode [t].read_mode) + str = {str, $psprintf("\t\t read bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", + bandwidth_mon.read_bandwidth, bandwidth_mon.read_bandwidth_percent)}; + + if (test_mode [t].read_mode & test_mode [t].write_mode) + str = {str, $psprintf("\t\tram bandwidth %0f MBps, %0f %% maximum ram bandwidth\n", + bandwidth_mon.bandwidth, bandwidth_mon.bandwidth_percent)}; + + msg.note(str); + + end : address_cycle + + end : burst_cycle + + end : test_mode_cycle + + + end : bandwidth_measurement + + end + + msg.note ("all test done"); + + repeat (100) @(sys_if.cb); + end + + endtask + + + +endprogram

hssdrc/trunk/testbench/tb_prog.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/hssrdc_driver_cbs_class.sv =================================================================== --- hssdrc/trunk/testbench/hssrdc_driver_cbs_class.sv (nonexistent) +++ hssdrc/trunk/testbench/hssrdc_driver_cbs_class.sv (revision 3) @@ -0,0 +1,71 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : hssrdc_driver_cbs_class.sv +// +// Description : base class for callbacks for API driver +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "sdram_transaction_class.sv" + +`ifndef __HSSDRC_DRIVER_CBS_CLASS__ + + `define __HSSDRC_DRIVER_CBS_CLASS__ + + class hssrdc_driver_cbs_class; + + // + // callback for command part of hssdrc_driver_class + // + + virtual task post_Command(input realtime t); + endtask + + // + // callback for write part of hssdrc_driver_class + // + + virtual task post_WriteData (input realtime t, sdram_transaction_class tr); + endtask + + // + // callback for read part of hssdrc_driver_class + // + + virtual task post_ReadData (input realtime t, sdram_transaction_class tr); + endtask + + endclass + +`endif

hssdrc/trunk/testbench/hssrdc_driver_cbs_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/hssrdc_scoreboard_class.sv =================================================================== --- hssdrc/trunk/testbench/hssrdc_scoreboard_class.sv (nonexistent) +++ hssdrc/trunk/testbench/hssrdc_scoreboard_class.sv (revision 3) @@ -0,0 +1,142 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : hssrdc_scoreboard_class.sv +// +// Description : scoreboard for test read transaction +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "tb_define.svh" + +`include "message_class.sv" +`include "hssrdc_driver_cbs_class.sv" + +class hssdrc_scoreboard_class extends hssrdc_driver_cbs_class; + + sdram_tr_mbx out_mbx; + message_class msg; + + event done; + + function new (message_class msg, ref event done); + + this.msg = msg; + + this.done = done; + + endfunction + + int checked_tr_num; + int check_err_num; + + // + // + // + + task start (); + checked_tr_num = 0; + check_err_num = 0; + endtask + + // + // + // + + virtual task post_ReadData (input realtime t, sdram_transaction_class tr); + tb_data_t golden_data2cmp; + tb_data_t data2cmp; + + tb_chid_t golden_chid2cmp; + tb_chid_t chid2cmp; + + tb_datam_t datam; + + int burst; + + string str; + begin + + burst = tr.burst + 1; + + golden_chid2cmp = tr.chid; + + for (int i = 0; i < burst; i++) begin + + datam = tr.wdatam [i]; + + data2cmp = MaskData(tr.rdata [i], datam); + golden_data2cmp = MaskData(tr.wdata [i], datam); + + chid2cmp = tr.rchid [i]; + + if (data2cmp !== golden_data2cmp) begin + str = $psprintf("data compare error at ba = %0d, rowa = %0d, cola = %0d : ", tr.ba, tr.rowa, tr.cola); + str = {str, ($psprintf("write data %h : read data %h", golden_data2cmp, data2cmp))}; + msg.err(str); + + check_err_num++; + end + + if (chid2cmp !== golden_chid2cmp) begin + str = $psprintf("chid compare error at ba = %0d, rowa = %0d, cola = %0d : ", tr.ba, tr.rowa, tr.cola); + str = {str, ($psprintf("write chid %h : read chid %h", golden_chid2cmp, chid2cmp))}; + msg.err(str); + + check_err_num++; + end + + end + + checked_tr_num++; + -> done; + end + endtask + + // + // + // + + function data_t MaskData (input tb_data_t data, tb_datam_t datam); + if (datam == 0) + MaskData = data; + else begin + for (int m = 0; m < $size(datam); m++) begin + for (int b = 0; b < 8; b++) begin + MaskData[8*m + b] = data [8*m + b] & ~datam[m]; + end + end + end + endfunction + +endclass

hssdrc/trunk/testbench/hssrdc_scoreboard_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/sdram_transaction_class.sv =================================================================== --- hssdrc/trunk/testbench/sdram_transaction_class.sv (nonexistent) +++ hssdrc/trunk/testbench/sdram_transaction_class.sv (revision 3) @@ -0,0 +1,220 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : sdram_transaction_class.sv +// +// Description : sdram transaction structure +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_define.vh" +`include "tb_define.svh" + +`ifndef __SDRAM_TRANSACTION_CLASS_SV__ + +`define __SDRAM_TRANSACTION_CLASS_SV__ + + class sdram_transaction_class; + + // transaction id + int id; + // transacton type for driver + tr_type_e_t tr_type ; + // input sdram path + rand tb_ba_t ba ; + rand tb_rowa_t rowa ; + rand tb_cola_t cola ; + rand tb_burst_t burst ; + rand tb_chid_t chid ; + // input data path + rand tb_data_t wdata [0:cBurstMaxValue-1]; + tb_datam_t wdatam [0:cBurstMaxValue-1]; + // output data path + tb_data_t rdata [0:cBurstMaxValue-1]; + tb_chid_t rchid [0:cBurstMaxValue-1]; + + // random generate controls + int burst_random_mode = 0; + int address_random_mode = 0; + // used in random generate variables + tb_ba_t last_used_ba; + tb_rowa_t last_used_rowa; + + + function new (int id = 0, tr_type_e_t tr_type = cTR_WRITE, int ba = 0, rowa = 0, cola = 0, burst = 1, chid = 0); + + this.id = id; + this.tr_type = tr_type; + this.ba = ba; + this.rowa = rowa; + this.cola = cola; + this.burst = burst - 1; + this.chid = chid; + + endfunction + + // + // function to generate linear data packet + // + + function void GetLinearPacket; + data_t tmp_data; + begin + + tmp_data = {ba, rowa, this.cola}; + + for (int i = 0; i <= burst; i++) + wdata [i] = tmp_data + i + 1; + + wdatam = '{default : 0}; + end + endfunction + + // + // + // + + function void GetRandomPacket; + data_t tmp_data; + begin + + assert ( std::randomize(wdata)) else $error ("random packet generate"); + + wdatam = '{default : 0}; + + end + endfunction + + // + // randomize callback function to store transaction addres's + // + function void post_randomize(); + last_used_ba = ba; + last_used_rowa = rowa; + endfunction + + // + // constraint for use for performance measuring + // + + // burst constraint + + // mode 0 : any birst, no cola allign + + // mode 1 : fixed burst = 1, cola allign + constraint burst_constraint_1 { (burst_random_mode == 1) -> burst == 0; } + // mode 2 : fixed burst = 2, cola allign + constraint burst_constraint_2 { (burst_random_mode == 2) -> burst == 1; } + // mode 3 : fixed burst = 4, cola allign + constraint burst_constraint_3 { (burst_random_mode == 3) -> burst == 3; } + // mode 4 : fixed burst == 8, cola allign + constraint burst_constraint_4 { (burst_random_mode == 4) -> burst == 7; } + // mode 5 : fixed burst == 16, cola allign + constraint burst_constraint_5 { (burst_random_mode == 5) -> burst == 15; } + // mode 6 : max performance burst, cola allign + constraint burst_constraint_6 { (burst_random_mode == 6) -> burst inside {0, 1, 3, 7, 15}; } + + // cola constraint + constraint cola_constraint { (burst_random_mode != 0) -> + (burst == 1) -> (cola[0] == 0); + (burst == 3) -> (cola[1:0] == 0); + (burst == 7) -> (cola[2:0] == 0); + (burst == 15) -> (cola[3:0] == 0); + } + + constraint burst_order {solve burst before cola; } + + // address constraint + + // mode 0 : same bank same row + constraint address_constraint_0 { (address_random_mode == 0) -> { + (ba == last_used_ba); + (rowa == last_used_rowa); + } + } + // mode 1 : same bank + constraint address_constraint_1 { (address_random_mode == 1) -> { + (ba == last_used_ba); + (rowa != last_used_rowa); + } + } + // mode 2 : any bank same row + constraint address_constraint_2 { (address_random_mode == 2) -> { + (ba != last_used_ba); + (rowa == last_used_rowa); + } + } + // mode 3 : linear bank same row + constraint address_constraint_3 { (address_random_mode == 3) -> { + (last_used_ba == 0) -> (ba == 1); + (last_used_ba == 1) -> (ba == 2); + (last_used_ba == 2) -> (ba == 3); + (last_used_ba == 3) -> (ba == 0); + (rowa == last_used_rowa); + } + } + // mode 4 : any bank any row + constraint address_constraint_4 { (address_random_mode == 4) -> { + (ba != last_used_ba); + (rowa != last_used_rowa); + } + } + // mode 5 : linear bank any row + constraint address_constraint_5 { (address_random_mode == 5) -> { + (last_used_ba == 0) -> (ba == 1); + (last_used_ba == 1) -> (ba == 2); + (last_used_ba == 2) -> (ba == 3); + (last_used_ba == 3) -> (ba == 0); + (rowa != last_used_rowa); + } + } + // mode 6 : ba varies more often than rowa + constraint address_constraint_6 { (address_random_mode == 6) -> { + ba dist { (ba == last_used_ba) := 1, (ba != last_used_ba) :/5}; // 1/6 const ba + rowa dist { (rowa == last_used_rowa) := 5, (rowa != last_used_rowa) :/1}; // 5/6 const rowa + } + } + // mode 7 : ba varies less often than rowa + constraint address_constraint_7 { (address_random_mode == 7) -> { + ba dist { (ba == last_used_ba) := 3, (ba != last_used_ba) :/1}; // 75% const ba + rowa dist { (rowa == last_used_rowa) := 1, (rowa != last_used_rowa) :/3}; // 25% const rowa + } + } + + endclass + // + // mailbox for connet agent with driver + // + typedef mailbox #(sdram_transaction_class) sdram_tr_mbx; + +`endif

hssdrc/trunk/testbench/sdram_transaction_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/hssdrc_driver_class.sv =================================================================== --- hssdrc/trunk/testbench/hssdrc_driver_class.sv (nonexistent) +++ hssdrc/trunk/testbench/hssdrc_driver_class.sv (revision 3) @@ -0,0 +1,351 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : hssdrc_driver_class.sv +// +// Description : low level API driver for hssdrc_controller +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_tb_sys_if.vh" + +`include "hssdrc_define.vh" + +`include "tb_define.svh" + +`include "hssrdc_driver_cbs_class.sv" + +`ifndef __HSSDRC_DRIVER_SV__ + + `define __HSSDRC_DRIVER_SV__ + + class hssrdc_driver_class; + + // callback quene + hssrdc_driver_cbs_class cbs[$]; + + // mailboxes to connect with transaction agent + sdram_tr_mbx in_mbx; + + // mailbox for connect command path with data path of this driver + sdram_tr_mbx wdata_mbx; + sdram_tr_mbx rdata_mbx; + + // + virtual hssdrc_tb_sys_if sys_if; + + // acknowledge mailbox for agent. used in locked transaction only + sdram_tr_ack_mbx done_mbx; + + // feedback to tb for waiting event + event write_done; + event read_done; + + // driver work modes + bit random_delay_mode = 0; + bit debug = 0; + + // + // + // + + function new (virtual hssdrc_tb_sys_if sys_if, sdram_tr_mbx in_mbx, sdram_tr_ack_mbx done_mbx); + + this.sys_if = sys_if; + + this.in_mbx = in_mbx; + + this.done_mbx = done_mbx; + + // internal not sized mailboxes : all must be controlled via in_mbx, out_mbx size + wdata_mbx = new; + rdata_mbx = new; + + endfunction + + // + // init interface task + // + + task init; + sys_if.cb.write <= 1'b0; + sys_if.cb.read <= 1'b0; + sys_if.cb.refr <= 1'b0; + sys_if.cb.cola <= '0; + sys_if.cb.rowa <= '0; + sys_if.cb.ba <= '0; + sys_if.cb.chid_i <= '0; + sys_if.cb.burst <= '0; + sys_if.cb.wdata <= '0; + sys_if.cb.wdatam <= '0; + endtask + + // + // start driver task + // + + task run; + init (); + fork + CommandDriver (); + WriteDataDriver (); + ReadDataDriver (); + join_none; + endtask + + // + // stop driver task + // + + task stop (); + disable this.CommandDriver; + disable this.WriteDataDriver; + disable this.ReadDataDriver; + endtask + + //----------------------------------------------------------------------- + // command driver + //----------------------------------------------------------------------- + + task CommandDriver; + sdram_transaction_class tr; + + bit [4:0] delay; // max delay is 32 bit + + begin + + @(sys_if.cb); + forever begin + + // syncronize mailbox to clock + if ( !in_mbx.try_get(tr) ) begin + @(sys_if.cb); + continue; + end + + if (debug) begin + if ((tr.tr_type == cTR_READ) || (tr.tr_type == cTR_READ_LOCKED)) + $display("%0t cmd get READ transaction id = %0d", $time, tr.id); + else if ((tr.tr_type == cTR_WRITE) || (tr.tr_type == cTR_WRITE_LOCKED)) + $display("%0t cmd get WRITE transaction id = %0d", $time, tr.id); + end + + if (random_delay_mode) begin + assert (std::randomize(delay) with {delay dist {0 := 1, !0 :/ 2};}) else + $error ("random delay generate error"); + + repeat (delay) @(sys_if.cb); + end + + + // set command on interface + SetCommand(tr); + + // if need callbacks + foreach ( cbs [i] ) cbs[i].post_Command ($realtime); + + // set command for write/read drivers + case (tr.tr_type) + cTR_WRITE, cTR_WRITE_LOCKED : wdata_mbx.put (tr); + cTR_READ , cTR_READ_LOCKED : rdata_mbx.put (tr); + endcase + + // for locked transactions wait done and set acknowledge + case (tr.tr_type) + cTR_WRITE_LOCKED : begin + @(write_done); + done_mbx.put (cTR_WRITE_LOCKED); + end + cTR_READ_LOCKED : begin + @(read_done); + done_mbx.put(cTR_READ_LOCKED); + end + cTR_REFR_LOCKED : begin + done_mbx.put (cTR_WRITE_LOCKED); + end + endcase + + end + end + endtask + + // + // + // + + task SetCommand (sdram_transaction_class tr); + + case (tr.tr_type) + cTR_WRITE, cTR_WRITE_LOCKED : begin + sys_if.cb.write <= 1'b1; + sys_if.cb.read <= 1'b0; + sys_if.cb.refr <= 1'b0; + end + cTR_READ, cTR_READ_LOCKED : begin + sys_if.cb.write <= 1'b0; + sys_if.cb.read <= 1'b1; + sys_if.cb.refr <= 1'b0; + end + cTR_REFR, cTR_REFR_LOCKED : begin + sys_if.cb.write <= 1'b0; + sys_if.cb.read <= 1'b0; + sys_if.cb.refr <= 1'b1; + end + endcase + + sys_if.cb.rowa <= tr.rowa; + sys_if.cb.cola <= tr.cola; + sys_if.cb.ba <= tr.ba; + sys_if.cb.burst <= tr.burst; + sys_if.cb.chid_i <= tr.chid; + + do + @(sys_if.cb); + while (sys_if.cb.ready != 1'b1); + + sys_if.cb.write <= 1'b0; + sys_if.cb.read <= 1'b0; + sys_if.cb.refr <= 1'b0; + + endtask + + //----------------------------------------------------------------------- + // write data driver + //----------------------------------------------------------------------- + + task WriteDataDriver; + + sdram_transaction_class tr; + int num; + + begin + + forever begin + wdata_mbx.get (tr); + + if (debug) + $display("%0t write driver get transaction id = %0d", $time, tr.id); + + num = tr.burst + 1; + + // set data + for (int i = 0; i < num; i++) + SetWrData (tr.wdata [i] , tr.wdatam [i]); + + -> write_done; + + if (debug) + $display("%0t write driver done transaction id = %0d", $time, tr.id); + + foreach ( cbs[i] ) cbs[i].post_WriteData($realtime, tr); + + end + end + endtask + + // + // + // +`ifndef HSSDRC_COMBINATIVE_USE_WDATA + task SetWrData ( input data_t data, datam_t datam); + sys_if.cb.wdata <= data; + sys_if.cb.wdatam <= datam; + + do + @(sys_if.cb); + while (sys_if.cb.use_wdata != 1'b1); + endtask +`else + task SetWrData ( input data_t data, datam_t datam); + do + @(sys_if.cb); + while (sys_if.cb.use_wdata != 1'b1); + + sys_if.cb.wdata <= data; + sys_if.cb.wdatam <= datam; + endtask +`endif + //----------------------------------------------------------------------- + // read part of driver + //----------------------------------------------------------------------- + + task ReadDataDriver; + + sdram_transaction_class tr; + int num; + + begin + forever begin + rdata_mbx.get (tr); + + if (debug) + $display("%0t read driver get transaction id = %0d", $time, tr.id); + + num = tr.burst + 1; + + for (int i = 0; i < num; i++) + GetRdData (tr.rdata [i], tr.rchid [i]); + + -> read_done; + + if (debug) + $display("%0t read driver done transaction id = %0d", $time, tr.id); + + foreach ( cbs[i] ) cbs[i].post_ReadData($realtime, tr); + + end + end + endtask + + // + // + // + + task GetRdData (output data_t data, chid_t chid); + + do + @(sys_if.cb); + while (sys_if.cb.vld_rdata != 1'b1); + + data = sys_if.cb.rdata; + chid = sys_if.cb.chid_o; + + endtask + + // + // + // + + endclass + +`endif

hssdrc/trunk/testbench/hssdrc_driver_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/hssrdc_bandwidth_monitor_class.sv =================================================================== --- hssdrc/trunk/testbench/hssrdc_bandwidth_monitor_class.sv (nonexistent) +++ hssdrc/trunk/testbench/hssrdc_bandwidth_monitor_class.sv (revision 3) @@ -0,0 +1,257 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : hssrdc_bandwidth_monitor_class.sv +// +// Description : bandwidth monitor measurement class +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_define.vh" +`include "hssdrc_timing.vh" +`include "hssdrc_tb_sys_if.vh" + +`include "sdram_transaction_class.sv" +`include "hssrdc_driver_cbs_class.sv" + + +`ifndef __HSSDRC_BANDWIDTH_MONITOR_CLASS__ + + `define __HSSDRC_BANDWIDTH_MONITOR_CLASS__ + + class hssdrc_bandwidth_monitor_class extends hssrdc_driver_cbs_class; + + virtual hssdrc_tb_sys_if sys_if; + + // bandwidth measurement FSM + enum {idle, wait_start, work} state = idle; + + // timestamps + realtime end_time; + realtime start_time; + + // word transfer counters + int unsigned wr_word_num; + int unsigned rd_word_num; + + // bandwidth measurement itself + real write_bandwidth ; + real read_bandwidth ; + real bandwidth ; + + real write_bandwidth_percent ; + real read_bandwidth_percent ; + real bandwidth_percent ; + + // semaphore to controll access to variables + semaphore sem; + + // bandwidth measurement parameters + real mbps_mfactor; + real max_bandwidth; + + // tb syncronization + int measured_tr_num = 0; + event done; + + function new (virtual hssdrc_tb_sys_if sys_if, ref event done); + sem = new (1); + + this.sys_if = sys_if; + + this.done = done; + endfunction + + + // + // function to start measurement process + // + + task start(); + + sem.get (1) ; + + // set begin + state = wait_start; + + // clear all counters + end_time = 0ns; + start_time = 0ns; + + wr_word_num = 0; + rd_word_num = 0; + + measured_tr_num = 0; + + sem.put (1) ; + endtask + + // + // function to stop measurement process + // + + task stop(); + sem.get (1); + + state = idle; + count_bandwidth(); + + sem.put (1); + + endtask + + // + // callback for command part of hssdrc_driver_class + // + + task post_Command (input realtime t); + endtask + + // + // callback for write part of hssdrc_driver_class + // + + task post_WriteData (input realtime t, sdram_transaction_class tr); + int burst; + begin + + burst = tr.burst + 1; + + sem.get (1); + + if (state == wait_start) begin + start_time = t; + state = work; + end + else if (state == work) begin + wr_word_num += burst; + end_time = t; + end + + measured_tr_num++; + -> done; + + sem.put (1); + end + endtask + + // + // callback for read part of hssdrc_driver_class + // + + task post_ReadData ( input realtime t, sdram_transaction_class tr); + int burst; + begin + + burst = tr.burst + 1; + + sem.get (1); + + if (state == wait_start) begin + start_time = t; + state = work; + end + else if (state == work) begin + rd_word_num += burst; + end_time = t; + end + + measured_tr_num++; + + -> done; + + sem.put (1); + end + endtask + + // + // measurement count function bwth = mbps_mfactor*num/(end_time - start_time); + // + + function void count_bandwidth(); + realtime delta; + int unsigned wrrd_word_num; + begin + + delta = (end_time - start_time); + + wrrd_word_num = wr_word_num + rd_word_num; + + write_bandwidth = (wr_word_num/delta)*mbps_mfactor; + read_bandwidth = (rd_word_num/delta)*mbps_mfactor; + bandwidth = (wrrd_word_num/delta)*mbps_mfactor; + + write_bandwidth_percent = write_bandwidth*100.0/max_bandwidth ; + read_bandwidth_percent = read_bandwidth *100.0/max_bandwidth ; + bandwidth_percent = bandwidth *100.0/max_bandwidth ; + + end + endfunction + + // + // task to get multiplicatin factor for counters + // + + task count_mbps_mfactor (int bytes_in_kilobytes) ; + realtime delta; + realtime scale; + begin + // define current timeunit value + delta = $realtime; + #1; + delta = $realtime - delta; + + // define time scale factor + scale = 1s/delta; + + // kilobytes + mbps_mfactor = real'(scale)/(bytes_in_kilobytes); + + // megabytes + mbps_mfactor = mbps_mfactor/(bytes_in_kilobytes); + + mbps_mfactor = mbps_mfactor*pDatamBits; + + // define max bandwwidth : 1 world per cycle period + @(sys_if.cb); + delta = $realtime; + @(sys_if.cb); + delta = $realtime - delta; + + max_bandwidth = (1/delta)*mbps_mfactor; + + end + endtask + + endclass + +`endif

hssdrc/trunk/testbench/hssrdc_bandwidth_monitor_class.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/testbench/tb_top.sv =================================================================== --- hssdrc/trunk/testbench/tb_top.sv (nonexistent) +++ hssdrc/trunk/testbench/tb_top.sv (revision 3) @@ -0,0 +1,182 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:54:00 $ +// +// Workfile : tb_top.sv +// +// Description : testbench top level +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_timescale.vh" +`include "hssdrc_define.vh" +`include "hssdrc_timing.vh" +`include "hssdrc_tb_sys_if.vh" + +module tb_top; + + parameter cPeriod = 1000.0/pClkMHz; + parameter cHalfPeriod = cPeriod/2.0; + + wire [pDataBits-1:0] dq; + wire [pDatamBits-1:0] dqm; + wire [pSdramAddrBits-1 :0] addr; + wire [pBaBits-1 :0] ba; + wire cke ; + wire cs_n ; + wire ras_n ; + wire cas_n ; + wire we_n ; + + logic sys_write; + logic sys_read ; + logic sys_refr ; + rowa_t sys_rowa ; + cola_t sys_cola ; + ba_t sys_ba ; + burst_t sys_burst ; + chid_t sys_chid_i; + data_t sys_wdata ; + datam_t sys_wdatam; + logic sys_ready ; + logic sys_use_wdata ; + logic sys_vld_rdata ; + chid_t sys_chid_o ; + data_t sys_rdata ; + + + bit clk_main ; + bit clk; + bit nclk; + + bit reset ; + bit sclr ; + + hssdrc_tb_sys_if sys_if (clk, reset, sclr); + + assign sys_write = sys_if.write ; + assign sys_read = sys_if.read ; + assign sys_refr = sys_if.refr ; + assign sys_rowa = sys_if.rowa ; + assign sys_cola = sys_if.cola ; + assign sys_ba = sys_if.ba ; + assign sys_burst = sys_if.burst ; + assign sys_chid_i = sys_if.chid_i; + assign sys_wdata = sys_if.wdata ; + assign sys_wdatam = sys_if.wdatam; + + assign sys_if.ready = sys_ready ; + assign sys_if.use_wdata = sys_use_wdata ; + assign sys_if.vld_rdata = sys_vld_rdata ; + assign sys_if.chid_o = sys_chid_o ; + assign sys_if.rdata = sys_rdata ; + + + mt48lc2m32b2 sdram_chip ( + .Dq (dq ), + .Addr (addr ), + .Ba (ba ), + .Clk (nclk ), + .Cke (cke ), + .Cs_n (cs_n ), + .Ras_n (ras_n), + .Cas_n (cas_n), + .We_n (we_n ), + .Dqm (dqm ) + ); + + sdram_interpretator inter ( + .ba (ba), + .cs_n (cs_n ), + .ras_n(ras_n), + .cas_n(cas_n), + .we_n (we_n ), + .a10 (addr [10] ) + ); + + hssdrc_top top( + .clk (clk ), + .reset (reset), + .sclr (sclr ), + // + .sys_write (sys_write ), + .sys_read (sys_read ), + .sys_refr (sys_refr ), + .sys_rowa (sys_rowa ), + .sys_cola (sys_cola ), + .sys_ba (sys_ba ), + .sys_burst (sys_burst ), + .sys_chid_i (sys_chid_i ), + .sys_wdata (sys_wdata ), + .sys_wdatam (sys_wdatam ), + .sys_ready (sys_ready ), + .sys_use_wdata (sys_use_wdata), + .sys_vld_rdata (sys_vld_rdata), + .sys_chid_o (sys_chid_o ), + .sys_rdata (sys_rdata ), + // + .dq (dq ), + .dqm (dqm ), + .addr (addr ), + .ba (ba ), + .cke (cke ), + .cs_n (cs_n ), + .ras_n (ras_n), + .cas_n (cas_n), + .we_n (we_n ) + ); + + initial begin : clock_generator + clk_main = 1'b0; + #(cHalfPeriod); + forever clk_main = #(cHalfPeriod) ~clk_main; + end + + always_comb begin + clk <= clk_main; + nclk <= #2 ~clk_main; // model output buffer delay + end + + assign sclr = 1'b0; + + initial begin : reset_generator + reset = 1'b1; + + repeat (4) @(posedge clk); + @(negedge clk); + + reset = 1'b0; + end + + tb_prog prog (sys_if.tb); + +endmodule

hssdrc/trunk/testbench/tb_top.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_data_path.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_data_path.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_data_path.v (revision 3) @@ -0,0 +1,405 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_data_path.v +// +// Description : sdram data (data & mask) path unit +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_timing.vh" +`include "hssdrc_define.vh" + +module hssdrc_data_path ( + clk , + reset , + sclr , + // + sys_wdata , + sys_wdatam , + sys_use_wdata , + sys_vld_rdata , + sys_chid_o , + sys_rdata , + // + arb_read , + arb_write , + arb_chid , + arb_burst , + // + dq , + dqm + ); + + input wire clk; + input wire reset; + input wire sclr; + + //-------------------------------------------------------------------------------------------------- + // system data interface + //-------------------------------------------------------------------------------------------------- + + input data_t sys_wdata ; + input datam_t sys_wdatam ; + output logic sys_use_wdata ; + output logic sys_vld_rdata ; + output chid_t sys_chid_o ; + output data_t sys_rdata ; + + //-------------------------------------------------------------------------------------------------- + // interface from arbiter throw multiplexer + //-------------------------------------------------------------------------------------------------- + + input wire arb_read ; + input wire arb_write ; + input chid_t arb_chid ; + input sdram_burst_t arb_burst ; + + //-------------------------------------------------------------------------------------------------- + // interface sdram chip + //-------------------------------------------------------------------------------------------------- + + inout wire [pDataBits-1 :0] dq; + output logic [pDatamBits-1 :0] dqm; + + //-------------------------------------------------------------------------------------------------- + // Mask paramters count via pBL, pCL parameters only for clarify. + // unit has been designed to use fixed lengh mask patterns + //-------------------------------------------------------------------------------------------------- + localparam cWDataMask = cSdramBL - 1; // - 1 cycle for write command itself + + localparam cRDataMask = cSdramBL - 1 + pCL - 2; // - 1 cycle for read command itself, + // - 2 cycle for read dqm latency + + localparam cDataMask = max(cWDataMask, cRDataMask); + + localparam cReadAllign = pCL + 1; // + 1 is capture register cycle + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + logic [3:0] use_wdata_srl; + wire use_wdata; + wire use_wdatam; + + logic [cDataMask-1 : 0] datam_srl; + logic datam; + + + + logic [3:0] vld_rdata_srl; + logic vld_rdata; + logic vld_rdata_allign_srl [cReadAllign-1 : 0]; + + chid_t chid_srl [3:0]; + chid_t chid; + chid_t chid_allign_srl [cReadAllign-1 : 0]; + + //-------------------------------------------------------------------------------------------------- + // use write data & mask + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : use_wdata_generate + if (reset) + use_wdata_srl <= 4'b0000; + else if (sclr) + use_wdata_srl <= 4'b0000; + else if (arb_write) + unique case (arb_burst) + 2'h0 : use_wdata_srl <= 4'b1000; + 2'h1 : use_wdata_srl <= 4'b1100; + 2'h2 : use_wdata_srl <= 4'b1110; + 2'h3 : use_wdata_srl <= 4'b1111; + endcase + else + use_wdata_srl <= (use_wdata_srl << 1); + end + + assign use_wdata = use_wdata_srl[3]; + assign use_wdatam = use_wdata_srl[3]; + + //-------------------------------------------------------------------------------------------------- + // read/write data mask for command terminate + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : data_burst_mask_generate + if (reset) + datam_srl <= '0; + else if (sclr) + datam_srl <= '0; + else begin + if (arb_write) + datam_srl <= WriteMaskBits(arb_burst); + else if (arb_read) + datam_srl <= ReadMaskBits(arb_burst); + else + datam_srl <= (datam_srl << 1); + end + end + + always_ff @(posedge clk or posedge reset) begin : data_mask_generate + if (reset) + datam <= 1'b0; + else if (sclr) + datam <= 1'b0; + else begin + if (arb_write) + datam <= 1'b0; + else if (arb_read) + datam <= FirstReadMaskBit(arb_burst); + else + datam <= datam_srl [cDataMask-1]; + end + end + + // + // dqm + // + + assign dqm = use_wdatam ? sys_wdatam : {pDatamBits{datam}}; + + //-------------------------------------------------------------------------------------------------- + // write data request + //-------------------------------------------------------------------------------------------------- + +`ifndef HSSDRC_COMBINATORY_USE_WDATA + + assign sys_use_wdata = use_wdata; + +`else + + logic [2:0] use_wdata_srl_small; + + always_ff @(posedge clk or posedge reset) begin : use_wdata_small_generate + if (reset) + use_wdata_srl_small <= 3'b000; + else if (sclr) + use_wdata_srl_small <= 3'b000; + else if (arb_write) + unique case (arb_burst) + 2'h0 : use_wdata_srl_small <= 3'b000; + 2'h1 : use_wdata_srl_small <= 3'b100; + 2'h2 : use_wdata_srl_small <= 3'b110; + 2'h3 : use_wdata_srl_small <= 3'b111; + endcase + else + use_wdata_srl_small <= (use_wdata_srl_small << 1); + end + + assign sys_use_wdata = arb_write | use_wdata_srl_small[2]; + +`endif + // + // dq + // + + assign dq = use_wdata ? sys_wdata : {pDataBits{1'bz}}; + + //-------------------------------------------------------------------------------------------------- + // read data + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : vld_rdata_generate + if (reset) + vld_rdata_srl <= 4'b0000; + else if (sclr) + vld_rdata_srl <= 4'b0000; + else if (arb_read) + unique case (arb_burst) + 2'h0 : vld_rdata_srl <= 4'b1000; + 2'h1 : vld_rdata_srl <= 4'b1100; + 2'h2 : vld_rdata_srl <= 4'b1110; + 2'h3 : vld_rdata_srl <= 4'b1111; + endcase + else + vld_rdata_srl <= (vld_rdata_srl << 1); + end + + assign vld_rdata = vld_rdata_srl [3]; + + // + // + // + + always_ff @(posedge clk) begin : chid_rdata_generate + int i; + + if (arb_read) begin + for (i = 0; i < 4; i++) + chid_srl[i] <= arb_chid; // load all with chid + end + else begin + for (i = 1; i < 4; i++) + chid_srl[i] <= chid_srl[i-1]; // shift left + end + end + + assign chid = chid_srl [3]; + + // + // + // + + always_ff @(posedge clk or posedge reset) begin : vld_rdata_allign_generate + int i; + + if (reset) begin + for (i = 0; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= 1'b0; + end + else if (sclr) begin + for (i = 0; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= 1'b0; + end + else begin + vld_rdata_allign_srl[0] <= vld_rdata; // shift left + + for (i = 1; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= vld_rdata_allign_srl [i-1]; + end + end + + + assign sys_vld_rdata = vld_rdata_allign_srl [cReadAllign-1]; + + // + // + // + + always_ff @(posedge clk) begin : chid_allign_generate + int i; + + chid_allign_srl[0] <= chid; // shift left + + for (i = 1; i < cReadAllign; i++) + chid_allign_srl[i] <= chid_allign_srl[i-1]; + end + + + assign sys_chid_o = chid_allign_srl [cReadAllign-1]; + + // + // + // + + always_ff @(posedge clk) begin : rdata_reclock + sys_rdata <= dq; + end + + //-------------------------------------------------------------------------------------------------- + // function to count write bit mask pattern for different burst value and + // for different Cas Latency paramter value + // full burst == 2'h3 no need to be masked + //-------------------------------------------------------------------------------------------------- + + function automatic bit [cDataMask-1:0] WriteMaskBits (input bit [1:0] burst); + if (pCL == 3) begin + WriteMaskBits = 4'b0000; + case (burst) + 2'h0 : WriteMaskBits = 4'b1110; + 2'h1 : WriteMaskBits = 4'b0110; + 2'h2 : WriteMaskBits = 4'b0010; + endcase + end + else if (pCL == 2) begin + WriteMaskBits = 3'b000; + case (burst) + 2'h0 : WriteMaskBits = 3'b111; + 2'h1 : WriteMaskBits = 3'b011; + 2'h2 : WriteMaskBits = 3'b001; + endcase + end + else if (pCL == 1) begin + WriteMaskBits = 3'b000; + case (burst) + 2'h0 : WriteMaskBits = 3'b111; + 2'h1 : WriteMaskBits = 3'b011; + 2'h2 : WriteMaskBits = 3'b001; + endcase + end + else begin + WriteMaskBits = '0; + end + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to count first read bit mask pattern for different burst value and + // for different Cas Latency paramter value + //-------------------------------------------------------------------------------------------------- + + function automatic bit FirstReadMaskBit (input bit [1:0] burst); + if ((pCL == 1) && (burst == 0)) + FirstReadMaskBit = 1'b1; + else + FirstReadMaskBit = 1'b0; + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to count read bit mask pattern for different burst value and + // for different Cas Latency paramter value + // full burst == 2'h3 no need to be masked + //-------------------------------------------------------------------------------------------------- + + function automatic bit [cDataMask-1:0] ReadMaskBits (input bit [1:0] burst); + if (pCL == 3) begin + ReadMaskBits = 4'b0000; + case (burst) + 2'h0 : ReadMaskBits = 4'b0111; + 2'h1 : ReadMaskBits = 4'b0011; + 2'h2 : ReadMaskBits = 4'b0001; + endcase + end + else if (pCL == 2) begin + ReadMaskBits = 3'b000; + case (burst) + 2'h0 : ReadMaskBits = 3'b111; + 2'h1 : ReadMaskBits = 3'b011; + 2'h2 : ReadMaskBits = 3'b001; + endcase + end + else if (pCL == 1) begin + ReadMaskBits = 3'b000; + case (burst) + 2'h0 : ReadMaskBits = 3'b110; + 2'h1 : ReadMaskBits = 3'b110; + 2'h2 : ReadMaskBits = 3'b010; + endcase + end + else begin + ReadMaskBits = '0; + end + endfunction + +endmodule

hssdrc/trunk/rtl/hssdrc_data_path.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_data_path_p1.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_data_path_p1.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_data_path_p1.v (revision 3) @@ -0,0 +1,429 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_data_path_p1.v +// +// Description : sdram data (data & mask) path unit +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_timing.vh" +`include "hssdrc_define.vh" + +module hssdrc_data_path_p1 ( + clk , + reset , + sclr , + // + sys_wdata , + sys_wdatam , + sys_use_wdata , + sys_vld_rdata , + sys_chid_o , + sys_rdata , + // + arb_read , + arb_write , + arb_chid , + arb_burst , + // + dq , + dqm + ); + + input wire clk; + input wire reset; + input wire sclr; + + //-------------------------------------------------------------------------------------------------- + // system data interface + //-------------------------------------------------------------------------------------------------- + + input data_t sys_wdata ; + input datam_t sys_wdatam ; + output logic sys_use_wdata ; + output logic sys_vld_rdata ; + output chid_t sys_chid_o ; + output data_t sys_rdata ; + + //-------------------------------------------------------------------------------------------------- + // interface from arbiter throw multiplexer + //-------------------------------------------------------------------------------------------------- + + input wire arb_read ; + input wire arb_write ; + input chid_t arb_chid ; + input sdram_burst_t arb_burst ; + + //-------------------------------------------------------------------------------------------------- + // interface sdram chip + //-------------------------------------------------------------------------------------------------- + + inout wire [pDataBits-1 :0] dq; + output logic [pDatamBits-1 :0] dqm; + + //-------------------------------------------------------------------------------------------------- + // Mask paramters count via pBL, pCL parameters only for clarify. + // unit has been designed to use fixed lengh mask patterns + //-------------------------------------------------------------------------------------------------- + localparam cWDataMask = cSdramBL - 1; // - 1 cycle for write command itself + + localparam cRDataMask = cSdramBL - 1 + pCL - 2; // - 1 cycle for read command itself, + // - 2 cycle for read dqm latency + + localparam cDataMask = max(cWDataMask, cRDataMask); + + localparam cReadAllign = pCL + 1 + 1; // + 1 is capture register cycle + // + 1 is additition command latency + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + data_t wdata_delayed; + logic use_wdata_delayed; + + logic [3:0] use_wdata_srl; + wire use_wdata; + wire use_wdatam; + + logic [cDataMask-1 : 0] datam_srl; + logic datam; + + + logic [3:0] vld_rdata_srl; + logic vld_rdata; + logic vld_rdata_allign_srl [cReadAllign-1 : 0]; + + chid_t chid_srl [3:0]; + chid_t chid; + chid_t chid_allign_srl [cReadAllign-1 : 0]; + + //-------------------------------------------------------------------------------------------------- + // use write data & mask + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : use_wdata_generate + if (reset) + use_wdata_srl <= 4'b0000; + else if (sclr) + use_wdata_srl <= 4'b0000; + else if (arb_write) + unique case (arb_burst) + 2'h0 : use_wdata_srl <= 4'b1000; + 2'h1 : use_wdata_srl <= 4'b1100; + 2'h2 : use_wdata_srl <= 4'b1110; + 2'h3 : use_wdata_srl <= 4'b1111; + endcase + else + use_wdata_srl <= (use_wdata_srl << 1); + end + + assign use_wdata = use_wdata_srl[3]; + assign use_wdatam = use_wdata_srl[3]; + + // + // read/write data mask for command terminate + // + + always_ff @(posedge clk or posedge reset) begin : data_burst_mask_generate + if (reset) + datam_srl <= '0; + else if (sclr) + datam_srl <= '0; + else begin + if (arb_write) + datam_srl <= WriteMaskBits(arb_burst); + else if (arb_read) + datam_srl <= ReadMaskBits(arb_burst); + else + datam_srl <= (datam_srl << 1); + end + end + + always_ff @(posedge clk or posedge reset) begin : data_mask_generate + if (reset) + datam <= 1'b0; + else if (sclr) + datam <= 1'b0; + else begin + if (arb_write) + datam <= 1'b0; + else if (arb_read) + datam <= FirstReadMaskBit(arb_burst); + else + datam <= datam_srl [cDataMask-1]; + end + end + + // + // dqm + // + + + always_ff @(posedge clk or posedge reset) begin + if (reset) + dqm <= '0; + else if (sclr) + dqm <= '0; + else + dqm <= use_wdatam ? sys_wdatam : {pDatamBits{datam}}; + end + + + //-------------------------------------------------------------------------------------------------- + // write data request + //-------------------------------------------------------------------------------------------------- + +`ifndef HSSDRC_COMBINATORY_USE_WDATA + + assign sys_use_wdata = use_wdata; + +`else + + logic [2:0] use_wdata_srl_small; + + always_ff @(posedge clk or posedge reset) begin : use_wdata_small_generate + if (reset) + use_wdata_srl_small <= 3'b000; + else if (sclr) + use_wdata_srl_small <= 3'b000; + else if (arb_write) + unique case (arb_burst) + 2'h0 : use_wdata_srl_small <= 3'b000; + 2'h1 : use_wdata_srl_small <= 3'b100; + 2'h2 : use_wdata_srl_small <= 3'b110; + 2'h3 : use_wdata_srl_small <= 3'b111; + endcase + else + use_wdata_srl_small <= (use_wdata_srl_small << 1); + end + + assign sys_use_wdata = arb_write | use_wdata_srl_small[2]; + +`endif + // + // dq + // + + + always_ff @(posedge clk) begin : wdata_reclock + wdata_delayed <= sys_wdata; + end + + always_ff @(posedge clk or posedge reset) begin : use_wdata_reclock + if (reset) + use_wdata_delayed <= 1'b0; + else + use_wdata_delayed <= use_wdata; + end + + + assign dq = use_wdata_delayed ? wdata_delayed : {pDataBits{1'bz}}; + + //-------------------------------------------------------------------------------------------------- + // read data + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : vld_rdata_generate + if (reset) + vld_rdata_srl <= 4'b0000; + else if (sclr) + vld_rdata_srl <= 4'b0000; + else if (arb_read) + unique case (arb_burst) + 2'h0 : vld_rdata_srl <= 4'b1000; + 2'h1 : vld_rdata_srl <= 4'b1100; + 2'h2 : vld_rdata_srl <= 4'b1110; + 2'h3 : vld_rdata_srl <= 4'b1111; + endcase + else + vld_rdata_srl <= (vld_rdata_srl << 1); + end + + assign vld_rdata = vld_rdata_srl [3]; + + // + // + // + + always_ff @(posedge clk) begin : chid_rdata_generate + int i; + + if (arb_read) begin + for (i = 0; i < 4; i++) + chid_srl[i] <= arb_chid; // load all with chid + end + else begin + for (i = 1; i < 4; i++) + chid_srl[i] <= chid_srl[i-1]; // shift left with last data stable + end + end + + assign chid = chid_srl [3]; + + // + // + // + + always_ff @(posedge clk or posedge reset) begin : vld_rdata_allign_generate + int i; + + if (reset) begin + for (i = 0; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= 1'b0; + end + else if (sclr) begin + for (i = 0; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= 1'b0; + end + else begin + vld_rdata_allign_srl[0] <= vld_rdata; // shift left + + for (i = 1; i < cReadAllign; i++) + vld_rdata_allign_srl[i] <= vld_rdata_allign_srl [i-1]; + end + end + + + assign sys_vld_rdata = vld_rdata_allign_srl [cReadAllign-1]; + + // + // + // + + always_ff @(posedge clk) begin : chid_allign_generate + int i; + + chid_allign_srl[0] <= chid; // shift left + + for (i = 1; i < cReadAllign; i++) + chid_allign_srl[i] <= chid_allign_srl[i-1]; + end + + + assign sys_chid_o = chid_allign_srl [cReadAllign-1]; + + // + // + // + + always_ff @(posedge clk) begin : rdata_reclock + sys_rdata <= dq; + end + + //-------------------------------------------------------------------------------------------------- + // function to count write bit mask pattern for different burst value and + // for different Cas Latency paramter value + // full burst == 2'h3 no need to be masked + //-------------------------------------------------------------------------------------------------- + + function automatic bit [cDataMask-1:0] WriteMaskBits (input bit [1:0] burst); + if (pCL == 3) begin + WriteMaskBits = 4'b0000; + case (burst) + 2'h0 : WriteMaskBits = 4'b1110; + 2'h1 : WriteMaskBits = 4'b0110; + 2'h2 : WriteMaskBits = 4'b0010; + endcase + end + else if (pCL == 2) begin + WriteMaskBits = 3'b000; + case (burst) + 2'h0 : WriteMaskBits = 3'b111; + 2'h1 : WriteMaskBits = 3'b011; + 2'h2 : WriteMaskBits = 3'b001; + endcase + end + else if (pCL == 1) begin + WriteMaskBits = 3'b000; + case (burst) + 2'h0 : WriteMaskBits = 3'b111; + 2'h1 : WriteMaskBits = 3'b011; + 2'h2 : WriteMaskBits = 3'b001; + endcase + end + else begin + WriteMaskBits = '0; + end + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to count first read bit mask pattern for different burst value and + // for different Cas Latency paramter value + //-------------------------------------------------------------------------------------------------- + + function automatic bit FirstReadMaskBit (input bit [1:0] burst); + if ((pCL == 1) && (burst == 0)) + FirstReadMaskBit = 1'b1; + else + FirstReadMaskBit = 1'b0; + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to count read bit mask pattern for different burst value and + // for different Cas Latency paramter value + // full burst == 2'h3 no need to be masked + //-------------------------------------------------------------------------------------------------- + + function automatic bit [cDataMask-1:0] ReadMaskBits (input bit [1:0] burst); + if (pCL == 3) begin + ReadMaskBits = 4'b0000; + case (burst) + 2'h0 : ReadMaskBits = 4'b0111; + 2'h1 : ReadMaskBits = 4'b0011; + 2'h2 : ReadMaskBits = 4'b0001; + endcase + end + else if (pCL == 2) begin + ReadMaskBits = 3'b000; + case (burst) + 2'h0 : ReadMaskBits = 3'b111; + 2'h1 : ReadMaskBits = 3'b011; + 2'h2 : ReadMaskBits = 3'b001; + endcase + end + else if (pCL == 1) begin + ReadMaskBits = 3'b000; + case (burst) + 2'h0 : ReadMaskBits = 3'b110; + 2'h1 : ReadMaskBits = 3'b110; + 2'h2 : ReadMaskBits = 3'b010; + endcase + end + else begin + ReadMaskBits = '0; + end + endfunction + +endmodule

hssdrc/trunk/rtl/hssdrc_data_path_p1.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_decoder.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_decoder.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_decoder.v (revision 3) @@ -0,0 +1,477 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_decoder.v +// +// Description : sdram command sequence decoder's array +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_decoder ( + clk , + reset , + sclr , + // + ba_map_update , + ba_map_clear , + ba_map_ba , + ba_map_rowa , + ba_map_pre_act_rw , + ba_map_act_rw , + ba_map_rw , + ba_map_all_close , + // + arb0_write , + arb0_read , + arb0_refr , + arb0_rowa , + arb0_cola , + arb0_ba , + arb0_burst , + arb0_chid , + arb0_ready , + // + arb1_write , + arb1_read , + arb1_refr , + arb1_rowa , + arb1_cola , + arb1_ba , + arb1_burst , + arb1_chid , + arb1_ready , + // + arb2_write , + arb2_read , + arb2_refr , + arb2_rowa , + arb2_cola , + arb2_ba , + arb2_burst , + arb2_chid , + arb2_ready , + // + dec0_pre_all , + dec0_refr , + dec0_pre , + dec0_act , + dec0_read , + dec0_write , + dec0_pre_all_enable , + dec0_refr_enable , + dec0_pre_enable , + dec0_act_enable , + dec0_read_enable , + dec0_write_enable , + dec0_locked , + dec0_last , + dec0_rowa , + dec0_cola , + dec0_ba , + dec0_chid , + dec0_burst , + // + dec1_pre_all , + dec1_refr , + dec1_pre , + dec1_act , + dec1_read , + dec1_write , + dec1_pre_all_enable , + dec1_refr_enable , + dec1_pre_enable , + dec1_act_enable , + dec1_read_enable , + dec1_write_enable , + dec1_locked , + dec1_last , + dec1_rowa , + dec1_cola , + dec1_ba , + dec1_chid , + dec1_burst , + // + dec2_pre_all , + dec2_refr , + dec2_pre , + dec2_act , + dec2_read , + dec2_write , + dec2_pre_all_enable , + dec2_refr_enable , + dec2_pre_enable , + dec2_act_enable , + dec2_read_enable , + dec2_write_enable , + dec2_locked , + dec2_last , + dec2_rowa , + dec2_cola , + dec2_ba , + dec2_chid , + dec2_burst + ); + + input wire clk ; + input wire reset; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // bank map interface + //-------------------------------------------------------------------------------------------------- + + output wire ba_map_update ; + output wire ba_map_clear ; + output ba_t ba_map_ba ; + output rowa_t ba_map_rowa ; + input wire ba_map_pre_act_rw; + input wire ba_map_act_rw ; + input wire ba_map_rw ; + input wire ba_map_all_close ; + + //-------------------------------------------------------------------------------------------------- + // interface from input arbiter + //-------------------------------------------------------------------------------------------------- + + input logic arb0_write ; + input logic arb0_read ; + input logic arb0_refr ; + input rowa_t arb0_rowa ; + input cola_t arb0_cola ; + input ba_t arb0_ba ; + input burst_t arb0_burst ; + input chid_t arb0_chid ; + output wire arb0_ready ; + // + input logic arb1_write ; + input logic arb1_read ; + input logic arb1_refr ; + input rowa_t arb1_rowa ; + input cola_t arb1_cola ; + input ba_t arb1_ba ; + input burst_t arb1_burst ; + input chid_t arb1_chid ; + output wire arb1_ready ; + // + input logic arb2_write ; + input logic arb2_read ; + input logic arb2_refr ; + input rowa_t arb2_rowa ; + input cola_t arb2_cola ; + input ba_t arb2_ba ; + input burst_t arb2_burst ; + input chid_t arb2_chid ; + output wire arb2_ready ; + + //-------------------------------------------------------------------------------------------------- + // inteface to output arbiter + //-------------------------------------------------------------------------------------------------- + + output logic dec0_pre_all ; + output logic dec0_refr ; + output logic dec0_pre ; + output logic dec0_act ; + output logic dec0_read ; + output logic dec0_write ; + input wire dec0_pre_all_enable; + input wire dec0_refr_enable ; + input wire dec0_pre_enable ; + input wire dec0_act_enable ; + input wire dec0_read_enable ; + input wire dec0_write_enable ; + output logic dec0_locked ; + output logic dec0_last ; + output rowa_t dec0_rowa ; + output cola_t dec0_cola ; + output ba_t dec0_ba ; + output chid_t dec0_chid ; + output sdram_burst_t dec0_burst ; + // + output logic dec1_pre_all ; + output logic dec1_refr ; + output logic dec1_pre ; + output logic dec1_act ; + output logic dec1_read ; + output logic dec1_write ; + input wire dec1_pre_all_enable; + input wire dec1_refr_enable ; + input wire dec1_pre_enable ; + input wire dec1_act_enable ; + input wire dec1_read_enable ; + input wire dec1_write_enable ; + output logic dec1_locked ; + output logic dec1_last ; + output rowa_t dec1_rowa ; + output cola_t dec1_cola ; + output ba_t dec1_ba ; + output chid_t dec1_chid ; + output sdram_burst_t dec1_burst ; + // + output logic dec2_pre_all ; + output logic dec2_refr ; + output logic dec2_pre ; + output logic dec2_act ; + output logic dec2_read ; + output logic dec2_write ; + input wire dec2_pre_all_enable; + input wire dec2_refr_enable ; + input wire dec2_pre_enable ; + input wire dec2_act_enable ; + input wire dec2_read_enable ; + input wire dec2_write_enable ; + output logic dec2_locked ; + output logic dec2_last ; + output rowa_t dec2_rowa ; + output cola_t dec2_cola ; + output ba_t dec2_ba ; + output chid_t dec2_chid ; + output sdram_burst_t dec2_burst ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + ba_t ba_latched ; + rowa_t rowa_latched; + + // + // local state ba_map signals + // + + wire state0__ba_map_update ; + wire state0__ba_map_clear ; + wire state0__ba_map_pre_act_rw ; + wire state0__ba_map_act_rw ; + wire state0__ba_map_rw ; + wire state0__ba_map_all_close ; + + wire state1__ba_map_update ; + wire state1__ba_map_clear ; + wire state1__ba_map_pre_act_rw ; + wire state1__ba_map_act_rw ; + wire state1__ba_map_rw ; + wire state1__ba_map_all_close ; + + wire state2__ba_map_update ; + wire state2__ba_map_clear ; + wire state2__ba_map_pre_act_rw ; + wire state2__ba_map_act_rw ; + wire state2__ba_map_rw ; + wire state2__ba_map_all_close ; + + //-------------------------------------------------------------------------------------------------- + // we can capture bank map data into register, becouse we have +1 tick in FSM + // for bank map decoding we can take data from any arbiter channel + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk) begin : ba_map_data_register + ba_latched <= arb0_ba; + rowa_latched <= arb0_rowa; + end + + // + // + // + + assign ba_map_ba = ba_latched; + assign ba_map_rowa = rowa_latched; + assign ba_map_update = state0__ba_map_update | state1__ba_map_update | state2__ba_map_update ; + assign ba_map_clear = state0__ba_map_clear | state1__ba_map_clear | state2__ba_map_clear ; + + assign state0__ba_map_pre_act_rw = ba_map_pre_act_rw ; + assign state0__ba_map_act_rw = ba_map_act_rw ; + assign state0__ba_map_rw = ba_map_rw ; + assign state0__ba_map_all_close = ba_map_all_close ; + + assign state1__ba_map_pre_act_rw = ba_map_pre_act_rw ; + assign state1__ba_map_act_rw = ba_map_act_rw ; + assign state1__ba_map_rw = ba_map_rw ; + assign state1__ba_map_all_close = ba_map_all_close ; + + assign state2__ba_map_pre_act_rw = ba_map_pre_act_rw ; + assign state2__ba_map_act_rw = ba_map_act_rw ; + assign state2__ba_map_rw = ba_map_rw ; + assign state2__ba_map_all_close = ba_map_all_close ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_decoder_state state0 ( + .clk (clk ), + .reset (reset), + .sclr (sclr ), + // + .ba_map_update (state0__ba_map_update ), + .ba_map_clear (state0__ba_map_clear ), + .ba_map_pre_act_rw (state0__ba_map_pre_act_rw), + .ba_map_act_rw (state0__ba_map_act_rw ), + .ba_map_rw (state0__ba_map_rw ), + .ba_map_all_close (state0__ba_map_all_close ), + // + .arb_write (arb0_write), + .arb_read (arb0_read ), + .arb_refr (arb0_refr ), + .arb_rowa (arb0_rowa ), + .arb_cola (arb0_cola ), + .arb_ba (arb0_ba ), + .arb_burst (arb0_burst), + .arb_chid (arb0_chid ), + .arb_ready (arb0_ready), + // + .dec_pre_all (dec0_pre_all), + .dec_refr (dec0_refr ), + .dec_pre (dec0_pre ), + .dec_act (dec0_act ), + .dec_read (dec0_read ), + .dec_write (dec0_write ), + // + .dec_pre_all_enable(dec0_pre_all_enable), + .dec_refr_enable (dec0_refr_enable ), + .dec_pre_enable (dec0_pre_enable ), + .dec_act_enable (dec0_act_enable ), + .dec_read_enable (dec0_read_enable ), + .dec_write_enable (dec0_write_enable ), + // + .dec_locked (dec0_locked), + .dec_last (dec0_last ), + // + .dec_rowa (dec0_rowa ), + .dec_cola (dec0_cola ), + .dec_ba (dec0_ba ), + .dec_chid (dec0_chid ), + // + .dec_burst (dec0_burst) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_decoder_state state1 ( + .clk (clk ), + .reset (reset), + .sclr (sclr ), + // + .ba_map_update (state1__ba_map_update ), + .ba_map_clear (state1__ba_map_clear ), + .ba_map_pre_act_rw (state1__ba_map_pre_act_rw), + .ba_map_act_rw (state1__ba_map_act_rw ), + .ba_map_rw (state1__ba_map_rw ), + .ba_map_all_close (state1__ba_map_all_close ), + // + .arb_write (arb1_write), + .arb_read (arb1_read ), + .arb_refr (arb1_refr ), + .arb_rowa (arb1_rowa ), + .arb_cola (arb1_cola ), + .arb_ba (arb1_ba ), + .arb_burst (arb1_burst), + .arb_chid (arb1_chid ), + .arb_ready (arb1_ready), + // + .dec_pre_all (dec1_pre_all), + .dec_refr (dec1_refr ), + .dec_pre (dec1_pre ), + .dec_act (dec1_act ), + .dec_read (dec1_read ), + .dec_write (dec1_write ), + // + .dec_pre_all_enable(dec1_pre_all_enable), + .dec_refr_enable (dec1_refr_enable ), + .dec_pre_enable (dec1_pre_enable ), + .dec_act_enable (dec1_act_enable ), + .dec_read_enable (dec1_read_enable ), + .dec_write_enable (dec1_write_enable ), + // + .dec_locked (dec1_locked), + .dec_last (dec1_last ), + // + .dec_rowa (dec1_rowa ), + .dec_cola (dec1_cola ), + .dec_ba (dec1_ba ), + .dec_chid (dec1_chid ), + // + .dec_burst (dec1_burst) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_decoder_state state2 ( + .clk (clk ), + .reset (reset), + .sclr (sclr ), + // + .ba_map_update (state2__ba_map_update ), + .ba_map_clear (state2__ba_map_clear ), + .ba_map_pre_act_rw (state2__ba_map_pre_act_rw), + .ba_map_act_rw (state2__ba_map_act_rw ), + .ba_map_rw (state2__ba_map_rw ), + .ba_map_all_close (state2__ba_map_all_close ), + // + .arb_write (arb2_write), + .arb_read (arb2_read ), + .arb_refr (arb2_refr ), + .arb_rowa (arb2_rowa ), + .arb_cola (arb2_cola ), + .arb_ba (arb2_ba ), + .arb_burst (arb2_burst), + .arb_chid (arb2_chid ), + .arb_ready (arb2_ready), + // + .dec_pre_all (dec2_pre_all), + .dec_refr (dec2_refr ), + .dec_pre (dec2_pre ), + .dec_act (dec2_act ), + .dec_read (dec2_read ), + .dec_write (dec2_write ), + // + .dec_pre_all_enable(dec2_pre_all_enable), + .dec_refr_enable (dec2_refr_enable ), + .dec_pre_enable (dec2_pre_enable ), + .dec_act_enable (dec2_act_enable ), + .dec_read_enable (dec2_read_enable ), + .dec_write_enable (dec2_write_enable ), + // + .dec_locked (dec2_locked), + .dec_last (dec2_last ), + // + .dec_rowa (dec2_rowa ), + .dec_cola (dec2_cola ), + .dec_ba (dec2_ba ), + .dec_chid (dec2_chid ), + // + .dec_burst (dec2_burst) + ); + +endmodule

hssdrc/trunk/rtl/hssdrc_decoder.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_decoder_state.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_decoder_state.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_decoder_state.v (revision 3) @@ -0,0 +1,534 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_decoder_state.v +// +// Description : sdram command sequence decoder +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_timing.vh" +`include "hssdrc_define.vh" + + +module hssdrc_decoder_state ( + clk , + reset , + sclr , + // + ba_map_update , + ba_map_clear , + ba_map_pre_act_rw , + ba_map_act_rw , + ba_map_rw , + ba_map_all_close , + // + arb_write , + arb_read , + arb_refr , + arb_rowa , + arb_cola , + arb_ba , + arb_burst , + arb_chid , + arb_ready , + // + dec_pre_all , + dec_refr , + dec_pre , + dec_act , + dec_read , + dec_write , + // + dec_pre_all_enable, + dec_refr_enable , + dec_pre_enable , + dec_act_enable , + dec_read_enable , + dec_write_enable , + // + dec_locked , + dec_last , + // + dec_rowa , + dec_cola , + dec_ba , + dec_chid , + // + dec_burst + ); + + input wire clk ; + input wire reset; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // bank map interface + //-------------------------------------------------------------------------------------------------- + + output logic ba_map_update ; + output logic ba_map_clear ; + input wire ba_map_pre_act_rw ; + input wire ba_map_act_rw ; + input wire ba_map_rw ; + input wire ba_map_all_close ; + + //-------------------------------------------------------------------------------------------------- + // interface from input arbiter + //-------------------------------------------------------------------------------------------------- + + input wire arb_write ; + input wire arb_read ; + input wire arb_refr ; + input rowa_t arb_rowa ; + input cola_t arb_cola ; + input ba_t arb_ba ; + input burst_t arb_burst ; + input chid_t arb_chid ; + output logic arb_ready ; + + //-------------------------------------------------------------------------------------------------- + // inteface to output arbiter + //-------------------------------------------------------------------------------------------------- + + // logical commands + output logic dec_pre_all ; + output logic dec_refr ; + output logic dec_pre ; + output logic dec_act ; + output logic dec_read ; + output logic dec_write ; + // logical commands en + input wire dec_pre_all_enable ; + input wire dec_refr_enable ; + input wire dec_pre_enable ; + input wire dec_act_enable ; + input wire dec_read_enable ; + input wire dec_write_enable ; + // addititional signal + output logic dec_locked ; + output logic dec_last ; + // control path + output rowa_t dec_rowa ; + output cola_t dec_cola ; + output ba_t dec_ba ; + output chid_t dec_chid ; + // + output sdram_burst_t dec_burst ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + localparam int cTrp_m1 = cTrp - 1; + localparam int cTrcd_m1 = cTrcd - 1; + + typedef enum { + STATE_RESET_BIT , // need for create simple true ready condition + STATE_IDLE_BIT , + STATE_DECODE_BIT , + STATE_PRE_BIT , + STATE_TRP_BIT , + STATE_ACT_BIT , + STATE_TRCD_BIT , + STATE_RW_BIT , + STATE_ADDR_INC_BIT, + STATE_PRE_ALL_BIT , + STATE_REFR_BIT + } state_bits_e; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + enum bit [10:0] { + STATE_RESET = (11'h1 << STATE_RESET_BIT) , + STATE_IDLE = (11'h1 << STATE_IDLE_BIT) , + STATE_DECODE = (11'h1 << STATE_DECODE_BIT) , + STATE_PRE = (11'h1 << STATE_PRE_BIT) , + STATE_TRP = (11'h1 << STATE_TRP_BIT) , + STATE_ACT = (11'h1 << STATE_ACT_BIT) , + STATE_TRCD = (11'h1 << STATE_TRCD_BIT) , + STATE_RW = (11'h1 << STATE_RW_BIT) , + STATE_ADDR_INC = (11'h1 << STATE_ADDR_INC_BIT) , + STATE_PRE_ALL = (11'h1 << STATE_PRE_ALL_BIT) , + STATE_REFR = (11'h1 << STATE_REFR_BIT) + } state, next_state; + + logic refr_mode ; + logic write_mode ; + + logic burst_done ; + logic early_burst_done; + + cola_t cola_latched ; + rowa_t rowa_latched ; + ba_t ba_latched ; + chid_t chid_latched ; + + logic [3:0] burst_latched ; + logic [3:0] burst_shift_cnt ; + + logic [3:0] available_burst ; + + logic [3:0] remained_burst ; + logic [1:0] remained_burst_high ; + logic [1:0] remained_burst_low ; + logic [1:0] remained_burst_low_latched; + + logic [3:0] last_used_burst; + + wire trp_cnt_done; + wire trcd_cnt_done; + + //-------------------------------------------------------------------------------------------------- + // use shift register instead of counter for trp time count + //-------------------------------------------------------------------------------------------------- + + generate + if (cTrp_m1 <= 1) begin : no_trp_cnt_generate + + assign trp_cnt_done = 1'b1; + + end + else begin : trp_cnt_generate + + logic [cTrp_m1-2:0] trp_cnt; + + always_ff @(posedge clk) begin + if (state [STATE_TRP_BIT]) + trp_cnt <= (trp_cnt << 1) | 1'b1; + else + trp_cnt <= '0; + end + + assign trp_cnt_done = trp_cnt [cTrp_m1-2]; + + end + endgenerate + + //-------------------------------------------------------------------------------------------------- + // use shift register instead of counter for trcd time count + //-------------------------------------------------------------------------------------------------- + + generate + if (cTrcd_m1 <= 1) begin : no_trcd_cnt_generate + + assign trcd_cnt_done = 1'b1; + + end + else begin : trcd_cnt_generate + + logic [cTrcd_m1-2:0] trcd_cnt; + + always_ff @(posedge clk) begin + if (state [STATE_TRCD_BIT]) + trcd_cnt <= (trcd_cnt << 1) | 1'b1; + else + trcd_cnt <= '0; + end + + assign trcd_cnt_done = trcd_cnt [cTrcd_m1-2]; + + end + endgenerate + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + always_comb begin : fsm_jump_decode + + next_state = STATE_RESET; + + unique case (1'b1) + + state [STATE_RESET_BIT] : begin + next_state = STATE_IDLE; + end + + state [STATE_IDLE_BIT] : begin + if (arb_write | arb_read | arb_refr) + next_state = STATE_DECODE; + else + next_state = STATE_IDLE; + end + // + // decode branch + // + state [STATE_DECODE_BIT] : begin + if (refr_mode) begin : shorten_refresh_decode + + if (ba_map_all_close) + next_state = STATE_REFR; + else + next_state = STATE_PRE_ALL; + + end + else begin : mode_of_rw_decode + + if (ba_map_pre_act_rw) + next_state = STATE_PRE; + else if (ba_map_rw) + next_state = STATE_RW; + else // if (ba_map_act_rw) + next_state = STATE_ACT; + + end + end + // + // pre branch + // + state [STATE_PRE_BIT] : begin + if (dec_pre_enable) + + if (cTrp_m1 == 0) + next_state = STATE_ACT; + else + next_state = STATE_TRP; + + else + next_state = STATE_PRE; + end + + state [STATE_TRP_BIT] : begin + if (trp_cnt_done) + next_state = STATE_ACT; + else + next_state = STATE_TRP; + end + // + // act branch + // + state [STATE_ACT_BIT] : begin + if (dec_act_enable) + + if (cTrcd_m1 == 0) + next_state = STATE_RW; + else + next_state = STATE_TRCD; + + else + next_state = STATE_ACT; + end + + state [STATE_TRCD_BIT] : begin + if (trcd_cnt_done) + next_state = STATE_RW; + else + next_state = STATE_TRCD; + end + // + // data branch + // + state [STATE_RW_BIT] : begin + if ((dec_write_enable & write_mode) | (dec_read_enable & ~write_mode)) begin : burst_done_decode + + if (burst_done) + next_state = STATE_IDLE; + else + next_state = STATE_ADDR_INC; + + end + else begin + next_state = STATE_RW; + end + end + + state [STATE_ADDR_INC_BIT] : begin + next_state = STATE_RW; + end + // + // refresh breanch + // + state [STATE_PRE_ALL_BIT] : begin + if (dec_pre_all_enable) + next_state = STATE_REFR; + else + next_state = STATE_PRE_ALL; + end + + state [STATE_REFR_BIT] : begin + if (dec_refr_enable) + next_state = STATE_IDLE; + else + next_state = STATE_REFR; + end + + endcase + end + + //--------------------------------------------------------------------------------------------------- + // + //--------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : fsm_register_process + if (reset) state <= STATE_RESET; + else if (sclr) state <= STATE_RESET; + else state <= next_state; + end + + //--------------------------------------------------------------------------------------------------- + // + //--------------------------------------------------------------------------------------------------- + + assign arb_ready = state[STATE_IDLE_BIT]; + + assign dec_pre_all = state[STATE_PRE_ALL_BIT]; + assign dec_refr = state[STATE_REFR_BIT]; + assign dec_pre = state[STATE_PRE_BIT]; + assign dec_act = state[STATE_ACT_BIT]; + assign dec_read = state[STATE_RW_BIT] & ~write_mode; + assign dec_write = state[STATE_RW_BIT] & write_mode; + assign dec_last = state[STATE_RW_BIT] & burst_done ; + + // + // instead of decode state_refr_bit & state_pre_all_bit we can use refresh mode register + // + + assign dec_locked = refr_mode; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + assign ba_map_update = state[STATE_DECODE_BIT] & ~refr_mode; + assign ba_map_clear = state[STATE_DECODE_BIT] & refr_mode; + + always_ff @(posedge clk) begin : mode_logic + if (state [STATE_IDLE_BIT]) begin + refr_mode <= arb_refr; + write_mode <= arb_write; + end + end + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk) begin : addr_chid_logic + + if (state[STATE_IDLE_BIT]) begin + rowa_latched <= arb_rowa; + ba_latched <= arb_ba; + chid_latched <= arb_chid; + end + + if (state[STATE_IDLE_BIT]) + cola_latched <= arb_cola; + else if (state[STATE_ADDR_INC_BIT]) + cola_latched <= cola_latched + last_used_burst; + + end + + assign dec_cola = cola_latched; + assign dec_rowa = rowa_latched; + assign dec_ba = ba_latched; + assign dec_chid = chid_latched; + + + //-------------------------------------------------------------------------------------------------- + // alligned burst max cycles is 4 + // burst [3:2] == 0 & burst[1:0] <= available_burst. 1 cycle is burst + // burst [3:2] != 0 & burst[1:0] <= available_burst. 1 cycle is burst shift_cnt burst_done + // burst [ 1.. 4] : encoded with [ 4'd0 : 4'd3] : cycle is 1 : burst_shift_cnt = 4'b0000 1 + // burst [ 5.. 8] : encoded with [ 4'd4 : 4'd7] : cycle is 2 : burst_shift_cnt = 4'b0001 0 + // burst [ 9..12] : encoded with [ 4'd8 : 4'd11] : cycle is 3 : burst_shift_cnt = 4'b0010 0 + // burst [13..16] : encoded with [4'd12 : 4'd15] : cycle is 4 : burst_shift_cnt = 4'b0100 0 + // + + // not alligned burst max cycles is 5 shift_cnt burst_done + // burst [ 1.. 4] : encoded with [ 4'd0 : 4'd3] : cycle is 2 : burst_shift_cnt = 4'b0001 0 + // burst [ 5.. 8] : encoded with [ 4'd4 : 4'd7] : cycle is 3 : burst_shift_cnt = 4'b0010 0 + // burst [ 9..12] : encoded with [ 4'd8 : 4'd11] : cycle is 4 : burst_shift_cnt = 4'b0100 0 + // burst [13..16] : encoded with [4'd12 : 4'd15] : cycle is 5 : burst_shift_cnt = 4'b1000 0 + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk) begin : burst_latch_logic + if (state[STATE_IDLE_BIT]) + burst_latched = arb_burst; + end + + // remember that burst has -1 offset + // available burst has -1 offset too + + assign available_burst = 4'b0011 - {2'b00, cola_latched[1:0]}; + + assign remained_burst = burst_latched - available_burst - 1'b1; + assign remained_burst_high = remained_burst[3:2]; + assign remained_burst_low = remained_burst[1:0]; + + assign early_burst_done = burst_shift_cnt[0]; + + always_ff @(posedge clk) begin : burst_logic + if (state[STATE_DECODE_BIT]) begin + + if (burst_latched <= available_burst) begin + + burst_shift_cnt <= '0; + + burst_done <= 1'b1; // only 1 transaction will be + dec_burst <= burst_latched[1:0]; + + end + else begin + + burst_shift_cnt <= '0; + burst_shift_cnt[remained_burst_high] <= 1'b1; + + remained_burst_low_latched <= remained_burst_low; + + burst_done <= 1'b0; // more then 2 transaction will be + + dec_burst <= available_burst[1:0]; + last_used_burst <= {2'b00, available_burst[1:0]} + 1'b1; // + 1 is compensation of -1 offset + + end + end + else if (state[STATE_ADDR_INC_BIT]) begin + + burst_shift_cnt <= burst_shift_cnt >> 1; + + burst_done <= early_burst_done; + // + if (early_burst_done) + dec_burst <= remained_burst_low_latched; // no transaction any more + else + dec_burst <= 2'b11; + // + last_used_burst <= 4'b0011 + 1'b1; + end + end + +endmodule

hssdrc/trunk/rtl/hssdrc_decoder_state.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_addr_path.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_addr_path.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_addr_path.v (revision 3) @@ -0,0 +1,207 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_addr_path.v +// +// Description : coder for translate logical onehot command to sdram command +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + + +module hssdrc_addr_path( + clk , + reset , + sclr , + // + arb_pre_all , + arb_refr , + arb_pre , + arb_act , + arb_read , + arb_write , + arb_lmr , + arb_rowa , + arb_cola , + arb_ba , + // + addr , + ba , + cke , + cs_n , + ras_n , + cas_n , + we_n + ); + + input wire clk; + input wire reset; + input wire sclr; + + //-------------------------------------------------------------------------------------------------- + // interface from output arbiter + //-------------------------------------------------------------------------------------------------- + + input wire arb_pre_all ; + input wire arb_refr ; + input wire arb_pre ; + input wire arb_act ; + input wire arb_read ; + input wire arb_write ; + input wire arb_lmr ; + input rowa_t arb_rowa ; + input cola_t arb_cola ; + input ba_t arb_ba ; + + //-------------------------------------------------------------------------------------------------- + // interface to sdram + //-------------------------------------------------------------------------------------------------- + + output sdram_addr_t addr; + output ba_t ba; + output logic cke; + output logic cs_n; + output logic ras_n; + output logic cas_n; + output logic we_n; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + logic [3:0] cs_n__ras_n__cas_n__we_n; + + // synthesis translate_off + wire [6:0] arb_cmd = {arb_pre_all, arb_refr, arb_pre, arb_act, arb_write, arb_read, arb_lmr}; + arb_cmd_assert : assert property (@(posedge clk) disable iff (reset) (arb_cmd !== 0) |-> $onehot(arb_cmd)); + // synthesis translate_on + + always_comb begin : logical_command_decode + + cs_n__ras_n__cas_n__we_n = 4'b0111; // nop + + unique case (1'b1) + arb_pre_all : cs_n__ras_n__cas_n__we_n = 4'b0010; // Pre + arb_refr : cs_n__ras_n__cas_n__we_n = 4'b0001; // Refr + arb_pre : cs_n__ras_n__cas_n__we_n = 4'b0010; // Pre + arb_act : cs_n__ras_n__cas_n__we_n = 4'b0011; // Act + arb_write : cs_n__ras_n__cas_n__we_n = 4'b0100; // Write + arb_read : cs_n__ras_n__cas_n__we_n = 4'b0101; // Read + arb_lmr : cs_n__ras_n__cas_n__we_n = 4'b0000; // Lmr (data == address) + default : begin end + endcase + end + + // + // don't use clocking disable + // + + assign cke = 1'b1; + + // synthesis translate_off + initial begin + {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // only to disable mt48lc2m warnings + end + // synthesis translate_on + + always_ff @(posedge clk or posedge reset) begin : sdram_control_register + if (reset) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop + else if (sclr) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop + else {cs_n, ras_n, cas_n, we_n} <= cs_n__ras_n__cas_n__we_n; + end + + always_ff @(posedge clk) begin : sdram_mux_addr_path + + ba <= arb_ba; + + if (arb_act | arb_lmr) + addr <= ResizeRowa(arb_rowa); + else + addr <= ResizeCola(arb_cola, arb_pre_all); + + end + + //-------------------------------------------------------------------------------------------------- + // function to get sdram address from row address. row address is transfered during + // act/lmr sdram command and is directly mapped to row address. + //-------------------------------------------------------------------------------------------------- + + function sdram_addr_t ResizeRowa (input rowa_t rowa); + int i; + sdram_addr_t addr_resized; + + for (i = 0; i < pSdramAddrBits; i++) begin + if (pRowaBits > i) + addr_resized[i] = rowa[i]; + else + addr_resized[i] = 1'b0; + end + + return addr_resized; + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to get sdram address from column address. column address is transfered during : + // 1. read/write sdram command and A10 is autoprecharge bit and if pColaBits > 10 then + // cola [$:10] is mapped to addr [$:11]. + // 2. pre sdram command and A10 is select all banks bit + //-------------------------------------------------------------------------------------------------- + + function sdram_addr_t ResizeCola (input cola_t cola, input bit pre_all); + int i; + sdram_addr_t addr_resized; + + for (i = 0; i < pSdramAddrBits; i++) begin + if (i < 10) begin + if (pColaBits > i) + addr_resized[i] = cola[i]; + else + addr_resized[i] = 1'b0; + end + else if (i == 10) begin + addr_resized[i] = pre_all; // Autoprecharge is not used -> A10 is always 1'b0 then read/write active + end + else begin + if (pColaBits > i) + addr_resized[i] = cola[i-1]; + else + addr_resized[i] = 1'b0; + end + end + + return addr_resized; + endfunction + +endmodule

hssdrc/trunk/rtl/hssdrc_addr_path.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_addr_path_p1.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_addr_path_p1.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_addr_path_p1.v (revision 3) @@ -0,0 +1,216 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_addr_path_p1.v +// +// Description : coder for translate logical onehot command to sdram command +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + + +module hssdrc_addr_path_p1( + clk , + reset , + sclr , + // + arb_pre_all , + arb_refr , + arb_pre , + arb_act , + arb_read , + arb_write , + arb_lmr , + arb_rowa , + arb_cola , + arb_ba , + // + addr , + ba , + cke , + cs_n , + ras_n , + cas_n , + we_n + ); + + input wire clk; + input wire reset; + input wire sclr; + + //-------------------------------------------------------------------------------------------------- + // interface from output arbiter + //-------------------------------------------------------------------------------------------------- + + input wire arb_pre_all ; + input wire arb_refr ; + input wire arb_pre ; + input wire arb_act ; + input wire arb_read ; + input wire arb_write ; + input wire arb_lmr ; + input rowa_t arb_rowa ; + input cola_t arb_cola ; + input ba_t arb_ba ; + + //-------------------------------------------------------------------------------------------------- + // interface to sdram + //-------------------------------------------------------------------------------------------------- + + output sdram_addr_t addr; + output ba_t ba; + output logic cke; + output logic cs_n; + output logic ras_n; + output logic cas_n; + output logic we_n; + + // + // + // + + logic [3:0] cs_n__ras_n__cas_n__we_n; + + sdram_addr_t addr_latched; + ba_t ba_latched; + + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : logical_command_decode + if (reset) + cs_n__ras_n__cas_n__we_n <= 4'b1111; // inheribit nop + else if (sclr) + cs_n__ras_n__cas_n__we_n <= 4'b1111; // inheribit nop + else begin + unique case (1'b1) + arb_pre_all : cs_n__ras_n__cas_n__we_n <= 4'b0010; // Pre + arb_refr : cs_n__ras_n__cas_n__we_n <= 4'b0001; // Refr + arb_pre : cs_n__ras_n__cas_n__we_n <= 4'b0010; // Pre + arb_act : cs_n__ras_n__cas_n__we_n <= 4'b0011; // Act + arb_write : cs_n__ras_n__cas_n__we_n <= 4'b0100; // Write + arb_read : cs_n__ras_n__cas_n__we_n <= 4'b0101; // Read + arb_lmr : cs_n__ras_n__cas_n__we_n <= 4'b0000; // Lmr (data == address) + default : cs_n__ras_n__cas_n__we_n <= 4'b0111; + endcase + end + end + + // + // don't use clocking disable + // + + assign cke = 1'b1; + + // synthesis translate_off + initial begin + {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // only to disable mt48lc2m warnings + end + // synthesis translate_on + + always_ff @(posedge clk or posedge reset) begin : sdram_control_register + if (reset) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop + else if (sclr) {cs_n, ras_n, cas_n, we_n} <= 4'b1111; // inheribit nop + else {cs_n, ras_n, cas_n, we_n} <= cs_n__ras_n__cas_n__we_n; + end + + always_ff @(posedge clk) begin : sdram_mux_addr_path + + ba_latched <= arb_ba; + ba <= ba_latched; + + + if (arb_act | arb_lmr) + addr_latched <= ResizeRowa(arb_rowa); + else + addr_latched <= ResizeCola(arb_cola, arb_pre_all); + + addr <= addr_latched; + end + + //-------------------------------------------------------------------------------------------------- + // function to get sdram address from row address. row address is transfered during + // act/lmr sdram command and is directly mapped to row address. + //-------------------------------------------------------------------------------------------------- + + function sdram_addr_t ResizeRowa (input rowa_t rowa); + int i; + sdram_addr_t addr_resized; + + for (i = 0; i < pSdramAddrBits; i++) begin + if (pRowaBits > i) + addr_resized[i] = rowa[i]; + else + addr_resized[i] = 1'b0; + end + + return addr_resized; + endfunction + + //-------------------------------------------------------------------------------------------------- + // function to get sdram address from column address. column address is transfered during : + // 1. read/write sdram command and A10 is autoprecharge bit and if pColaBits > 10 then + // cola [$:10] is mapped to addr [$:11]. + // 2. pre sdram command and A10 is select all banks bit + //-------------------------------------------------------------------------------------------------- + + function sdram_addr_t ResizeCola (input cola_t cola, input bit pre_all); + int i; + sdram_addr_t addr_resized; + + for (i = 0; i < pSdramAddrBits; i++) begin + if (i < 10) begin + if (pColaBits > i) + addr_resized[i] = cola[i]; + else + addr_resized[i] = 1'b0; + end + else if (i == 10) begin + addr_resized[i] = pre_all; // Autoprecharge is not used -> A10 is always 1'b0 then read/write active + end + else begin + if (pColaBits > i) + addr_resized[i] = cola[i-1]; + else + addr_resized[i] = 1'b0; + end + end + + return addr_resized; + endfunction + +endmodule

hssdrc/trunk/rtl/hssdrc_addr_path_p1.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_mux.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_mux.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_mux.v (revision 3) @@ -0,0 +1,153 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_mux.v +// +// Description : multiplexer for sdram signals +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_mux + ( + init_done , + // + init_state_pre_all , + init_state_refr , + init_state_lmr , + init_state_rowa , + // + arb_pre_all , + arb_refr , + arb_pre , + arb_act , + arb_read , + arb_write , + arb_rowa , + arb_cola , + arb_ba , + arb_chid , + arb_burst , + // + mux_pre_all , + mux_refr , + mux_pre , + mux_act , + mux_read , + mux_write , + mux_lmr , + mux_rowa , + mux_cola , + mux_ba , + mux_chid , + mux_burst + ); + + input wire init_done; + + //-------------------------------------------------------------------------------------------------- + // interface from inis state controller + //-------------------------------------------------------------------------------------------------- + + input wire init_state_pre_all ; + input wire init_state_refr ; + input wire init_state_lmr ; + input rowa_t init_state_rowa ; + + //-------------------------------------------------------------------------------------------------- + // interface from output arbiter + //-------------------------------------------------------------------------------------------------- + + input wire arb_pre_all ; + input wire arb_refr ; + input wire arb_pre ; + input wire arb_act ; + input wire arb_read ; + input wire arb_write ; + input rowa_t arb_rowa ; + input cola_t arb_cola ; + input ba_t arb_ba ; + input chid_t arb_chid ; + input sdram_burst_t arb_burst ; + + //-------------------------------------------------------------------------------------------------- + // interface to data/addr path units + //-------------------------------------------------------------------------------------------------- + + output logic mux_pre_all ; + output logic mux_refr ; + output logic mux_pre ; + output logic mux_act ; + output logic mux_read ; + output logic mux_write ; + output logic mux_lmr ; + output rowa_t mux_rowa ; + output cola_t mux_cola ; + output ba_t mux_ba ; + output chid_t mux_chid ; + output sdram_burst_t mux_burst ; + + //------------------------------------------------------------------------------------------------- + // there is no reason to mask or mux arbiter_if signals, becouse during init state phase + // init_done == 0 and this signals is cleared inside decoders and after init state phase + // init_done == 1 and init_state_if signals will be cleared also + //------------------------------------------------------------------------------------------------- + + assign mux_pre_all = arb_pre_all | init_state_pre_all; + assign mux_refr = arb_refr | init_state_refr ; + + // this will be synthesis as simple logic, becouse init_state_rowa is constant + assign mux_rowa = init_done ? arb_rowa : init_state_rowa ; + + assign mux_pre = arb_pre ; + assign mux_act = arb_act ; + assign mux_read = arb_read ; + assign mux_write = arb_write ; + + assign mux_lmr = init_state_lmr; + + // + // no mux becouse init state phase not use this sdram ports + // + + assign mux_cola = arb_cola ; + assign mux_ba = arb_ba ; + assign mux_burst = arb_burst; + assign mux_chid = arb_chid ; + +endmodule + + +

hssdrc/trunk/rtl/hssdrc_mux.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_access_manager.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_access_manager.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_access_manager.v (revision 3) @@ -0,0 +1,538 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_access_manager.v +// +// Description : sdram bank access manager +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +// used command sequenceces +// 1. {pre a -> act a -> rw a} -> {pre a -> act a -> rw a } +// -> {rw a } +// -> {pre_all -> refr} +// 2. {pre a -> act a -> rw a} -> {pre b -> act b -> rw b } +// -> {act b -> rw b} +// -> {rw b } +// -> {pre_all -> refr} +// 3. {pre_all -> refr} -> refr +// -> act +// +// just need to control : +// +-------------------+-------------------------+--------------------------+ +// | command | sequental decoder part | concurent/pipeline part | +// +===================+=========================+==========================+ +// | pre [0] -> | act [0] | act [1,2,3] | +// | pre [0] -> | | pre [1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | pre [1] -> | act [1] | act [0,2,3] | +// | pre [1] -> | | pre [0,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | pre [2] -> | act [2] | act [0,1,3] | +// | pre [2] -> | | pre [0,1,3] | +// +-------------------+-------------------------+--------------------------+ +// | pre [3] -> | act [3] | act [0,1,2] | +// | pre [3] -> | | pre [0,1,2] | +// +-------------------+-------------------------+--------------------------+ +// | act [0] -> | write [0] | | +// | act [0] -> | | act [1,2,3] | +// | act [0] -> | | pre [0,1,2,3] | +// | act [0] -> | read [0] | | +// +-------------------+-------------------------+--------------------------+ +// | act [1] -> | write [1] | | +// | act [1] -> | | act [0,2,3] | +// | act [1] -> | | pre [0,1,2,3] | +// | act [1] -> | read [1] | | +// +-------------------+-------------------------+--------------------------+ +// | act [2] -> | write [2] | | +// | act [2] -> | | act [0,1,3] | +// | act [2] -> | | pre [0,1,2,3] | +// | act [2] -> | read [2] | | +// +-------------------+-------------------------+--------------------------+ +// | act [3] -> | write [3] | | +// | act [3] -> | | act [0,1,2] | +// | act [3] -> | | pre [0,1,2,3] | +// | act [3] -> | read [3] | | +// +-------------------+-------------------------+--------------------------+ +// | write/read [0] -> | | pre [0,1,2,3] | +// | write/read [0] -> | | act [1,2,3] | +// | write/read [0] -> | | write[0,1,2,3] | +// | write/read [0] -> | | read [0,1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | write/read [1] -> | | pre [0,1,2,3] | +// | write/read [1] -> | | act [0,2,3] | +// | write/read [1] -> | | write[0,1,2,3] | +// | write/read [1] -> | | read [0,1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | write/read [2] -> | | pre [0,1,2,3] | +// | write/read [2] -> | | act [0,1,3] | +// | write/read [2] -> | | write[0,1,2,3] | +// | write/read [2] -> | | read [0,1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | write/read [3] -> | | pre [0,1,2,3] | +// | write/read [3] -> | | act [0,1,2] | +// | write/read [3] -> | | write[0,1,2,3] | +// | write/read [3] -> | | read [0,1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// | pre_all -> | refr | | +// | | | | +// +-------------------+-------------------------+--------------------------+ +// | refr -> | | refr | +// | refr -> | | act[0,1,2,3] | +// +-------------------+-------------------------+--------------------------+ +// +// +// +// +-----------------+---------------+-----------------+---------------------+-----------+ +// | past command | control tread | current command | contol time value | note | +// +=================+===============+=================+=====================+===========+ +// | act [0] | 0 | pre [0] | Tras | | +// | write [0] | 1 | | Twr + Burst | 1,2,3 | +// | read [0] | 2 | | Burst | bank | +// | pre [1,2,3] | | | 0 | is | +// | act [1,2,3] | | | 0 | same | +// | write [1,2,3] | | | 0 | | +// | read [1,2,3] | | | 0 | | +// +-----------------+---------------+-----------------+---------------------+-----------+ +// | pre [0] | 3 [1]_ | act [0] | Trp | | +// | refr | 4 | | Trfc | 1,2,3 | +// | act [0] | 5 | | Trc | | +// | act [1,2,3] | 6 | | Trrd | bank | +// | pre [1,2,3] | | | 0 | is | +// | write [1,2,3] | | | 0 | same | +// | read [1,2,3] | | | 0 | | +// +-----------------+---------------+-----------------+---------------------+-----------+ +// | act [0] | 7 [1]_ | write [0] | Trcd | 1,2,3 | +// | write [0,1,2,3] | 8 | | Burst | bank | +// | read [0,1,2,3] | 9 | | Burst + CL + 1(?bta)| is | +// | | | | | same | +// +-----------------+---------------+-----------------+---------------------+-----------+ +// | act [0] | 10 [1]_ | read [0] | Trcd | 1,2,3 | +// | write [0,1,2,3] | 11 | | Burst + 1(?bta) | bank | +// | read [0,1,2,3] | 12 | | Burst | is | +// | | | | | same | +// +-----------------+---------------+-----------------+---------------------+-----------+ +// | pre_all | 13 | refr | Trp | | +// | refr | 14 | | Trfc | | +// +-----------------+---------------+-----------------+---------------------+-----------+ +// +// ..[1] Trp (pre -> act) & Trcd (act -> read/write) contolled internal in decoder FSM +// + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" +`include "hssdrc_timing.vh" + +module hssdrc_access_manager ( + clk , + reset , + sclr , + // + arb_pre_all , + arb_refr , + arb_pre , + arb_act , + arb_read , + arb_write , + arb_ba , + arb_burst , + // + am_pre_all_enable , + am_refr_enable , + am_pre_enable , + am_act_enable , + am_read_enable , + am_write_enable + ); + + input wire clk; + input wire reset; + input wire sclr; + + //-------------------------------------------------------------------------------------------------- + // interface from output arbiter + //-------------------------------------------------------------------------------------------------- + + input logic arb_pre_all ; + input logic arb_refr ; + input logic arb_pre ; + input logic arb_act ; + input logic arb_read ; + input logic arb_write ; + input ba_t arb_ba ; + input sdram_burst_t arb_burst ; + + //-------------------------------------------------------------------------------------------------- + // outputs + //-------------------------------------------------------------------------------------------------- + + output logic am_pre_all_enable ; + output logic am_refr_enable ; + output logic [0:3] am_pre_enable ; + output logic [0:3] am_act_enable ; + output logic [0:3] am_read_enable ; + output logic [0:3] am_write_enable ; + + + //-------------------------------------------------------------------------------------------------- + // all timings is select using shift register techique. + // enable is 1'b1 level on output. + // all shift is shift rigth. + // shift register command load pattern is 'b{{x{1'b0}}, {y{1'b1}}} + //-------------------------------------------------------------------------------------------------- + + //-------------------------------------------------------------------------------------------------- + // take into acount load shift register cycle + //-------------------------------------------------------------------------------------------------- + + localparam int cTras_m1 = cTras - 1; + localparam int cTrfc_m1 = cTrfc - 1; +// localparam int cTrc_m1 = cTrc - 1; tras + trp contolled +// localparam int cTrcd_m1 = cTrcd - 1; fsm contolled + localparam int cTwr_m1 = cTwr - 1; + localparam int cTrp_m1 = cTrp - 1; + localparam int cTrrd_m1 = cTrrd - 1; + localparam int cSdramBL_m1 = cSdramBL - 1; + + //-------------------------------------------------------------------------------------------------- + // tread 0/1/2 : Tras (act -> pre) & Twr + Burst (write -> pre) & Burst (read -> write) + // Twr + Burst & Burst control via one register becouse write/read has atomic access + //-------------------------------------------------------------------------------------------------- + + localparam int cPreActEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1); + localparam int cPreRwEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1); + + typedef logic [cPreActEnableLength-1:0] pre_act_enable_srl_t; + typedef logic [cPreRwEnableLength-1 :0] pre_rw_enable_srl_t; + + // to pre load patterns + localparam pre_act_enable_srl_t cPreActEnableInitValue = {cPreActEnableLength{1'b1}}; + localparam pre_act_enable_srl_t cPreActEnableActValue = PercentRelation(cTras_m1, cPreActEnableLength); + + // to pre load patterns + localparam pre_rw_enable_srl_t cPreRwEnableInitValue = {cPreRwEnableLength{1'b1}}; + + // Remember : burst already has -1 offset (!!!!) + function automatic pre_rw_enable_srl_t PreRwEnableWriteValue (input sdram_burst_t burst); + PreRwEnableWriteValue = PercentRelation (cTwr_m1 + burst, cPreRwEnableLength); + endfunction + + function automatic pre_rw_enable_srl_t PreRwEnableReadValue (input sdram_burst_t burst); + PreRwEnableReadValue = PercentRelation (burst, cPreRwEnableLength); + endfunction + + // each bank has own control registers + pre_act_enable_srl_t pre_act_enable_srl [0:3]; + pre_rw_enable_srl_t pre_rw_enable_srl [0:3]; + + wire [0:3] pre_enable ; + + genvar p; + + generate + + for (p = 0; p < 4; p++) begin : pre_enable_generate + + always_ff @(posedge clk or posedge reset) begin : pre_enable_shift_register + + if (reset) + pre_act_enable_srl [p] <= cPreActEnableInitValue; + else if (sclr) + pre_act_enable_srl [p] <= cPreActEnableInitValue; + else begin + if (arb_act && (arb_ba == p)) + pre_act_enable_srl [p] <= cPreActEnableActValue; + else + pre_act_enable_srl [p] <= (pre_act_enable_srl [p] << 1) | 1'b1; + end + + + if (reset) + pre_rw_enable_srl [p] <= cPreRwEnableInitValue; + else if (sclr) + pre_rw_enable_srl [p] <= cPreRwEnableInitValue; + else begin + if (arb_write && (arb_ba == p)) + pre_rw_enable_srl [p] <= PreRwEnableWriteValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1); + else if (arb_read && (arb_ba == p)) + pre_rw_enable_srl [p] <= PreRwEnableReadValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1); + else + pre_rw_enable_srl [p] <= (pre_rw_enable_srl [p] << 1) | 1'b1; + end + + end + + assign pre_enable [p] = pre_rw_enable_srl [p] [cPreRwEnableLength-1] ; + + end + + endgenerate + + //-------------------------------------------------------------------------------------------------- + // pre_all_enable has same logic as pre enable. + // pre_all_enable == &(pre_enable), but for increase performance it have own control registers + //-------------------------------------------------------------------------------------------------- + + pre_act_enable_srl_t pre_all_act_enable_srl ; + pre_rw_enable_srl_t pre_all_rw_enable_srl ; + + wire pre_all_enable; + + always_ff @(posedge clk or posedge reset) begin : pre_all_enable_shift_register + + if (reset) + pre_all_act_enable_srl <= cPreActEnableInitValue; + else if (sclr) + pre_all_act_enable_srl <= cPreActEnableInitValue; + else begin + if (arb_act) + pre_all_act_enable_srl <= cPreActEnableActValue; + else + pre_all_act_enable_srl <= (pre_all_act_enable_srl << 1) | 1'b1; + end + + + if (reset) + pre_all_rw_enable_srl <= cPreRwEnableInitValue; + else if (sclr) + pre_all_rw_enable_srl <= cPreRwEnableInitValue; + else begin + if (arb_write) + pre_all_rw_enable_srl <= PreRwEnableWriteValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1); + else if (arb_read) + pre_all_rw_enable_srl <= PreRwEnableReadValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1); + else + pre_all_rw_enable_srl <= (pre_all_rw_enable_srl << 1) | 1'b1; + end + + end + + assign pre_all_enable = pre_all_rw_enable_srl [cPreRwEnableLength-1]; + + //-------------------------------------------------------------------------------------------------- + // tread 4/5/6 : Trfc (refr -> act) & Trc (act -> act) & Trrd (act a -> act b) + // Trc don't need to be contolled, becouse Trc = Tras + Trcd + // Trfc & Trrd control via one register becouse refr -> any act has locked & sequental access. + // for Trc we can use 1 register, becouse act a -> act a is imposible sequence + //-------------------------------------------------------------------------------------------------- + + localparam int cActEnableLength = max (cTrfc_m1, cTrrd_m1); + + typedef logic [cActEnableLength-1:0] act_enable_srl_t; + + // to act load patterns + localparam act_enable_srl_t cActEnableInitValue = {cActEnableLength{1'b1}}; + localparam act_enable_srl_t cActEnableRefrValue = PercentRelation(cTrfc_m1, cActEnableLength); + localparam act_enable_srl_t cActEnableActValue = PercentRelation(cTrrd_m1, cActEnableLength); + + act_enable_srl_t act_enable_srl ; + + wire [0:3] act_enable ; + + always_ff @(posedge clk or posedge reset) begin : act_enable_shift_register + + if (reset) + act_enable_srl <= cActEnableInitValue; + else if (sclr) + act_enable_srl <= cActEnableInitValue; + else begin + + if (arb_refr) + act_enable_srl <= cActEnableRefrValue; + else if (arb_act) + act_enable_srl <= cActEnableActValue; + else + act_enable_srl <= (act_enable_srl << 1) | 1'b1; + + end + end + + assign act_enable = {4{act_enable_srl [cActEnableLength-1]}} ; + + //-------------------------------------------------------------------------------------------------- + // tread 8/9 : Burst (write -> write) & Burst + CL + BTA (read -> write). + // control via one register becouse write/read -> write is atomic sequental access. + //-------------------------------------------------------------------------------------------------- + + localparam int cWriteEnableLength = max (cSdramBL_m1, cSdramBL_m1 + pCL + pBTA); + + typedef logic [cWriteEnableLength-1:0] write_enable_srl_t; + + // to write load patterns + localparam write_enable_srl_t cWriteEnableInitValue = {cWriteEnableLength{1'b1}}; + + // Remember : burst already has -1 offset (!!!!) + function automatic write_enable_srl_t WriteEnableWriteValue (input sdram_burst_t burst); + WriteEnableWriteValue = PercentRelation(burst, cWriteEnableLength); + endfunction + + function automatic write_enable_srl_t WriteEnableReadValue (input sdram_burst_t burst); + WriteEnableReadValue = PercentRelation(burst + pCL + pBTA, cWriteEnableLength); + endfunction + + write_enable_srl_t write_enable_srl; + + wire [0:3] write_enable ; + + always_ff @(posedge clk or posedge reset) begin : write_enable_shift_register + + if (reset) + write_enable_srl <= cWriteEnableInitValue; + else if (sclr) + write_enable_srl <= cWriteEnableInitValue; + else begin + if (arb_write) + write_enable_srl <= WriteEnableWriteValue (arb_burst); + else if (arb_read) + write_enable_srl <= WriteEnableReadValue (arb_burst); + else + write_enable_srl <= (write_enable_srl << 1) | 1'b1; + end + end + + assign write_enable = {4{write_enable_srl [cWriteEnableLength-1]}}; + + //-------------------------------------------------------------------------------------------------- + // tread 11/12 : Burst + BTA (write -> read) & Burst (read -> read). + // contorl via one register becouse write/read -> read is atomic sequental access + // BTA from write -> read is not need !!! becouse read have read latency !!!! + //-------------------------------------------------------------------------------------------------- + + localparam int cReadEnableLength = max(cSdramBL_m1, cSdramBL_m1); + + typedef logic [cReadEnableLength-1:0] read_enable_srl_t; + + // to read load patterns + localparam read_enable_srl_t cReadEnableInitValue = {cReadEnableLength{1'b1}}; + // Remember : burst already has -1 offset (!!!!) + function automatic read_enable_srl_t ReadEnableWriteValue (input sdram_burst_t burst); + ReadEnableWriteValue = PercentRelation(burst, cReadEnableLength); + endfunction + + function automatic read_enable_srl_t ReadEnableReadValue (input sdram_burst_t burst); + ReadEnableReadValue = PercentRelation(burst, cReadEnableLength); + endfunction + + read_enable_srl_t read_enable_srl; + + wire [0:3] read_enable ; + + always_ff @(posedge clk or posedge reset) begin : read_enable_shift_register + + if (reset) + read_enable_srl <= cReadEnableInitValue; + else if (sclr) + read_enable_srl <= cReadEnableInitValue; + else begin + if (arb_write) + read_enable_srl <= ReadEnableWriteValue (arb_burst); + else if (arb_read) + read_enable_srl <= ReadEnableReadValue (arb_burst); + else + read_enable_srl <= (read_enable_srl << 1) | 1'b1; + end + + end + + assign read_enable = {4{read_enable_srl [cReadEnableLength-1]}}; + + //-------------------------------------------------------------------------------------------------- + // tread 13/14 : Trp (pre_all -> refr) & Trfc (refr -> refr). + // contol via one register becouse pre_all/refr has locked access & (pre_all -> refr) has sequental access + //-------------------------------------------------------------------------------------------------- + + localparam int cRefrEnableLength = max (cTrp_m1, cTrfc_m1); + + typedef logic [cRefrEnableLength-1:0] refr_enable_srl_t; + + // to refr load patterns + localparam refr_enable_srl_t cRefrEnableInitValue = {cRefrEnableLength{1'b1}}; + localparam refr_enable_srl_t cRefrEnablePreAllValue = PercentRelation( cTrp_m1, cRefrEnableLength); + localparam refr_enable_srl_t cRefrEnableRefrValue = PercentRelation(cTrfc_m1, cRefrEnableLength); + + refr_enable_srl_t refr_enable_srl; + + wire refr_enable; + + always_ff @(posedge clk or posedge reset) begin : refr_enable_shift_register + + if (reset) + refr_enable_srl <= cRefrEnableInitValue; + else if (sclr) + refr_enable_srl <= cRefrEnableInitValue; + else begin + if (arb_pre_all) + refr_enable_srl <= cRefrEnablePreAllValue; + else if (arb_refr) + refr_enable_srl <= cRefrEnableRefrValue; + else + refr_enable_srl <= (refr_enable_srl << 1) | 1'b1; + end + + end + + assign refr_enable = refr_enable_srl [cRefrEnableLength-1]; + + //-------------------------------------------------------------------------------------------------- + // output mapping + //-------------------------------------------------------------------------------------------------- + + assign am_pre_all_enable = pre_all_enable; + assign am_refr_enable = refr_enable; + assign am_act_enable = act_enable; + assign am_pre_enable = pre_enable; + assign am_write_enable = write_enable; + assign am_read_enable = read_enable; + + //-------------------------------------------------------------------------------------------------- + // function to generate 'b{{{data}1'b0}, {{length-data}{1'b1}}} shift register load pattern + //-------------------------------------------------------------------------------------------------- + + function automatic int unsigned PercentRelation (input int unsigned data, length); + int unsigned value; + int i; + int ones_num; + + value = 0; + ones_num = length - data; // number of ones from lsb in constant vector + for ( i = 0; i < length; i++) begin + if (i < ones_num) value[i] = 1'b1; + else value[i] = 1'b0; + end + + return value; + endfunction + + +endmodule +

hssdrc/trunk/rtl/hssdrc_access_manager.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_refr_counter.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_refr_counter.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_refr_counter.v (revision 3) @@ -0,0 +1,131 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_refr_counter.v +// +// Description : refresh time decode, counter based fsm +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_timing.vh" +`include "hssdrc_define.vh" + +module hssdrc_refr_counter ( + clk , + reset , + sclr , + ack , + hi_req , + low_req + ); + + input wire clk ; + input wire reset ; + input wire sclr ; + + input wire ack ; + output logic hi_req ; + output logic low_req ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + localparam cCntWidth = clogb2(cRefCounterMaxTime); + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + logic [cCntWidth-1 : 0] cnt; + + // + // + // + + always_ff @(posedge clk or posedge reset) begin : refresh_interval_counter + if (reset) + cnt <= '0; + else if (sclr | ack) + cnt <= '0; + else + cnt <= cnt + 1'b1; + end + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + +`ifdef HSSDRC_REFR_LOW_DISABLE + + assign low_req = 1'b0; + +`else + + always_ff @(posedge clk or posedge reset) begin : low_priopity_refresh_request_set + if (reset) + low_req <= 1'b0; + else if (sclr | ack) + low_req <= 1'b0; + else if (cnt > cRefrWindowLowPriorityTime) + low_req <= 1'b1; + end + +`endif + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + +`ifdef HSSDRC_REFR_HI_DISABLE + + assign hi_req = 1'b0; + +`else + + always_ff @(posedge clk or posedge reset) begin : high_priority_refresh_request_set + if (reset) + hi_req <= 1'b0; + else if (sclr | ack) + hi_req <= 1'b0; + else if (cnt > cRefrWindowHighPriorityTime) + hi_req <= 1'b1; + end + +`endif + + // + // + // +endmodule

hssdrc/trunk/rtl/hssdrc_refr_counter.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_arbiter_in.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_arbiter_in.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_arbiter_in.v (revision 3) @@ -0,0 +1,255 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_arbiter_in.v +// +// Description : input 3 way decode arbiter +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_arbiter_in ( + clk , + reset , + sclr , + // + sys_write , + sys_read , + sys_refr , + sys_rowa , + sys_cola , + sys_ba , + sys_burst , + sys_chid_i , + sys_ready , + // + refr_cnt_ack , + refr_cnt_hi_req , + refr_cnt_low_req , + // + dec0_write , + dec0_read , + dec0_refr , + dec0_rowa , + dec0_cola , + dec0_ba , + dec0_burst , + dec0_chid , + dec0_ready , + // + dec1_write , + dec1_read , + dec1_refr , + dec1_rowa , + dec1_cola , + dec1_ba , + dec1_burst , + dec1_chid , + dec1_ready , + // + dec2_write , + dec2_read , + dec2_refr , + dec2_rowa , + dec2_cola , + dec2_ba , + dec2_burst , + dec2_chid , + dec2_ready + ); + + input wire clk ; + input wire reset ; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // interface from refresh cycle generator + //-------------------------------------------------------------------------------------------------- + + output logic refr_cnt_ack ; + input wire refr_cnt_hi_req ; + input wire refr_cnt_low_req ; + + //-------------------------------------------------------------------------------------------------- + // interface from system + //-------------------------------------------------------------------------------------------------- + + input wire sys_write ; + input wire sys_read ; + input wire sys_refr ; + input rowa_t sys_rowa ; + input cola_t sys_cola ; + input ba_t sys_ba ; + input burst_t sys_burst ; + input chid_t sys_chid_i ; + output logic sys_ready ; + + //-------------------------------------------------------------------------------------------------- + // interface to sdram sequence decoders + //-------------------------------------------------------------------------------------------------- + + output logic dec0_write ; + output logic dec0_read ; + output logic dec0_refr ; + output rowa_t dec0_rowa ; + output cola_t dec0_cola ; + output ba_t dec0_ba ; + output burst_t dec0_burst ; + output chid_t dec0_chid ; + input wire dec0_ready ; + // + output logic dec1_write ; + output logic dec1_read ; + output logic dec1_refr ; + output rowa_t dec1_rowa ; + output cola_t dec1_cola ; + output ba_t dec1_ba ; + output burst_t dec1_burst ; + output chid_t dec1_chid ; + input wire dec1_ready ; + // + output logic dec2_write ; + output logic dec2_read ; + output logic dec2_refr ; + output rowa_t dec2_rowa ; + output cola_t dec2_cola ; + output ba_t dec2_ba ; + output burst_t dec2_burst ; + output chid_t dec2_chid ; + input wire dec2_ready ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + wire sys_lock ; + wire low_req_lock ; + wire arb_write ; + wire arb_read ; + wire arb_refr ; + wire arb_ready ; + wire arb_ack ; + wire arb_refr_ack ; + logic [2:0] arb; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + assign sys_lock = refr_cnt_hi_req; + assign low_req_lock = sys_write | sys_read | sys_refr; + + // + // + // + + assign arb_write = sys_write & ~sys_lock; + assign arb_read = sys_read & ~sys_lock; + assign arb_refr = sys_refr | refr_cnt_hi_req | (refr_cnt_low_req & ~low_req_lock); + assign arb_ready = dec0_ready | dec1_ready | dec2_ready; + + // + // + // + + assign arb_ack = arb_ready & (arb_write | arb_read | arb_refr); + assign arb_refr_ack = arb_ready & arb_refr ; + + // + // + // + + assign refr_cnt_ack = arb_refr_ack; + + // + // + // + + assign sys_ready = arb_ready & ~sys_lock; + + // + // + // + + always_ff @(posedge clk or posedge reset) begin : arbiter_logic + if (reset) + arb <= 3'b001; + else if (sclr) + arb <= 3'b001; + else if (arb_ack) + arb <= {arb[1:0], arb[2]}; + end + + // + // + // + + assign dec0_write = arb_write & arb[0]; + assign dec0_read = arb_read & arb[0]; + assign dec0_refr = arb_refr & arb[0]; + assign dec0_rowa = sys_rowa ; + assign dec0_cola = sys_cola ; + assign dec0_ba = sys_ba ; + assign dec0_burst = sys_burst ; + assign dec0_chid = sys_chid_i; + + // + // + // + + assign dec1_write = arb_write & arb[1]; + assign dec1_read = arb_read & arb[1]; + assign dec1_refr = arb_refr & arb[1]; + assign dec1_rowa = sys_rowa ; + assign dec1_cola = sys_cola ; + assign dec1_ba = sys_ba ; + assign dec1_burst = sys_burst ; + assign dec1_chid = sys_chid_i; + + // + // + // + + assign dec2_write = arb_write & arb[2]; + assign dec2_read = arb_read & arb[2]; + assign dec2_refr = arb_refr & arb[2]; + assign dec2_rowa = sys_rowa ; + assign dec2_cola = sys_cola ; + assign dec2_ba = sys_ba ; + assign dec2_burst = sys_burst ; + assign dec2_chid = sys_chid_i; + +endmodule

hssdrc/trunk/rtl/hssdrc_arbiter_in.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_arbiter_out.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_arbiter_out.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_arbiter_out.v (revision 3) @@ -0,0 +1,631 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_arbiter_out.v +// +// Description : output 3 way decode arbiter +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_arbiter_out ( + clk , + reset , + sclr , + // + dec0_pre_all , + dec0_refr , + dec0_pre , + dec0_act , + dec0_read , + dec0_write , + dec0_pre_all_enable, + dec0_refr_enable , + dec0_pre_enable , + dec0_act_enable , + dec0_read_enable , + dec0_write_enable , + dec0_locked , + dec0_last , + dec0_rowa , + dec0_cola , + dec0_ba , + dec0_chid , + dec0_burst , + // + dec1_pre_all , + dec1_refr , + dec1_pre , + dec1_act , + dec1_read , + dec1_write , + dec1_pre_all_enable, + dec1_refr_enable , + dec1_pre_enable , + dec1_act_enable , + dec1_read_enable , + dec1_write_enable , + dec1_locked , + dec1_last , + dec1_rowa , + dec1_cola , + dec1_ba , + dec1_chid , + dec1_burst , + // + dec2_pre_all , + dec2_refr , + dec2_pre , + dec2_act , + dec2_read , + dec2_write , + dec2_pre_all_enable, + dec2_refr_enable , + dec2_pre_enable , + dec2_act_enable , + dec2_read_enable , + dec2_write_enable , + dec2_locked , + dec2_last , + dec2_rowa , + dec2_cola , + dec2_ba , + dec2_chid , + dec2_burst , + // + am_pre_all_enable , + am_refr_enable , + am_pre_enable , + am_act_enable , + am_read_enable , + am_write_enable , + // + arb_pre_all , + arb_refr , + arb_pre , + arb_act , + arb_read , + arb_write , + arb_rowa , + arb_cola , + arb_ba , + arb_chid , + arb_burst + ); + + input wire clk ; + input wire reset; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // interface from sequence decoders + //-------------------------------------------------------------------------------------------------- + + input wire dec0_pre_all ; + input wire dec0_refr ; + input wire dec0_pre ; + input wire dec0_act ; + input wire dec0_read ; + input wire dec0_write ; + output logic dec0_pre_all_enable; + output logic dec0_refr_enable ; + output logic dec0_pre_enable ; + output logic dec0_act_enable ; + output logic dec0_read_enable ; + output logic dec0_write_enable ; + input wire dec0_locked ; + input wire dec0_last ; + input rowa_t dec0_rowa ; + input cola_t dec0_cola ; + input ba_t dec0_ba ; + input chid_t dec0_chid ; + input sdram_burst_t dec0_burst ; + // + input wire dec1_pre_all ; + input wire dec1_refr ; + input wire dec1_pre ; + input wire dec1_act ; + input wire dec1_read ; + input wire dec1_write ; + output logic dec1_pre_all_enable; + output logic dec1_refr_enable ; + output logic dec1_pre_enable ; + output logic dec1_act_enable ; + output logic dec1_read_enable ; + output logic dec1_write_enable ; + input wire dec1_locked ; + input wire dec1_last ; + input rowa_t dec1_rowa ; + input cola_t dec1_cola ; + input ba_t dec1_ba ; + input chid_t dec1_chid ; + input sdram_burst_t dec1_burst ; + // + input wire dec2_pre_all ; + input wire dec2_refr ; + input wire dec2_pre ; + input wire dec2_act ; + input wire dec2_read ; + input wire dec2_write ; + output logic dec2_pre_all_enable; + output logic dec2_refr_enable ; + output logic dec2_pre_enable ; + output logic dec2_act_enable ; + output logic dec2_read_enable ; + output logic dec2_write_enable ; + input wire dec2_locked ; + input wire dec2_last ; + input rowa_t dec2_rowa ; + input cola_t dec2_cola ; + input ba_t dec2_ba ; + input chid_t dec2_chid ; + input sdram_burst_t dec2_burst ; + + //-------------------------------------------------------------------------------------------------- + // interface from access manager + //-------------------------------------------------------------------------------------------------- + + input wire am_pre_all_enable ; + input wire am_refr_enable ; + input wire [0:3] am_pre_enable ; + input wire [0:3] am_act_enable ; + input wire [0:3] am_read_enable ; + input wire [0:3] am_write_enable ; + + //-------------------------------------------------------------------------------------------------- + // interface to multiplexer + //-------------------------------------------------------------------------------------------------- + + output logic arb_pre_all ; + output logic arb_refr ; + output logic arb_pre ; + output logic arb_act ; + output logic arb_read ; + output logic arb_write ; + output rowa_t arb_rowa ; + output cola_t arb_cola ; + output ba_t arb_ba ; + output chid_t arb_chid ; + output sdram_burst_t arb_burst ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + enum bit [1:0] {ARB0, ARB1, ARB2} arb, ba_rowa_mux; + + logic arb_ack; + + logic dec0_access_enable; + logic dec1_access_enable; + logic dec2_access_enable; + + logic dec0_bank_access_enable; + logic dec1_bank_access_enable; + logic dec2_bank_access_enable; + + logic dec1_can_have_access_when_arb_is_0 ; + logic dec2_can_have_access_when_arb_is_0 ; + + logic dec2_can_have_access_when_arb_is_1 ; + logic dec0_can_have_access_when_arb_is_1 ; + + logic dec0_can_have_access_when_arb_is_2 ; + logic dec1_can_have_access_when_arb_is_2 ; + + logic dec0_access_done; + logic dec1_access_done; + logic dec2_access_done; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : arbiter_logic + if (reset) + arb <= ARB0; + else if (sclr) + arb <= ARB0; + else if (arb_ack) + unique case (arb) + ARB0 : arb <= ARB1; + ARB1 : arb <= ARB2; + ARB2 : arb <= ARB0; + endcase + end + + // + // + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + // use act command sharing + assign dec0_bank_access_enable = (dec0_pre & am_pre_enable [dec0_ba] ) | + (dec0_act & am_act_enable [dec0_ba] ) ; + + assign dec1_bank_access_enable = (dec1_pre & am_pre_enable [dec1_ba] ) | + (dec1_act & am_act_enable [dec1_ba] ) ; + + assign dec2_bank_access_enable = (dec2_pre & am_pre_enable [dec2_ba] ) | + (dec2_act & am_act_enable [dec2_ba] ) ; + `else + // not use act command sharing + assign dec0_bank_access_enable = (dec0_pre & am_pre_enable [dec0_ba] ) ; + + assign dec1_bank_access_enable = (dec1_pre & am_pre_enable [dec1_ba] ) ; + + assign dec2_bank_access_enable = (dec2_pre & am_pre_enable [dec2_ba] ) ; + `endif + // + // + // + assign dec0_access_enable = (dec0_read & am_read_enable [dec0_ba] ) | + (dec0_write & am_write_enable [dec0_ba] ) | + (dec0_pre & am_pre_enable [dec0_ba] ) | + (dec0_act & am_act_enable [dec0_ba] ) ; + + assign dec1_access_enable = (dec1_read & am_read_enable [dec1_ba] ) | + (dec1_write & am_write_enable [dec1_ba] ) | + (dec1_pre & am_pre_enable [dec1_ba] ) | + (dec1_act & am_act_enable [dec1_ba] ) ; + + + assign dec2_access_enable = (dec2_read & am_read_enable [dec2_ba] ) | + (dec2_write & am_write_enable [dec2_ba] ) | + (dec2_pre & am_pre_enable [dec2_ba] ) | + (dec2_act & am_act_enable [dec2_ba] ) ; + // + // + // + assign dec0_access_done = (dec0_refr & dec0_refr_enable) | + (dec0_last & + ((dec0_read & dec0_read_enable ) | + ( dec0_write & dec0_write_enable )) + ); + + assign dec1_access_done = (dec1_refr & dec1_refr_enable) | + (dec1_last & + ((dec1_read & dec1_read_enable ) | + ( dec1_write & dec1_write_enable )) + ); + + assign dec2_access_done = (dec2_refr & dec2_refr_enable) | + (dec2_last & + ((dec2_read & dec2_read_enable ) | + ( dec2_write & dec2_write_enable )) + ); + // + // + // + assign arb_ack = (dec0_access_done && (arb == ARB0)) | + (dec1_access_done && (arb == ARB1)) | + (dec2_access_done && (arb == ARB2)); + //-------------------------------------------------------------------------------------------------- + // decoder roundabout : dec0 -> dec1 -> dec2 -> dec0 -> dec1 + // + // arbiter for command pipeline need in folow comparators : + // 0 : dec0 - dec1 -> select dec1 + // : dec0 - dec2 & dec1 - dec2 -> select dec2 + // 1 : dec1 - dec2 -> select dec2 + // : dec1 - dec2 & dec2 - dec0 -> select dec0 + // 2 : dec2 - dec0 -> select dec0 + // : dec2 - dec1 & dec0 - dec1 -> select dec1 + // we can reclock it. becouse "ba" and "locked" is valid 1 tick before command + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk) begin : locked_and_bank_access_comparator + dec1_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec1_ba != dec0_ba); + dec2_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec2_ba != dec0_ba) & ~dec1_locked & (dec2_ba != dec1_ba); + + dec2_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec2_ba != dec1_ba); + dec0_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec0_ba != dec1_ba) & ~dec2_locked & (dec0_ba != dec2_ba); + + dec0_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec0_ba != dec2_ba); + dec1_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec1_ba != dec2_ba) & ~dec0_locked & (dec1_ba != dec0_ba); + end + + // + // + // + + always_comb begin : control_path_arbiter + + dec0_pre_all_enable = 1'b0; + dec0_refr_enable = 1'b0; + dec0_pre_enable = 1'b0; + dec0_act_enable = 1'b0; + dec0_read_enable = 1'b0; + dec0_write_enable = 1'b0; + + dec1_pre_all_enable = 1'b0; + dec1_refr_enable = 1'b0; + dec1_pre_enable = 1'b0; + dec1_act_enable = 1'b0; + dec1_read_enable = 1'b0; + dec1_write_enable = 1'b0; + + dec2_pre_all_enable = 1'b0; + dec2_refr_enable = 1'b0; + dec2_pre_enable = 1'b0; + dec2_act_enable = 1'b0; + dec2_read_enable = 1'b0; + dec2_write_enable = 1'b0; + + arb_pre_all = 1'b0; + arb_refr = 1'b0; + arb_pre = 1'b0; + arb_act = 1'b0; + arb_read = 1'b0; + arb_write = 1'b0; + + ba_rowa_mux = arb; + + unique case (arb) + ARB0 : begin : dec0_is_master + + dec0_pre_all_enable = am_pre_all_enable ; + dec0_refr_enable = am_refr_enable ; + dec0_pre_enable = am_pre_enable [dec0_ba]; + dec0_act_enable = am_act_enable [dec0_ba]; + dec0_read_enable = am_read_enable [dec0_ba]; + dec0_write_enable = am_write_enable [dec0_ba]; + + arb_pre_all = dec0_pre_all & dec0_pre_all_enable ; + arb_refr = dec0_refr & dec0_refr_enable ; + arb_pre = dec0_pre & dec0_pre_enable ; + arb_act = dec0_act & dec0_act_enable ; + arb_read = dec0_read & dec0_read_enable ; + arb_write = dec0_write & dec0_write_enable ; + +`ifndef HSSDRC_SHARE_NONE_DECODER + + if (~dec0_access_enable) begin + + if (dec1_can_have_access_when_arb_is_0) begin + + ba_rowa_mux = ARB1; + // + dec1_pre_enable = am_pre_enable [dec1_ba]; + + arb_pre = dec1_pre & dec1_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec1_act_enable = am_act_enable [dec1_ba]; + + arb_act = dec1_act & dec1_act_enable ; + `endif + + end + + `ifndef HSSDRC_SHARE_ONE_DECODER + if (~dec1_bank_access_enable & dec2_can_have_access_when_arb_is_0) begin + `else + else if (dec2_can_have_access_when_arb_is_0) begin + `endif + ba_rowa_mux = ARB2; + // + dec2_pre_enable = am_pre_enable [dec2_ba]; + + arb_pre = dec2_pre & dec2_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec2_act_enable = am_act_enable [dec2_ba]; + + arb_act = dec2_act & dec2_act_enable ; + `endif + + end + end +`endif // HSSDRC_SHARE_NONE_DECODER + end + + ARB1 : begin : dec1_is_master + + dec1_pre_all_enable = am_pre_all_enable ; + dec1_refr_enable = am_refr_enable ; + dec1_pre_enable = am_pre_enable [dec1_ba]; + dec1_act_enable = am_act_enable [dec1_ba]; + dec1_read_enable = am_read_enable [dec1_ba]; + dec1_write_enable = am_write_enable [dec1_ba]; + + arb_pre_all = dec1_pre_all & dec1_pre_all_enable ; + arb_refr = dec1_refr & dec1_refr_enable ; + arb_pre = dec1_pre & dec1_pre_enable ; + arb_act = dec1_act & dec1_act_enable ; + arb_read = dec1_read & dec1_read_enable ; + arb_write = dec1_write & dec1_write_enable ; + +`ifndef HSSDRC_SHARE_NONE_DECODER + + if (~dec1_access_enable) begin + + if (dec2_can_have_access_when_arb_is_1) begin + + ba_rowa_mux = ARB2; + // + dec2_pre_enable = am_pre_enable [dec2_ba]; + + arb_pre = dec2_pre & dec2_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec2_act_enable = am_act_enable [dec2_ba]; + + arb_act = dec2_act & dec2_act_enable ; + `endif + + end + + `ifndef HSSDRC_SHARE_ONE_DECODER + if (~dec2_bank_access_enable & dec0_can_have_access_when_arb_is_1) begin + `else + else if (dec0_can_have_access_when_arb_is_1) begin + `endif + ba_rowa_mux = ARB0; + // + dec0_pre_enable = am_pre_enable [dec0_ba]; + + arb_pre = dec0_pre & dec0_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec0_act_enable = am_act_enable [dec0_ba]; + + arb_act = dec0_act & dec0_act_enable ; + `endif + + end + end +`endif // HSSDRC_SHARE_NONE_DECODER + end + + ARB2 : begin : dec2_is_master + + dec2_pre_all_enable = am_pre_all_enable ; + dec2_refr_enable = am_refr_enable ; + dec2_pre_enable = am_pre_enable [dec2_ba] ; + dec2_act_enable = am_act_enable [dec2_ba] ; + dec2_read_enable = am_read_enable [dec2_ba] ; + dec2_write_enable = am_write_enable [dec2_ba] ; + + arb_pre_all = dec2_pre_all & dec2_pre_all_enable ; + arb_refr = dec2_refr & dec2_refr_enable ; + arb_pre = dec2_pre & dec2_pre_enable ; + arb_act = dec2_act & dec2_act_enable ; + arb_read = dec2_read & dec2_read_enable ; + arb_write = dec2_write & dec2_write_enable ; + +`ifndef HSSDRC_SHARE_NONE_DECODER + + if (~dec2_access_enable) begin + + if (dec0_can_have_access_when_arb_is_2) begin + + ba_rowa_mux = ARB0; + // + dec0_pre_enable = am_pre_enable [dec0_ba]; + + arb_pre = dec0_pre & dec0_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec0_act_enable = am_act_enable [dec0_ba]; + + arb_act = dec0_act & dec0_act_enable ; + `endif + + end + + `ifndef HSSDRC_SHARE_ONE_DECODER + if (~dec0_bank_access_enable & dec1_can_have_access_when_arb_is_2) begin + `else + else if (dec1_can_have_access_when_arb_is_2) begin + `endif + ba_rowa_mux = ARB1; + // + dec1_pre_enable = am_pre_enable [dec1_ba]; + + arb_pre = dec1_pre & dec1_pre_enable ; + // + `ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + dec1_act_enable = am_act_enable [dec1_ba]; + + arb_act = dec1_act & dec1_act_enable ; + `endif + + end + end +`endif // HSSDRC_SHARE_NONE_DECODER + end + endcase + end + + + + always_comb begin : mux_addr_path2arbiter + + // + // no complex mux : used in read/write command + // + + arb_cola = dec0_cola; + arb_chid = dec0_chid; + arb_burst = dec0_burst; + + unique case (arb) + ARB0 : begin + arb_cola = dec0_cola; + arb_chid = dec0_chid; + arb_burst = dec0_burst; + end + ARB1 : begin + arb_cola = dec1_cola; + arb_chid = dec1_chid; + arb_burst = dec1_burst; + end + ARB2 : begin + arb_cola = dec2_cola; + arb_chid = dec2_chid; + arb_burst = dec2_burst; + end + default : begin end + endcase + + // + // complex mux used in pre command + // + + arb_ba = dec0_ba; + + unique case (ba_rowa_mux) + ARB0 : arb_ba = dec0_ba; + ARB1 : arb_ba = dec1_ba; + ARB2 : arb_ba = dec2_ba; + endcase + + // + // complex mux used in act command + // + + arb_rowa = dec0_rowa; + +`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND + unique case (ba_rowa_mux) +`else + unique case (arb) +`endif + ARB0 : arb_rowa = dec0_rowa; + ARB1 : arb_rowa = dec1_rowa; + ARB2 : arb_rowa = dec2_rowa; + endcase + + end + +endmodule

hssdrc/trunk/rtl/hssdrc_arbiter_out.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_ba_map.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_ba_map.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_ba_map.v (revision 3) @@ -0,0 +1,136 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_ba_map.v +// +// Description : bank & row map unit +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_ba_map ( + clk , + reset , + sclr , + // + update , + clear , + ba , + rowa , + // + pre_act_rw , + act_rw , + rw , + all_close + + ); + + input wire clk ; + input wire reset ; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // interface from sequence decoders + //-------------------------------------------------------------------------------------------------- + + input wire update ; + input wire clear ; + input ba_t ba ; + input rowa_t rowa ; + + //-------------------------------------------------------------------------------------------------- + // interface to sequence decoders + //-------------------------------------------------------------------------------------------------- + + output logic pre_act_rw ; + output logic act_rw ; + output logic rw ; + output logic all_close ; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + logic [3:0] bank_open; + rowa_t row_open [0:3]; + wire bank_is_open; + wire row_is_open; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + always_ff @(posedge clk or posedge reset) begin : bank_open_map_process + if (reset) + bank_open <= '0; + else if (sclr) + bank_open <= '0; + else begin + if (clear) + bank_open <= '0; + else if (update) + bank_open [ba] <= 1'b1; + else begin + end + end + end + + // + // + // + + always_ff @(posedge clk) begin : row_open_map_process + if (update) + row_open[ba] <= rowa; + end + + // + // + // + + assign bank_is_open = bank_open [ba]; + assign row_is_open = (row_open [ba] == rowa); + + // + // + // + + assign rw = bank_is_open & row_is_open; + assign pre_act_rw = bank_is_open & ~row_is_open; + assign act_rw = ~bank_is_open; + assign all_close = (bank_open == 0); + +endmodule

hssdrc/trunk/rtl/hssdrc_ba_map.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_top.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_top.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_top.v (revision 3) @@ -0,0 +1,758 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_top.v +// +// Description : top level of memory controller +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_define.vh" + +module hssdrc_top ( + clk , + reset , + sclr , + sys_write , + sys_read , + sys_refr , + sys_rowa , + sys_cola , + sys_ba , + sys_burst , + sys_chid_i , + sys_wdata , + sys_wdatam , + sys_ready , + sys_use_wdata , + sys_vld_rdata , + sys_chid_o , + sys_rdata , + dq , + dqm , + addr , + ba , + cke , + cs_n , + ras_n , + cas_n , + we_n + ); + + input wire clk ; + input wire reset; + input wire sclr ; + + //-------------------------------------------------------------------------------------------------- + // system interface + //-------------------------------------------------------------------------------------------------- + + input wire sys_write ; + input wire sys_read ; + input wire sys_refr ; + input rowa_t sys_rowa ; + input cola_t sys_cola ; + input ba_t sys_ba ; + input burst_t sys_burst ; + input chid_t sys_chid_i ; + input data_t sys_wdata ; + input datam_t sys_wdatam ; + + output logic sys_ready ; + output logic sys_use_wdata ; + output logic sys_vld_rdata ; + output chid_t sys_chid_o ; + output data_t sys_rdata ; + + //-------------------------------------------------------------------------------------------------- + // sdram interface + //-------------------------------------------------------------------------------------------------- + + inout wire [pDataBits-1:0] dq; + output datam_t dqm; + output sdram_addr_t addr; + output ba_t ba; + output logic cke; + output logic cs_n; + output logic ras_n; + output logic cas_n; + output logic we_n; + + //-------------------------------------------------------------------------------------------------- + // internal signals + //-------------------------------------------------------------------------------------------------- + + wire init_done; + wire hssdrc_sclr; + + //-------------------------------------------------------------------------------------------------- + // refr_cnt <-> arbiter_in + //-------------------------------------------------------------------------------------------------- + + wire refr_cnt___ack ; + wire refr_cnt___hi_req ; + wire refr_cnt___low_req ; + + //-------------------------------------------------------------------------------------------------- + // arbiter_in <-> decoder's + //-------------------------------------------------------------------------------------------------- + + wire arbiter_in0___write ; + wire arbiter_in0___read ; + wire arbiter_in0___refr ; + rowa_t arbiter_in0___rowa ; + cola_t arbiter_in0___cola ; + ba_t arbiter_in0___ba ; + burst_t arbiter_in0___burst ; + chid_t arbiter_in0___chid ; + wire arbiter_in0___ready ; + // + wire arbiter_in1___write ; + wire arbiter_in1___read ; + wire arbiter_in1___refr ; + rowa_t arbiter_in1___rowa ; + cola_t arbiter_in1___cola ; + ba_t arbiter_in1___ba ; + burst_t arbiter_in1___burst ; + chid_t arbiter_in1___chid ; + wire arbiter_in1___ready ; + // + wire arbiter_in2___write ; + wire arbiter_in2___read ; + wire arbiter_in2___refr ; + rowa_t arbiter_in2___rowa ; + cola_t arbiter_in2___cola ; + ba_t arbiter_in2___ba ; + burst_t arbiter_in2___burst ; + chid_t arbiter_in2___chid ; + wire arbiter_in2___ready ; + + //-------------------------------------------------------------------------------------------------- + // ba_map <-> decoder's + //-------------------------------------------------------------------------------------------------- + + wire ba_map___update ; + wire ba_map___clear ; + ba_t ba_map___ba ; + rowa_t ba_map___rowa ; + wire ba_map___pre_act_rw ; + wire ba_map___act_rw ; + wire ba_map___rw ; + wire ba_map___all_close ; + + //-------------------------------------------------------------------------------------------------- + // decoder's <-> arbiter_out + //-------------------------------------------------------------------------------------------------- + + wire dec0___pre_all ; + wire dec0___refr ; + wire dec0___pre ; + wire dec0___act ; + wire dec0___read ; + wire dec0___write ; + wire dec0___pre_all_enable ; + wire dec0___refr_enable ; + wire dec0___pre_enable ; + wire dec0___act_enable ; + wire dec0___read_enable ; + wire dec0___write_enable ; + wire dec0___locked ; + wire dec0___last ; + rowa_t dec0___rowa ; + cola_t dec0___cola ; + ba_t dec0___ba ; + chid_t dec0___chid ; + sdram_burst_t dec0___burst ; + // + wire dec1___pre_all ; + wire dec1___refr ; + wire dec1___pre ; + wire dec1___act ; + wire dec1___read ; + wire dec1___write ; + wire dec1___pre_all_enable ; + wire dec1___refr_enable ; + wire dec1___pre_enable ; + wire dec1___act_enable ; + wire dec1___read_enable ; + wire dec1___write_enable ; + wire dec1___locked ; + wire dec1___last ; + rowa_t dec1___rowa ; + cola_t dec1___cola ; + ba_t dec1___ba ; + chid_t dec1___chid ; + sdram_burst_t dec1___burst ; + // + wire dec2___pre_all ; + wire dec2___refr ; + wire dec2___pre ; + wire dec2___act ; + wire dec2___read ; + wire dec2___write ; + wire dec2___pre_all_enable ; + wire dec2___refr_enable ; + wire dec2___pre_enable ; + wire dec2___act_enable ; + wire dec2___read_enable ; + wire dec2___write_enable ; + wire dec2___locked ; + wire dec2___last ; + rowa_t dec2___rowa ; + cola_t dec2___cola ; + ba_t dec2___ba ; + chid_t dec2___chid ; + sdram_burst_t dec2___burst ; + + //-------------------------------------------------------------------------------------------------- + // access_manager -> arbiter_out + //-------------------------------------------------------------------------------------------------- + + wire access_manager___pre_all_enable ; + wire access_manager___refr_enable ; + wire [0:3] access_manager___pre_enable ; + wire [0:3] access_manager___act_enable ; + wire [0:3] access_manager___read_enable ; + wire [0:3] access_manager___write_enable ; + + //-------------------------------------------------------------------------------------------------- + // arbiter_out -> multiplexer/access_manager + //-------------------------------------------------------------------------------------------------- + + wire arbiter_out___pre_all ; + wire arbiter_out___refr ; + wire arbiter_out___pre ; + wire arbiter_out___act ; + wire arbiter_out___read ; + wire arbiter_out___write ; + rowa_t arbiter_out___rowa ; + cola_t arbiter_out___cola ; + ba_t arbiter_out___ba ; + chid_t arbiter_out___chid ; + sdram_burst_t arbiter_out___burst ; + + //-------------------------------------------------------------------------------------------------- + // init_state -> multiplexer + //-------------------------------------------------------------------------------------------------- + + wire init_state___pre_all ; + wire init_state___refr ; + wire init_state___lmr ; + rowa_t init_state___rowa ; + + //-------------------------------------------------------------------------------------------------- + // multiplexer -> sdram_addr_path/sdram_data_path + //-------------------------------------------------------------------------------------------------- + + wire mux___pre_all ; + wire mux___refr ; + wire mux___pre ; + wire mux___act ; + wire mux___read ; + wire mux___write ; + wire mux___lmr ; + rowa_t mux___rowa ; + cola_t mux___cola ; + ba_t mux___ba ; + chid_t mux___chid ; + sdram_burst_t mux___burst ; + + // + // this clear use to disable fsm that must be off when sdram chip is not configured + // + + assign hssdrc_sclr = sclr | ~init_done; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + hssdrc_refr_counter refr_cnt( + .clk (clk ), + .reset (reset), + .sclr (hssdrc_sclr ), // use internal sclr becouse there is refresh "fsm" + .ack (refr_cnt___ack ), + .hi_req (refr_cnt___hi_req ), + .low_req (refr_cnt___low_req) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_arbiter_in arbiter_in ( + .clk (clk ), + .reset (reset), + .sclr (hssdrc_sclr ), // use internal sclr becouse there is arbiter fsm + // + .sys_write (sys_write ) , + .sys_read (sys_read ) , + .sys_refr (sys_refr ) , + .sys_rowa (sys_rowa ) , + .sys_cola (sys_cola ) , + .sys_ba (sys_ba ) , + .sys_burst (sys_burst ) , + .sys_chid_i (sys_chid_i) , + .sys_ready (sys_ready ) , + // + .refr_cnt_ack (refr_cnt___ack ), + .refr_cnt_hi_req (refr_cnt___hi_req ), + .refr_cnt_low_req (refr_cnt___low_req), + // + .dec0_write (arbiter_in0___write), + .dec0_read (arbiter_in0___read ), + .dec0_refr (arbiter_in0___refr ), + .dec0_rowa (arbiter_in0___rowa ), + .dec0_cola (arbiter_in0___cola ), + .dec0_ba (arbiter_in0___ba ), + .dec0_burst (arbiter_in0___burst), + .dec0_chid (arbiter_in0___chid ), + .dec0_ready (arbiter_in0___ready), + // + .dec1_write (arbiter_in1___write), + .dec1_read (arbiter_in1___read ), + .dec1_refr (arbiter_in1___refr ), + .dec1_rowa (arbiter_in1___rowa ), + .dec1_cola (arbiter_in1___cola ), + .dec1_ba (arbiter_in1___ba ), + .dec1_burst (arbiter_in1___burst), + .dec1_chid (arbiter_in1___chid ), + .dec1_ready (arbiter_in1___ready), + // + .dec2_write (arbiter_in2___write), + .dec2_read (arbiter_in2___read ), + .dec2_refr (arbiter_in2___refr ), + .dec2_rowa (arbiter_in2___rowa ), + .dec2_cola (arbiter_in2___cola ), + .dec2_ba (arbiter_in2___ba ), + .dec2_burst (arbiter_in2___burst), + .dec2_chid (arbiter_in2___chid ), + .dec2_ready (arbiter_in2___ready) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_ba_map ba_map ( + .clk (clk ), + .reset (reset), + .sclr (hssdrc_sclr), // use internal sclr becouse there is bank access map + // + .update (ba_map___update), + .clear (ba_map___clear ), + .ba (ba_map___ba ), + .rowa (ba_map___rowa ), + // + .pre_act_rw (ba_map___pre_act_rw), + .act_rw (ba_map___act_rw ), + .rw (ba_map___rw ), + .all_close (ba_map___all_close ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_decoder decoder ( + .clk (clk ), + .reset (reset), + .sclr (hssdrc_sclr), // use internal sclr becouse there is decoders fsm + // + .ba_map_update (ba_map___update ), + .ba_map_clear (ba_map___clear ), + .ba_map_ba (ba_map___ba ), + .ba_map_rowa (ba_map___rowa ), + // + .ba_map_pre_act_rw (ba_map___pre_act_rw), + .ba_map_act_rw (ba_map___act_rw ), + .ba_map_rw (ba_map___rw ), + .ba_map_all_close (ba_map___all_close ), + // + .arb0_write (arbiter_in0___write), + .arb0_read (arbiter_in0___read ), + .arb0_refr (arbiter_in0___refr ), + .arb0_rowa (arbiter_in0___rowa ), + .arb0_cola (arbiter_in0___cola ), + .arb0_ba (arbiter_in0___ba ), + .arb0_burst (arbiter_in0___burst), + .arb0_chid (arbiter_in0___chid ), + .arb0_ready (arbiter_in0___ready), + // + .arb1_write (arbiter_in1___write), + .arb1_read (arbiter_in1___read ), + .arb1_refr (arbiter_in1___refr ), + .arb1_rowa (arbiter_in1___rowa ), + .arb1_cola (arbiter_in1___cola ), + .arb1_ba (arbiter_in1___ba ), + .arb1_burst (arbiter_in1___burst), + .arb1_chid (arbiter_in1___chid ), + .arb1_ready (arbiter_in1___ready), + // + .arb2_write (arbiter_in2___write), + .arb2_read (arbiter_in2___read ), + .arb2_refr (arbiter_in2___refr ), + .arb2_rowa (arbiter_in2___rowa ), + .arb2_cola (arbiter_in2___cola ), + .arb2_ba (arbiter_in2___ba ), + .arb2_burst (arbiter_in2___burst), + .arb2_chid (arbiter_in2___chid ), + .arb2_ready (arbiter_in2___ready), + // + .dec0_pre_all (dec0___pre_all ), + .dec0_refr (dec0___refr ), + .dec0_pre (dec0___pre ), + .dec0_act (dec0___act ), + .dec0_read (dec0___read ), + .dec0_write (dec0___write ), + .dec0_pre_all_enable(dec0___pre_all_enable), + .dec0_refr_enable (dec0___refr_enable ), + .dec0_pre_enable (dec0___pre_enable ), + .dec0_act_enable (dec0___act_enable ), + .dec0_read_enable (dec0___read_enable ), + .dec0_write_enable (dec0___write_enable ), + .dec0_locked (dec0___locked ), + .dec0_last (dec0___last ), + .dec0_rowa (dec0___rowa ), + .dec0_cola (dec0___cola ), + .dec0_ba (dec0___ba ), + .dec0_chid (dec0___chid ), + .dec0_burst (dec0___burst ), + // + .dec1_pre_all (dec1___pre_all ), + .dec1_refr (dec1___refr ), + .dec1_pre (dec1___pre ), + .dec1_act (dec1___act ), + .dec1_read (dec1___read ), + .dec1_write (dec1___write ), + .dec1_pre_all_enable(dec1___pre_all_enable), + .dec1_refr_enable (dec1___refr_enable ), + .dec1_pre_enable (dec1___pre_enable ), + .dec1_act_enable (dec1___act_enable ), + .dec1_read_enable (dec1___read_enable ), + .dec1_write_enable (dec1___write_enable ), + .dec1_locked (dec1___locked ), + .dec1_last (dec1___last ), + .dec1_rowa (dec1___rowa ), + .dec1_cola (dec1___cola ), + .dec1_ba (dec1___ba ), + .dec1_chid (dec1___chid ), + .dec1_burst (dec1___burst ), + // + .dec2_pre_all (dec2___pre_all ), + .dec2_refr (dec2___refr ), + .dec2_pre (dec2___pre ), + .dec2_act (dec2___act ), + .dec2_read (dec2___read ), + .dec2_write (dec2___write ), + .dec2_pre_all_enable(dec2___pre_all_enable), + .dec2_refr_enable (dec2___refr_enable ), + .dec2_pre_enable (dec2___pre_enable ), + .dec2_act_enable (dec2___act_enable ), + .dec2_read_enable (dec2___read_enable ), + .dec2_write_enable (dec2___write_enable ), + .dec2_locked (dec2___locked ), + .dec2_last (dec2___last ), + .dec2_rowa (dec2___rowa ), + .dec2_cola (dec2___cola ), + .dec2_ba (dec2___ba ), + .dec2_chid (dec2___chid ), + .dec2_burst (dec2___burst ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_arbiter_out arbiter_out( + .clk (clk), + .reset (reset), + .sclr (hssdrc_sclr), // use internal sclr becouse there is arbiter fsm + // + .dec0_pre_all (dec0___pre_all ), + .dec0_refr (dec0___refr ), + .dec0_pre (dec0___pre ), + .dec0_act (dec0___act ), + .dec0_read (dec0___read ), + .dec0_write (dec0___write ), + .dec0_pre_all_enable(dec0___pre_all_enable), + .dec0_refr_enable (dec0___refr_enable ), + .dec0_pre_enable (dec0___pre_enable ), + .dec0_act_enable (dec0___act_enable ), + .dec0_read_enable (dec0___read_enable ), + .dec0_write_enable (dec0___write_enable ), + .dec0_locked (dec0___locked ), + .dec0_last (dec0___last ), + .dec0_rowa (dec0___rowa ), + .dec0_cola (dec0___cola ), + .dec0_ba (dec0___ba ), + .dec0_chid (dec0___chid ), + .dec0_burst (dec0___burst ), + // + .dec1_pre_all (dec1___pre_all ), + .dec1_refr (dec1___refr ), + .dec1_pre (dec1___pre ), + .dec1_act (dec1___act ), + .dec1_read (dec1___read ), + .dec1_write (dec1___write ), + .dec1_pre_all_enable(dec1___pre_all_enable), + .dec1_refr_enable (dec1___refr_enable ), + .dec1_pre_enable (dec1___pre_enable ), + .dec1_act_enable (dec1___act_enable ), + .dec1_read_enable (dec1___read_enable ), + .dec1_write_enable (dec1___write_enable ), + .dec1_locked (dec1___locked ), + .dec1_last (dec1___last ), + .dec1_rowa (dec1___rowa ), + .dec1_cola (dec1___cola ), + .dec1_ba (dec1___ba ), + .dec1_chid (dec1___chid ), + .dec1_burst (dec1___burst ), + // + .dec2_pre_all (dec2___pre_all ), + .dec2_refr (dec2___refr ), + .dec2_pre (dec2___pre ), + .dec2_act (dec2___act ), + .dec2_read (dec2___read ), + .dec2_write (dec2___write ), + .dec2_pre_all_enable(dec2___pre_all_enable), + .dec2_refr_enable (dec2___refr_enable ), + .dec2_pre_enable (dec2___pre_enable ), + .dec2_act_enable (dec2___act_enable ), + .dec2_read_enable (dec2___read_enable ), + .dec2_write_enable (dec2___write_enable ), + .dec2_locked (dec2___locked ), + .dec2_last (dec2___last ), + .dec2_rowa (dec2___rowa ), + .dec2_cola (dec2___cola ), + .dec2_ba (dec2___ba ), + .dec2_chid (dec2___chid ), + .dec2_burst (dec2___burst ), + // + .am_pre_all_enable (access_manager___pre_all_enable), + .am_refr_enable (access_manager___refr_enable ), + .am_pre_enable (access_manager___pre_enable ), + .am_act_enable (access_manager___act_enable ), + .am_read_enable (access_manager___read_enable ), + .am_write_enable (access_manager___write_enable ), + // + .arb_pre_all (arbiter_out___pre_all), + .arb_refr (arbiter_out___refr ), + .arb_pre (arbiter_out___pre ), + .arb_act (arbiter_out___act ), + .arb_read (arbiter_out___read ), + .arb_write (arbiter_out___write ), + .arb_rowa (arbiter_out___rowa ), + .arb_cola (arbiter_out___cola ), + .arb_ba (arbiter_out___ba ), + .arb_chid (arbiter_out___chid ), + .arb_burst (arbiter_out___burst ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_access_manager access_manager ( + .clk (clk ), + .reset (reset), + .sclr (hssdrc_sclr), // use internal sclr becouse there is access "fsm's" + // + .arb_pre_all (arbiter_out___pre_all), + .arb_refr (arbiter_out___refr ), + .arb_pre (arbiter_out___pre ), + .arb_act (arbiter_out___act ), + .arb_read (arbiter_out___read ), + .arb_write (arbiter_out___write ), + .arb_ba (arbiter_out___ba ), + .arb_burst (arbiter_out___burst ), + // + .am_pre_all_enable (access_manager___pre_all_enable), + .am_refr_enable (access_manager___refr_enable ), + .am_pre_enable (access_manager___pre_enable ), + .am_act_enable (access_manager___act_enable ), + .am_read_enable (access_manager___read_enable ), + .am_write_enable (access_manager___write_enable ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_init_state init_state( + .clk (clk ), + .reset (reset), + .sclr (sclr ), // use external sclr becouse this is initial start fsm + .init_done (init_done), + .pre_all (init_state___pre_all), + .refr (init_state___refr ), + .lmr (init_state___lmr ), + .rowa (init_state___rowa ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + hssdrc_mux mux ( + .init_done (init_done), + // + .init_state_pre_all (init_state___pre_all), + .init_state_refr (init_state___refr ), + .init_state_lmr (init_state___lmr ), + .init_state_rowa (init_state___rowa ), + // + .arb_pre_all (arbiter_out___pre_all), + .arb_refr (arbiter_out___refr ), + .arb_pre (arbiter_out___pre ), + .arb_act (arbiter_out___act ), + .arb_read (arbiter_out___read ), + .arb_write (arbiter_out___write ), + .arb_rowa (arbiter_out___rowa ), + .arb_cola (arbiter_out___cola ), + .arb_ba (arbiter_out___ba ), + .arb_chid (arbiter_out___chid ), + .arb_burst (arbiter_out___burst ), + // + .mux_pre_all (mux___pre_all), + .mux_refr (mux___refr ), + .mux_pre (mux___pre ), + .mux_act (mux___act ), + .mux_read (mux___read ), + .mux_write (mux___write ), + .mux_lmr (mux___lmr ), + .mux_rowa (mux___rowa ), + .mux_cola (mux___cola ), + .mux_ba (mux___ba ), + .mux_chid (mux___chid ), + .mux_burst (mux___burst ) + ); + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + `ifndef HSSDRC_DQ_PIPELINE + + hssdrc_data_path data_path ( + .clk (clk ), + .reset (reset), + .sclr (sclr ), // use external sclr becouse there is no any fsm + // + .sys_wdata (sys_wdata ), + .sys_wdatam (sys_wdatam ), + .sys_use_wdata (sys_use_wdata), + .sys_vld_rdata (sys_vld_rdata), + .sys_chid_o (sys_chid_o ), + .sys_rdata (sys_rdata ), + // + .arb_read (mux___read ), + .arb_write (mux___write ), + .arb_chid (mux___chid ), + .arb_burst (mux___burst ), + // + .dq (dq ), + .dqm (dqm ) + ); + + `else + + hssdrc_data_path_p1 data_path_p1 ( + .clk (clk ), + .reset (reset), + .sclr (sclr ), // use external sclr becouse there is no any fsm + // + .sys_wdata (sys_wdata ), + .sys_wdatam (sys_wdatam ), + .sys_use_wdata (sys_use_wdata), + .sys_vld_rdata (sys_vld_rdata), + .sys_chid_o (sys_chid_o ), + .sys_rdata (sys_rdata ), + // + .arb_read (mux___read ), + .arb_write (mux___write ), + .arb_chid (mux___chid ), + .arb_burst (mux___burst ), + // + .dq (dq ), + .dqm (dqm ) + ); + + `endif + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + `ifndef HSSDRC_DQ_PIPELINE + + hssdrc_addr_path addr_path( + .clk (clk ), + .reset (reset), + .sclr (sclr ), // use external sclr becouse there is no any fsm + // + .arb_pre_all (mux___pre_all), + .arb_refr (mux___refr ), + .arb_pre (mux___pre ), + .arb_act (mux___act ), + .arb_read (mux___read ), + .arb_write (mux___write ), + .arb_lmr (mux___lmr ), + .arb_rowa (mux___rowa ), + .arb_cola (mux___cola ), + .arb_ba (mux___ba ), + // + .addr (addr ), + .ba (ba ), + .cke (cke ), + .cs_n (cs_n ), + .ras_n (ras_n), + .cas_n (cas_n), + .we_n (we_n ) + ); + + `else + + hssdrc_addr_path_p1 addr_path_p1( + .clk (clk ), + .reset (reset), + .sclr (sclr ), // use external sclr becouse there is no any fsm + // + .arb_pre_all (mux___pre_all), + .arb_refr (mux___refr ), + .arb_pre (mux___pre ), + .arb_act (mux___act ), + .arb_read (mux___read ), + .arb_write (mux___write ), + .arb_lmr (mux___lmr ), + .arb_rowa (mux___rowa ), + .arb_cola (mux___cola ), + .arb_ba (mux___ba ), + // + .addr (addr ), + .ba (ba ), + .cke (cke ), + .cs_n (cs_n ), + .ras_n (ras_n), + .cas_n (cas_n), + .we_n (we_n ) + ); + + `endif + +endmodule + +

hssdrc/trunk/rtl/hssdrc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/rtl/hssdrc_init_state.v =================================================================== --- hssdrc/trunk/rtl/hssdrc_init_state.v (nonexistent) +++ hssdrc/trunk/rtl/hssdrc_init_state.v (revision 3) @@ -0,0 +1,154 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:52:43 $ +// +// Workfile : hssdrc_init_state.v +// +// Description : sdram chip initialization unit +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_timescale.vh" + +`include "hssdrc_timing.vh" +`include "hssdrc_define.vh" + +module hssdrc_init_state ( + clk , + reset , + sclr , + init_done , + pre_all , + refr , + lmr , + rowa + ); + + input wire clk ; + input wire reset; + input wire sclr ; + + output logic init_done; + output logic pre_all ; + output logic refr ; + output logic lmr ; + output rowa_t rowa ; + + assign rowa = cInitLmrValue; + + //--------------------------------------------------------------------------------------------------- + // counter based FSM + // fsm has 1 counter divided by 2 part : + // cnt_high - decode for wait init interval + // cnt_low - execute command sequence when wait done. + // true init time is ~= (1.1 - 1.2) pInit_time for less logic resource using + //--------------------------------------------------------------------------------------------------- + + localparam int unsigned cInitPre = 1; + localparam int unsigned cInitRefr0 = cInitPre + cTrp; + localparam int unsigned cInitRefr1 = cInitRefr0 + cTrfc; + localparam int unsigned cInitLmr = cInitRefr1 + cTrfc; + localparam int unsigned cInitDone = cInitLmr + cTmrd + 1; + + // + // counter parameters + // + + localparam int unsigned cInitCntLowWidth = clogb2(cInitDone); + localparam int unsigned cInitCntHighMax = (cInitTime >> cInitCntLowWidth) + 1; + localparam int unsigned cInitCntWidth = clogb2(cInitCntHighMax) + cInitCntLowWidth; + + //-------------------------------------------------------------------------------------------------- + // + //-------------------------------------------------------------------------------------------------- + + logic [cInitCntWidth-1 : 0] cnt; + logic [cInitCntLowWidth-1 : 0] cnt_low; + logic [cInitCntWidth-1 : cInitCntLowWidth] cnt_high; + + logic cnt_high_is_max; + + assign cnt_low = cnt [cInitCntLowWidth-1 : 0]; + assign cnt_high = cnt [cInitCntWidth-1 : cInitCntLowWidth]; + + + always_ff @(posedge clk or posedge reset) begin : cnt_fsm + if (reset) + cnt <= '0; + else if (sclr) + cnt <= '0; + else if (~init_done) + cnt <= cnt + 1'b1; + end + + + always_ff @(posedge clk or posedge reset) begin : cnt_fsm_comparator + if (reset) + cnt_high_is_max <= 1'b0; + else if (sclr) + cnt_high_is_max <= 1'b0; + else + cnt_high_is_max <= (cnt_high == cInitCntHighMax); + end + + + always_ff @(posedge clk or posedge reset) begin : cnt_fsm_decode + if (reset) begin + init_done <= 1'b0; + pre_all <= 1'b0; + refr <= 1'b0; + lmr <= 1'b0; + end + else if (sclr) begin + init_done <= 1'b0; + pre_all <= 1'b0; + refr <= 1'b0; + lmr <= 1'b0; + end + else begin + + pre_all <= 1'b0; + refr <= 1'b0; + lmr <= 1'b0; + + unique case (cnt_low) + cInitPre : pre_all <= cnt_high_is_max; + cInitRefr0 : refr <= cnt_high_is_max; + cInitRefr1 : refr <= cnt_high_is_max; + cInitLmr : lmr <= cnt_high_is_max; + cInitDone : init_done <= cnt_high_is_max; + default : begin end + endcase + + end + end + +endmodule

hssdrc/trunk/rtl/hssdrc_init_state.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/include/hssdrc_tb_sys_if.vh =================================================================== --- hssdrc/trunk/include/hssdrc_tb_sys_if.vh (nonexistent) +++ hssdrc/trunk/include/hssdrc_tb_sys_if.vh (revision 3) @@ -0,0 +1,99 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:51:55 $ +// +// Workfile : hssdrc_tb_sys_if.vh +// +// Description : system interface to memory controller +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_define.vh" + +`ifndef __HSSDRC_TB_SYS_IF_VH__ + + `define __HSSDRC_TB_SYS_IF_VH__ + + interface hssdrc_tb_sys_if (clk, reset, sclr); + input wire clk ; + input wire reset; + input wire sclr ; + // + logic write; + logic read; + logic refr; + rowa_t rowa; + cola_t cola; + ba_t ba; + burst_t burst; + chid_t chid_i; + data_t wdata; + datam_t wdatam; + // + logic ready; + logic use_wdata; + logic vld_rdata; + chid_t chid_o; + data_t rdata; + // + modport master ( output rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam, + input ready, use_wdata, vld_rdata, chid_o, rdata); + modport slave ( input rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam, + output ready, use_wdata, vld_rdata, chid_o, rdata); + // synthesis translate_off + clocking cb @(posedge clk); + default input #1ns output #1ns; + output rowa, cola, ba, burst, chid_i, write, read, refr, wdata, wdatam; + input ready, use_wdata, vld_rdata, chid_o, rdata; + endclocking + // + modport tb (input clk, reset, sclr, clocking cb); + // + wire [2:0] cmd_vect = {write, read, refr}; + wire sys_reset = reset | sclr; + // + property cmd_onehot; + @(cb) disable iff (sys_reset) (cmd_vect != 0) |-> $onehot(cmd_vect); + endproperty + // + property rst_output(logic signal); + @(cb) (sys_reset) |-> not (signal); + endproperty + // + assert property (cmd_onehot) else $error ("command overlaped violation error"); + assert property (rst_output(ready)) else $error ("hssdc reaady output reset violation error"); + assert property (rst_output(use_wdata)) else $error ("hssdc use_wdata output reset violation error"); + assert property (rst_output(vld_rdata)) else $error ("hssdc vld_rdata output reset violation error"); + // synthesis translate_on + + endinterface + +`endif

hssdrc/trunk/include/hssdrc_tb_sys_if.vh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/include/hssdrc_timescale.vh =================================================================== --- hssdrc/trunk/include/hssdrc_timescale.vh (nonexistent) +++ hssdrc/trunk/include/hssdrc_timescale.vh (revision 3) @@ -0,0 +1,44 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:51:55 $ +// +// Workfile : hssdrc_timescale.vh +// +// Description : simulation time settings +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +// synthesis translate_off + + timeunit 1ns; + timeprecision 10ps; + +// synthesis translate_on

hssdrc/trunk/include/hssdrc_timescale.vh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/include/hssdrc_timing.vh =================================================================== --- hssdrc/trunk/include/hssdrc_timing.vh (nonexistent) +++ hssdrc/trunk/include/hssdrc_timing.vh (revision 3) @@ -0,0 +1,93 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:51:55 $ +// +// Workfile : hssdrc_timing.vh +// +// Description : controller sdram timing paramters +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`ifndef __HSSDRC_TIMING_VH__ + + `define __HSSDRC_TIMING_VH__ + + //`define HSSDRC_SIMULATE_TIMING // uncomment for easy debug arefr sequence + + //------------------------------------------------- + // sdram controller clock settings in MHz + //------------------------------------------------- + parameter real pClkMHz = 133.0; + //------------------------------------------------- + // sdram chip timing paramters in "ns" for -6 CL3 + //------------------------------------------------- + parameter real pTras_time = 42.0; // act a -> prech a + parameter real pTrfc_time = 60.0; // refr -> !nop + parameter real pTrc_time = 60.0; // act a -> act a (Tras + Trcd) + parameter real pTrcd_time = 18.0; // act a -> write/read a + parameter real pTrp_time = 18.0; // prech a -> !nop + parameter real pTrrd_time = 12.0; // act a -> act b + parameter real pTwr_time = 12.0; // write a -> prech a + + `ifndef HSSDRC_SIMULATE_TIMING + parameter real pRefr_time = 15625.0; // refr -> refr + parameter real pInit_time = 100000.0; // power up -> refr + `else + parameter real pRefr_time = 500.0; // simulate only refr -> refr + parameter real pInit_time = 500.0; // simulate only power up -> refr + `endif + //------------------------------------------------- + // sdram chip normalaize to clock parameters + //------------------------------------------------- + parameter int cTras = 0.5 + (pTras_time * pClkMHz)/1000.0; // act a -> prech a + parameter int cTrfc = 0.5 + (pTrfc_time * pClkMHz)/1000.0; // refr -> !nop + parameter int cTrc = 0.5 + ( pTrc_time * pClkMHz)/1000.0; // act a -> act a + parameter int cTrcd = 0.5 + (pTrcd_time * pClkMHz)/1000.0; // act a -> write/read a + parameter int cTrp = 0.5 + ( pTrp_time * pClkMHz)/1000.0; // prech a -> !nop + parameter int cTrrd = 0.5 + (pTrrd_time * pClkMHz)/1000.0; // act a -> act b + parameter int cTwr = 0.5 + ( pTwr_time * pClkMHz)/1000.0; // write a -> prech a + parameter int cTmrd = 2; // lmr -> !nop (not used) + parameter int cInitTime = 0.5 + (pInit_time * pClkMHz)/1000.0; + //------------------------------------------------- + // refresh parameters + //------------------------------------------------- + parameter real pRefrWindowLowPriority = 0.85; + parameter real pRefrWindowHighPriority = 0.95; + parameter int cRefCounterMaxTime = 0.5 + (pRefr_time * pClkMHz)/1000.0; + parameter int cRefrWindowLowPriorityTime = 0.5 + (pRefrWindowLowPriority * pRefr_time * pClkMHz)/1000.0; + parameter int cRefrWindowHighPriorityTime = 0.5 + (pRefrWindowHighPriority * pRefr_time * pClkMHz)/1000.0; + //------------------------------------------------- + // sdram controller use 0/1 cycle bus turnaround + //------------------------------------------------- + parameter int pBTA = 1; // set 0 if not need + + // +`endif

hssdrc/trunk/include/hssdrc_timing.vh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/include/hssdrc_define.vh =================================================================== --- hssdrc/trunk/include/hssdrc_define.vh (nonexistent) +++ hssdrc/trunk/include/hssdrc_define.vh (revision 3) @@ -0,0 +1,139 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:51:55 $ +// +// Workfile : hssdrc_define.vh +// +// Description : controller hardware paramters & settings +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`ifndef __HSSDRC_DEFINE_VH__ + + `define __HSSDRC_DEFINE_VH__ + + //`define HSSDRC_DQ_PIPELINE // uncomment when need dq data register output + //`define HSSDRC_REFR_HI_DISABLE // uncomment when not need high priority refresh logic + //`define HSSDRC_REFR_LOW_DISABLE // uncomment when not need low priority refresh logic + //---------------------------------------------------------------------------------- + // default : controller used use_wdata signal with register output type + // optionaly : controller can use combinative use_wdata signal which set 1 cycle early + //---------------------------------------------------------------------------------- + //`define HSSDRC_COMBINATORY_USE_WDATA // uncomment when need to use non register use_wdata signal + //---------------------------------------------------------------------------------- + // default : decoders sharing PRE & ACT command inside sdram command pipeline waiting + //---------------------------------------------------------------------------------- + //`define HSSDRC_NOT_SHARE_ACT_COMMAND // uncomment for not generate logic for share ACT command + //---------------------------------------------------------------------------------- + // default : 2 decoders sharing sdram command pipeline inside PRE & ACT command waiting + //---------------------------------------------------------------------------------- + //`define HSSDRC_SHARE_ONE_DECODER // uncoment for only 1 decoder share + //`define HSSDRC_SHARE_NONE_DECODER // uncoment for none decoder share + //---------------------------------------------------------------------------------- + // sdram controller command interface parameters + //---------------------------------------------------------------------------------- + parameter int pRowaBits = 11; // >= 11 (0..10) + parameter int pColaBits = 8; // <= pRowBits + parameter int pBaBits = 2; // fixed == 2 (don't change !!!) + parameter int pBurstBits = 4; // <= 4 + parameter int pChIdBits = 2; // >= 1 + //---------------------------------------------------------------------------------- + // sdram controller data interface & sdram chip data interface parameters + //---------------------------------------------------------------------------------- + parameter int pDataBits = 32; // >= 8 + parameter int pDatamBits = byte_lanes(pDataBits); + //---------------------------------------------------------------------------------- + // sdram controller command interface parameters + //---------------------------------------------------------------------------------- + parameter int pSdramAddrBits = 11; // (>= pRowaBits & >= 11) + parameter int pSdramBurstBits = 2; // fixed == 2 (don't change !!!) + parameter int cSdramBL = 2**pSdramBurstBits; + //---------------------------------------------------------------------------------- + // sdram controller mode parameters (don't change except CL !!!!) + //---------------------------------------------------------------------------------- + parameter bit pInitWBM = 1'b0; // write burst mode = programed burst + parameter bit [1:0] pInitOM = 1'b0; // operation mode = standart + parameter bit [2:0] pCL = 3'b011; // cas latency = 3 + parameter bit pInitBT = 1'b0; // burst type = sequental + parameter bit [2:0] pInitBL = 3'b010; // burst = 4 + + parameter bit [pSdramAddrBits-1:10] pReserved = '0; + parameter bit [pSdramAddrBits-1: 0] cInitLmrValue = {pReserved, pInitWBM, pInitOM, pCL, pInitBT, pInitBL}; + //---------------------------------------------------------------------------------- + // used types + //---------------------------------------------------------------------------------- + typedef logic [pColaBits - 1 : 0] cola_t; + typedef logic [pRowaBits - 1 : 0] rowa_t; + typedef logic [pBaBits - 1 : 0] ba_t; + typedef logic [pBurstBits - 1 : 0] burst_t; + typedef logic [pChIdBits - 1 : 0] chid_t; + typedef logic [pDataBits - 1 : 0] data_t; + typedef logic [pDatamBits - 1 : 0] datam_t; + + typedef logic [pSdramAddrBits-1 :0] sdram_addr_t; + typedef logic [pSdramBurstBits-1:0] sdram_burst_t; + //---------------------------------------------------------------------------------- + // + //---------------------------------------------------------------------------------- + function automatic int clogb2 (input int data); + int i; + + for (i = 0; 2**i < data; i++) + clogb2 = i + 1; + endfunction + //---------------------------------------------------------------------------------- + // + //---------------------------------------------------------------------------------- + function automatic int byte_lanes (input int data); + int num; + + byte_lanes = 0; + + num = data; + // synthesis translate_off + assert (num != 0) else $error ("wrong data parameter"); + // synthesis translate_on + while (num > 0) begin + byte_lanes++; + num = num - 8; + end + + endfunction + //---------------------------------------------------------------------------------- + // + //---------------------------------------------------------------------------------- + function automatic int unsigned max(input int unsigned a, b); + if (a >= b) max = a; + else max = b; + endfunction + +`endif +

hssdrc/trunk/include/hssdrc_define.vh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/include/tb_define.svh =================================================================== --- hssdrc/trunk/include/tb_define.svh (nonexistent) +++ hssdrc/trunk/include/tb_define.svh (revision 3) @@ -0,0 +1,157 @@ +// +// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline +// +// Project Nick : HSSDRC +// +// Version : 1.0-beta +// +// Revision : $Revision: 1.1 $ +// +// Date : $Date: 2008-03-06 13:51:55 $ +// +// Workfile : tb_define.svh +// +// Description : testbench types, values, parameters +// +// HSSDRC is licensed under MIT License +// +// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of +// this software and associated documentation files (the "Software"), to deal in +// the Software without restriction, including without limitation the rights to +// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +// the Software, and to permit persons to whom the Software is furnished to do so, +// subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// + + +`include "hssdrc_define.vh" + +`ifndef __TB_DEFINE_SVH__ + + `define __TB_DEFINE_SVH__ + + // + // tb types without Z, X states + // + typedef bit [pColaBits - 1 : 0] tb_cola_t; + typedef bit [pRowaBits - 1 : 0] tb_rowa_t; + typedef bit [pBaBits - 1 : 0] tb_ba_t; + typedef bit [pBurstBits - 1 : 0] tb_burst_t; + typedef bit [pChIdBits - 1 : 0] tb_chid_t; + typedef bit [pDataBits - 1 : 0] tb_data_t; + typedef bit [pDatamBits - 1 : 0] tb_datam_t; + + // + // ram test parameters for correctness test + // + + localparam int cColaMaxValue = 2**pColaBits; + localparam int cRowaMaxValue = 2**pRowaBits; + localparam int cBaMaxValue = 2**pBaBits; + localparam int cBurstMaxValue = 2**pBurstBits; + + // + // number of transactions in random correctness test + // + + localparam int cTransactionMaxValue = cColaMaxValue*cBaMaxValue*cRowaMaxValue; + + // + // time interval for bandwidth measure for each bandwidth measure mode + // + + const time cPerfomanceInterval = 200us;//10ms; + + // + // number of transaction for done log message + // + + const int cTransactionLogPeriod = 1024; + + // + // bandwidth measure modes + // + + typedef struct packed { + bit read_mode; + bit write_mode; + } test_mode_t; // used tests : 1 - write, 2 - read, 3 write -> read; + + int burst_mode [$] = '{1, 2, 3, 4, 5}; + int address_mode [$] = '{0, 1, 2, 3, 4, 5}; + test_mode_t test_mode [$] = '{1, 2, 3} ; + + const string test_mode_name [4] = '{ + 0 : "error mode", + 1 : "sequental write", + 2 : "sequental read", + 3 : "sequental write -> read" + }; + + const string burst_mode_name [7] = '{ + 0 : "burst mode : {any, no cola allign}", + 1 : "burst mode : {fixed == 1, cola allign}", + 2 : "burst mode : {fixed == 2, cola allign}", + 3 : "burst mode : {fixed == 4, cola allign}", + 4 : "burst mode : {fixed == 8, cola allign}", + 5 : "burst mode : {fixed == 16, cola allign}", + 6 : "burst mode : {any inside [1,2, 4,8,16], cola allign}" + }; + + const string address_mode_name [8] = '{ + 0 : "address mode : {same bank : same row}", + 1 : "address mode : {same bank : any row}", + 2 : "address mode : {any bank : same row}", + 3 : "address mode : {linear bank : same row}", + 4 : "address mode : {any bank : any row}", + 5 : "address mode : {linear bank : any row}", + 6 : "address mode : {any bank : any row : ba varies more often than rowa}", + 7 : "address mode : {any bank : any row : ba varies less often than rowa}" + }; + + // + // virtual transaction tread types & parameters + // + + localparam int cTreadMaxNumber = cBaMaxValue*cRowaMaxValue; + localparam int cTreadPointerWidth = clogb2(cTreadMaxNumber); + + typedef bit [cTreadPointerWidth-1:0] sdram_tread_ptr_t; + + typedef struct { + ba_t ba; + rowa_t rowa; + cola_t cola; + } sdram_tread_state_s_t; + + // + // sdram transaction types + // + + typedef enum {cTR_WRITE, cTR_READ, cTR_REFR, + cTR_WRITE_LOCKED, cTR_READ_LOCKED, cTR_REFR_LOCKED + } tr_type_e_t; + + // + // transaction acknowledge mailbox. use only for locked transaction + // + + typedef mailbox #(tr_type_e_t) sdram_tr_ack_mbx; + + // + // + // + +`endif

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hssdrc/trunk/doc/hssdrc_design_document_rev10.odt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/doc/hssdrc_design_document.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: hssdrc/trunk/doc/hssdrc_design_document.pdf =================================================================== --- hssdrc/trunk/doc/hssdrc_design_document.pdf (nonexistent) +++ hssdrc/trunk/doc/hssdrc_design_document.pdf (revision 3)

hssdrc/trunk/doc/hssdrc_design_document.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: hssdrc/trunk/core/test.v =================================================================== --- hssdrc/trunk/core/test.v (nonexistent) +++ hssdrc/trunk/core/test.v (revision 3) @@ -0,0 +1,367 @@ +// Testbench for Micron SDR SDRAM Verilog models + +`timescale 1ns / 1ps + +module test; + +reg [31 : 0] dq; // SDRAM I/O +reg [10 : 0] addr; // SDRAM Address +reg [1 : 0] ba; // Bank Address +reg clk; // Clock +reg cke; // Synchronous Clock Enable +reg cs_n; // CS# +reg ras_n; // RAS# +reg cas_n; // CAS# +reg we_n; // WE# +reg [3 : 0] dqm; // I/O Mask + +wire [31 : 0] DQ = dq; + +parameter hi_z = 32'bz; // Hi-Z + +parameter tCK = 10; // Clock Period + +mt48lc2m32b2 sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm); + +initial begin + clk = 1'b0; + cke = 1'b0; + cs_n = 1'b1; + dq = hi_z; +end + +always #5 clk = ~clk; + +/* +always @ (posedge clk) begin + $strobe("at time %t clk=%b cke=%b CS#=%b RAS#=%b CAS#=%b WE#=%b dqm=%b addr=%b ba=%b DQ=%d", + $time, clk, cke, cs_n, ras_n, cas_n, we_n, dqm, addr, ba, DQ); +end +*/ + +task active; + input [1 : 0] bank; + input [10 : 0] row; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 1; + dqm = 0; + ba = bank; + addr = row; + dq = dq_in; + end +endtask + +task auto_refresh; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 0; + we_n = 1; + dqm = 0; + //ba = 0; + //addr = 0; + dq = hi_z; + end +endtask + +task burst_term; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 1; + cas_n = 1; + we_n = 0; + dqm = 0; + //ba = 0; + //addr = 0; + dq = dq_in; + end +endtask + +task load_mode_reg; + input [10 : 0] op_code; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 0; + we_n = 0; + dqm = 0; + ba = 0; + addr = op_code; + dq = hi_z; + end +endtask + +task nop; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 1; + cas_n = 1; + we_n = 1; + dqm = dqm_in; + //ba = 0; + //addr = 0; + dq = dq_in; + end +endtask + +task precharge_bank_0; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 0; + dqm = dqm_in; + ba = 0; + addr = 0; + dq = dq_in; + end +endtask + +task precharge_bank_1; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 0; + dqm = dqm_in; + ba = 1; + addr = 0; + dq = dq_in; + end +endtask + +task precharge_bank_2; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 0; + dqm = dqm_in; + ba = 2; + addr = 0; + dq = dq_in; + end +endtask + +task precharge_bank_3; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 0; + dqm = dqm_in; + ba = 3; + addr = 0; + dq = dq_in; + end +endtask + +task precharge_all_bank; + input [3 : 0] dqm_in; + input [31 : 0] dq_in; + begin + cke = 1; + cs_n = 0; + ras_n = 0; + cas_n = 1; + we_n = 0; + dqm = dqm_in; + ba = 0; + addr = 1024; // A10 = 1 + dq = dq_in; + end +endtask + +task read; + input [1 : 0] bank; + input [10 : 0] column; + input [31 : 0] dq_in; + input [3 : 0] dqm_in; + begin + cke = 1; + cs_n = 0; + ras_n = 1; + cas_n = 0; + we_n = 1; + dqm = dqm_in; + ba = bank; + addr = column; + dq = dq_in; + end +endtask + +task write; + input [1 : 0] bank; + input [10 : 0] column; + input [31 : 0] dq_in; + input [3 : 0] dqm_in; + begin + cke = 1; + cs_n = 0; + ras_n = 1; + cas_n = 0; + we_n = 0; + dqm = dqm_in; + ba = bank; + addr = column; + dq = dq_in; + end +endtask + +initial begin + begin + // Initialize + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; precharge_all_bank(0, hi_z); // Precharge ALL Bank + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; auto_refresh; // Auto Refresh + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; auto_refresh; // Auto Refresh + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; load_mode_reg (50); // Load Mode: Lat = 3, BL = 4, Seq + #tCK; nop (0, hi_z); // Nop + + // Write with auto precharge to bank 0 (non-interrupt) + #tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; write (0, 1024, 100, 0); // Write : Bank = 0, Col = 0, Dqm = 0, Auto Precharge + #tCK; nop (0, 101); // Nop + #tCK; nop (0, 102); // Nop + #tCK; nop (0, 103); // Nop + #tCK; nop (0, hi_z); // Nop + + // Write with auto precharge to bank 1 (non-interrupt) + #tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; write (1, 1024, 200, 0); // Write : Bank = 1, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, 201); // Nop + #tCK; nop (0, 202); // Nop + #tCK; nop (0, 203); // Nop + #tCK; nop (0, hi_z); // Nop + + // Write with auto precharge to bank 2 (non-interrupt) + #tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; write (2, 1024, 300, 0); // Write : Bank = 2, Col = 0, Dqm = 0, Auto Precharge + #tCK; nop (0, 301); // Nop + #tCK; nop (0, 302); // Nop + #tCK; nop (0, 303); // Nop + #tCK; nop (0, hi_z); // Nop + + // Write with auto precharge to bank 3 (non-interrupt) + #tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; write (3, 1024, 400, 0); // Write : Bank = 3, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, 401); // Nop + #tCK; nop (0, 402); // Nop + #tCK; nop (0, 403); // Nop + #tCK; nop (0, hi_z); // Nop + + // Read with auto precharge to bank 0 (non-interrupt) + #tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; read (0, 1024, hi_z, 0); // Read : Bank = 0, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + + // Read with auto precharge to bank 1 (non-interrupt) + #tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; read (1, 1024, hi_z, 0); // Read : Bank = 1, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + + // Read with auto precharge to bank 2 (non-interrupt) + #tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; read (2, 1024, hi_z, 0); // Read : Bank = 2, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + + // Read with auto precharge to bank 3 (non-interrupt) + #tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0 + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; read (3, 1024, hi_z, 0); // Read : Bank = 3, Col = 0, Dqm = 0, Auto precharge + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; nop (0, hi_z); // Nop + #tCK; + end +$stop; +$finish; +end + +endmodule + +

hssdrc/trunk/core/test.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/core/mt48lc2m32b2.v =================================================================== --- hssdrc/trunk/core/mt48lc2m32b2.v (nonexistent) +++ hssdrc/trunk/core/mt48lc2m32b2.v (revision 3) @@ -0,0 +1,1096 @@ +/************************************************************************** +* +* File Name: MT48LC2M32B2.V +* Version: 2.1 +* Date: June 6th, 2002 +* Model: BUS Functional +* Simulator: Model Technology +* +* Dependencies: None +* +* Email: modelsupport@micron.com +* Company: Micron Technology, Inc. +* Model: MT48LC2M32B2 (512K x 32 x 4 Banks) +* +* Description: Micron 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright � 2001 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Date Changes +* --- -------------------------- --------------------------------------- +* 2.1 SH 06/06/2002 - Typo in bank multiplex +* Micron Technology Inc. +* +* 2.0 SH 04/30/2002 - Second release +* Micron Technology Inc. +* +**************************************************************************/ + +`timescale 1ns / 1ps + +module mt48lc2m32b2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 524287; + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank) + reg Read_precharge [0 : 3]; // R Auto Precharge + reg Write_precharge [0 : 3]; // W Auto Precharge + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank + integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter + integer Count_precharge [0 : 3]; // RW Auto Precharge Counter + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Prev_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_1 = ~Mode_reg[6] & ~Mode_reg[5] & Mode_reg[4]; + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug = 1'b1; // Debug messages : 1 = On + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define WRITE 3 + `define PRECH 4 + `define A_REF 5 + `define BST 6 + `define LMR 7 + + // Timing Parameters for -6 CL3 + parameter tAC = 5.5; + parameter tHZ = 5.5; + parameter tOH = 2.5; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 42.0; + parameter tRC = 60.0; + parameter tRCD = 18.0; + parameter tRFC = 60.0; + parameter tRP = 18.0; + parameter tRRD = 12.0; + parameter tWRa = 6.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns) + parameter tWRm = 12.0; // A2 Version - Manual precharge mode (14 ns) + + // Timing Check variable + time MRD_chk; + time WR_chkm [0 : 3]; + time RFC_chk, RRD_chk; + time RC_chk0, RC_chk1, RC_chk2, RC_chk3; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + initial begin + Dq_reg = {data_bits{1'bz}}; + Data_in_enable = 0; Data_out_enable = 0; + Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1; + Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0; + WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0; + RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0; + RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0; + MRD_chk = 0; RFC_chk = 0; RRD_chk = 0; + RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0; + RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0; + RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; + RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; + $timeformat (-9, 1, " ns", 12); + end + + // System clock generator + always begin + @ (posedge Clk) begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @ (negedge Clk) begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] === 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] === 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] === 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] === 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // Read or Write Interrupt Counter + if (RW_interrupt_write[0] === 1'b1) begin + RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1; + end + if (RW_interrupt_write[1] === 1'b1) begin + RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1; + end + if (RW_interrupt_write[2] === 1'b1) begin + RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1; + end + if (RW_interrupt_write[3] === 1'b1) begin + RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // Auto Refresh + if (Aref_enable === 1'b1) begin + if (Debug) begin + $display ("%m : at time %t AREF : Auto Refresh", $time); + end + + // Auto Refresh to Auto Refresh + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time); + end + + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time); + end + + // Precharge to Refresh + if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin + $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + + // Load Mode Register to Auto Refresh + if (MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time); + end + + // Record Current tRFC time + RFC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable === 1'b1) begin + // Register Mode + Mode_reg = Addr; + + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Debug) begin + $display ("%m : at time %t LMR : Load Mode Register", $time); + // CAS Latency + case (Addr[6 : 4]) + 3'b001 : $display ("%m : CAS Latency = 1"); + 3'b010 : $display ("%m : CAS Latency = 2"); + 3'b011 : $display ("%m : CAS Latency = 3"); + default : $display ("%m : CAS Latency = Reserved"); + endcase + + // Burst Length + case (Addr[2 : 0]) + 3'b000 : $display ("%m : Burst Length = 1"); + 3'b001 : $display ("%m : Burst Length = 2"); + 3'b010 : $display ("%m : Burst Length = 4"); + 3'b011 : $display ("%m : Burst Length = 8"); + 3'b111 : $display ("%m : Burst Length = Full"); + default : $display ("%m : Burst Length = Reserved"); + endcase + + // Burst Type + if (Addr[3] === 1'b0) begin + $display ("%m : Burst Type = Sequential"); + end else if (Addr[3] === 1'b1) begin + $display ("%m : Burst Type = Interleaved"); + end else begin + $display ("%m : Burst Type = Reserved"); + end + + // Write Burst Mode + if (Addr[9] === 1'b0) begin + $display ("%m : Write Burst Mode = Programmed Burst Length"); + end else if (Addr[9] === 1'b1) begin + $display ("%m : Write Burst Mode = Single Location Access"); + end else begin + $display ("%m : Write Burst Mode = Reserved"); + end + end + + // Precharge to Load Mode Register + if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin + $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + + // Precharge to Load Mode Register + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time); + end + + // Auto Refresh to Load Mode Register + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time); + end + + // Load Mode Register to Load Mode Register + if (MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + + // Reset MRD Counter + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable === 1'b1) begin + // Activate an open bank can corrupt data + if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) || + (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin + $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time); + end + + // Activate Bank 0 + if (Ba === 2'b00 && Pc_b0 === 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk0 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time); + end + + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time); + end + + // Record variables + Act_b0 = 1'b1; + Pc_b0 = 1'b0; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk0 = $time; + RC_chk0 = $time; + RCD_chk0 = $time; + end + + if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk1 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time); + end + + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time); + end + + // Record variables + Act_b1 = 1'b1; + Pc_b1 = 1'b0; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk1 = $time; + RC_chk1 = $time; + RCD_chk1 = $time; + end + + if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk2 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time); + end + + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time); + end + + // Record variables + Act_b2 = 1'b1; + Pc_b2 = 1'b0; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk2 = $time; + RC_chk2 = $time; + RCD_chk2 = $time; + end + + if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk3 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time); + end + + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time); + end + + // Record variables + Act_b3 = 1'b1; + Pc_b3 = 1'b0; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk3 = $time; + RC_chk3 = $time; + RCD_chk3 = $time; + end + + // Active Bank A to Active Bank B + if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + + // Auto Refresh to Activate + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba); + end + + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + + // Record variables for checking violation + RRD_chk = $time; + Prev_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + // Load Mode Register to Precharge + if ($time - MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time); + end + + // Precharge Bank 0 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin + Act_b0 = 1'b0; + Pc_b0 = 1'b1; + RP_chk0 = $time; + + // Activate to Precharge + if ($time - RAS_chk0 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[0] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 1 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin + Act_b1 = 1'b0; + Pc_b1 = 1'b1; + RP_chk1 = $time; + + // Activate to Precharge + if ($time - RAS_chk1 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[1] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 2 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin + Act_b2 = 1'b0; + Pc_b2 = 1'b1; + RP_chk2 = $time; + + // Activate to Precharge + if ($time - RAS_chk2 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[2] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 3 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin + Act_b3 = 1'b0; + Pc_b3 = 1'b1; + RP_chk3 = $time; + + // Activate to Precharge + if ($time - RAS_chk3 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[3] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin + Data_in_enable = 1'b0; + end + + // Precharge Command Pipeline for Read + if (Cas_latency_3 === 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 === 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end else if (Cas_latency_1 === 1'b1) begin + Command[0] = `PRECH; + Bank_precharge[0] = Ba; + A10_precharge[0] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term === 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 === 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end else if (Cas_latency_1 == 1'b1) begin + Command[0] = `BST; + end + + // Display debug message + if (Debug) begin + $display ("%m : at time %t BST : Burst Terminate",$time); + end + end + + // Read, Write, Column Latch + if (Read_enable === 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("%m : at time %t ERROR: Bank is not Activated for Read", $time); + end + + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || + (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || + (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || + (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin + $display("%m : at time %t ERROR: tRCD violation during Read", $time); + end + + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + Command[2] = `READ; + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `READ; + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end else if (Cas_latency_1 == 1'b1) begin + Command[0] = `READ; + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_write[RW_interrupt_bank] = 1'b1; + RW_interrupt_counter[RW_interrupt_bank] = 0; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time); + end + end + end + + // Read with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + RW_interrupt_bank = Ba; + Read_precharge[Ba] = 1'b1; + end + end + + // Write Command + if (Write_enable == 1'b1) begin + // Activate to Write + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("%m : at time %t ERROR: Bank is not Activated for Write", $time); + end + + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || + (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || + (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || + (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin + $display("%m : at time %t ERROR: tRCD violation during Read", $time); + end + + // Latch Write command, Bank, and Column + Command[0] = `WRITE; + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_write[RW_interrupt_bank] = 1'b1; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); + end + end + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_read[RW_interrupt_bank] = 1'b1; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); + end + end + end + + // Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + RW_interrupt_bank = Ba; + Write_precharge[Ba] = 1'b1; + end + end + + /* + Write with Auto Precharge Calculation + The device start internal precharge when: + 1. Meet minimum tRAS requirement + and 2. tWR cycle(s) after last valid data + or 3. Interrupt by a Read or Write (with or without Auto Precharge) + + Note: Model is starting the internal precharge 1 cycle after they meet all the + requirement but tRP will be compensate for the time after the 1 cycle. + */ + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3 + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3 + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3 + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3 + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. Meet minimum tRAS requirement + // and 2. CAS Latency - 1 cycles before last burst + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 1 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) begin + $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + case (Bank_addr[0]) + 2'b00 : Row = B0_row_addr; + 2'b01 : Row = B1_row_addr; + 2'b10 : Row = B2_row_addr; + 2'b11 : Row = B3_row_addr; + endcase + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + case (Bank_addr[0]) + 2'b00 : Row = B0_row_addr; + 2'b01 : Row = B1_row_addr; + 2'b10 : Row = B2_row_addr; + 2'b11 : Row = B3_row_addr; + endcase + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + case (Bank) + 2'b00 : Dq_dqm = Bank0 [{Row, Col}]; + 2'b01 : Dq_dqm = Bank1 [{Row, Col}]; + 2'b10 : Dq_dqm = Bank2 [{Row, Col}]; + 2'b11 : Dq_dqm = Bank3 [{Row, Col}]; + endcase + + // Dqm operation + if (Dqm[0] == 1'b0) begin + Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + end + if (Dqm[1] == 1'b0) begin + Dq_dqm [15 : 8] = Dq [15 : 8]; + end + if (Dqm[2] == 1'b0) begin + Dq_dqm [23 : 16] = Dq [23 : 16]; + end + if (Dqm[3] == 1'b0) begin + Dq_dqm [31 : 24] = Dq [31 : 24]; + end + + // Write to memory + case (Bank) + 2'b00 : Bank0 [{Row, Col}] = Dq_dqm; + 2'b01 : Bank1 [{Row, Col}] = Dq_dqm; + 2'b10 : Bank2 [{Row, Col}] = Dq_dqm; + 2'b11 : Bank3 [{Row, Col}] = Dq_dqm; + endcase + + // Display debug message + if (Dqm !== 4'b1111) begin + // Record tWR for manual precharge + WR_chkm [Bank] = $time; + + if (Debug) begin + $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %h", $time, Bank, Row, Col, Dq_dqm); + end + end else begin + if (Debug) begin + $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end + end + + // Advance burst counter subroutine + #tHZ Burst_decode; + + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + // Array buffer + case (Bank) + 2'b00 : Dq_dqm = Bank0[{Row, Col}]; + 2'b01 : Dq_dqm = Bank1[{Row, Col}]; + 2'b10 : Dq_dqm = Bank2[{Row, Col}]; + 2'b11 : Dq_dqm = Bank3[{Row, Col}]; + endcase + + // Dqm operation + if (Dqm_reg0 [0] == 1'b1) begin + Dq_dqm [ 7 : 0] = 8'bz; + end + if (Dqm_reg0 [1] == 1'b1) begin + Dq_dqm [15 : 8] = 8'bz; + end + if (Dqm_reg0 [2] == 1'b1) begin + Dq_dqm [23 : 16] = 8'bz; + end + if (Dqm_reg0 [3] == 1'b1) begin + Dq_dqm [31 : 24] = 8'bz; + end + + // Display debug message + if (Dqm_reg0 !== 4'b1111) begin + Dq_reg = #tAC Dq_dqm; + if (Debug) begin + $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %h", $time, Bank, Row, Col, Dq_reg); + end + end else begin + Dq_reg = #tHZ {data_bits{1'bz}}; + if (Debug) begin + $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end + end + + // Advance burst counter subroutine + Burst_decode; + end + end + + // Burst counter decode + task Burst_decode; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + // Timing Parameters for -6 CL3 + specify + specparam + tAH = 1.0, // Addr, Ba Hold Time + tAS = 1.5, // Addr, Ba Setup Time + tCH = 2.5, // Clock High-Level Width + tCL = 2.5, // Clock Low-Level Width + tCK = 6.0, // Clock Cycle Time + tDH = 1.0, // Data-in Hold Time + tDS = 1.5, // Data-in Setup Time + tCKH = 1.0, // CKE Hold Time + tCKS = 1.5, // CKE Setup Time + tCMH = 1.0, // CS#, RAS#, CAS#, WE#, DQM# Hold Time + tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time + $width (posedge Clk, tCH); + $width (negedge Clk, tCL); + $period (negedge Clk, tCK); + $period (posedge Clk, tCK); + $setuphold(posedge Clk, Cke, tCKS, tCKH); + $setuphold(posedge Clk, Cs_n, tCMS, tCMH); + $setuphold(posedge Clk, Cas_n, tCMS, tCMH); + $setuphold(posedge Clk, Ras_n, tCMS, tCMH); + $setuphold(posedge Clk, We_n, tCMS, tCMH); + $setuphold(posedge Clk, Addr, tAS, tAH); + $setuphold(posedge Clk, Ba, tAS, tAH); + $setuphold(posedge Clk, Dqm, tCMS, tCMH); + $setuphold(posedge Dq_chk, Dq, tDS, tDH); + endspecify + +endmodule

hssdrc/trunk/core/mt48lc2m32b2.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/sim/compile.do =================================================================== --- hssdrc/trunk/sim/compile.do (nonexistent) +++ hssdrc/trunk/sim/compile.do (revision 3) @@ -0,0 +1,59 @@ + +set need_quit 1 +set need_del 1 + +set debug 1 + +if {$debug} { + set opt novopt +} else { + set opt O4 +} +# +#set used project dir +# +set prjdir E:/work_des00/Project/prj_10_hssdrc + +set coredir $prjdir/core +set rtldir $prjdir/rtl +set tbdir $prjdir/testbench +set incdir $prjdir/include + +if {$need_del} { + vdel -all work +} + +vlib work +# core codes +vlog $coredir/mt48lc2m32b2.v +# headers codes +# rtl codes +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_data_path.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_data_path_p1.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_addr_path.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_addr_path_p1.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_mux.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_init_state.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_arbiter_out.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_access_manager.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_decoder_state.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_decoder.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_ba_map.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_arbiter_in.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_refr_counter.v +vlog -$opt -sv -lint -incr +incdir+$incdir+$rtldir $rtldir/hssdrc_top.v + +# tb codes +vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/sdram_interpretator.sv + +vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/tb_prog.sv +vlog -$opt -sv -lint +incdir+$incdir+$tbdir $tbdir/tb_top.sv + +if {$need_quit} { + quit +} + + + + +

hssdrc/trunk/sim/compile.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/sim/sim.do =================================================================== --- hssdrc/trunk/sim/sim.do (nonexistent) +++ hssdrc/trunk/sim/sim.do (revision 3) @@ -0,0 +1,133 @@ + +onbreak {resume} + +proc r {} { + restart -force -all +} + +transcript file "" + +set debug 1 + +if {$debug} { + set seed [clock seconds] +} else { + set seed [clock seconds] +} + +#transcript file transcript + +if {$debug} { +vsim -novopt -sv_seed $seed -wlf hssdrc_work.wlf work.tb_top + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +radix hexadecimal + +add wave -noupdate -divider system +add wave -noupdate -format Logic /tb_top/clk +add wave -noupdate -format Logic /tb_top/reset +add wave -noupdate -format Logic /tb_top/sclr + +add wave -noupdate -divider sys_if_req_resp +add wave -noupdate -format Logic /tb_top/sys_write +add wave -noupdate -format Logic /tb_top/sys_read +add wave -noupdate -format Logic /tb_top/sys_refr +add wave -noupdate -format Logic /tb_top/sys_ready + +add wave -noupdate -divider sys_if_req_data +add wave -noupdate -format Literal /tb_top/sys_rowa +add wave -noupdate -format Literal /tb_top/sys_cola +add wave -noupdate -format Literal /tb_top/sys_ba +add wave -noupdate -format Literal /tb_top/sys_burst +add wave -noupdate -format Literal /tb_top/sys_chid_i + +add wave -noupdate -divider sys_if_data +add wave -noupdate -format Literal /tb_top/sys_wdata +add wave -noupdate -format Literal /tb_top/sys_wdatam +add wave -noupdate -format Logic /tb_top/sys_use_wdata + +add wave -noupdate -format Logic /tb_top/sys_chid_o +add wave -noupdate -format Literal /tb_top/sys_rdata +add wave -noupdate -format Logic /tb_top/sys_vld_rdata + +add wave -noupdate -divider sdram_if +add wave -noupdate -format Logic /tb_top/nclk +add wave -noupdate -format Literal /tb_top/inter/cmd_e +add wave -noupdate -format Literal /tb_top/dq +add wave -noupdate -format Literal /tb_top/dqm +add wave -noupdate -format Literal /tb_top/addr +add wave -noupdate -format Literal /tb_top/ba +add wave -noupdate -format Logic /tb_top/cs_n +add wave -noupdate -format Logic /tb_top/ras_n +add wave -noupdate -format Logic /tb_top/cas_n +add wave -noupdate -format Logic /tb_top/we_n + +add wave -noupdate -divider am +add wave -noupdate -format Logic /tb_top/top/access_manager/am_pre_all_enable +add wave -noupdate -format Logic /tb_top/top/access_manager/am_refr_enable +add wave -noupdate -format Literal /tb_top/top/access_manager/am_pre_enable +add wave -noupdate -format Literal /tb_top/top/access_manager/am_act_enable +add wave -noupdate -format Literal /tb_top/top/access_manager/am_read_enable +add wave -noupdate -format Literal /tb_top/top/access_manager/am_write_enable + +add wave -noupdate -divider mux +add wave -noupdate -format Logic /tb_top/top/mux/mux_pre_all +add wave -noupdate -format Logic /tb_top/top/mux/mux_refr +add wave -noupdate -format Logic /tb_top/top/mux/mux_pre +add wave -noupdate -format Logic /tb_top/top/mux/mux_act +add wave -noupdate -format Logic /tb_top/top/mux/mux_read +add wave -noupdate -format Logic /tb_top/top/mux/mux_write +add wave -noupdate -format Logic /tb_top/top/mux/mux_lmr +add wave -noupdate -format Literal /tb_top/top/mux/mux_burst + +add wave -noupdate -divider state +add wave -noupdate -format Literal /tb_top/top/decoder/state0/state +add wave -noupdate -format Literal /tb_top/top/decoder/state1/state +add wave -noupdate -format Literal /tb_top/top/decoder/state2/state + +add wave -noupdate -divider ba_map +add wave -noupdate -format Logic /tb_top/top/ba_map/update +add wave -noupdate -format Logic /tb_top/top/ba_map/clear +add wave -noupdate -format Literal /tb_top/top/ba_map/ba +add wave -noupdate -format Literal /tb_top/top/ba_map/rowa +add wave -noupdate -format Logic /tb_top/top/ba_map/pre_act_rw +add wave -noupdate -format Logic /tb_top/top/ba_map/act_rw +add wave -noupdate -format Logic /tb_top/top/ba_map/rw +add wave -noupdate -format Logic /tb_top/top/ba_map/all_close + +add wave -noupdate -divider init_state +add wave -noupdate -format Logic /tb_top/top/init_state/init_done + +add wave -noupdate -divider refr_cnt +add wave -noupdate -format Logic /tb_top/top/refr_cnt/ack +add wave -noupdate -format Logic /tb_top/top/refr_cnt/hi_req +add wave -noupdate -format Logic /tb_top/top/refr_cnt/low_req + + + +TreeUpdate [SetDefaultTree] +configure wave -namecolwidth 203 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {1000 ps} + +log -r /* + +} else { + vsim -sv_seed $seed work.tb_top + run -all + quit +} +

hssdrc/trunk/sim/sim.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk/readme.txt =================================================================== --- hssdrc/trunk/readme.txt (nonexistent) +++ hssdrc/trunk/readme.txt (revision 3) @@ -0,0 +1,8 @@ +Logical project decsription + +core - external not under development IP cores +doc - project documentation +include - common rtl, testbench header files +rtl - rtl models of project units +sim - simulation scripts for verivication +testbench - verification enviroment for project

hssdrc/trunk/readme.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hssdrc/trunk =================================================================== --- hssdrc/trunk (nonexistent) +++ hssdrc/trunk (revision 3)

hssdrc/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: hssdrc/web_uploads =================================================================== --- hssdrc/web_uploads (nonexistent) +++ hssdrc/web_uploads (revision 3)

hssdrc/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: hssdrc/branches =================================================================== --- hssdrc/branches (nonexistent) +++ hssdrc/branches (revision 3)

hssdrc/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: hssdrc/tags =================================================================== --- hssdrc/tags (nonexistent) +++ hssdrc/tags (revision 3)

hssdrc/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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