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/tags/ver/modelsim.ini
0,0 → 1,1058
; Copyright 1991-2007 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
work = modelsim/work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile=1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VcomZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VcomZeroInOptions = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageNoSub = 0
 
; Automatically exclude VHDL case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Turn on code coverage in VHDL generate blocks. Default is on.
CoverGenerate = 1
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
vlog95compat = 0
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal to or more than 1M are
; marked as sparse)
SparseMemThreshold = 1048576
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VlogZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VlogZeroInOptions = ""
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VoptZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VoptZeroInOptions = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Turn on code coverage in VLOG generate blocks. Default is on.
CoverGenerate = 1
 
; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is on.
CoverCells = 0
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
; 1 -- Turn off all optimizations that affect coverage reports.
; 2 -- Allow optimizations that allow large performance improvements
; by invoking sequential processes only when the data changes.
; Allow VHDL FF recognition. This may make major reductions in
; coverage counts.
; 3 -- In addition, allow optimizations that may change expressions or
; remove some statements. Allow constant propagation.
; 4 -- In addition, allow optimizations that may remove major regions of
; code by changing assignments to built-ins or removing unused
; signals. Allow VHDL subprogram inlining. Change Verilog gates to
; continuous assignments.
CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobeDefault".
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupPerInstanceDefault".
; SVCovergroupPerInstanceDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
[vsim]
 
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ns
 
; Enables certain code coverage exclusions automatically. Set AutoExclusions = none to disable.
AutoExclusions = fsm
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
; level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
 
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name: # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1
 
 
; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable System Verilog assertion messages
; Info and Warning are disabled by default
; IgnoreSVAInfo = 0
; IgnoreSVAWarning = 0
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify whether to enable SystemVerilog DPI out-of-the-blue call.
; Out-of-the-blue call refers to a SystemVerilog export function call
; directly from a C function that don't have the proper context setup
; as done in DPI-C import C functions. When this is enabled, one can
; call a DPI export function (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
 
; Should the tool conform to the 2001 or 2005 VPI object model
; Note that System Verilog objects are only available in the 2005 object model
; The tool default is the latest available LRM behavior
; Options here are: 2001 2005 latest
; PliCompatDefault = 2005
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
; This is necessary when C++ files have been compiled with aCC's -AA option.
; The default behavior is to use /usr/lib/libCsup.sl.
; UseCsupV2 = 1
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; Note: these ini variables can be overriden by the vsim command
; line switch "-onfinish <ask|stop|exit>".
OnFinish = ask
 
; Print "simstats" result at the end of simulation before shutdown.
; If this is enabled, the simstats result will be printed out before shutdown.
; The default is off.
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA concurrent assertion pass enable.
; For SVA, Default is on when the assertion has a pass action block or vsim switch -assertdebug is used and the visibility flag "+acc=a" is turned on in vopt.
; For PSL, Default is on only when vsim switch "-assertdebug" is used and the visibility flag "+acc=a" is turned on in vopt.
; AssertionPassEnable = 0
 
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0
 
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1
 
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1
 
; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to not include them.
; ToggleVlogIntegers = 1
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off.
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enable or disable generation of more detailed information about the sampling of covergroup,
; cross, and coverpoints. It provides the details of the number of times the covergroup
; instance and type were sampled, as well as details about why covergroup, cross and
; coverpoint were not covered. A non-zero value is to enable this feature. 0 is to
; disable this feature. Default is 0;
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VsimZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VsimZeroInOptions = ""
 
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0
 
; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000
 
; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; SolveFailSeverity = 0
 
; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
 
; When SolveFailDebug is enabled, this value specifies the algorithm used to
; discover conflicts between constraints for randomize() failures.
; The default is "many".
;
; Valid schemes are:
; "many" = best for determining conflicts due to many related constraints
; "few" = best for determining conflicts due to few related constraints
;
; SolveFailDebugScheme = many
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum number of constraint subsets that will be tested for
; conflicts.
; The default is 0 (no limit).
; SolveFailDebugLimit = 0
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum size of constraint subsets that will be tested for
; conflicts.
; The default value is 0 (no limit).
; SolveFailDebugMaxSet = 0
 
; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the complexity of
; the constraint scenario (both in memory and time spent during evaluation)
; exceeds the specified limit. This value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of
; the constraint solver for others.
; The default value is "" (no options).
;
; Valid flags are:
; i = disable bit interleaving for >, >=, <, <= constraints
; n = disable bit interleaving for all constraints
; r = reverse bit interleaving
;
; SolveFlags =
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; Note: To achieve the same random sequences, solver optimizations and/or
; bug fixes introduced since the specified release may be disabled -
; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
 
; Control transcripting of Verilog display system task messages.
; These system tasks include $display[bho], $strobe[bho],
; Smonitor{bho], and $write[bho]. They also include the analogous
; file I/O tasks that write to STDOUT (i.e. $fwrite or $fdisplay).
; The default is to have messages appear only in the transcript.
; The other settings are to send messages to the wlf file only
; (messages that are recorded in the wlf file can be viewed in the
; MsgViewer) or to both the transcript and the wlf file. The valid
; values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
/tags/ver/src/topEntity.vhd
0,0 → 1,22
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
 
entity topEntity is
port( clk, rst : in std_logic;
lcd_data : out std_logic_vector (7 downto 0);
lcd_rs, lcd_rw, lcd_ena : out std_logic;
led : out std_logic_vector (0 downto 0) ); -- used for debug purposes
end topEntity;
 
architecture structural of topEntity is
signal clk_400 : std_logic; -- clock with 4us period, used for debug
begin
div1000: generic_freq_div
port map (clk_in => clk, clk => clk_400);
 
lcd_1: lcd1
port map (clk => clk, rst => rst, clk_400 => clk_400, lcd_rs => lcd_rs,
lcd_ena => lcd_ena, lcd_rw => lcd_rw,
lcd_data (7 downto 0) => lcd_data (7 downto 0), led(0) => led(0) );
end structural;
/tags/ver/src/topEntity.do
0,0 → 1,3
add wave *
run 1000 ns
restart -nowave
/tags/ver/src/asci_types.vhd
0,0 → 1,59
library ieee;
use ieee.std_logic_1164.all;
 
package asci_types is
type lcd_char is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL );
type lcd_matrix is array(natural range 1 TO 80) of lcd_char;
TYPE char_std_matrix IS array(lcd_char RANGE NUL TO DEL) OF std_logic_vector(7 DOWNTO 0);
constant char2std : char_std_matrix :=
("00000000", "00000001", "00000010", "00000011",
"00000100", "00000101", "00000110", "00000111",
"00001000", "00001001", "00001010", "00001011",
"00001100", "00001101", "00001110", "00001111",
"00010000", "00010001", "00010010", "00010011",
"00010100", "00010101", "00010110", "00010111",
"00011000", "00011001", "00011010", "00011011",
"00011100", "00011101", "00011110", "00011111",
"00100000", "00100001", "00100010", "00100011",
"00100100", "00100101", "00100110", "00100111",
"00101000", "00101001", "00101010", "00101011",
"00101100", "00101101", "00101110", "00101111",
"00110000", "00110001", "00110010", "00110011",
"00110100", "00110101", "00110110", "00110111",
"00111000", "00111001", "00111010", "00111011",
"00111100", "00111101", "00111110", "00111111",
"01000000", "01000001", "01000010", "01000011",
"01000100", "01000101", "01000110", "01000111",
"01001000", "01001001", "01001010", "01001011",
"01001100", "01001101", "01001110", "01001111",
"01010000", "01010001", "01010010", "01010011",
"01010100", "01010101", "01010110", "01010111",
"01011000", "01011001", "01011010", "01011011",
"01011100", "01011101", "01011110", "01011111",
"01100000", "01100001", "01100010", "01100011",
"01100100", "01100101", "01100110", "01100111",
"01101000", "01101001", "01101010", "01101011",
"01101100", "01101101", "01101110", "01101111",
"01110000", "01110001", "01110010", "01110011",
"01110100", "01110101", "01110110", "01110111",
"01111000", "01111001", "01111010", "01111011",
"01111100", "01111101", "01111110", "01111111");
END asci_types;
/tags/ver/src/lcd1.vhd
0,0 → 1,1260
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.asci_types.all;
 
ENTITY lcd1 IS
generic( one_usec_factor : INTEGER := 1e2/2-1; -- 1e8/2-1 for 1s period @ 100 MHz
max_factor : INTEGER := 100000; -- the longest delay needed (init. time)
init_factor : INTEGER := 100000; -- 100 ms, initialization time
normal_factor : INTEGER := 50; -- 50 us, standard waiting time
extended_factor : INTEGER := 2000; -- 2 ms, waiting time after clear display and cursor at home commands
constant ext_mode : std_logic_vector(9 downto 0) := "0000110100"; -- goto extension mode
constant lines_4 : std_logic_vector(9 downto 0) := "0000001001"; -- 4 lines, 5x8 font, goto normal mode
constant data_8bit : std_logic_vector(9 downto 0) := "0000110000"; -- 8 bit data
constant display_on : std_logic_vector(9 downto 0) := "0000001100"; -- display on, cursos off, blinking off
constant display_clear : std_logic_vector(9 downto 0) := "0000000001"; -- clear display
constant entry_mode : std_logic_vector(9 downto 0) := "0000000110" -- goto entry mode
);
port( clk_400, clk, rst : IN std_logic; -- low active reset, clk_400 has a 4 us period
lcd_rs : OUT std_logic; -- H=data L=command
lcd_rw : OUT std_logic; -- H=read L=write
lcd_ena : OUT STD_LOGIC;
lcd_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
led : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); -- used for debug purposes
END lcd1;
 
 
ARCHITECTURE behavioral OF lcd1 IS
TYPE state IS ( init_start, wait_set1, set1, wait_eset, eset, wait_set2, set2, wait_lcd_on,
lcd_on, wait_lcd_clear, lcd_clear, wait_lcd_entr, lcd_entr,
wait_l1s1, l1s1, wait_l1s2, l1s2, wait_l1s3, l1s3, wait_l1s4, l1s4, wait_l1s5, l1s5,
wait_l1s6, l1s6, wait_l1s7, l1s7, wait_l1s8, l1s8, wait_l1s9, l1s9, wait_l1s10, l1s10,
wait_l1s11, l1s11, wait_l1s12, l1s12, wait_l1s13, l1s13, wait_l1s14, l1s14, wait_l1s15, l1s15,
wait_l1s16, l1s16, wait_l1s17, l1s17, wait_l1s18, l1s18, wait_l1s19, l1s19, wait_l1s20, l1s20,
wait_l2s1, l2s1, wait_l2s2, l2s2, wait_l2s3, l2s3, wait_l2s4, l2s4, wait_l2s5, l2s5,
wait_l2s6, l2s6, wait_l2s7, l2s7, wait_l2s8, l2s8, wait_l2s9, l2s9, wait_l2s10, l2s10,
wait_l2s11, l2s11, wait_l2s12, l2s12, wait_l2s13, l2s13, wait_l2s14, l2s14, wait_l2s15, l2s15,
wait_l2s16, l2s16, wait_l2s17, l2s17, wait_l2s18, l2s18, wait_l2s19, l2s19, wait_l2s20, l2s20,
wait_l3s1, l3s1, wait_l3s2, l3s2, wait_l3s3, l3s3, wait_l3s4, l3s4, wait_l3s5, l3s5,
wait_l3s6, l3s6, wait_l3s7, l3s7, wait_l3s8, l3s8, wait_l3s9, l3s9, wait_l3s10, l3s10,
wait_l3s11, l3s11, wait_l3s12, l3s12, wait_l3s13, l3s13, wait_l3s14, l3s14, wait_l3s15, l3s15,
wait_l3s16, l3s16, wait_l3s17, l3s17, wait_l3s18, l3s18, wait_l3s19, l3s19, wait_l3s20, l3s20,
wait_l4s1, l4s1, wait_l4s2, l4s2, wait_l4s3, l4s3, wait_l4s4, l4s4, wait_l4s5, l4s5,
wait_l4s6, l4s6, wait_l4s7, l4s7, wait_l4s8, l4s8, wait_l4s9, l4s9, wait_l4s10, l4s10,
wait_l4s11, l4s11, wait_l4s12, l4s12, wait_l4s13, l4s13, wait_l4s14, l4s14, wait_l4s15, l4s15,
wait_l4s16, l4s16, wait_l4s17, l4s17, wait_l4s18, l4s18, wait_l4s19, l4s19, wait_l4s20, l4s20,
wait_new_line1, new_line1, wait_new_line2, new_line2, wait_new_line3, new_line3, wait_new_line4, new_line4,
wait_renew );
signal pr_state, nxt_state : state;
signal one_usec, rst_int : STD_LOGIC := '0';
signal counter : INTEGER RANGE 0 TO max_factor;
SIGNAL lcd_data_int : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal str1, lcd_reg : lcd_matrix;
BEGIN
lcd_reg <= str1;
str1 <= ( ' ',' ',' ',' ',' ','T','U',' ','C','h','e','m','n','i','t','z',' ',' ',' ',' ',
' ',' ',' ',' ',' ',' ',' ',' ','S','S','E',' ',' ',' ',' ',' ',' ',' ',' ',' ',
' ',' ','D','i','m','o',' ','P','e','p','e','l','y','a','s','h','e','v',' ',' ',
' ',' ',' ',' ',' ',' ',' ',' ','-','-','-',' ',' ',' ',' ',' ',' ',' ',' ',' ' );
lcd_rw <= '0'; -- only writing to the LCD needed, lcd_data_int(8) is never used
lcd_rs <= lcd_data_int(9);
lcd_data <= lcd_data_int(7 downto 0);
led(0) <= clk_400;
--------------------------------------------------------------------------------------
-- generates a signal with 1us period
--------------------------------------------------------------------------------------
one_sec_p: process(clk)
VARIABLE temp : integer RANGE 0 TO one_usec_factor;
begin
IF clk'event AND clk='1' THEN
IF rst_int='0' THEN
temp := 0;
one_usec <= '1'; -- because dalay_p counts on a positive transition
else
iF temp>=one_usec_factor THEN
temp := 0;
one_usec <= NOT one_usec;
else
temp := temp + 1;
END if;
END if;
END IF;
END process;
 
 
--------------------------------------------------------------------------------------
-- delays generetor
--------------------------------------------------------------------------------------
delay_p: process(clk)
variable temp0 : integer RANGE 0 TO max_factor;
VARIABLE flag : STD_LOGIC := '0';
BEGIN
IF clk'EVENT AND clk='1' THEN
IF rst_int='0' THEN
temp0 := 0;
else
IF one_usec='0' AND flag='1' THEN
flag := '0';
END IF;
--the following part is executed only on a positive transition of one_usec
IF one_usec='1' AND flag='0' THEN
flag := '1';
IF
temp0>=max_factor THEN
temp0 := 0;
ELSE
temp0 := temp0 + 1;
end if;
END if;
END if;
END if;
counter <= temp0;
END process;
 
-------------------------------------------------------------------------------
-- LCD enable signal generation
-------------------------------------------------------------------------------
lcd_en: process(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN
IF counter=1 THEN
lcd_ena <= '1';
ELSE
lcd_ena <= '0';
END IF;
END IF;
END process;
 
---------------------------------------------------------------------------------
-- MORE automat
---------------------------------------------------------------------------------
main_s_p: process(clk)
begin
if clk'event and clk='1' then
IF rst='0' THEN
pr_state <= init_start;
else
pr_state <= nxt_state;
end if;
END if;
end process;
 
 
main_c_p: process(pr_state,counter)
begin
case pr_state is
WHEN init_start =>
nxt_state <= wait_set1;
rst_int <= '0';
lcd_data_int <= (OTHERS => '0');
WHEN wait_set1 =>
IF counter>=init_factor THEN
nxt_state <= set1;
ELSE
nxt_state <= wait_set1;
END IF;
lcd_data_int <= (OTHERS => '0');
rst_int <= '1';
WHEN set1 =>
nxt_state <= wait_eset;
rst_int <= '0';
lcd_data_int <= ext_mode; -- goto extension mode
WHEN wait_eset =>
IF counter>=normal_factor THEN
nxt_state <= eset;
ELSE
nxt_state <= wait_eset;
END IF;
lcd_data_int <= ext_mode;
rst_int <= '1';
WHEN eset =>
nxt_state <= wait_set2;
rst_int <= '0';
lcd_data_int <= lines_4; -- 4 lines. 5x8 font, goto normal mode
WHEN wait_set2 =>
IF counter>=normal_factor THEN
nxt_state <= set2;
ELSE
nxt_state <= wait_set2;
END IF;
lcd_data_int <= lines_4;
rst_int <= '1';
WHEN set2 =>
nxt_state <= wait_lcd_on;
rst_int <= '0';
lcd_data_int <= data_8bit; -- 8 bit data
WHEN wait_lcd_on =>
IF counter>=normal_factor THEN
nxt_state <= lcd_on;
ELSE
nxt_state <= wait_lcd_on;
END IF;
lcd_data_int <= data_8bit;
rst_int <= '1';
WHEN lcd_on =>
nxt_state <= wait_lcd_clear;
rst_int <= '0';
lcd_data_int <= display_on; -- display on, cursor off, blinking off,
WHEN wait_lcd_clear =>
IF counter>=normal_factor THEN
nxt_state <= lcd_clear;
ELSE
nxt_state <= wait_lcd_clear;
END IF;
lcd_data_int <= display_on;
rst_int <= '1';
WHEN lcd_clear =>
nxt_state <= wait_lcd_entr;
rst_int <= '0';
lcd_data_int <= display_clear; -- clear display
WHEN wait_lcd_entr =>
IF counter>=extended_factor THEN
nxt_state <= lcd_entr;
ELSE
nxt_state <= wait_lcd_entr;
END IF;
lcd_data_int <= display_clear;
rst_int <= '1';
WHEN lcd_entr =>
nxt_state <= wait_l1s1;
rst_int <= '0';
lcd_data_int <= entry_mode; -- goto entry mode, cursor moves right, shift off
WHEN wait_l1s1 =>
IF counter>=normal_factor THEN
nxt_state <= l1s1;
ELSE
nxt_state <= wait_l1s1;
END IF;
lcd_data_int <= entry_mode;
rst_int <= '1';
-------------------------------------------------------------------------------
-- line 1
-------------------------------------------------------------------------------
WHEN l1s1 =>
nxt_state <= wait_l1s2;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(1));
WHEN wait_l1s2 =>
IF counter>=normal_factor THEN
nxt_state <= l1s2;
ELSE
nxt_state <= wait_l1s2;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(1));
rst_int <= '1';
WHEN l1s2 =>
nxt_state <= wait_l1s3;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(2));
WHEN wait_l1s3 =>
IF counter>=normal_factor THEN
nxt_state <= l1s3;
ELSE
nxt_state <= wait_l1s3;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(2));
rst_int <= '1';
WHEN l1s3 =>
nxt_state <= wait_l1s4;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(3));
WHEN wait_l1s4 =>
IF counter>=normal_factor THEN
nxt_state <= l1s4;
ELSE
nxt_state <= wait_l1s4;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(3));
rst_int <= '1';
WHEN l1s4 =>
nxt_state <= wait_l1s5;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(4));
WHEN wait_l1s5 =>
IF counter>=normal_factor THEN
nxt_state <= l1s5;
ELSE
nxt_state <= wait_l1s5;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(4));
rst_int <= '1';
WHEN l1s5 =>
nxt_state <= wait_l1s6;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(5));
WHEN wait_l1s6 =>
IF counter>=normal_factor THEN
nxt_state <= l1s6;
ELSE
nxt_state <= wait_l1s6;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(5));
rst_int <= '1';
WHEN l1s6 =>
nxt_state <= wait_l1s7;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(6));
WHEN wait_l1s7 =>
IF counter>=normal_factor THEN
nxt_state <= l1s7;
ELSE
nxt_state <= wait_l1s7;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(6));
rst_int <= '1';
WHEN l1s7 =>
nxt_state <= wait_l1s8;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(7));
WHEN wait_l1s8 =>
IF counter>=normal_factor THEN
nxt_state <= l1s8;
ELSE
nxt_state <= wait_l1s8;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(7));
rst_int <= '1';
WHEN l1s8 =>
nxt_state <= wait_l1s9;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(8));
WHEN wait_l1s9 =>
IF counter>=normal_factor THEN
nxt_state <= l1s9;
ELSE
nxt_state <= wait_l1s9;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(8));
rst_int <= '1';
WHEN l1s9 =>
nxt_state <= wait_l1s10;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(9));
WHEN wait_l1s10 =>
IF counter>=normal_factor THEN
nxt_state <= l1s10;
ELSE
nxt_state <= wait_l1s10;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(9));
rst_int <= '1';
WHEN l1s10 =>
nxt_state <= wait_l1s11;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(10));
WHEN wait_l1s11 =>
IF counter>=normal_factor THEN
nxt_state <= l1s11;
ELSE
nxt_state <= wait_l1s11;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(10));
rst_int <= '1';
WHEN l1s11 =>
nxt_state <= wait_l1s12;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(11));
WHEN wait_l1s12 =>
IF counter>=normal_factor THEN
nxt_state <= l1s12;
ELSE
nxt_state <= wait_l1s12;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(11));
rst_int <= '1';
WHEN l1s12 =>
nxt_state <= wait_l1s13;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(12));
WHEN wait_l1s13 =>
IF counter>=normal_factor THEN
nxt_state <= l1s13;
ELSE
nxt_state <= wait_l1s13;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(12));
rst_int <= '1';
WHEN l1s13 =>
nxt_state <= wait_l1s14;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(13));
WHEN wait_l1s14 =>
IF counter>=normal_factor THEN
nxt_state <= l1s14;
ELSE
nxt_state <= wait_l1s14;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(13));
rst_int <= '1';
WHEN l1s14 =>
nxt_state <= wait_l1s15;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(14));
WHEN wait_l1s15 =>
IF counter>=normal_factor THEN
nxt_state <= l1s15;
ELSE
nxt_state <= wait_l1s15;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(14));
rst_int <= '1';
WHEN l1s15 =>
nxt_state <= wait_l1s16;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(15));
WHEN wait_l1s16 =>
IF counter>=normal_factor THEN
nxt_state <= l1s16;
ELSE
nxt_state <= wait_l1s16;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(15));
rst_int <= '1';
WHEN l1s16 =>
nxt_state <= wait_l1s17;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(16));
WHEN wait_l1s17 =>
IF counter>=normal_factor THEN
nxt_state <= l1s17;
ELSE
nxt_state <= wait_l1s17;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(16));
rst_int <= '1';
WHEN l1s17 =>
nxt_state <= wait_l1s18;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(17));
WHEN wait_l1s18 =>
IF counter>=normal_factor THEN
nxt_state <= l1s18;
ELSE
nxt_state <= wait_l1s18;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(17));
rst_int <= '1';
WHEN l1s18 =>
nxt_state <= wait_l1s19;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(18));
WHEN wait_l1s19 =>
IF counter>=normal_factor THEN
nxt_state <= l1s19;
ELSE
nxt_state <= wait_l1s19;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(18));
rst_int <= '1';
WHEN l1s19 =>
nxt_state <= wait_l1s20;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(19));
WHEN wait_l1s20 =>
IF counter>=normal_factor THEN
nxt_state <= l1s20;
ELSE
nxt_state <= wait_l1s20;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(19));
rst_int <= '1';
WHEN l1s20 =>
nxt_state <= wait_new_line1;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(20));
WHEN wait_new_line1 =>
IF counter>=normal_factor THEN
nxt_state <= new_line1;
ELSE
nxt_state <= wait_new_line1;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(20));
rst_int <= '1';
WHEN new_line1 =>
nxt_state <= wait_l2s1;
rst_int <= '0';
lcd_data_int <= "0010100000";
WHEN wait_l2s1 =>
IF counter>=normal_factor THEN
nxt_state <= l2s1;
ELSE
nxt_state <= wait_l2s1;
END IF;
lcd_data_int <= "0010100000";
rst_int <= '1';
-------------------------------------------------------------------------------
-- line 2
-------------------------------------------------------------------------------
WHEN l2s1 =>
nxt_state <= wait_l2s2;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(21));
WHEN wait_l2s2 =>
IF counter>=normal_factor THEN
nxt_state <= l2s2;
ELSE
nxt_state <= wait_l2s2;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(21));
rst_int <= '1';
WHEN l2s2 =>
nxt_state <= wait_l2s3;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(22));
WHEN wait_l2s3 =>
IF counter>=normal_factor THEN
nxt_state <= l2s3;
ELSE
nxt_state <= wait_l2s3;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(22));
rst_int <= '1';
WHEN l2s3 =>
nxt_state <= wait_l2s4;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(23));
WHEN wait_l2s4 =>
IF counter>=normal_factor THEN
nxt_state <= l2s4;
ELSE
nxt_state <= wait_l2s4;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(23));
rst_int <= '1';
WHEN l2s4 =>
nxt_state <= wait_l2s5;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(24));
WHEN wait_l2s5 =>
IF counter>=normal_factor THEN
nxt_state <= l2s5;
ELSE
nxt_state <= wait_l2s5;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(24));
rst_int <= '1';
WHEN l2s5 =>
nxt_state <= wait_l2s6;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(25));
WHEN wait_l2s6 =>
IF counter>=normal_factor THEN
nxt_state <= l2s6;
ELSE
nxt_state <= wait_l2s6;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(25));
rst_int <= '1';
WHEN l2s6 =>
nxt_state <= wait_l2s7;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(26));
WHEN wait_l2s7 =>
IF counter>=normal_factor THEN
nxt_state <= l2s7;
ELSE
nxt_state <= wait_l2s7;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(26));
rst_int <= '1';
WHEN l2s7 =>
nxt_state <= wait_l2s8;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(27));
WHEN wait_l2s8 =>
IF counter>=normal_factor THEN
nxt_state <= l2s8;
ELSE
nxt_state <= wait_l2s8;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(27));
rst_int <= '1';
WHEN l2s8 =>
nxt_state <= wait_l2s9;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(28));
WHEN wait_l2s9 =>
IF counter>=normal_factor THEN
nxt_state <= l2s9;
ELSE
nxt_state <= wait_l2s9;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(28));
rst_int <= '1';
WHEN l2s9 =>
nxt_state <= wait_l2s10;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(29));
WHEN wait_l2s10 =>
IF counter>=normal_factor THEN
nxt_state <= l2s10;
ELSE
nxt_state <= wait_l2s10;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(29));
rst_int <= '1';
WHEN l2s10 =>
nxt_state <= wait_l2s11;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(30));
WHEN wait_l2s11 =>
IF counter>=normal_factor THEN
nxt_state <= l2s11;
ELSE
nxt_state <= wait_l2s11;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(30));
rst_int <= '1';
WHEN l2s11 =>
nxt_state <= wait_l2s12;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(31));
WHEN wait_l2s12 =>
IF counter>=normal_factor THEN
nxt_state <= l2s12;
ELSE
nxt_state <= wait_l2s12;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(31));
rst_int <= '1';
WHEN l2s12 =>
nxt_state <= wait_l2s13;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(32));
WHEN wait_l2s13 =>
IF counter>=normal_factor THEN
nxt_state <= l2s13;
ELSE
nxt_state <= wait_l2s13;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(32));
rst_int <= '1';
WHEN l2s13 =>
nxt_state <= wait_l2s14;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(33));
WHEN wait_l2s14 =>
IF counter>=normal_factor THEN
nxt_state <= l2s14;
ELSE
nxt_state <= wait_l2s14;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(33));
rst_int <= '1';
WHEN l2s14 =>
nxt_state <= wait_l2s15;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(34));
WHEN wait_l2s15 =>
IF counter>=normal_factor THEN
nxt_state <= l2s15;
ELSE
nxt_state <= wait_l2s15;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(34));
rst_int <= '1';
WHEN l2s15 =>
nxt_state <= wait_l2s16;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(35));
WHEN wait_l2s16 =>
IF counter>=normal_factor THEN
nxt_state <= l2s16;
ELSE
nxt_state <= wait_l2s16;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(35));
rst_int <= '1';
WHEN l2s16 =>
nxt_state <= wait_l2s17;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(36));
WHEN wait_l2s17 =>
IF counter>=normal_factor THEN
nxt_state <= l2s17;
ELSE
nxt_state <= wait_l2s17;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(36));
rst_int <= '1';
WHEN l2s17 =>
nxt_state <= wait_l2s18;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(37));
WHEN wait_l2s18 =>
IF counter>=normal_factor THEN
nxt_state <= l2s18;
ELSE
nxt_state <= wait_l2s18;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(37));
rst_int <= '1';
WHEN l2s18 =>
nxt_state <= wait_l2s19;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(38));
WHEN wait_l2s19 =>
IF counter>=normal_factor THEN
nxt_state <= l2s19;
ELSE
nxt_state <= wait_l2s19;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(38));
rst_int <= '1';
WHEN l2s19 =>
nxt_state <= wait_l2s20;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(39));
WHEN wait_l2s20 =>
IF counter>=normal_factor THEN
nxt_state <= l2s20;
ELSE
nxt_state <= wait_l2s20;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(39));
rst_int <= '1';
WHEN l2s20 =>
nxt_state <= wait_new_line2;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(40));
WHEN wait_new_line2 =>
IF counter>=normal_factor THEN
nxt_state <= new_line2;
ELSE
nxt_state <= wait_new_line2;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(40));
rst_int <= '1';
WHEN new_line2 =>
nxt_state <= wait_l3s1;
rst_int <= '0';
lcd_data_int <= "0011000000";
WHEN wait_l3s1 =>
IF counter>=normal_factor THEN
nxt_state <= l3s1;
ELSE
nxt_state <= wait_l3s1;
END IF;
lcd_data_int <= "0011000000";
rst_int <= '1';
 
-------------------------------------------------------------------------------
-- line 3
-------------------------------------------------------------------------------
WHEN l3s1 =>
nxt_state <= wait_l3s2;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(41));
WHEN wait_l3s2 =>
IF counter>=normal_factor THEN
nxt_state <= l3s2;
ELSE
nxt_state <= wait_l3s2;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(41));
rst_int <= '1';
WHEN l3s2 =>
nxt_state <= wait_l3s3;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(42));
WHEN wait_l3s3 =>
IF counter>=normal_factor THEN
nxt_state <= l3s3;
ELSE
nxt_state <= wait_l3s3;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(42));
rst_int <= '1';
WHEN l3s3 =>
nxt_state <= wait_l3s4;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(43));
WHEN wait_l3s4 =>
IF counter>=normal_factor THEN
nxt_state <= l3s4;
ELSE
nxt_state <= wait_l3s4;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(43));
rst_int <= '1';
WHEN l3s4 =>
nxt_state <= wait_l3s5;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(44));
WHEN wait_l3s5 =>
IF counter>=normal_factor THEN
nxt_state <= l3s5;
ELSE
nxt_state <= wait_l3s5;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(44));
rst_int <= '1';
WHEN l3s5 =>
nxt_state <= wait_l3s6;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(45));
WHEN wait_l3s6 =>
IF counter>=normal_factor THEN
nxt_state <= l3s6;
ELSE
nxt_state <= wait_l3s6;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(45));
rst_int <= '1';
WHEN l3s6 =>
nxt_state <= wait_l3s7;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(46));
WHEN wait_l3s7 =>
IF counter>=normal_factor THEN
nxt_state <= l3s7;
ELSE
nxt_state <= wait_l3s7;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(46));
rst_int <= '1';
WHEN l3s7 =>
nxt_state <= wait_l3s8;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(47));
WHEN wait_l3s8 =>
IF counter>=normal_factor THEN
nxt_state <= l3s8;
ELSE
nxt_state <= wait_l3s8;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(47));
rst_int <= '1';
WHEN l3s8 =>
nxt_state <= wait_l3s9;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(48));
WHEN wait_l3s9 =>
IF counter>=normal_factor THEN
nxt_state <= l3s9;
ELSE
nxt_state <= wait_l3s9;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(48));
rst_int <= '1';
WHEN l3s9 =>
nxt_state <= wait_l3s10;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(49));
WHEN wait_l3s10 =>
IF counter>=normal_factor THEN
nxt_state <= l3s10;
ELSE
nxt_state <= wait_l3s10;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(49));
rst_int <= '1';
WHEN l3s10 =>
nxt_state <= wait_l3s11;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(50));
WHEN wait_l3s11 =>
IF counter>=normal_factor THEN
nxt_state <= l3s11;
ELSE
nxt_state <= wait_l3s11;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(50));
rst_int <= '1';
WHEN l3s11 =>
nxt_state <= wait_l3s12;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(51));
WHEN wait_l3s12 =>
IF counter>=normal_factor THEN
nxt_state <= l3s12;
ELSE
nxt_state <= wait_l3s12;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(51));
rst_int <= '1';
WHEN l3s12 =>
nxt_state <= wait_l3s13;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(52));
WHEN wait_l3s13 =>
IF counter>=normal_factor THEN
nxt_state <= l3s13;
ELSE
nxt_state <= wait_l3s13;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(52));
rst_int <= '1';
WHEN l3s13 =>
nxt_state <= wait_l3s14;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(53));
WHEN wait_l3s14 =>
IF counter>=normal_factor THEN
nxt_state <= l3s14;
ELSE
nxt_state <= wait_l3s14;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(53));
rst_int <= '1';
WHEN l3s14 =>
nxt_state <= wait_l3s15;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(54));
WHEN wait_l3s15 =>
IF counter>=normal_factor THEN
nxt_state <= l3s15;
ELSE
nxt_state <= wait_l3s15;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(54));
rst_int <= '1';
WHEN l3s15 =>
nxt_state <= wait_l3s16;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(55));
WHEN wait_l3s16 =>
IF counter>=normal_factor THEN
nxt_state <= l3s16;
ELSE
nxt_state <= wait_l3s16;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(55));
rst_int <= '1';
WHEN l3s16 =>
nxt_state <= wait_l3s17;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(56));
WHEN wait_l3s17 =>
IF counter>=normal_factor THEN
nxt_state <= l3s17;
ELSE
nxt_state <= wait_l3s17;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(56));
rst_int <= '1';
WHEN l3s17 =>
nxt_state <= wait_l3s18;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(57));
WHEN wait_l3s18 =>
IF counter>=normal_factor THEN
nxt_state <= l3s18;
ELSE
nxt_state <= wait_l3s18;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(57));
rst_int <= '1';
WHEN l3s18 =>
nxt_state <= wait_l3s19;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(58));
WHEN wait_l3s19 =>
IF counter>=normal_factor THEN
nxt_state <= l3s19;
ELSE
nxt_state <= wait_l3s19;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(58));
rst_int <= '1';
WHEN l3s19 =>
nxt_state <= wait_l3s20;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(59));
WHEN wait_l3s20 =>
IF counter>=normal_factor THEN
nxt_state <= l3s20;
ELSE
nxt_state <= wait_l3s20;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(59));
rst_int <= '1';
WHEN l3s20 =>
nxt_state <= wait_new_line3;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(60));
WHEN wait_new_line3 =>
IF counter>=normal_factor THEN
nxt_state <= new_line3;
ELSE
nxt_state <= wait_new_line3;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(60));
rst_int <= '1';
WHEN new_line3 =>
nxt_state <= wait_l4s1;
rst_int <= '0';
lcd_data_int <= "0011100000";
WHEN wait_l4s1 =>
IF counter>=normal_factor THEN
nxt_state <= l4s1;
ELSE
nxt_state <= wait_l4s1;
END IF;
lcd_data_int <= "0011100000";
rst_int <= '1';
 
-------------------------------------------------------------------------------
-- line 4
-------------------------------------------------------------------------------
WHEN l4s1 =>
nxt_state <= wait_l4s2;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(61));
WHEN wait_l4s2 =>
IF counter>=normal_factor THEN
nxt_state <= l4s2;
ELSE
nxt_state <= wait_l4s2;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(61));
rst_int <= '1';
WHEN l4s2 =>
nxt_state <= wait_l4s3;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(62));
WHEN wait_l4s3 =>
IF counter>=normal_factor THEN
nxt_state <= l4s3;
ELSE
nxt_state <= wait_l4s3;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(62));
rst_int <= '1';
WHEN l4s3 =>
nxt_state <= wait_l4s4;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(63));
WHEN wait_l4s4 =>
IF counter>=normal_factor THEN
nxt_state <= l4s4;
ELSE
nxt_state <= wait_l4s4;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(63));
rst_int <= '1';
WHEN l4s4 =>
nxt_state <= wait_l4s5;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(64));
WHEN wait_l4s5 =>
IF counter>=normal_factor THEN
nxt_state <= l4s5;
ELSE
nxt_state <= wait_l4s5;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(64));
rst_int <= '1';
WHEN l4s5 =>
nxt_state <= wait_l4s6;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(65));
WHEN wait_l4s6 =>
IF counter>=normal_factor THEN
nxt_state <= l4s6;
ELSE
nxt_state <= wait_l4s6;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(65));
rst_int <= '1';
WHEN l4s6 =>
nxt_state <= wait_l4s7;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(66));
WHEN wait_l4s7 =>
IF counter>=normal_factor THEN
nxt_state <= l4s7;
ELSE
nxt_state <= wait_l4s7;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(66));
rst_int <= '1';
WHEN l4s7 =>
nxt_state <= wait_l4s8;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(67));
WHEN wait_l4s8 =>
IF counter>=normal_factor THEN
nxt_state <= l4s8;
ELSE
nxt_state <= wait_l4s8;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(67));
rst_int <= '1';
WHEN l4s8 =>
nxt_state <= wait_l4s9;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(68));
WHEN wait_l4s9 =>
IF counter>=normal_factor THEN
nxt_state <= l4s9;
ELSE
nxt_state <= wait_l4s9;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(68));
rst_int <= '1';
WHEN l4s9 =>
nxt_state <= wait_l4s10;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(69));
WHEN wait_l4s10 =>
IF counter>=normal_factor THEN
nxt_state <= l4s10;
ELSE
nxt_state <= wait_l4s10;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(69));
rst_int <= '1';
WHEN l4s10 =>
nxt_state <= wait_l4s11;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(70));
WHEN wait_l4s11 =>
IF counter>=normal_factor THEN
nxt_state <= l4s11;
ELSE
nxt_state <= wait_l4s11;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(70));
rst_int <= '1';
WHEN l4s11 =>
nxt_state <= wait_l4s12;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(71));
WHEN wait_l4s12 =>
IF counter>=normal_factor THEN
nxt_state <= l4s12;
ELSE
nxt_state <= wait_l4s12;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(71));
rst_int <= '1';
WHEN l4s12 =>
nxt_state <= wait_l4s13;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(72));
WHEN wait_l4s13 =>
IF counter>=normal_factor THEN
nxt_state <= l4s13;
ELSE
nxt_state <= wait_l4s13;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(72));
rst_int <= '1';
WHEN l4s13 =>
nxt_state <= wait_l4s14;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(73));
WHEN wait_l4s14 =>
IF counter>=normal_factor THEN
nxt_state <= l4s14;
ELSE
nxt_state <= wait_l4s14;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(73));
rst_int <= '1';
WHEN l4s14 =>
nxt_state <= wait_l4s15;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(74));
WHEN wait_l4s15 =>
IF counter>=normal_factor THEN
nxt_state <= l4s15;
ELSE
nxt_state <= wait_l4s15;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(74));
rst_int <= '1';
WHEN l4s15 =>
nxt_state <= wait_l4s16;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(75));
WHEN wait_l4s16 =>
IF counter>=normal_factor THEN
nxt_state <= l4s16;
ELSE
nxt_state <= wait_l4s16;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(75));
rst_int <= '1';
WHEN l4s16 =>
nxt_state <= wait_l4s17;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(76));
WHEN wait_l4s17 =>
IF counter>=normal_factor THEN
nxt_state <= l4s17;
ELSE
nxt_state <= wait_l4s17;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(76));
rst_int <= '1';
WHEN l4s17 =>
nxt_state <= wait_l4s18;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(77));
WHEN wait_l4s18 =>
IF counter>=normal_factor THEN
nxt_state <= l4s18;
ELSE
nxt_state <= wait_l4s18;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(77));
rst_int <= '1';
WHEN l4s18 =>
nxt_state <= wait_l4s19;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(78));
WHEN wait_l4s19 =>
IF counter>=normal_factor THEN
nxt_state <= l4s19;
ELSE
nxt_state <= wait_l4s19;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(78));
rst_int <= '1';
WHEN l4s19 =>
nxt_state <= wait_l4s20;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(79));
WHEN wait_l4s20 =>
IF counter>=normal_factor THEN
nxt_state <= l4s20;
ELSE
nxt_state <= wait_l4s20;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(79));
rst_int <= '1';
WHEN l4s20 =>
nxt_state <= wait_new_line4;
rst_int <= '0';
lcd_data_int <= '1' & '0' & char2std(lcd_reg(80));
WHEN wait_new_line4 =>
IF counter>=normal_factor THEN
nxt_state <= new_line4;
ELSE
nxt_state <= wait_new_line4;
END IF;
lcd_data_int <= '1' & '0' & char2std(lcd_reg(80));
rst_int <= '1';
WHEN new_line4 =>
nxt_state <= wait_renew;
rst_int <= '0';
lcd_data_int <= "0000000010";
WHEN wait_renew =>
IF counter>=extended_factor THEN
nxt_state <= l1s1;
ELSE
nxt_state <= wait_renew;
END IF;
lcd_data_int <= "0000000010";
rst_int <= '1';
WHEN OTHERS =>
nxt_state <= init_start;
rst_int <= '0';
lcd_data_int <= (OTHERS => '0');
END case;
END process;
END behavioral;
/tags/ver/src/topEntity_tb.vhd
0,0 → 1,87
 
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:44:54 03/26/2008
-- Design Name: counter
-- Module Name: counter_tb.vhd
-- Project Name: clk_tb
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: counter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY topEntity_tb IS
END topEntity_tb;
 
ARCHITECTURE behavior OF topEntity_tb IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topEntity
PORT(
clk : IN std_logic;
rst : IN std_logic;
lcd_data : OUT std_logic_vector(7 downto 0);
lcd_ena, lcd_rs, lcd_rw : out std_logic;
led : out std_logic_vector (0 downto 0) );
 
END COMPONENT;
 
--Inputs
SIGNAL clk : std_logic := '0';
signal rst : std_logic := '1'; -- low active reset
--Outputs
SIGNAL lcd_data : std_logic_vector(7 downto 0);
signal lcd_ena, lcd_rs, lcd_rw : std_logic;
signal led : std_logic_vector (0 downto 0);
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: topEntity PORT MAP(
clk => clk,
rst => rst, lcd_ena => lcd_ena, lcd_rs => lcd_rs, lcd_rw => lcd_rw,
lcd_data => lcd_data, led => led
);
 
tb_clk : PROCESS
BEGIN
 
-- Wait 100 ns for global reset to finish
--wait for 100 ns;
 
clk <= not clk;
wait for 5 ns;
-- Place stimulus here
END PROCESS;
 
tb_s: PROCESS
BEGIN
wait for 15 ms;
rst <= '0';
wait for 25 ms;
rst <= '1';
wait;
 
END PROCESS;
END;
/tags/ver/src/BACKUP/topEntity.vhd
0,0 → 1,22
library ieee;
use ieee.std_logic_1164.all;
use work.components.all;
 
entity topEntity is
port( clk, j_down : in std_logic;
lcd_data : out std_logic_vector (7 downto 0);
lcd_rs, lcd_rw, lcd_ena : out std_logic );
end topEntity;
 
architecture structural of topEntity is
signal clk_400 : std_logic;
begin
div1000: generic_freq_div
port map (clk_in => clk, clk => clk_400);
 
lcd_1: lcd1
port map (clk => clk, rst => j_down, clk_400 => clk_400, lcd_rs => lcd_rs,
lcd_ena => lcd_ena, lcd_rw => lcd_rw,
lcd_data (7 downto 0) => lcd_data (7 downto 0) );
end structural;
/tags/ver/src/BACKUP/lcd.txt
0,0 → 1,242
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity lcd is
Port ( lcd_data : out std_logic_vector (7 downto 4);
clk : in std_logic;
reset : in std_logic;
lcd_enable : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end lcd ;
 
architecture behavioural of lcd is
 
type state_type is (warmup, setfunc, clear1, clear2, setmode1, setmode2, write1, home1, home2);
 
signal state : state_type;
 
attribute syn_state_machine : boolean;
attribute syn_state_machine of state : signal is true;
 
signal count : std_logic_vector(3 downto 0);
signal finished : std_logic; -- set high if done write cycle
 
signal char_mode : std_logic_vector(1 downto 0);
 
--defining the display
constant N: integer :=8;
type arr is array (1 to N) of std_logic_vector(7 downto 0);
 
constant display_char1 : arr := (x"A0", --blank
X"68", --h
X"74", --t
X"74", --t
X"70", --p
X"3A", --:
X"2F", --/
X"2F"); --/
 
constant display_char2 : arr := (X"77", --w
X"77", --w
X"77", --w
X"2E", --.
X"66", --f
X"70", --p
X"67", --g
X"61"); --a
 
constant display_char3 : arr := (X"2E", --.
X"62", --b
X"65", --e
X"88", --blank
X"88", --blank
X"88", --blank
X"88", --blank
X"88"); --blank
 
constant display_char4 : arr := (X"A0", --blank
X"88", --blank
X"58", --X
X"49", --I
X"4F", --O
X"53", --S
X"88", --blank
X"88"); --blank
 
signal display_char : arr;
 
begin
lcd_rw <= '0';
lcd_enable <= clk; --not clk; -- this is very important! if enable is not pulsed, lcd will not write
 
char_mode_process: process (char_mode)
begin
case char_mode is
when "00" =>
display_char <= display_char1;
when "01" =>
display_char <= display_char2;
when "10" =>
display_char <= display_char3;
when "11" =>
display_char <= display_char4;
when OTHERS =>
display_char <= display_char1;
end case;
end process;
 
state_set: process (clk, reset, finished)
begin
if (reset = '1') then
 
state <= warmup; --setfunc;
count <= (others => '0');
char_mode <= (others => '0');
 
elsif (clk'event and clk = '1') then
case state is
 
when warmup =>
lcd_rs <= '0';
lcd_data <= "0011"; --"0000"; -- do nothing
if count = "0111" then --0111
count <= (others => '0');
state <= setfunc;
else
count <= count + '1';
state <= warmup;
end if;
 
when setfunc =>
lcd_rs <= '0';
lcd_data <= "0010";
finished <= '0';
 
if count = "0010" then --0010
count <= (others => '0');
state <= clear1;
else
count <= count + '1';
state <= setfunc;
end if;
 
when clear1 =>
 
lcd_rs <= '0';
lcd_data <= "0000";
state <= clear2;
 
when clear2 =>
lcd_rs <= '0';
if count = "0111" then
state <= setmode1;
count <= (others => '0');
lcd_data <= "1111";
else
count <= count + '1';
lcd_data <= "0001";
state <= clear1;
end if;
 
when setmode1 =>
lcd_rs <= '0';
lcd_data <= "0000";
state <= setmode2;
finished <= '0';
 
when setmode2 =>
lcd_rs <= '0';
lcd_data <= "0110";
state <= write1;
 
when write1 =>
if finished = '1' then
state <= home1;
else
lcd_rs <= '1';
count <= count + '1';
state <= write1;
 
CASE count IS
 
WHEN "0000" =>
lcd_data <= display_char(1)(7 downto 4);
 
WHEN "0001" =>
lcd_data <= display_char(1)(3 downto 0);
 
WHEN "0010" =>
lcd_data <= display_char(2)(7 downto 4);
 
WHEN "0011" =>
lcd_data <= display_char(2)(3 downto 0);
 
WHEN "0100"=>
lcd_data <= display_char(3)(7 downto 4);
 
WHEN "0101"=>
lcd_data <= display_char(3)(3 downto 0);
 
WHEN "0110"=>
lcd_data <= display_char(4)(7 downto 4);
 
WHEN "0111"=>
lcd_data <= display_char(4)(3 downto 0);
 
WHEN "1000" =>
lcd_data <= display_char(5)(7 downto 4);
 
WHEN "1001" =>
lcd_data <= display_char(5)(3 downto 0);
 
WHEN "1010" =>
lcd_data <= display_char(6)(7 downto 4);
 
WHEN "1011" =>
lcd_data <= display_char(6)(3 downto 0);
 
WHEN "1100" =>
lcd_data <= display_char(7)(7 downto 4);
 
WHEN "1101" =>
lcd_data <= display_char(7)(3 downto 0);
 
WHEN "1110" =>
lcd_data <= display_char(8)(7 downto 4);
--finished <= '1'; -- needed to set done low before valid data is gone
--char_mode <= char_mode + '1';
 
WHEN "1111" =>
lcd_data <= display_char(8)(3 downto 0);
finished <= '1'; -- needed to set done low before valid data is gone
char_mode <= char_mode + '1';
 
WHEN OTHERS =>
lcd_data <= "0000"; -- ' '
 
END CASE;
end if;
 
when home1 =>
lcd_rs <= '0';
lcd_data <= "0000";
state <= home2;
finished <= '0';
count <= (others => '0');
 
when home2 =>
lcd_rs <= '0';
lcd_data <= "0111";
state <= write1;
 
end case;
 
end if;
 
end process;
 
end behavioural;
tags/ver/src/BACKUP/lcd.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/ver/src/BACKUP/topEntity.do =================================================================== --- tags/ver/src/BACKUP/topEntity.do (nonexistent) +++ tags/ver/src/BACKUP/topEntity.do (revision 3) @@ -0,0 +1,3 @@ +add wave * +run 1000 ns +restart -nowave Index: tags/ver/src/BACKUP/array_types.vhd =================================================================== --- tags/ver/src/BACKUP/array_types.vhd (nonexistent) +++ tags/ver/src/BACKUP/array_types.vhd (revision 3) @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +package array_types is +-- type vector_array is array(natural range <>) of std_logic_vector(7 downto 0); + type vector_array is array(natural range <>, natural range <>) of std_logic; +end array_types; + + \ No newline at end of file Index: tags/ver/src/BACKUP/examle2_tb.vhd =================================================================== --- tags/ver/src/BACKUP/examle2_tb.vhd (nonexistent) +++ tags/ver/src/BACKUP/examle2_tb.vhd (revision 3) @@ -0,0 +1,103 @@ +-------------------------------------------------------------------------------- +-- Company: TU Chemnitz, SSE +-- Engineer: Dimo Pepelyashev +-- +-- Create Date: 17:08:23 03/13/2008 +-- Design Name: dff +-- Module Name: dff_tb.vhd +-- Project Name: dff +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Test Bench for module: dff +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY tlc_tb IS +END tcl_tb; + +ARCHITECTURE behavior OF tlc_tb IS + + type sample is record + clk : std_logic; + rst : std_logic; + j-left, j_right : std_logic; + led : std_logic_vector (2 downto 0); + end record; + + type sample_array is array(natural range <>) of sample; + + constant test_data : sample_array := + ( ('1','0','1', '0'), + ('0','0','1', '0'), + ('1','0','0', '0'), + ('0','0','1', '0'), + ('1','0','1', '0'), + ('0','0','1', '0'), + ('1','0','1', '0'), + ('0','0','1', '0'), + ('1','0','1', '1'), + ('0','1','1', '0'), + ('1','1','0', '0'), + ('0','0','1', '0'), + ('1','0','1', '0'), + ('0','0','1', '0'), + ('1','0','0', '0'), + ('0','0','0', '0'), + ('1','0','0', '1'), + ('0','0','0', '0'), + ('1','0','0', '0'), + ('0','0','1', '0'), + ('1','0','1', '0'), + ('0','0','1', '0'), + ('1','0','1', '0') + ); + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT fsm_detector + PORT( + clk : IN std_logic; + rst : in std_logic; + d : in std_logic; + output : out std_logic ); + END COMPONENT; + + --Inputs + SIGNAL clk : std_logic := '0'; + SIGNAL rst : std_logic := '0'; + signal d : std_logic := '0'; + --Outputs + SIGNAL output : std_logic; + + +BEGIN +uut: fsm_detector -- Instantiate the Unit Under Test (UUT) + PORT MAP( clk => clk, + rst => rst, + d => d, + output => output ); + +tb: PROCESS + BEGIN + wait for 100 ns; -- Wait 100 ns for global reset to finish + for i in test_data'range loop + clk <= test_data(i).clk; + rst <= test_data(i).rst; + d <= test_data(i).d; +-- wait for 1 ns; --dimo + wait for 2 ns; + assert output = test_data(i).output + report "wrong output!" + severity error; + end loop; + wait; -- will wait forever + END PROCESS; +END; Index: tags/ver/src/BACKUP/lcd.vhd =================================================================== --- tags/ver/src/BACKUP/lcd.vhd (nonexistent) +++ tags/ver/src/BACKUP/lcd.vhd (revision 3) @@ -0,0 +1,243 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity lcd is + Port ( lcd_data : out std_logic_vector (7 downto 4); + clk : in std_logic; + reset : in std_logic; + lcd_enable : out STD_LOGIC_VECTOR (1 DOWNTO 0); + lcd_rs : out std_logic; + lcd_rw : out std_logic + ); +end lcd ; + +architecture behavioural of lcd is + + type state_type is (warmup, setfunc, clear1, clear2, setmode1, setmode2, write1, home1, home2); + + signal state : state_type; + + attribute syn_state_machine : boolean; + attribute syn_state_machine of state : signal is true; + + signal count : std_logic_vector(3 downto 0); + signal finished : std_logic; -- set high if done write cycle + + signal char_mode : std_logic_vector(1 downto 0); + + --defining the display + constant N: integer :=8; + type arr is array (1 to N) of std_logic_vector(7 downto 0); + + constant display_char1 : arr := (x"A0", --blank + X"68", --h + X"74", --t + X"74", --t + X"70", --p + X"3A", --: + X"2F", --/ + X"2F"); --/ + + constant display_char2 : arr := (X"77", --w + X"77", --w + X"77", --w + X"2E", --. + X"66", --f + X"70", --p + X"67", --g + X"61"); --a + + constant display_char3 : arr := (X"2E", --. + X"62", --b + X"65", --e + X"88", --blank + X"88", --blank + X"88", --blank + X"88", --blank + X"88"); --blank + + constant display_char4 : arr := (X"A0", --blank + X"88", --blank + X"58", --X + X"49", --I + X"4F", --O + X"53", --S + X"88", --blank + X"88"); --blank + + signal display_char : arr; + +begin + lcd_rw <= '0'; + lcd_enable(1) <= clk; --not clk; -- this is very important! if enable is not pulsed, lcd will not write + lcd_enable(0) <= clk; + + char_mode_process: process (char_mode) + begin + case char_mode is + when "00" => + display_char <= display_char1; + when "01" => + display_char <= display_char2; + when "10" => + display_char <= display_char3; + when "11" => + display_char <= display_char4; + when OTHERS => + display_char <= display_char1; + end case; + end process; + + state_set: process (clk, reset, finished) + begin + if (reset = '1') then + + state <= warmup; --setfunc; + count <= (others => '0'); + char_mode <= (others => '0'); + + elsif (clk'event and clk = '1') then + case state is + + when warmup => + lcd_rs <= '0'; + lcd_data <= "0011"; --"0000"; -- do nothing + if count = "0111" then --0111 + count <= (others => '0'); + state <= setfunc; + else + count <= count + '1'; + state <= warmup; + end if; + + when setfunc => + lcd_rs <= '0'; + lcd_data <= "0010"; + finished <= '0'; + + if count = "0010" then --0010 + count <= (others => '0'); + state <= clear1; + else + count <= count + '1'; + state <= setfunc; + end if; + + when clear1 => + + lcd_rs <= '0'; + lcd_data <= "0000"; + state <= clear2; + + when clear2 => + lcd_rs <= '0'; + if count = "0111" then + state <= setmode1; + count <= (others => '0'); + lcd_data <= "1111"; + else + count <= count + '1'; + lcd_data <= "0001"; + state <= clear1; + end if; + + when setmode1 => + lcd_rs <= '0'; + lcd_data <= "0000"; + state <= setmode2; + finished <= '0'; + + when setmode2 => + lcd_rs <= '0'; + lcd_data <= "0110"; + state <= write1; + + when write1 => + if finished = '1' then + state <= home1; + else + lcd_rs <= '1'; + count <= count + '1'; + state <= write1; + + CASE count IS + + WHEN "0000" => + lcd_data <= display_char(1)(7 downto 4); + + WHEN "0001" => + lcd_data <= display_char(1)(3 downto 0); + + WHEN "0010" => + lcd_data <= display_char(2)(7 downto 4); + + WHEN "0011" => + lcd_data <= display_char(2)(3 downto 0); + + WHEN "0100"=> + lcd_data <= display_char(3)(7 downto 4); + + WHEN "0101"=> + lcd_data <= display_char(3)(3 downto 0); + + WHEN "0110"=> + lcd_data <= display_char(4)(7 downto 4); + + WHEN "0111"=> + lcd_data <= display_char(4)(3 downto 0); + + WHEN "1000" => + lcd_data <= display_char(5)(7 downto 4); + + WHEN "1001" => + lcd_data <= display_char(5)(3 downto 0); + + WHEN "1010" => + lcd_data <= display_char(6)(7 downto 4); + + WHEN "1011" => + lcd_data <= display_char(6)(3 downto 0); + + WHEN "1100" => + lcd_data <= display_char(7)(7 downto 4); + + WHEN "1101" => + lcd_data <= display_char(7)(3 downto 0); + + WHEN "1110" => + lcd_data <= display_char(8)(7 downto 4); + --finished <= '1'; -- needed to set done low before valid data is gone + --char_mode <= char_mode + '1'; + + WHEN "1111" => + lcd_data <= display_char(8)(3 downto 0); + finished <= '1'; -- needed to set done low before valid data is gone + char_mode <= char_mode + '1'; + + WHEN OTHERS => + lcd_data <= "0000"; -- ' ' + + END CASE; + end if; + + when home1 => + lcd_rs <= '0'; + lcd_data <= "0000"; + state <= home2; + finished <= '0'; + count <= (others => '0'); + + when home2 => + lcd_rs <= '0'; + lcd_data <= "0111"; + state <= write1; + + end case; + + end if; + + end process; + +end behavioural; Index: tags/ver/src/BACKUP/asci_types.vhd =================================================================== --- tags/ver/src/BACKUP/asci_types.vhd (nonexistent) +++ tags/ver/src/BACKUP/asci_types.vhd (revision 3) @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; + +package asci_types is + type lcd_char is ( + NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, + BS, HT, LF, VT, FF, CR, SO, SI, + DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, + CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, + ' ', '!', '"', '#', '$', '%', '&', ''', + '(', ')', '*', '+', ',', '-', '.', '/', + '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', ':', ';', '<', '=', '>', '?', + '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', + 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', + 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', + 'X', 'Y', 'Z', '[', '\', ']', '^', '_', + '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', + 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', + 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', + 'x', 'y', 'z', '{', '|', '}', '~', DEL ); + type lcd_matrix is array(natural range 1 TO 80) of lcd_char; + TYPE char_std_matrix IS array(lcd_char RANGE NUL TO DEL) OF std_logic_vector(7 DOWNTO 0); +-- TYPE lcd_matrix IS ARRAY(NATURAL RANGE 1 TO 80) OF character; +-- TYPE char_std_matrix IS ARRAY (CHARACTER RANGE NUL TO DEL) OF std_logic_vector(7 DOWNTO 0); + constant char2std : char_std_matrix := + ("00000000", "00000001", "00000010", "00000011", + "00000100", "00000101", "00000110", "00000111", + "00001000", "00001001", "00001010", "00001011", + "00001100", "00001101", "00001110", "00001111", + "00010000", "00010001", "00010010", "00010011", + "00010100", "00010101", "00010110", "00010111", + "00011000", "00011001", "00011010", "00011011", + "00011100", "00011101", "00011110", "00011111", + "00100000", "00100001", "00100010", "00100011", + "00100100", "00100101", "00100110", "00100111", + "00101000", "00101001", "00101010", "00101011", + "00101100", "00101101", "00101110", "00101111", + "00110000", "00110001", "00110010", "00110011", + "00110100", "00110101", "00110110", "00110111", + "00111000", "00111001", "00111010", "00111011", + "00111100", "00111101", "00111110", "00111111", + "01000000", "01000001", "01000010", "01000011", + "01000100", "01000101", "01000110", "01000111", + "01001000", "01001001", "01001010", "01001011", + "01001100", "01001101", "01001110", "01001111", + "01010000", "01010001", "01010010", "01010011", + "01010100", "01010101", "01010110", "01010111", + "01011000", "01011001", "01011010", "01011011", + "01011100", "01011101", "01011110", "01011111", + "01100000", "01100001", "01100010", "01100011", + "01100100", "01100101", "01100110", "01100111", + "01101000", "01101001", "01101010", "01101011", + "01101100", "01101101", "01101110", "01101111", + "01110000", "01110001", "01110010", "01110011", + "01110100", "01110101", "01110110", "01110111", + "01111000", "01111001", "01111010", "01111011", + "01111100", "01111101", "01111110", "01111111"); +END asci_types; + + Index: tags/ver/src/BACKUP/lcd1.vhd =================================================================== --- tags/ver/src/BACKUP/lcd1.vhd (nonexistent) +++ tags/ver/src/BACKUP/lcd1.vhd (revision 3) @@ -0,0 +1,1245 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.asci_types.all; + +ENTITY lcd1 IS + generic( one_usec_factor : INTEGER := 1e2/2-1; -- 1e8/2-1 for 1s at 100MHz + max_factor : INTEGER := 100000; -- the biggest delay needed + init_factor : INTEGER := 100000; -- 100ms + normal_factor : INTEGER := 50; -- 50us + extended_factor : INTEGER := 2000 -- 2ms + ); + port( clk_400, clk, rst : IN std_logic; + lcd_rs : OUT std_logic; -- H=data L=command + lcd_rw : OUT std_logic; -- H=read L=write + lcd_ena : OUT STD_LOGIC; -- enable at H-L transition , put clock +-- signal with 1 or 4 us period here. + lcd_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); -- 7th bit is MSB +END lcd1; + + +ARCHITECTURE behavioral OF lcd1 IS + TYPE state IS ( init_start, wait_set1, set1, wait_eset, eset, wait_set2, set2, wait_lcd_on, + lcd_on, wait_lcd_clear, lcd_clear, wait_lcd_entr, lcd_entr, + wait_l1s1, l1s1, wait_l1s2, l1s2, wait_l1s3, l1s3, wait_l1s4, l1s4, wait_l1s5, l1s5, + wait_l1s6, l1s6, wait_l1s7, l1s7, wait_l1s8, l1s8, wait_l1s9, l1s9, wait_l1s10, l1s10, + wait_l1s11, l1s11, wait_l1s12, l1s12, wait_l1s13, l1s13, wait_l1s14, l1s14, wait_l1s15, l1s15, + wait_l1s16, l1s16, wait_l1s17, l1s17, wait_l1s18, l1s18, wait_l1s19, l1s19, wait_l1s20, l1s20, + wait_l2s1, l2s1, wait_l2s2, l2s2, wait_l2s3, l2s3, wait_l2s4, l2s4, wait_l2s5, l2s5, + wait_l2s6, l2s6, wait_l2s7, l2s7, wait_l2s8, l2s8, wait_l2s9, l2s9, wait_l2s10, l2s10, + wait_l2s11, l2s11, wait_l2s12, l2s12, wait_l2s13, l2s13, wait_l2s14, l2s14, wait_l2s15, l2s15, + wait_l2s16, l2s16, wait_l2s17, l2s17, wait_l2s18, l2s18, wait_l2s19, l2s19, wait_l2s20, l2s20, + wait_l3s1, l3s1, wait_l3s2, l3s2, wait_l3s3, l3s3, wait_l3s4, l3s4, wait_l3s5, l3s5, + wait_l3s6, l3s6, wait_l3s7, l3s7, wait_l3s8, l3s8, wait_l3s9, l3s9, wait_l3s10, l3s10, + wait_l3s11, l3s11, wait_l3s12, l3s12, wait_l3s13, l3s13, wait_l3s14, l3s14, wait_l3s15, l3s15, + wait_l3s16, l3s16, wait_l3s17, l3s17, wait_l3s18, l3s18, wait_l3s19, l3s19, wait_l3s20, l3s20, + wait_l4s1, l4s1, wait_l4s2, l4s2, wait_l4s3, l4s3, wait_l4s4, l4s4, wait_l4s5, l4s5, + wait_l4s6, l4s6, wait_l4s7, l4s7, wait_l4s8, l4s8, wait_l4s9, l4s9, wait_l4s10, l4s10, + wait_l4s11, l4s11, wait_l4s12, l4s12, wait_l4s13, l4s13, wait_l4s14, l4s14, wait_l4s15, l4s15, + wait_l4s16, l4s16, wait_l4s17, l4s17, wait_l4s18, l4s18, wait_l4s19, l4s19, wait_l4s20, l4s20, + wait_new_line1, new_line1, wait_new_line2, new_line2, wait_new_line3, new_line3, wait_new_line4, new_line4, + wait_renew ); + signal pr_state, nxt_state : state; + signal one_usec, rst_int : STD_LOGIC := '0'; + signal counter : INTEGER RANGE 0 TO max_factor; + SIGNAL lcd_data_int : STD_LOGIC_VECTOR (9 DOWNTO 0); + signal str1, lcd_reg : lcd_matrix; +BEGIN + lcd_reg <= str1; + str1 <= ( ' ',' ',' ',' ',' ',' ','T','U',' ','C','h','e','m','n','i','t','z',' ',' ',' ', + ' ',' ',' ',' ',' ',' ',' ',' ','S','S','E',' ',' ',' ',' ',' ',' ',' ',' ',' ', + ' ',' ',' ','D','i','m','o',' ','P','e','p','e','l','y','a','s','h','e','v',' ', + ' ',' ',' ',' ',' ',' ',' ',' ',' ','-','-','-',' ',' ',' ',' ',' ',' ',' ',' ' ); + lcd_rw <= '0'; -- only writing to the LCD needed, lcd_data_int(8) is never used + lcd_rs <= lcd_data_int(9); + lcd_data <= lcd_data_int(7 downto 0); + lcd_ena <= clk_400; + +-------------------------------------------------------------------------------------- +-- generates a signal with 1us period +-------------------------------------------------------------------------------------- +one_sec_p: process(clk) + VARIABLE temp : integer RANGE 0 TO one_usec_factor; + begin + IF clk'event AND clk='1' THEN + IF rst_int='0' THEN + temp := 0; + one_usec <= '0'; + else + iF temp>=one_usec_factor THEN + temp := 0; + one_usec <= NOT one_usec; + else + temp := temp + 1; + END if; + END if; + END IF; + END process; + + +-------------------------------------------------------------------------------------- +-- delays generetor +-------------------------------------------------------------------------------------- +delay_p: process(clk) + variable temp0 : integer RANGE 0 TO max_factor; + VARIABLE flag : STD_LOGIC := '0'; +BEGIN + IF clk'EVENT AND clk='1' THEN + IF rst_int='0' THEN + temp0 := 0; + else + IF one_usec='0' AND flag='1' THEN + flag := '0'; + END IF; +--this part is executed only on a positive transition of the one_usec signal + IF one_usec='1' AND flag='0' THEN + flag := '1'; + IF + temp0>=max_factor THEN + temp0 := 0; + ELSE + temp0 := temp0 + 1; + end if; + END if; + END if; + END if; + counter <= temp0; +END process; + +--------------------------------------------------------------------------------- +-- MORE automat, in order to save some registers, you can use MAELY too +--------------------------------------------------------------------------------- +main_s_p: process(clk) + begin + if clk'event and clk='1' then + IF rst='0' THEN + pr_state <= init_start; + else + pr_state <= nxt_state; + end if; + END if; + end process; + + +main_c_p: process(pr_state,counter) +begin + case pr_state is + WHEN init_start => + nxt_state <= wait_set1; + rst_int <= '0'; + lcd_data_int <= (OTHERS => '0'); + WHEN wait_set1 => + IF counter>=init_factor THEN + nxt_state <= set1; + ELSE + nxt_state <= wait_set1; + END IF; + lcd_data_int <= (OTHERS => '0'); + rst_int <= '1'; + WHEN set1 => + nxt_state <= wait_eset; + rst_int <= '0'; + lcd_data_int <= "0000110100"; + WHEN wait_eset => + IF counter>=normal_factor THEN + nxt_state <= eset; + ELSE + nxt_state <= wait_eset; + END IF; + lcd_data_int <= "0000110100"; + rst_int <= '1'; + WHEN eset => + nxt_state <= wait_set2; + rst_int <= '0'; + lcd_data_int <= "0000001001"; + WHEN wait_set2 => + IF counter>=normal_factor THEN + nxt_state <= set2; + ELSE + nxt_state <= wait_set2; + END IF; + lcd_data_int <= "0000001001"; + rst_int <= '1'; + WHEN set2 => + nxt_state <= wait_lcd_on; + rst_int <= '0'; + lcd_data_int <= "0000110000"; + WHEN wait_lcd_on => + IF counter>=normal_factor THEN + nxt_state <= lcd_on; + ELSE + nxt_state <= wait_lcd_on; + END IF; + lcd_data_int <= "0000110000"; + rst_int <= '1'; + WHEN lcd_on => + nxt_state <= wait_lcd_clear; + rst_int <= '0'; + lcd_data_int <= "0000001111"; + WHEN wait_lcd_clear => + IF counter>=normal_factor THEN + nxt_state <= lcd_clear; + ELSE + nxt_state <= wait_lcd_clear; + END IF; + lcd_data_int <= "0000001111"; + rst_int <= '1'; + WHEN lcd_clear => + nxt_state <= wait_lcd_entr; + rst_int <= '0'; + lcd_data_int <= "0000000001"; + WHEN wait_lcd_entr => + IF counter>=extended_factor THEN + nxt_state <= lcd_entr; + ELSE + nxt_state <= wait_lcd_clear; + END IF; + lcd_data_int <= "0000000001"; + rst_int <= '1'; + WHEN lcd_entr => + nxt_state <= wait_l1s1; + rst_int <= '0'; + lcd_data_int <= "0000000110"; + WHEN wait_l1s1 => + IF counter>=normal_factor THEN + nxt_state <= l1s1; + ELSE + nxt_state <= wait_l1s1; + END IF; + lcd_data_int <= "0000000110"; + rst_int <= '1'; +------------------------------------------------------------------------------- +-- line 1 +------------------------------------------------------------------------------- + WHEN l1s1 => + nxt_state <= wait_l1s2; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(1)); + WHEN wait_l1s2 => + IF counter>=normal_factor THEN + nxt_state <= l1s2; + ELSE + nxt_state <= wait_l1s2; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(1)); + rst_int <= '1'; + WHEN l1s2 => + nxt_state <= wait_l1s3; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(2)); + WHEN wait_l1s3 => + IF counter>=normal_factor THEN + nxt_state <= l1s3; + ELSE + nxt_state <= wait_l1s3; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(2)); + rst_int <= '1'; + WHEN l1s3 => + nxt_state <= wait_l1s4; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(3)); + WHEN wait_l1s4 => + IF counter>=normal_factor THEN + nxt_state <= l1s4; + ELSE + nxt_state <= wait_l1s4; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(3)); + rst_int <= '1'; + WHEN l1s4 => + nxt_state <= wait_l1s5; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(4)); + WHEN wait_l1s5 => + IF counter>=normal_factor THEN + nxt_state <= l1s5; + ELSE + nxt_state <= wait_l1s5; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(4)); + rst_int <= '1'; + WHEN l1s5 => + nxt_state <= wait_l1s6; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(5)); + WHEN wait_l1s6 => + IF counter>=normal_factor THEN + nxt_state <= l1s6; + ELSE + nxt_state <= wait_l1s6; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(5)); + rst_int <= '1'; + WHEN l1s6 => + nxt_state <= wait_l1s7; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(6)); + WHEN wait_l1s7 => + IF counter>=normal_factor THEN + nxt_state <= l1s7; + ELSE + nxt_state <= wait_l1s7; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(6)); + rst_int <= '1'; + WHEN l1s7 => + nxt_state <= wait_l1s8; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(7)); + WHEN wait_l1s8 => + IF counter>=normal_factor THEN + nxt_state <= l1s8; + ELSE + nxt_state <= wait_l1s8; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(7)); + rst_int <= '1'; + WHEN l1s8 => + nxt_state <= wait_l1s9; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(8)); + WHEN wait_l1s9 => + IF counter>=normal_factor THEN + nxt_state <= l1s9; + ELSE + nxt_state <= wait_l1s9; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(8)); + rst_int <= '1'; + WHEN l1s9 => + nxt_state <= wait_l1s10; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(9)); + WHEN wait_l1s10 => + IF counter>=normal_factor THEN + nxt_state <= l1s10; + ELSE + nxt_state <= wait_l1s10; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(9)); + rst_int <= '1'; + WHEN l1s10 => + nxt_state <= wait_l1s11; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(10)); + WHEN wait_l1s11 => + IF counter>=normal_factor THEN + nxt_state <= l1s11; + ELSE + nxt_state <= wait_l1s11; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(10)); + rst_int <= '1'; + WHEN l1s11 => + nxt_state <= wait_l1s12; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(11)); + WHEN wait_l1s12 => + IF counter>=normal_factor THEN + nxt_state <= l1s12; + ELSE + nxt_state <= wait_l1s12; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(11)); + rst_int <= '1'; + WHEN l1s12 => + nxt_state <= wait_l1s13; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(12)); + WHEN wait_l1s13 => + IF counter>=normal_factor THEN + nxt_state <= l1s13; + ELSE + nxt_state <= wait_l1s13; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(12)); + rst_int <= '1'; + WHEN l1s13 => + nxt_state <= wait_l1s14; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(13)); + WHEN wait_l1s14 => + IF counter>=normal_factor THEN + nxt_state <= l1s14; + ELSE + nxt_state <= wait_l1s14; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(13)); + rst_int <= '1'; + WHEN l1s14 => + nxt_state <= wait_l1s15; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(14)); + WHEN wait_l1s15 => + IF counter>=normal_factor THEN + nxt_state <= l1s15; + ELSE + nxt_state <= wait_l1s15; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(14)); + rst_int <= '1'; + WHEN l1s15 => + nxt_state <= wait_l1s16; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(15)); + WHEN wait_l1s16 => + IF counter>=normal_factor THEN + nxt_state <= l1s16; + ELSE + nxt_state <= wait_l1s16; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(15)); + rst_int <= '1'; + WHEN l1s16 => + nxt_state <= wait_l1s17; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(16)); + WHEN wait_l1s17 => + IF counter>=normal_factor THEN + nxt_state <= l1s17; + ELSE + nxt_state <= wait_l1s17; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(16)); + rst_int <= '1'; + WHEN l1s17 => + nxt_state <= wait_l1s18; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(17)); + WHEN wait_l1s18 => + IF counter>=normal_factor THEN + nxt_state <= l1s18; + ELSE + nxt_state <= wait_l1s18; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(17)); + rst_int <= '1'; + WHEN l1s18 => + nxt_state <= wait_l1s19; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(18)); + WHEN wait_l1s19 => + IF counter>=normal_factor THEN + nxt_state <= l1s19; + ELSE + nxt_state <= wait_l1s19; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(18)); + rst_int <= '1'; + WHEN l1s19 => + nxt_state <= wait_l1s20; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(19)); + WHEN wait_l1s20 => + IF counter>=normal_factor THEN + nxt_state <= l1s20; + ELSE + nxt_state <= wait_l1s20; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(19)); + rst_int <= '1'; + WHEN l1s20 => + nxt_state <= wait_new_line1; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(20)); + WHEN wait_new_line1 => + IF counter>=normal_factor THEN + nxt_state <= new_line1; + ELSE + nxt_state <= wait_new_line1; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(20)); + rst_int <= '1'; + WHEN new_line1 => + nxt_state <= wait_l2s1; + rst_int <= '0'; + lcd_data_int <= "0010100000"; + WHEN wait_l2s1 => + IF counter>=normal_factor THEN + nxt_state <= l2s1; + ELSE + nxt_state <= wait_l2s1; + END IF; + lcd_data_int <= "0010100000"; + rst_int <= '1'; +------------------------------------------------------------------------------- +-- line 2 +------------------------------------------------------------------------------- + WHEN l2s1 => + nxt_state <= wait_l2s2; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(21)); + WHEN wait_l2s2 => + IF counter>=normal_factor THEN + nxt_state <= l2s2; + ELSE + nxt_state <= wait_l2s2; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(21)); + rst_int <= '1'; + WHEN l2s2 => + nxt_state <= wait_l2s3; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(22)); + WHEN wait_l2s3 => + IF counter>=normal_factor THEN + nxt_state <= l2s3; + ELSE + nxt_state <= wait_l2s3; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(22)); + rst_int <= '1'; + WHEN l2s3 => + nxt_state <= wait_l2s4; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(23)); + WHEN wait_l2s4 => + IF counter>=normal_factor THEN + nxt_state <= l2s4; + ELSE + nxt_state <= wait_l2s4; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(23)); + rst_int <= '1'; + WHEN l2s4 => + nxt_state <= wait_l2s5; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(24)); + WHEN wait_l2s5 => + IF counter>=normal_factor THEN + nxt_state <= l2s5; + ELSE + nxt_state <= wait_l2s5; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(24)); + rst_int <= '1'; + WHEN l2s5 => + nxt_state <= wait_l2s6; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(25)); + WHEN wait_l2s6 => + IF counter>=normal_factor THEN + nxt_state <= l2s6; + ELSE + nxt_state <= wait_l2s6; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(25)); + rst_int <= '1'; + WHEN l2s6 => + nxt_state <= wait_l2s7; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(26)); + WHEN wait_l2s7 => + IF counter>=normal_factor THEN + nxt_state <= l2s7; + ELSE + nxt_state <= wait_l2s7; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(26)); + rst_int <= '1'; + WHEN l2s7 => + nxt_state <= wait_l2s8; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(27)); + WHEN wait_l2s8 => + IF counter>=normal_factor THEN + nxt_state <= l2s8; + ELSE + nxt_state <= wait_l2s8; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(27)); + rst_int <= '1'; + WHEN l2s8 => + nxt_state <= wait_l2s9; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(28)); + WHEN wait_l2s9 => + IF counter>=normal_factor THEN + nxt_state <= l2s9; + ELSE + nxt_state <= wait_l2s9; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(28)); + rst_int <= '1'; + WHEN l2s9 => + nxt_state <= wait_l2s10; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(29)); + WHEN wait_l2s10 => + IF counter>=normal_factor THEN + nxt_state <= l2s10; + ELSE + nxt_state <= wait_l2s10; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(29)); + rst_int <= '1'; + WHEN l2s10 => + nxt_state <= wait_l2s11; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(30)); + WHEN wait_l2s11 => + IF counter>=normal_factor THEN + nxt_state <= l2s11; + ELSE + nxt_state <= wait_l2s11; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(30)); + rst_int <= '1'; + WHEN l2s11 => + nxt_state <= wait_l2s12; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(31)); + WHEN wait_l2s12 => + IF counter>=normal_factor THEN + nxt_state <= l2s12; + ELSE + nxt_state <= wait_l2s12; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(31)); + rst_int <= '1'; + WHEN l2s12 => + nxt_state <= wait_l2s13; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(32)); + WHEN wait_l2s13 => + IF counter>=normal_factor THEN + nxt_state <= l2s13; + ELSE + nxt_state <= wait_l2s13; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(32)); + rst_int <= '1'; + WHEN l2s13 => + nxt_state <= wait_l2s14; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(33)); + WHEN wait_l2s14 => + IF counter>=normal_factor THEN + nxt_state <= l2s14; + ELSE + nxt_state <= wait_l2s14; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(33)); + rst_int <= '1'; + WHEN l2s14 => + nxt_state <= wait_l2s15; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(34)); + WHEN wait_l2s15 => + IF counter>=normal_factor THEN + nxt_state <= l2s15; + ELSE + nxt_state <= wait_l2s15; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(34)); + rst_int <= '1'; + WHEN l2s15 => + nxt_state <= wait_l2s16; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(35)); + WHEN wait_l2s16 => + IF counter>=normal_factor THEN + nxt_state <= l2s16; + ELSE + nxt_state <= wait_l2s16; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(35)); + rst_int <= '1'; + WHEN l2s16 => + nxt_state <= wait_l2s17; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(36)); + WHEN wait_l2s17 => + IF counter>=normal_factor THEN + nxt_state <= l2s17; + ELSE + nxt_state <= wait_l2s17; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(36)); + rst_int <= '1'; + WHEN l2s17 => + nxt_state <= wait_l2s18; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(37)); + WHEN wait_l2s18 => + IF counter>=normal_factor THEN + nxt_state <= l2s18; + ELSE + nxt_state <= wait_l2s18; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(37)); + rst_int <= '1'; + WHEN l2s18 => + nxt_state <= wait_l2s19; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(38)); + WHEN wait_l2s19 => + IF counter>=normal_factor THEN + nxt_state <= l2s19; + ELSE + nxt_state <= wait_l2s19; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(38)); + rst_int <= '1'; + WHEN l2s19 => + nxt_state <= wait_l2s20; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(39)); + WHEN wait_l2s20 => + IF counter>=normal_factor THEN + nxt_state <= l2s20; + ELSE + nxt_state <= wait_l2s20; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(39)); + rst_int <= '1'; + WHEN l2s20 => + nxt_state <= wait_new_line2; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(40)); + WHEN wait_new_line2 => + IF counter>=normal_factor THEN + nxt_state <= new_line2; + ELSE + nxt_state <= wait_new_line2; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(40)); + rst_int <= '1'; + WHEN new_line2 => + nxt_state <= wait_l3s1; + rst_int <= '0'; + lcd_data_int <= "0011000000"; + WHEN wait_l3s1 => + IF counter>=normal_factor THEN + nxt_state <= l3s1; + ELSE + nxt_state <= wait_l3s1; + END IF; + lcd_data_int <= "0011000000"; + rst_int <= '1'; + +------------------------------------------------------------------------------- +-- line 3 +------------------------------------------------------------------------------- + WHEN l3s1 => + nxt_state <= wait_l3s2; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(41)); + WHEN wait_l3s2 => + IF counter>=normal_factor THEN + nxt_state <= l3s2; + ELSE + nxt_state <= wait_l3s2; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(41)); + rst_int <= '1'; + WHEN l3s2 => + nxt_state <= wait_l3s3; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(42)); + WHEN wait_l3s3 => + IF counter>=normal_factor THEN + nxt_state <= l3s3; + ELSE + nxt_state <= wait_l3s3; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(42)); + rst_int <= '1'; + WHEN l3s3 => + nxt_state <= wait_l3s4; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(43)); + WHEN wait_l3s4 => + IF counter>=normal_factor THEN + nxt_state <= l3s4; + ELSE + nxt_state <= wait_l3s4; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(43)); + rst_int <= '1'; + WHEN l3s4 => + nxt_state <= wait_l3s5; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(44)); + WHEN wait_l3s5 => + IF counter>=normal_factor THEN + nxt_state <= l3s5; + ELSE + nxt_state <= wait_l3s5; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(44)); + rst_int <= '1'; + WHEN l3s5 => + nxt_state <= wait_l3s6; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(45)); + WHEN wait_l3s6 => + IF counter>=normal_factor THEN + nxt_state <= l3s6; + ELSE + nxt_state <= wait_l3s6; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(45)); + rst_int <= '1'; + WHEN l3s6 => + nxt_state <= wait_l3s7; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(46)); + WHEN wait_l3s7 => + IF counter>=normal_factor THEN + nxt_state <= l3s7; + ELSE + nxt_state <= wait_l3s7; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(46)); + rst_int <= '1'; + WHEN l3s7 => + nxt_state <= wait_l3s8; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(47)); + WHEN wait_l3s8 => + IF counter>=normal_factor THEN + nxt_state <= l3s8; + ELSE + nxt_state <= wait_l3s8; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(47)); + rst_int <= '1'; + WHEN l3s8 => + nxt_state <= wait_l3s9; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(48)); + WHEN wait_l3s9 => + IF counter>=normal_factor THEN + nxt_state <= l3s9; + ELSE + nxt_state <= wait_l3s9; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(48)); + rst_int <= '1'; + WHEN l3s9 => + nxt_state <= wait_l3s10; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(49)); + WHEN wait_l3s10 => + IF counter>=normal_factor THEN + nxt_state <= l3s10; + ELSE + nxt_state <= wait_l3s10; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(49)); + rst_int <= '1'; + WHEN l3s10 => + nxt_state <= wait_l3s11; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(50)); + WHEN wait_l3s11 => + IF counter>=normal_factor THEN + nxt_state <= l3s11; + ELSE + nxt_state <= wait_l3s11; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(50)); + rst_int <= '1'; + WHEN l3s11 => + nxt_state <= wait_l3s12; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(51)); + WHEN wait_l3s12 => + IF counter>=normal_factor THEN + nxt_state <= l3s12; + ELSE + nxt_state <= wait_l3s12; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(51)); + rst_int <= '1'; + WHEN l3s12 => + nxt_state <= wait_l3s13; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(52)); + WHEN wait_l3s13 => + IF counter>=normal_factor THEN + nxt_state <= l3s13; + ELSE + nxt_state <= wait_l3s13; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(52)); + rst_int <= '1'; + WHEN l3s13 => + nxt_state <= wait_l3s14; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(53)); + WHEN wait_l3s14 => + IF counter>=normal_factor THEN + nxt_state <= l3s14; + ELSE + nxt_state <= wait_l3s14; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(53)); + rst_int <= '1'; + WHEN l3s14 => + nxt_state <= wait_l3s15; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(54)); + WHEN wait_l3s15 => + IF counter>=normal_factor THEN + nxt_state <= l3s15; + ELSE + nxt_state <= wait_l3s15; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(54)); + rst_int <= '1'; + WHEN l3s15 => + nxt_state <= wait_l3s16; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(55)); + WHEN wait_l3s16 => + IF counter>=normal_factor THEN + nxt_state <= l3s16; + ELSE + nxt_state <= wait_l3s16; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(55)); + rst_int <= '1'; + WHEN l3s16 => + nxt_state <= wait_l3s17; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(56)); + WHEN wait_l3s17 => + IF counter>=normal_factor THEN + nxt_state <= l3s17; + ELSE + nxt_state <= wait_l3s17; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(56)); + rst_int <= '1'; + WHEN l3s17 => + nxt_state <= wait_l3s18; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(57)); + WHEN wait_l3s18 => + IF counter>=normal_factor THEN + nxt_state <= l3s18; + ELSE + nxt_state <= wait_l3s18; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(57)); + rst_int <= '1'; + WHEN l3s18 => + nxt_state <= wait_l3s19; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(58)); + WHEN wait_l3s19 => + IF counter>=normal_factor THEN + nxt_state <= l3s19; + ELSE + nxt_state <= wait_l3s19; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(58)); + rst_int <= '1'; + WHEN l3s19 => + nxt_state <= wait_l3s20; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(59)); + WHEN wait_l3s20 => + IF counter>=normal_factor THEN + nxt_state <= l3s20; + ELSE + nxt_state <= wait_l3s20; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(59)); + rst_int <= '1'; + WHEN l3s20 => + nxt_state <= wait_new_line3; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(60)); + WHEN wait_new_line3 => + IF counter>=normal_factor THEN + nxt_state <= new_line3; + ELSE + nxt_state <= wait_new_line3; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(60)); + rst_int <= '1'; + WHEN new_line3 => + nxt_state <= wait_l4s1; + rst_int <= '0'; + lcd_data_int <= "0011100000"; + WHEN wait_l4s1 => + IF counter>=normal_factor THEN + nxt_state <= l4s1; + ELSE + nxt_state <= wait_l4s1; + END IF; + lcd_data_int <= "0011100000"; + rst_int <= '1'; + +------------------------------------------------------------------------------- +-- line 4 +------------------------------------------------------------------------------- + WHEN l4s1 => + nxt_state <= wait_l4s2; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(61)); + WHEN wait_l4s2 => + IF counter>=normal_factor THEN + nxt_state <= l4s2; + ELSE + nxt_state <= wait_l4s2; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(61)); + rst_int <= '1'; + WHEN l4s2 => + nxt_state <= wait_l4s3; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(62)); + WHEN wait_l4s3 => + IF counter>=normal_factor THEN + nxt_state <= l4s3; + ELSE + nxt_state <= wait_l4s3; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(62)); + rst_int <= '1'; + WHEN l4s3 => + nxt_state <= wait_l4s4; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(63)); + WHEN wait_l4s4 => + IF counter>=normal_factor THEN + nxt_state <= l4s4; + ELSE + nxt_state <= wait_l4s4; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(63)); + rst_int <= '1'; + WHEN l4s4 => + nxt_state <= wait_l4s5; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(64)); + WHEN wait_l4s5 => + IF counter>=normal_factor THEN + nxt_state <= l4s5; + ELSE + nxt_state <= wait_l4s5; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(64)); + rst_int <= '1'; + WHEN l4s5 => + nxt_state <= wait_l4s6; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(65)); + WHEN wait_l4s6 => + IF counter>=normal_factor THEN + nxt_state <= l4s6; + ELSE + nxt_state <= wait_l4s6; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(65)); + rst_int <= '1'; + WHEN l4s6 => + nxt_state <= wait_l4s7; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(66)); + WHEN wait_l4s7 => + IF counter>=normal_factor THEN + nxt_state <= l4s7; + ELSE + nxt_state <= wait_l4s7; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(66)); + rst_int <= '1'; + WHEN l4s7 => + nxt_state <= wait_l4s8; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(67)); + WHEN wait_l4s8 => + IF counter>=normal_factor THEN + nxt_state <= l4s8; + ELSE + nxt_state <= wait_l4s8; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(67)); + rst_int <= '1'; + WHEN l4s8 => + nxt_state <= wait_l4s9; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(68)); + WHEN wait_l4s9 => + IF counter>=normal_factor THEN + nxt_state <= l4s9; + ELSE + nxt_state <= wait_l4s9; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(68)); + rst_int <= '1'; + WHEN l4s9 => + nxt_state <= wait_l4s10; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(69)); + WHEN wait_l4s10 => + IF counter>=normal_factor THEN + nxt_state <= l4s10; + ELSE + nxt_state <= wait_l4s10; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(69)); + rst_int <= '1'; + WHEN l4s10 => + nxt_state <= wait_l4s11; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(70)); + WHEN wait_l4s11 => + IF counter>=normal_factor THEN + nxt_state <= l4s11; + ELSE + nxt_state <= wait_l4s11; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(70)); + rst_int <= '1'; + WHEN l4s11 => + nxt_state <= wait_l4s12; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(71)); + WHEN wait_l4s12 => + IF counter>=normal_factor THEN + nxt_state <= l4s12; + ELSE + nxt_state <= wait_l4s12; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(71)); + rst_int <= '1'; + WHEN l4s12 => + nxt_state <= wait_l4s13; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(72)); + WHEN wait_l4s13 => + IF counter>=normal_factor THEN + nxt_state <= l4s13; + ELSE + nxt_state <= wait_l4s13; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(72)); + rst_int <= '1'; + WHEN l4s13 => + nxt_state <= wait_l4s14; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(73)); + WHEN wait_l4s14 => + IF counter>=normal_factor THEN + nxt_state <= l4s14; + ELSE + nxt_state <= wait_l4s14; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(73)); + rst_int <= '1'; + WHEN l4s14 => + nxt_state <= wait_l4s15; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(74)); + WHEN wait_l4s15 => + IF counter>=normal_factor THEN + nxt_state <= l4s15; + ELSE + nxt_state <= wait_l4s15; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(74)); + rst_int <= '1'; + WHEN l4s15 => + nxt_state <= wait_l4s16; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(75)); + WHEN wait_l4s16 => + IF counter>=normal_factor THEN + nxt_state <= l4s16; + ELSE + nxt_state <= wait_l4s16; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(75)); + rst_int <= '1'; + WHEN l4s16 => + nxt_state <= wait_l4s17; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(76)); + WHEN wait_l4s17 => + IF counter>=normal_factor THEN + nxt_state <= l4s17; + ELSE + nxt_state <= wait_l4s17; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(76)); + rst_int <= '1'; + WHEN l4s17 => + nxt_state <= wait_l4s18; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(77)); + WHEN wait_l4s18 => + IF counter>=normal_factor THEN + nxt_state <= l4s18; + ELSE + nxt_state <= wait_l4s18; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(77)); + rst_int <= '1'; + WHEN l4s18 => + nxt_state <= wait_l4s19; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(78)); + WHEN wait_l4s19 => + IF counter>=normal_factor THEN + nxt_state <= l4s19; + ELSE + nxt_state <= wait_l4s19; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(78)); + rst_int <= '1'; + WHEN l4s19 => + nxt_state <= wait_l4s20; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(79)); + WHEN wait_l4s20 => + IF counter>=normal_factor THEN + nxt_state <= l4s20; + ELSE + nxt_state <= wait_l4s20; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(79)); + rst_int <= '1'; + WHEN l4s20 => + nxt_state <= wait_new_line4; + rst_int <= '0'; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(80)); + WHEN wait_new_line4 => + IF counter>=normal_factor THEN + nxt_state <= new_line4; + ELSE + nxt_state <= wait_new_line4; + END IF; + lcd_data_int <= '1' & '0' & char2std(lcd_reg(80)); + rst_int <= '1'; + WHEN new_line4 => + nxt_state <= wait_renew; + rst_int <= '0'; + lcd_data_int <= "0000000010"; + WHEN wait_renew => + IF counter>=extended_factor THEN + nxt_state <= l1s1; + ELSE + nxt_state <= wait_renew; + END IF; + lcd_data_int <= "0000000010"; + rst_int <= '1'; +------------------------------------------------------------------------------- +-- +------------------------------------------------------------------------------- + WHEN OTHERS => + nxt_state <= init_start; + rst_int <= '0'; + lcd_data_int <= (OTHERS => '0'); + END case; + END process; + + +END behavioral; Index: tags/ver/src/BACKUP/topEntity_tb.vhd =================================================================== --- tags/ver/src/BACKUP/topEntity_tb.vhd (nonexistent) +++ tags/ver/src/BACKUP/topEntity_tb.vhd (revision 3) @@ -0,0 +1,105 @@ + +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:44:54 03/26/2008 +-- Design Name: counter +-- Module Name: counter_tb.vhd +-- Project Name: clk_tb +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: counter +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY topEntity_tb IS +END topEntity_tb; + +ARCHITECTURE behavior OF topEntity_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT topEntity + PORT( + clk : IN std_logic; + j_down, j_left, j_right, j_up : IN std_logic; + led : OUT std_logic_vector(3 downto 0) ); + END COMPONENT; + + --Inputs + SIGNAL clk : std_logic := '0'; + signal j_down : std_logic := '1'; + SIGNAL j_right : std_logic := '1'; + SIGNAL j_left : std_logic := '1'; + signal j_up : std_logic := '1'; + + --Outputs + SIGNAL led : std_logic_vector(3 downto 0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: topEntity PORT MAP( + clk => clk, + j_down => j_down, j_left => j_left, j_right => j_right, j_up => j_up, + led => led + ); + + tb_clk : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + --wait for 100 ns; + + clk <= not clk; + wait for 5 ns; + -- Place stimulus here + END PROCESS; + + tb_s: PROCESS + BEGIN + wait for 15 ms; + j_down <= '0'; + wait for 25 ms; + j_down <= '1'; + wait for 150 ms; + j_left <= '0'; + wait for 35 ms; + j_left <= '1'; + wait for 100 ms; + j_right <= '0'; + wait for 30 ms; + j_right <= '1'; +-- wait for 70 ms; +-- j_left <= '0'; +-- wait for 30 ms ; +-- j_left <= '1'; +-- wait for 100 ms; +-- j_up <= '0'; +-- wait for 40 ms; +-- j_up <= '1'; +-- wait for 120 ms; +-- j_right <= '0'; +-- wait for 35 ms; +-- j_right <= '1'; + wait; + + END PROCESS; +END; Index: tags/ver/src/BACKUP/components.vhd =================================================================== --- tags/ver/src/BACKUP/components.vhd (nonexistent) +++ tags/ver/src/BACKUP/components.vhd (revision 3) @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +package components is + component generic_freq_div is + port( clk_in : in std_logic; clk : out std_logic); + end component; + + component lcd1 is + port( clk_400, clk, rst : in std_logic; + lcd_data : out std_logic_vector (7 downto 0); + lcd_ena, lcd_rw, lcd_rs : out std_logic ); + end component; + +end components; \ No newline at end of file Index: tags/ver/src/BACKUP/topEntity.ut =================================================================== --- tags/ver/src/BACKUP/topEntity.ut (nonexistent) +++ tags/ver/src/BACKUP/topEntity.ut (revision 3) @@ -0,0 +1,30 @@ + +-g DebugBitstream:No +-g Binary:no +-b +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFF0001 +-g DCMShutDown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:NoWait +-g Security:None +-g Persist:No +-g ReadBack +-g DonePipe:No +-g DriveDone:No Index: tags/ver/src/BACKUP/generic_freq_div.vhd =================================================================== --- tags/ver/src/BACKUP/generic_freq_div.vhd (nonexistent) +++ tags/ver/src/BACKUP/generic_freq_div.vhd (revision 3) @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity generic_freq_div is + generic( factor : integer := 400); --factor have to be an even number; 1000 for 100kHz at 100MHz + port( clk_in : in std_logic; -- 400 for 4us clock at 100MHz + clk : out std_logic ); +end generic_freq_div; + + +architecture behavioral of generic_freq_div is +begin +div: process(clk_in) + variable count : integer range 0 to factor/2-1; + variable tmp : std_logic := '0'; + begin + if clk_in'event and clk_in='1' then + if count>=factor/2-1 then + count := 0; + tmp := not tmp; + else + count := count + 1; + end if; + end if; + clk <= tmp; + end process; +end behavioral; Index: tags/ver/src/BACKUP/topEntity.ucf =================================================================== --- tags/ver/src/BACKUP/topEntity.ucf (nonexistent) +++ tags/ver/src/BACKUP/topEntity.ucf (revision 3) @@ -0,0 +1,49 @@ +#NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) + +NET "lcd_DATA<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<2>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<3>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<4>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<5>" LOC = "C10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<6>" LOC = "E10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<7>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_ena" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#NET "lcd_EN2" LOC = "H11" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; # zusaetzliches Enable fuer Grafi +NET "lcd_rs" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +NET "lcd_rw" LOC = "F10" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; + + +#NET "j_up" LOC = "AD4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick up low active +NET "j_down" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low active +#NET "j_left" LOC = "AE4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick left low active +#NET "j_right" LOC = "AC6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick right low active +#NET "rst" LOC = "AA7" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick push low active + +#NET "turn_on" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) #dip switch low active +#NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + +#NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) +#NET "leds(0)" LOC = "G21" | IOSTANDARD = LVCMOS33; #led(4) +#NET "leds(1)" LOC = "G23" | IOSTANDARD = LVCMOS33; #led(5) +#NET "leds(2)" LOC = "H23" | IOSTANDARD = LVCMOS33; #led(6) +#NET "leds(3)" LOC = "J21" | IOSTANDARD = LVCMOS33; #led(7) + +#NET "in_vector(0)" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) dip switches are low-active +#NET "in_vector(1)" LOC = "AD15" | IOSTANDARD = LVCMOS25; #dip_sw(1) +#NET "in_vector(2)" LOC = "AD19" | IOSTANDARD = LVCMOS25; #dip_sw(2) +#NET "in_vector(3)" LOC = "AD23" | IOSTANDARD = LVCMOS25; #dip_sw(3) +#NET "in_vector(4)" LOC = "AF21" | IOSTANDARD = LVCMOS25; #dip_sw(4) +#NET "in_vector(5)" LOC = "AF22" | IOSTANDARD = LVCMOS25; #dip_sw(5) +#NET "in_vector(6)" LOC = "W15" | IOSTANDARD = LVCMOS25; #dip_sw(6) +#NET "in_vector(7)" LOC = "W16" | IOSTANDARD = LVCMOS25; #dip_sw(7) + +#NET "enable" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low-active +NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + Index: tags/ver/src/components.vhd =================================================================== --- tags/ver/src/components.vhd (nonexistent) +++ tags/ver/src/components.vhd (revision 3) @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +package components is + component generic_freq_div is + port( clk_in : in std_logic; clk : out std_logic); + end component; + + component lcd1 is + port( clk_400, clk, rst : in std_logic; + lcd_data : out std_logic_vector (7 downto 0); + lcd_ena, lcd_rw, lcd_rs : out std_logic; + led : out std_logic_vector (0 downto 0) ); + end component; + +end components; Index: tags/ver/src/topEntity.ut =================================================================== --- tags/ver/src/topEntity.ut (nonexistent) +++ tags/ver/src/topEntity.ut (revision 3) @@ -0,0 +1,30 @@ + +-g DebugBitstream:No +-g Binary:no +-b +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFF0001 +-g DCMShutDown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:NoWait +-g Security:None +-g Persist:No +-g ReadBack +-g DonePipe:No +-g DriveDone:No Index: tags/ver/src/generic_freq_div.vhd =================================================================== --- tags/ver/src/generic_freq_div.vhd (nonexistent) +++ tags/ver/src/generic_freq_div.vhd (revision 3) @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity generic_freq_div is + generic( factor : integer := 400); -- should be an even number (period_of_clk=factor*period_of_clk_in) + port( clk_in : in std_logic; + clk : out std_logic ); +end generic_freq_div; + + +architecture behavioral of generic_freq_div is +begin +div: process(clk_in) + variable count : integer range 0 to factor/2-1; + variable tmp : std_logic := '0'; + begin + if clk_in'event and clk_in='1' then + if count>=factor/2-1 then + count := 0; + tmp := not tmp; + else + count := count + 1; + end if; + end if; + clk <= tmp; + end process; +end behavioral; Index: tags/ver/src/topEntity.ucf =================================================================== --- tags/ver/src/topEntity.ucf (nonexistent) +++ tags/ver/src/topEntity.ucf (revision 3) @@ -0,0 +1,50 @@ +#NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) + +NET "lcd_DATA<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<2>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<3>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<4>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<5>" LOC = "C10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<6>" LOC = "E10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_DATA<7>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | IOBDELAY = NONE ; +NET "lcd_ena" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#NET "lcd_EN2" LOC = "H11" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; # zusaetzliches Enable fuer Grafi +NET "lcd_rs" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +NET "lcd_rw" LOC = "F10" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; + + +#NET "j_up" LOC = "AD4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick up low active +#NET "j_down" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low active +NET "rst" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +#NET "j_left" LOC = "AE4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick left low active +#NET "j_right" LOC = "AC6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick right low active +#NET "rst" LOC = "AA7" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick push low active + +#NET "turn_on" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) #dip switch low active +#NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + +NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) +#NET "leds(0)" LOC = "G21" | IOSTANDARD = LVCMOS33; #led(4) +#NET "leds(1)" LOC = "G23" | IOSTANDARD = LVCMOS33; #led(5) +#NET "leds(2)" LOC = "H23" | IOSTANDARD = LVCMOS33; #led(6) +#NET "leds(3)" LOC = "J21" | IOSTANDARD = LVCMOS33; #led(7) + +#NET "in_vector(0)" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) dip switches are low-active +#NET "in_vector(1)" LOC = "AD15" | IOSTANDARD = LVCMOS25; #dip_sw(1) +#NET "in_vector(2)" LOC = "AD19" | IOSTANDARD = LVCMOS25; #dip_sw(2) +#NET "in_vector(3)" LOC = "AD23" | IOSTANDARD = LVCMOS25; #dip_sw(3) +#NET "in_vector(4)" LOC = "AF21" | IOSTANDARD = LVCMOS25; #dip_sw(4) +#NET "in_vector(5)" LOC = "AF22" | IOSTANDARD = LVCMOS25; #dip_sw(5) +#NET "in_vector(6)" LOC = "W15" | IOSTANDARD = LVCMOS25; #dip_sw(6) +#NET "in_vector(7)" LOC = "W16" | IOSTANDARD = LVCMOS25; #dip_sw(7) + +#NET "enable" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low-active +NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + Index: tags/ver/bin/route_ngc =================================================================== --- tags/ver/bin/route_ngc (nonexistent) +++ tags/ver/bin/route_ngc (revision 3) @@ -0,0 +1,15 @@ +#!/bin/sh +# route entity ucf-file device effort bitgen +#ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6 +rm -f $1.ngd +echo ngdbuild $1.ngc -aul -uc $2 -p $3# -sd $6/xst -sd $6 +ngdbuild $1.ngc -aul -uc $2 -p $3 #-sd $6/xst -sd $6 +#ngdbuild $1.ngc -aul -uc $2 -p $3 +echo map -pr b -p $3 $1 +map -pr b -p $3 $1 +echo par -ol $4 -w $1 $1.ncd +par -ol $4 -w $1 $1.ncd +echo trce -v 25 $1.ncd $1.pcf +trce -v 25 $1.ncd $1.pcf +echo bitgen $1 -l -m -w -d -f $5 +bitgen $1 -l -m -w -d -f $5
tags/ver/bin/route_ngc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/ver/bin/load_modules =================================================================== --- tags/ver/bin/load_modules (nonexistent) +++ tags/ver/bin/load_modules (revision 3) @@ -0,0 +1,4 @@ +module load mentor/modelsim/6.3d-64 +module load xilinx/ise-9.2i-64 + + Index: tags/ver/bin/vscript =================================================================== --- tags/ver/bin/vscript (nonexistent) +++ tags/ver/bin/vscript (revision 3) @@ -0,0 +1 @@ +echo vcom $1
tags/ver/bin/vscript Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/ver/bin/xstvhdl =================================================================== --- tags/ver/bin/xstvhdl (nonexistent) +++ tags/ver/bin/xstvhdl (revision 3) @@ -0,0 +1 @@ +echo vhdl work $1 \ No newline at end of file
tags/ver/bin/xstvhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/ver/notes =================================================================== --- tags/ver/notes (nonexistent) +++ tags/ver/notes (revision 3) @@ -0,0 +1,28 @@ +vlib work -- create work library fo the simulation + +vmap work work -- this map the new work library, the second work is the path +to the library, could be vsim/work or something like this. + +vcom -quiet -93 -work work my_vhdl_file_to_compile.vhd + +----- +vlib -- create library +vmap -- list all mapped librarys +vmap -- map logical library to real one +vmap -del -- delete logical mapping +vcom -93 -check_synthesis -force_refresh -work --if you specifiy more than one file, you must start with the lowest file +in the hierarchie. You should comile the design vhdl source files and the +testbench vhdl file. +vsim . --start vsim and specify the TOP-Level + +=modelsim/work +=work += could be logical name "work" or unix path "modelsim/work" +=src/abc.vhd +=work.dff_tb + +---- +vsim -c work.dff_tb -do first.do + +--tlc1 is ok?, tlc2 is ok but green is 3ms longer, tlc3 is absolutely ok but +should be corrected in order to synthesize, \ No newline at end of file Index: tags/ver/modelsim/work/topentity/structural.dat =================================================================== --- tags/ver/modelsim/work/topentity/structural.dat (nonexistent) +++ tags/ver/modelsim/work/topentity/structural.dat (revision 3) @@ -0,0 +1,5 @@ +p"0= 0^cx̋t4o>Gi)\ncE:ɶm\" Q'_uyI0ODJ⍧MJ W>Ηn!h'$o ++" +X-mfkhg Va !C V$E KPZ +uD\ +^<Zfpa$WqF/\QCMR=mlVjiB#?n+*kVSKsu[MEtE;tsHJm"EzaL˞k71WAi#*8(l +Y&ftzƔaψ O G zhĀ$뚿 \ No newline at end of file Index: tags/ver/modelsim/work/topentity/_primary.dat =================================================================== --- tags/ver/modelsim/work/topentity/_primary.dat (nonexistent) +++ tags/ver/modelsim/work/topentity/_primary.dat (revision 3) @@ -0,0 +1,4 @@ +p4D810 +Z3 04 12 8 work topentity_tb behavior 1 +Z4 =2-001636847494-485684b4-a96c8-18f +Z5 o-quiet -auto_acc_if_foreign -work work +Z6 tExplicit 1 +Z7 OL;O;6.3d;37 +Pasci_types +Z8 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2 +32 +Z9 Mx1 17 __model_tech/ieee 14 std_logic_1164 +Z10 w1213612700 +Z11 8src/asci_types.vhd +Z12 Fsrc/asci_types.vhd +l0 +L4 +Z13 V`3hTfYOZkbRESoiV6HXQm0 +Z14 OL;C;6.3d;37 +R6 +Pcomponents +R8 +32 +R9 +Z15 w1213612778 +Z16 8src/components.vhd +Z17 Fsrc/components.vhd +l0 +L4 +Z18 V>6fYR``OLP:1HiED4?jlf0 +R14 +R6 +Egeneric_freq_div +Z19 w1213613517 +Z20 DPx17 __model_tech/ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F6B7KDMZ2 +R14 +R6 +Abehavioral +R29 +R20 +R8 +Z33 DEx40 /export/jack/dimo/vhdl/lcd/modelsim/work 4 lcd1 0 22 P7Pl`YB^3g0Va>6B7KDMZ2 +32 +Mx3 17 __model_tech/ieee 14 std_logic_1164 +Mx2 17 __model_tech/ieee 11 numeric_std +Mx1 40 /export/jack/dimo/vhdl/lcd/modelsim/work 10 asci_types +l54 +L28 +Z34 VEnF;`@e6igVB6fYR``OLP:1HiED4?jlf0 +R8 +32 +Z37 8src/topEntity.vhd +Z38 Fsrc/topEntity.vhd +l0 +L5 +Z39 V1`QdD;dRN7SVP>5kB@G722 +R14 +R6 +Astructural +R33 +R24 +R36 +R8 +Z40 DEx40 /export/jack/dimo/vhdl/lcd/modelsim/work 9 topentity 0 22 1`QdD;dRN7SVP>5kB@G722 +32 +R25 +Mx1 40 /export/jack/dimo/vhdl/lcd/modelsim/work 10 components +l14 +L12 +Z41 VbQmV;I6hDkRgCQaK6;HLh^G@zS1 +R14 +R6 +Abehavior +R40 +R20 +R8 +DEx40 /export/jack/dimo/vhdl/lcd/modelsim/work 12 topentity_tb 0 22 05CQaK6;HLh^G@zS1 +32 +R25 +R26 +l58 +L36 +Z46 V>BSTchCfYP7_B8Z2JN=?g3 +R14 +R6 Index: tags/ver/modelsim/work/_opt/vopt0tbdig =================================================================== --- tags/ver/modelsim/work/_opt/vopt0tbdig (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt0tbdig (revision 3) @@ -0,0 +1,3 @@ +p4 +V ߾Жn87 +'3&sT=Ds \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt9t09sq =================================================================== --- tags/ver/modelsim/work/_opt/vopt9t09sq (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt9t09sq (revision 3) @@ -0,0 +1,18 @@ +p4~c6f9aOj +g} )W9`_sUUP +{ Qc סs:vGTdS +> 8WK$G~pf`9\Zg +tM ΤDD`L+UPh +K@ a; p+td4CR@. +![clwIyI ހ x.]9}Fgeǝr-fqC O6$f>f +b)T ~`EY6E!6R! +Ka +4,̙ow`I4RVUV9=_gP47#0o:fcFXG%QB_k;ur'MK'i^\ ygq5Us\*jB]NB's>;qP=n[9 3(:Nw^٢-wr-ؐu=-8˫.E[&wx,o7t;%_,Rd\Sbu{Y3wJv}"&:JnF +F0kfnER*LdkCrywb +$[ 1 Bl +w1ϸ,V!`7cR[ΰUc \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt20vdf9 =================================================================== --- tags/ver/modelsim/work/_opt/vopt20vdf9 (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt20vdf9 (revision 3) @@ -0,0 +1 @@ +p45Q&"s0.ş$k2IZ:T3zd;58jRu9kIzuDUtj@kꍡ"~k{E++6g< \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptb76g0w =================================================================== --- tags/ver/modelsim/work/_opt/voptb76g0w (nonexistent) +++ tags/ver/modelsim/work/_opt/voptb76g0w (revision 3) @@ -0,0 +1,4 @@ +p4<'m4 ?;@ϞA,$BV&Ci3D<=)E+F̹"G? HIpJOKwL`&uM_N-09O@;P/BQ# +-RѪS?TUVq+WNX<4Y[Q6Z d#S[#3<\K\]t/^^-_k`'iaҞb8c҂'-dS/e=4fZL6geNh?izjxk,lwmaun^o1pAqCr/>s7txu.vgwm1exR3yb9;<͕D#A5И +ɯ!4 ˭pΜhghy[| 1 gwqbt&tOKpJcߥ\cڧQf]n0n ܑ +ʮA8~e2}#V&i{cYd\.a*9zzożHPj +{ջnkVleWiTÝk?đ'¢C-J|CZuEF?e] ]>ʍb9;<͚D#A5 +ɯ!4 ˭phghy[| ף1 ؄gwqbt&tOKܚpJcߥޘ\cQf]n0n ↰㖹ܑ +A8~e2}#V&i{cYd\.a*9zzoHPj +{ջnkVleWiTk?'¢C-J|CZEEv?U]<m=5b9 Gr69Ǔ3*T"I 'j*X!Z*x4Z"x +K#(&YI'j;X!J;h$J2 h +[3(&HI'j+Y0 [+x%J3 i[#8&Y +H6k*Y0K:x4J#i[39'X +Y7z;I K+y4K2i Z297H +Y7j:Y J:x 4Z" +xK#('XX'k;Y1Z;i$K"iZ#(6XH '{+H [:x5J#i +[397X +H '{*I1J;h 5[3 y +K#8&Y +Y6j*X1 J;h %K" yK29'Y +H7j:Y [*x%[# i +[3(&XY6z:H1Z*i$Z" +iZ#97X +I6k;X!Z:h $[3 +i +Z2('IH&k+Y!K*y$J#xK#(7YI&{;I J*y4Z3 hZ#(&YY 7j+Y0 J:i4J3xJ#(6HH'z;H1 K;i$[3 iZ2)7IY6k;Y J;h%Z2 +h [38&I H'z:I *0\~0(6ўċg{1v[ā!g߸r>7Tz]ȮpZ< +u "*kp'\NTxl'3jK^Rz'`=@Sߢ)o<*^M̞my +[>l01<Y=HTfV@mV2@0VDC aRvE\$`pW\#b=Oo{!r5 *B޸gXدv:0)'iۛ5x̙]Zb[1B 7( / F4g4asTyUcw+c`RFOP7 !|6G#iakZFtQ>Ϣ +,ܟk{)<ɸ]M~_ޞX ɡjo ~x/3Q~tatt +m]GraL˞k71WAi#*8(l +Y&fk71WAi#*86z,qFfYK G p"Ij;N$ιU"GEV%N4 OtQ򯘡C^q! \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptcv7cma =================================================================== --- tags/ver/modelsim/work/_opt/voptcv7cma (nonexistent) +++ tags/ver/modelsim/work/_opt/voptcv7cma (revision 3) @@ -0,0 +1,5 @@ +pb7b7S$"2 3 6 7 7 7 8 >2>2?3?3?7?7? 7? 7? +7?7@6@6@8@8=C I2I2I( +LN Q3Q( S3S( +VWtz*U%_*[7Vk71WAi9>aL˞k71WAi#*8(l +Y&fk71WAi#*86z,qFfYM G p"Ij1Dԫ;9UL!wA`TP0[+n'HM=.'H>%j֡YQajz9V+W4q \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt10cb3h =================================================================== --- tags/ver/modelsim/work/_opt/vopt10cb3h (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt10cb3h (revision 3) @@ -0,0 +1,12 @@ +p"0= 0^c{̋to>Gi)X< #2=^{ ++,A N 5 bB/&)61=p0a: JK ufL +2qRxHq] LfQeZTFupT}DDEVg"Z0xgNj uT + ENf(L?3Ҁ a +^ ++W%8 qw=p`4BaS4 +%xC%o`'FXvwqFq-@1 qewJb$L]= cD; C +W8 +qQB8) >_ 5IY wS5TNҝ49H$HŞowlwrk; +<^nꨴC'w,8Ղ,ϥ#7: >١H;c;+ +Ku2_V٫[zi3>6®em+jl~'Fk5%ܥS`*ʸދ;Ւq6li?f8`~|~#u^=ZMYHoY +W&3^xlް"Y؛w7CjdʧB \ No newline at end of file Index: tags/ver/modelsim/work/_opt/_deps =================================================================== --- tags/ver/modelsim/work/_opt/_deps (nonexistent) +++ tags/ver/modelsim/work/_opt/_deps (revision 3) @@ -0,0 +1,28 @@ +E)Z w8tzkW~DvrkLQ1eGN,Wb7m$@H#&8<-jZi0! tl1\0;4ǣi3(ɮ)^X!Wa?~7TSI5wZNy@~=lUߛ+)ܴD?y`¹NY46%Ѥ#'?ʹ2rJEnČ+0_QԧBDkԔ>^nFfAA@ | -kǹA\# ג(>(۹ڦVuWQ Vs.=Ȁ -k3gλ# +w(qV}= x[y!^s+/O!ՇXSH*tE" AOmցcθΧ RC~rh{i"dM,\LCrpHwKCr\{N +Z9;DAJ;g\ғfjӀɫ}%GϐLelLR̔թ`'JYzI>Ў4X$-ð%AgqEm9'8;45%nUpE C +3Bp¤i"o%M$;!U"-tB1r[>8ZX/[>p. 0ʘiAz6 (q<+:tq4D{#4ˠߏ+l" ˰ +\G6yti!3uY G̶az&68WTН}?_P[R1A~Cϓ@ +d5)̼%Ybx)'pwnW0{_81S +^ZAΝTqtx40XUk,m_tB7!S﯑AMP OI+ؒ;} ]8k0-1A". 37j_ ѵ> u:jq +1v7m~>F6{;Lڈ40I +. ]cGPnQ)x0cIK(*V}絆2qV?&EW+HiRɞχt/eN$VҊ?E¢aMd` B* +'lX0\4ӭeEc|ĺ RPk(iq4S5;;+tr.[j_X_ѵ;_Ӓ3{ۮUJHUWX~3PF"Pha+J樀 eCvzBI% C +Vπ~eyTb]yh.r-nl DE r)T`5!P[q#}y:1B:-LX`{~rRjߣ2Iۂ\x}ަKʿ6nɸHAd8d`Ie⍦ 0;rdDNXշcev!ˊ3鸿觖eRcح@ ي7>-b"5Y$}eKZ1G=&B+ +> }kWO +CᢋJ+ p=pݐ\+/i7[!%K Ot +_ڝfZ٠P\Yԣir]ډQ G0lUzJB',@Hp jr=jfaFF̪v')Dcڻ_ʺ̢E(Ar%ٽa%/uLzQXX?eXX]cK7K/d֒lp&* +] +.W:E_A^X7@@0u&ꫢwe ϿU`1UcJ2'X4WPTbo1H +x +0B;Wq4\'n~GO}sW]mҦ \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt9iq64f =================================================================== --- tags/ver/modelsim/work/_opt/vopt9iq64f (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt9iq64f (revision 3) @@ -0,0 +1,147 @@ +p"0= 0^c1̋t$o>Gi)\kc;n-9iВ>ؚĬ `+ +%_t fs > +,t+nk1ql\(vc]/Z)ճ.qNCӺ2pd5[>HϵOYtfs >!,"t+#nk1$ql%\(v&c]/'Z())ճ.*+q,N-CӺ2p.d5/[0>H1ϵO2Yt3fs4>5,6t+7nk18ql9\(v:c]/;Z<)=ճ.>?q@NACӺ2pBd5C[D>HEϵOFYtGfsH>I,Jt+Knk1LqlM\(vNc]/OZP)Qճ.RSqTNUCӺ2pVd5W[X>HYϵOZYt[fs\>],^t+_nk1`qla\(vbc]/cZd)eճ.fgqhNiCӺ2pjd5k[l>HmϵOnYtofsp>q,rt+snk1tqlu\(vvc]/wZx)yճ.z{q|N}CӺ2p~d5[>HϵOYtfs>,t+nk1ql\(vc]/Z)ճ.㹏qNCӺ2pd5[>HϵOYtfs>,t+nk1ql\(vc]/Z)ճ.㹣qNCӺ2pd5[>HϵOYtfs>,t+nk1ql\(vc]/Z)ճ.㹷qB.4A;i:\mʻpjYwup}҇'}+! 07l=X;₴<@ ;$Q$ +Ƞ  Tʺa{}P ؀-waun^.Q NJA +NC5L Ǽ*ʳ(W̜h#ӑ)waun^.Q NJA +NC5 +QǚLڥBN2@% +DZǿ>Gx8gl'ebS%]ǚLڥBN2@% +DZǿ5a +s^LJA uSC"4Qj̼+h׮)2ؗ +֨5a +s^LJA uP^8 ǚMǥOߜ̺ǰc"\GxC.%A8gm:eǾR8 ǚMǥOߜ̺ǵک'z|ʕY4E_d OFGc4!AT6~Y~4MCJVMZn\Hw +^`NVa]OY1]6h-䄳*觪 ۼ?ώe^dAQX">3poNvdU؁r'1K⥡Q0l<2:k*%C7)aTXmRX^6Cn);&}`~4AԞ,6!ҥ, suaVtH/.i p\-˽7z&(sOwr) iwGiVc:5U5CJ-!=\ q  "%# 3/""A18g!I`&k? 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B #A -B +C 6A D #C -D +E 6C F #E -F +G 6E H #G -H +I 6G J #I -J +K 6I L #K -L +M a M  +q +>A^]+mN +P +2P +X2.m  +^],m  +]0m--O cP 6 AQ #P R 9Q +S 6O R T U 2S V #U -V +W 6U X #W -X +Y 6W Z #Y -Z +[ 6Y \ #[ -\ +] 6[ ^ #] -^ +_ 6] ` #_ -` +a 6_ b #a -b +c 6a d #c -d +e a e  +q +1m  +>#^]3m  +4m  +5m--f cg 6 Bh #g i 9h +j 6f i k l 2j m #l -m +n 6l o #n -o +p 6n q #p -q +r 6p s #r -s +t 6r u #t -u +v 6t w #v -w +x 6v y #x -y +z 6x { #z -{ +| a |  +q +> +^]7m} +P +2P +X2:m  +^]8m  +]<m--~ c 6 B #  9 + 6~    2  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + a   +q +=m  +>^]?m  +@m  +Am-- c 6 C #  9 + 6    2  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + a   +q +>^]Cm +P +2P +X2Fm  +^]Dm  +]Hm-- c 6 C #  9 + 6    2  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + a   +q +Im  +>^]Km  +Lm  +Mm-- c 6 D #  9 + 6    2  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + a   +q +>^]Om +P +2P +X2Rm  + ^]Pm  + ]Tm-- c 6 D #  9 + 6    2  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + 6  # - + a   +q +Um  +>|^]Wm  +Xm  +Ym-- c 6 E #  9 + 6    2  # - + 6  # - + 6  # - + 6  +# - + + +6  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +>b^][m + + +P +2P +X2^m  +^]\m  +]`m-- +c +6 E + +# +  +9 + + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + +! +a ! + +q +am  +>D^]cm  +dm  +em--" +c# +6 F$ +## + % +9$ + +& +6" + % + ' +( +2& + ) +#( +-) + +* +6( + + +#* +-+ + +, +6* + - +#, +-- + +. +6, + / +#. +-/ + +0 +6. + 1 +#0 +-1 + +2 +60 + 3 +#2 +-3 + +4 +62 + 5 +#4 +-5 + +6 +64 + 7 +#6 + -7 + +8 +a 8 + +q +>+^]gm9 + +P +2P +X2jm  +^]hm  +]lm--: +c; +6 F< +#; + = +9< + +> +6: + = + ? +@ +2> + A +#@ +-A + +B +6@ + C +#B +-C + +D +6B + E +#D +-E + +F +6D + G +#F +-G + +H +6F + I +#H +-I + +J +6H + K +#J +-K + +L +6J + M +#L +-M + +N +6L + O +#N + -O + +P +a P + +q +mm  +> ^]om  +pm  +qm--Q +cR +6 GS +#R + T +9S + +U +6Q + T + V +W +2U + X +#W +-X + +Y +6W + Z +#Y +-Z + +[ +6Y + \ +#[ +-\ + +] +6[ + ^ +#] +-^ + +_ +6] + ` +#_ +-` + +a +6_ + b +#a +-b + +c +6a + d +#c +-d + +e +6c + f +#e + -f + +g +a g + +q +>^]smh + +P +2P +X2#vm  +'^#]tm  +']xm--i +cj +6 Gk +#j + l +9k + +m +6i + l + n +o +2m + p +#o +-p + +q +6o + r +#q +-r + +s +6q + t +#s +-t + +u +6s + v +#u +-v + +w +6u + x +#w +-x + +y +6w + z +#y +-z + +{ +6y + | +#{ +-| + +} +6{ + ~ +#} + -~ + + +a  + +q +ym  +>^]{m  +|m  +}m-- +c +6 H +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +>^]m + +P +2P +X2-m  +1^-]m  +1]m-- +c +6 H +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +m  +>^]m  +m  +m-- +c +6 I +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +>^]m + +P +2P +X27m  +;^7]m  +;]m-- +c +6 I +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +m  +>e^]m  +m  +m-- +c +6 J +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# +- + + +6 +  +# + - + + +a  + +q +>L^]m + +P +2P +X2Am  +E^A]m  +E]m-- +c +6 J +# +  +9 + + +6 +  +  + +2 +  +# +- + + +6 +  +# +- + +6 + #- +6 #- +6 #- +6 #- +6  #-  + +6  # + -  + a   +q +m  +>-^]m  +m  +m-- +c6 K# 9 +6 +  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6  #-  +!6 "#! -" +#a # +q +>^]m$ +P +2P +X2Km  +O^K]m  +O]m--%c&6 K'#& (9' +)6% ( *+2) ,#+-, +-6+ .#--. +/6- 0#/-0 +16/ 2#1-2 +361 4#3-4 +563 6#5-6 +765 8#7-8 +967 :#9 -: +;a ; +q +m  +>^]m  +m  +m--<c=6 L>#= ?9> +@6< ? AB2@ C#B-C +D6B E#D-E +F6D G#F-G +H6F I#H-I +J6H K#J-K +L6J M#L-M +N6L O#N-O +P6N Q#P -Q +Ra R +q +>^]mS +P +2P +X2Um  +Y^U]m  +Y]m--TcU6 LV#U W9V +X6T W YZ2X [#Z-[ +\6Z ]#\-] +^6\ _#^-_ +`6^ a#`-a +b6` c#b-c +d6b e#d-e +f6d g#f-g +h6f i#h -i +ja j +q +m  +>^]m  +m  +m--kcl6 Mm#l n9m +o6k n pq2o r#q-r +s6q t#s-t +u6s v#u-v +w6u x#w-x +y6w z#y-z +{6y |#{-| +}6{ ~#}-~ +6} # - +a  +q +>^]m +P +2P +X2_m  +c^_]m  +c]m--c6 M# 9 +6  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 # - +a  +q +m  +>^]m  +m  +m--c6 N# 9 +6  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 # - +a  +q +>m^]m +P +2P +X2im  +m^i]m  +m]m--c6 N# 9 +6  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 # - +a  +q +m  +>N^]m  +m  +m--c6 O# 9 +6  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 # - +a  +q +>5^]m +P +2P +X2sm  +w^s]m  +w]m--c6 O# 9 +6  2 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 #- +6 # - +a  +q +m  +>^]m  +m  +m x  +>^]m +P +P +X}m  +^}]m  +]m   +m  +>^=]m  +m  +m } +>]m]]] + +Sa + +a +  +a +0 +a +X +a + +`  +`0 +`@P +`P +`` +`p( +.V + +SV  +] ,.` + +SV +V + +]-;.h + +]<. + +]]```12```````one_usec_factor``max_factor_fact``init_factor_fac`` 0normal_factor_f`` +Xextended_factor`` ext_modext_mode`` lines_4`` +0data_8bitta_8bi``Pxdisplay_onplay_``display_cleary_``entry_modery_mo``(clk_400LLPclk400LLprst400LLlcd_rsLLlcd_rwLLlcd_enaLLlcd_datacd_dataLLleddataLL8init_startt_stawait_set1it_setset1setwait_esetit_eseesetesewait_set2it_setset2setwait_lcd_on_lcdlcd_ondwait_lcd_cleardlcd_cleard_cleawait_lcd_entrcdlcd_entrcd_entrwait_l1s1it_l1sl1s1l1swait_l1s2it_l1sl1s2l1swait_l1s3it_l1sl1s3l1swait_l1s4it_l1sl1s4l1swait_l1s5it_l1sl1s5l1swait_l1s6it_l1sl1s6l1swait_l1s7it_l1sl1s7l1swait_l1s8it_l1sl1s8l1swait_l1s9it_l1sl1s9l1swait_l1s10t_l1sl1s101swait_l1s11t_l1sl1s111swait_l1s12t_l1sl1s121swait_l1s13t_l1sl1s131swait_l1s14t_l1sl1s141swait_l1s15t_l1sl1s151swait_l1s16t_l1sl1s161swait_l1s17t_l1sl1s171swait_l1s18t_l1sl1s181swait_l1s19t_l1sl1s191swait_l1s20t_l1sl1s201swait_l2s1it_l2sl2s1l2swait_l2s2it_l2sl2s2l2swait_l2s3it_l2sl2s3l2swait_l2s4it_l2sl2s4l2swait_l2s5it_l2sl2s5l2swait_l2s6it_l2sl2s6l2swait_l2s7it_l2sl2s7l2swait_l2s8it_l2sl2s8l2swait_l2s9it_l2sl2s9l2swait_l2s10t_l2sl2s102swait_l2s11t_l2sl2s112swait_l2s12t_l2sl2s122swait_l2s13t_l2sl2s132swait_l2s14t_l2sl2s142swait_l2s15t_l2sl2s152swait_l2s16t_l2sl2s162swait_l2s17t_l2sl2s172swait_l2s18t_l2sl2s182swait_l2s19t_l2sl2s192swait_l2s20t_l2sl2s202swait_l3s1it_l3sl3s1l3swait_l3s2it_l3sl3s2l3swait_l3s3it_l3sl3s3l3swait_l3s4it_l3sl3s4l3swait_l3s5it_l3sl3s5l3swait_l3s6it_l3sl3s6l3swait_l3s7it_l3sl3s7l3swait_l3s8it_l3sl3s8l3swait_l3s9it_l3sl3s9l3swait_l3s10t_l3sl3s103swait_l3s11t_l3sl3s113swait_l3s12t_l3sl3s123swait_l3s13t_l3sl3s133swait_l3s14t_l3sl3s143swait_l3s15t_l3sl3s153swait_l3s16t_l3sl3s163swait_l3s17t_l3sl3s173swait_l3s18t_l3sl3s183swait_l3s19t_l3sl3s193swait_l3s20t_l3sl3s203swait_l4s1it_l4sl4s1l4swait_l4s2it_l4sl4s2l4swait_l4s3it_l4sl4s3l4swait_l4s4it_l4sl4s4l4swait_l4s5it_l4sl4s5l4swait_l4s6it_l4sl4s6l4swait_l4s7it_l4sl4s7l4swait_l4s8it_l4sl4s8l4swait_l4s9it_l4sl4s9l4swait_l4s10t_l4sl4s104swait_l4s11t_l4sl4s114swait_l4s12t_l4sl4s124swait_l4s13t_l4sl4s134swait_l4s14t_l4sl4s144swait_l4s15t_l4sl4s154swait_l4s16t_l4sl4s164swait_l4s17t_l4sl4s174swait_l4s18t_l4sl4s184swait_l4s19t_l4sl4s194swait_l4s20t_l4sl4s204swait_new_line1wnew_line1w_linewait_new_line2wnew_line2w_linewait_new_line3wnew_line3w_linewait_new_line4wnew_line4w_linewait_renewt_renXcmr| +(-7<FKUZekv|    $ . 3 = B L Q [ ` j o y ~                 + + + +$ +/ +5 +@ +F +Q +W +a +f +p +u + + + + + + + + + + + + + + + + + +    " - 3 > D O U ` f q w                       + 1 < B M S ^ d o u                + + + +& +5 +? +pr_stater_stateLL1nxt_statet_statLL1(one_usecne_usecLL2Prst_intLL2xcounterLL3lcd_data_intataLL4str1ataLL5lcd_regLL5line__55ine__55line__56ine__56line__60ine__60line__61ine__61line__62ine__62line__63ine__63one_sec_pe_sec_delay_p#MERGED#lcd_en,main_s_pmain_c_pain_c_p     TU Chemnitz            SSE           Dimo Pepelyashev          ---         `?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrsvwxyz{|}~tu(Hhbehavioralaviorlcd1iortempiortemp0orflagorsrc/lcd1.vhdcd11bb3 3f9 {1ba8 3f2 {1420 42e {{t13e0 } {1400 } {0 55}} 1429 42e {{} {13e0 } {0 59}} 1432 42e {{} {6d0 } {0 60}} 143b 42e {{t13b8 } {6b0 } {0 61}} 1444 42e {{t13b8 } {710 } {0 62}} 144d 42e {{t650 } {738 } {0 63}} 1456 42e {{t670 1350 670 1378 } {1350 } {0 68}} 1460 42e {{t670 1378 670 1350 } {1398 } {0 90}} 1468 42e {{t670 1398 670 1328 690 } {6f0 1300 } {0 119}} 1480 42e {{t1398 t1300 1398 1300 1400 } {1328 1378 13b8 } {0 145}} }} `$ \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt620za5 =================================================================== --- tags/ver/modelsim/work/_opt/vopt620za5 (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt620za5 (revision 3) @@ -0,0 +1,2 @@ +p"0= 0^cx̋t5o>Gi)\&~2.Mȑ,g6 η}Ԛu8"/dxJ Mh A& a9 TX\+, +5|&{ r Vzu:m&gq-TdS?H9ߩҌ¼iW[-mQ ׁފJ!{E&]Ѣn+.2O|j|7C|CcE^J[垟(/Hzc ^b>e2nlނT VO>G~0gFsB \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptfqg0j1 =================================================================== --- tags/ver/modelsim/work/_opt/voptfqg0j1 (nonexistent) +++ tags/ver/modelsim/work/_opt/voptfqg0j1 (revision 3) @@ -0,0 +1,49 @@ +4%  +] +/(*u + + +$ +n/p + + +n -  + +d +0  n- + +d + 0 ! +nt +/n-  +  +  +e +> +]]]mm   + +S   0#  + + +R m  + + +X +m6 +/ +` ^ +]m/m  +- + ]m  +m]]] + + + +Sa +h + . + +SV +V + +]]`factorv``hclk_invLLclkinvLL divinvbehavioralaviorgeneric_freq_divreq_divcountivtmptivsrc/generic_freq_div.vhddiv.vhdd7 3f9 {cc 3f2 {c8 42e {{t88 88 } {a8 } {0 15}} }}  \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptmf2fks =================================================================== --- tags/ver/modelsim/work/_opt/voptmf2fks (nonexistent) +++ tags/ver/modelsim/work/_opt/voptmf2fks (revision 3) @@ -0,0 +1,73 @@ +m255 +K3 +Z0 cModel Technology Builtin Library +13 +Z1 dD:\qa\buildsites\6.3d\builds\win32\modeltech +Penv +Z2 OL;C;6.3d;37 +32 +b1 +Z3 OP;C;6.3d;37 +Z4 w1196138599 +Z5 d$MODEL_TECH/.. +Z6 8vhdl_src/std/env.vhd +Z7 Fvhdl_src/std/env.vhd +l0 +L1 +VMSh;Gmh>9BNn + + +  +?n + + +   +@n +8 8 +?n0 + + +H H +?n P + + +X X +?np + + +h h +@nhh +  + +] +t +  + + > + t +  +  +> + +] ]]Dm ]Im  +  + +Jm +? + + +Sw +]x +]Lm ^]]] ]Om]Pm ? + +Sw +]x +]Qm  +Rm ? + +Sw +]x +]Sm  +Tm +? + + +Sw +]]Vm^ ]!]] + +S$ . + +#]!. + +$]%]``clky.vhLL2rsty.vhLL3lcd_datacd_dataLL6lcd_enaLL70lcd_rsLL7Plcd_rwLL7pledrwLL8uutrwAworkwtopentitypentitstructuralucturtb_clkrtb_skrbehaviorehaviortopentity_tbtitsrc/topEntity_tb.vhd_tb20b 3f9 {202 3f2 {1f6 42e {{c8 } {c8 } {0 68}} 1fd 42e {{} {e8 } {0 79}} }} \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptceghcs =================================================================== --- tags/ver/modelsim/work/_opt/voptceghcs (nonexistent) +++ tags/ver/modelsim/work/_opt/voptceghcs (revision 3) @@ -0,0 +1,106 @@ +4% ] +/^u + + + +h + + + + + + +$ +n-0 + +d +0 n-P + +d + 0 n( +x( +d +80 n@-@ + +d +H0 nP-P + +d +X0 n`-` + +d +h0  nph +ph +d +0 ! + +n- + +d +0  0 + S   ^]n8 + + +  +n +( + + +  +@diz +] + + +S +  *^] " `   +n + + +  +n( + + +  +n +H + + +   +n +  + + +  +"8 ` + +h + + + + +n + + +h h +n + + +X X +n + + +H H +n + +  +" ` c*   + + + + +dz + ] +]] + + ] ]```clkcd1LL(rstcd1LLHlcd_datacd_dataLLhlcd_rsaLLlcd_rwaLLlcd_enaLLledenaLL clk_400LL +div1000clk_in0workngeneric_freq_divreq_divbehavioralaviorlcd_1orlcd1orstructuralucturtopentitypentitsrc/topEntity.vhdity.vh2c4 3f9 {2b9 3f2 {}}  \ No newline at end of file Index: tags/ver/modelsim/work/_opt/voptrsqcrc =================================================================== --- tags/ver/modelsim/work/_opt/voptrsqcrc (nonexistent) +++ tags/ver/modelsim/work/_opt/voptrsqcrc (revision 3) @@ -0,0 +1,8 @@ +p4<'m4<IҠE!#A#A #A +#A #A #A +#A#A#A #A +#A   +!!!!!lL{FݬJsLMq6h$ryoVka2sLMq +3"&첣sLMq +3" D/hk~XElA.oϙ-u]9VUK \ No newline at end of file Index: tags/ver/modelsim/work/_opt/vopt89cw3q =================================================================== --- tags/ver/modelsim/work/_opt/vopt89cw3q (nonexistent) +++ tags/ver/modelsim/work/_opt/vopt89cw3q (revision 3) @@ -0,0 +1,2 @@ +p4<'m4>4>(???(DDEE +GH2IEJ2J(LELMEN2N2N(PEPETZZ[[ +\ +^_2`[b2b\c\f2f\g\i[ij[l[l[q3q[q(rwwyz3{ {(!} }("#$1(%11(&13'11((2()4(*3+ 1(,1(-4(.2(/1(02(142 (334 +1(51(642 (72(81(92(:4; +(<34 +1(=1(>4; +(?2(@1(A2(B4C(D34 +1(E1(F4C(G2(H1(I2(J4K(L34 +1(M1(N4K(O2(P1(Q2(R4S(T3U 1(V1(W4S(X2(Y1(Z2([4\(]34 +1(^1(_4\(`2(a1(b2(c4  5d  5(e34 +1(f1(g4  5d  5(h2(i1(j2(k4  5d  5(l34 +1(m1(n4  5d  5(o2(p1(q2(r4  5d  5(s34 + 1 (t 1 (u +4 +  5 +d +  5 +(v2(w1(x2(y4  5d  5(z34 +1({1(|4  5d  5(}2(~1(2(4  5d  5( 3 4 +!1!(#1#(%4%  5%d%  5%(&2&((1(()2)(*4*  5*d*  5*(,3,4 +-1-(/1/(141  51d1  51(222(414(525(646  56d6  56(8384 +919(;1;(=4=  5=d=  5=(>2>(@1@(A2A(B4B  5BdB  5B(D3D4 +E1E(G1G(I4I  5IdI  5I(J2J(L1L(M2M(N4N  5NdN  5N(P3P4 +Q1Q(S1S(U4U  5UdU  5U(V2V(X1X(Y2Y(Z4Z  5ZdZ  5Z(\3\4 +]1](_1_(a4a  5ada  5a(b2b(d1d(e2e(f4f  5fdf  5f(h3h4 +i1i(k1k(m4m  5mdm  5m(n2n(p1p(q2q(r4r  5rdr  5r(t3t4 +u1u(w1w(y4y  5ydy  5y(z2z(|1|(}2}(~4~  5~d~  5~(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1( +1 +( 4   5 d   5 (  +2 +( +1( 2( 4  5d  5( +34 +1(1(4  5d  5(2(1(2(4  5d  5(34 + 1 ("1"($4$  5$d$  5$(%2%('1'((2(()4)  5)d)  5)(+3+4 +,1,(.1.(040  50d0  50(121(313( 424(!545  55d5  55("7374 +818(#:1:($<4<  5<d<  5<(%=2=(&?1?('@2@((A4A  5AdA  5A()C3C4 +D1D(*F1F(+H4H  5HdH  5H(,I2I(-K1K(.L2L(/M4M  5MdM  5M(0O3O4 +P1P(1R1R(2T4T  5TdT  5T(3U2U(4W1W(5X2X(6Y4Y  5YdY  5Y(7[3[4 +\1\(8^1^(9`4`  5`d`  5`(:a2a(;c1c(<d2d(=e4e  5ede  5e(>g3g4 +h1h(?j1j(@l4l  5ldl  5l(Am2m(Bo1o(Cp2p(Dq4q  5qdq  5q(Es3s4 +t1t(Fv1v(Gx4x  5xdx  5x(Hy2y(I{1{(J|2|(K}4}  5}d}  5}(L34 +1(M1(N4  5d  5(O2(P1(Q2(R4  5d  5(S34 +1(T1(U4  5d  5(V2(W1(X2(Y4  5d  5(Z34 +1([1(\4  5d  5(]2(^1(_2(`4  5d  5(a34 +1(b1(c4  5d  5(d2(e1(f2(g4  5d  5(h34 +1(i1(j4  5d  5(k2(l1(m2(n4  5d  5(o34 +1(p1(q4  5d  5(r2(s1(t2(u4  5d  5(v34 +1(w1(x4  5d  5(y2(z1({2(|4  5d  5(}34 +1(~1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1( +1 +( 4   5 d   5 ( +2 +(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 + 1 ("1"($4$  5$d$  5$(%2%('1'((2(()4)  5)d)  5)(+3+4 +,1,(.1.(040  50d0  50(121(313(424(545  55d5  55(7374 +818(:1:(<4<  5<d<  5<(=2=(?1?(@2@(A4A  5AdA  5A(C3C4 +D1D(F1F(H4H  5HdH  5H(I2I(K1K(L2L(M4M  5MdM  5M(O3O4 +P1P(R1R(T4T  5TdT  5T(U2U(W1W(X2X(Y4Y  5YdY  5Y([3[4 +\1\(^1^(`4`  5`d`  5`(a2a(c1c(d2d(e4e  5ede  5e(g3g4 +h1h(j1j(l4l  5ldl  5l(m2m(o1o(p2p(q4q  5qdq  5q(s3s4 +t1t(v1v(x4x  5xdx  5x(y2y({1{(|2|(}4}  5}d}  5}(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5( 34 +1( +1( 4  5d  5( 2( +1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1( 4  5d  5(!2("1(#2($4  5d  5(%34 +1(&1('4  5d  5((2()1(*2(+4  5d  5(,34 +1(- +1 +(. 4   5 d   5 (/ +2 +(01(12(24  5d  5(334 +1(41(54  5d  5(62(71(82(94  5d  5(:34 + 1 (;"1"(<$4$  5$d$  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HF`g0qvu&@!H[;bݝ$.zB-@| +1@qyz7[ĎXA\I^ +E.(Ͼܷ^ݪʻ0b;:?3RpkZBp=!!@a:;&B \ No newline at end of file Index: tags/ver/modelsim/work/lcd1/behavioral.dbs =================================================================== --- tags/ver/modelsim/work/lcd1/behavioral.dbs (nonexistent) +++ tags/ver/modelsim/work/lcd1/behavioral.dbs (revision 3) @@ -0,0 +1,128 @@ +pb7b7S"1 1 2 2 33 4 5 5  7 5757( +858( < <( +==4=(>>4>(???(DDEE +GH2IEJ2J(LELMEN2N2N(PEPETZZ[[ +\ +^_2`[b2b\c\f2f\g\i[ij[l[l[q3q[q(rwwyz3{ {(!} }("#$1(%11(&13'11((2()4(*3+ 1(,1(-4(.2(/1(02(142 (334 +1(51(642 (72(81(92(:4; +(<34 +1(=1(>4; +(?2(@1(A2(B4C(D34 +1(E1(F4C(G2(H1(I2(J4K(L34 +1(M1(N4K(O2(P1(Q2(R4S(T3U 1(V1(W4S(X2(Y1(Z2([4\(]34 +1(^1(_4\(`2(a1(b2(c4  5d  5(e34 +1(f1(g4  5d  5(h2(i1(j2(k4  5d  5(l34 +1(m1(n4  5d  5(o2(p1(q2(r4  5d  5(s34 + 1 (t 1 (u +4 +  5 +d +  5 +(v2(w1(x2(y4  5d  5(z34 +1({1(|4  5d  5(}2(~1(2(4  5d  5( 3 4 +!1!(#1#(%4%  5%d%  5%(&2&((1(()2)(*4*  5*d*  5*(,3,4 +-1-(/1/(141  51d1  51(222(414(525(646  56d6  56(8384 +919(;1;(=4=  5=d=  5=(>2>(@1@(A2A(B4B  5BdB  5B(D3D4 +E1E(G1G(I4I  5IdI  5I(J2J(L1L(M2M(N4N  5NdN  5N(P3P4 +Q1Q(S1S(U4U  5UdU  5U(V2V(X1X(Y2Y(Z4Z  5ZdZ  5Z(\3\4 +]1](_1_(a4a  5ada  5a(b2b(d1d(e2e(f4f  5fdf  5f(h3h4 +i1i(k1k(m4m  5mdm  5m(n2n(p1p(q2q(r4r  5rdr  5r(t3t4 +u1u(w1w(y4y  5ydy  5y(z2z(|1|(}2}(~4~  5~d~  5~(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1( +1 +( 4   5 d   5 (  +2 +( +1( 2( 4  5d  5( +34 +1(1(4  5d  5(2(1(2(4  5d  5(34 + 1 ("1"($4$  5$d$  5$(%2%('1'((2(()4)  5)d)  5)(+3+4 +,1,(.1.(040  50d0  50(121(313( 424(!545  55d5  55("7374 +818(#:1:($<4<  5<d<  5<(%=2=(&?1?('@2@((A4A  5AdA  5A()C3C4 +D1D(*F1F(+H4H  5HdH  5H(,I2I(-K1K(.L2L(/M4M  5MdM  5M(0O3O4 +P1P(1R1R(2T4T  5TdT  5T(3U2U(4W1W(5X2X(6Y4Y  5YdY  5Y(7[3[4 +\1\(8^1^(9`4`  5`d`  5`(:a2a(;c1c(<d2d(=e4e  5ede  5e(>g3g4 +h1h(?j1j(@l4l  5ldl  5l(Am2m(Bo1o(Cp2p(Dq4q  5qdq  5q(Es3s4 +t1t(Fv1v(Gx4x  5xdx  5x(Hy2y(I{1{(J|2|(K}4}  5}d}  5}(L34 +1(M1(N4  5d  5(O2(P1(Q2(R4  5d  5(S34 +1(T1(U4  5d  5(V2(W1(X2(Y4  5d  5(Z34 +1([1(\4  5d  5(]2(^1(_2(`4  5d  5(a34 +1(b1(c4  5d  5(d2(e1(f2(g4  5d  5(h34 +1(i1(j4  5d  5(k2(l1(m2(n4  5d  5(o34 +1(p1(q4  5d  5(r2(s1(t2(u4  5d  5(v34 +1(w1(x4  5d  5(y2(z1({2(|4  5d  5(}34 +1(~1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1( +1 +( 4   5 d   5 ( +2 +(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 + 1 ("1"($4$  5$d$  5$(%2%('1'((2(()4)  5)d)  5)(+3+4 +,1,(.1.(040  50d0  50(121(313(424(545  55d5  55(7374 +818(:1:(<4<  5<d<  5<(=2=(?1?(@2@(A4A  5AdA  5A(C3C4 +D1D(F1F(H4H  5HdH  5H(I2I(K1K(L2L(M4M  5MdM  5M(O3O4 +P1P(R1R(T4T  5TdT  5T(U2U(W1W(X2X(Y4Y  5YdY  5Y([3[4 +\1\(^1^(`4`  5`d`  5`(a2a(c1c(d2d(e4e  5ede  5e(g3g4 +h1h(j1j(l4l  5ldl  5l(m2m(o1o(p2p(q4q  5qdq  5q(s3s4 +t1t(v1v(x4x  5xdx  5x(y2y({1{(|2|(}4}  5}d}  5}(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5( 34 +1( +1( 4  5d  5( 2( +1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4(34 +1(1(4(2(1(2(4  5d  5(34 +1(1( 4  5d  5(!2("1(#2($4  5d  5(%34 +1(&1('4  5d  5((2()1(*2(+4  5d  5(,34 +1(- +1 +(. 4   5 d   5 (/ +2 +(01(12(24  5d  5(334 +1(41(54  5d  5(62(71(82(94  5d  5(:34 + 1 (;"1"(<$4$  5$d$  5$(=%2%(>'1'(?(2((@)4)  5)d)  5)(A+3+4 +,1,(B.1.(C040  50d0  50(D121(E313(F424(G545  55d5  55(H7374 +818(I:1:(J<4<  5<d<  5<(K=2=(L?1?(M@2@(NA4A  5AdA  5A(OC3C4 +D1D(PF1F(QH4H  5HdH  5H(RI2I(SK1K(TL2L(UM4M  5MdM  5M(VO3O4 +P1P(WR1R(XT4T  5TdT  5T(YU2U(ZW1W([X2X(\Y4Y  5YdY  5Y(][3[4 +\1\(^^1^(_`4`  5`d`  5`(`a2a(ac1c(bd2d(ce4e  5ede  5e(dg3g4 +h1h(ej1j(fl4l  5ldl  5l(gm2m(ho1o(ip2p(jq4q  5qdq  5q(ks3s4 +t1t(lv1v(mx4x  5xdx  5x(ny2y(o{1{(p|2|(q}4}  5}d}  5}(r34 +1(s1(t4  5d  5(u2(v1(w2(x4  5d  5(y34 +1(z1({4  5d  5(|2(}1(~2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4  5d  5(34 +1(1(4  5d  5(2(1(2(4(3U 1(1(4(2(1(2(4(tza^WDk71WAi9>aL˞k71WAi#*8(l +Y&fk71WAi#*86z,qFfYtzئZ)85)P G p"Ij8&58䲸M~c6f9aOj +g} )W9`_sUUP +{ Qc סs:vGTdS +> 8WK$G~pf`9\Zg +tM ΤDD`L+UPh +K@ a; p+td4CR@. +![clwIyI ހ x.]9}Fgeǝr-fqC O6$f>f +b)T ~`EY6E!6R! +Ka +4,̙ow`I4RVUV9=_gP47#0o:fcFXG%QB_k;ur'MK'i^\ ygq5Us\*jB]NB's>;qP=n[9 3(:Nw^٢-wr-ؐu=-8˫.E[&wx,o7t;%_,Rd\Sbu{Y3wJv}"&:JnF +F0kfnER*LdkCrywb +$[ 1 Bl +w1ϸ,V!`7cR[ΰUc \ No newline at end of file Index: tags/ver/modelsim/work/lcd1/_primary.dbs =================================================================== --- tags/ver/modelsim/work/lcd1/_primary.dbs (nonexistent) +++ tags/ver/modelsim/work/lcd1/_primary.dbs (revision 3) @@ -0,0 +1,8 @@ +p4<'m4<IҠE!#A#A #A +#A #A #A +#A#A#A #A +#A   +!!!!!lL{FݬJsLMq6h$ryoVka2sLMq +3"&첣sLMq +3" D/hk~XElA.oϙ-u]9VUK \ No newline at end of file Index: tags/ver/modelsim/work/topentity_tb/behavior.dat =================================================================== --- tags/ver/modelsim/work/topentity_tb/behavior.dat (nonexistent) +++ tags/ver/modelsim/work/topentity_tb/behavior.dat (revision 3) @@ -0,0 +1,12 @@ +p"0= 0^c{̋to>Gi)X< #2=^{ ++,A N 5 bB/&)61=p0a: JK ufL +2qRxHq] LfQeZTFupT}DDEVg"Z0xgNj uT + ENf(L?3Ҁ a +^ ++W%8 qw=p`4BaS4 +%xC%o`'FXvwqFq-@1 qewJb$L]= cD; C +W8 +qQB8) >_ 5IY wS5TNҝ49H$HŞowlwrk; +<^nꨴC'w,8Ղ,ϥ#7: >١H;c;+ +Ku2_V٫[zi3>6®em+jl~'Fk5%ܥS`*ʸދ;Ւq6li?f8`~|~#u^=ZMYHoY +W&3^xlް"Y؛w7CjdʧB \ No newline at end of file Index: tags/ver/modelsim/work/topentity_tb/behavior.dbs =================================================================== --- tags/ver/modelsim/work/topentity_tb/behavior.dbs (nonexistent) +++ tags/ver/modelsim/work/topentity_tb/behavior.dbs (revision 3) @@ -0,0 +1,5 @@ +pb7b7S$"2 3 6 7 7 7 8 >2>2?3?3?7?7? 7? 7? +7?7@6@6@8@8=C I2I2I( +LN Q3Q( S3S( +VWtz*U%_*[7Vk71WAi9>aL˞k71WAi#*8(l +Y&fk71WAi#*86z,qFfYM G p"Ij1Dԫ;9UL!wA`TP0[+n'HM=.'H>%j֡YQajz9V+W4q \ No newline at end of file Index: tags/ver/modelsim/work/topentity_tb/_primary.dat =================================================================== --- tags/ver/modelsim/work/topentity_tb/_primary.dat (nonexistent) +++ tags/ver/modelsim/work/topentity_tb/_primary.dat (revision 3) @@ -0,0 +1,3 @@ +p4 +V ߾Жn87 +'3&sT=Ds \ No newline at end of file Index: tags/ver/modelsim/work/topentity_tb/_primary.dbs =================================================================== --- tags/ver/modelsim/work/topentity_tb/_primary.dbs (nonexistent) +++ tags/ver/modelsim/work/topentity_tb/_primary.dbs (revision 3) @@ -0,0 +1,3 @@ +p4<'m4D810 +04 12 8 work topentity_tb behavior 1 +Z2 =2-001636847494-485684b4-a96c8-18f +Z3 o-quiet -auto_acc_if_foreign -work work +Z4 tExplicit 1 +Z5 OL;O;6.3d;37 +Pasci_types +Z6 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2 +Z7 w1213612700 +Z8 8src/asci_types.vhd +Z9 Fsrc/asci_types.vhd +l0 +L4 +Z10 V`3hTfYOZkbRESoiV6HXQm0 +Z11 OL;C;6.3d;37 +32 +Z12 Mx1 4 ieee 14 std_logic_1164 +R4 +Pcomponents +R6 +Z13 w1213612778 +Z14 8src/components.vhd +Z15 Fsrc/components.vhd +l0 +L4 +Z16 V>6fYR``OLP:1HiED4?jlf0 +R11 +32 +R12 +R4 +Egeneric_freq_div +Z17 w1213613517 +Z18 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F6B7KDMZ2 +R11 +32 +R4 +Abehavioral +R27 +R18 +R6 +Z31 DEx4 work 4 lcd1 0 22 P7Pl`YB^3g0Va>6B7KDMZ2 +l54 +L28 +Z32 VEnF;`@e6igVB6fYR``OLP:1HiED4?jlf0 +R6 +Z38 8src/topEntity.vhd +Z39 Fsrc/topEntity.vhd +l0 +L5 +Z40 V1`QdD;dRN7SVP>5kB@G722 +R11 +32 +R4 +Astructural +R37 +R6 +Z41 DEx4 work 9 topentity 0 22 1`QdD;dRN7SVP>5kB@G722 +l14 +L12 +Z42 VbQmV;I6hDkRgCQaK6;HLh^G@zS1 +R11 +32 +R4 +Abehavior +R18 +R6 +Z48 DEx4 work 12 topentity_tb 0 22 05CQaK6;HLh^G@zS1 +l58 +L36 +Z49 V>BSTchCfYP7_B8Z2JN=?g3 +R11 +32 +R24 +R25 +R4 Index: tags/ver/modelsim/work/generic_freq_div/behavioral.dat =================================================================== --- tags/ver/modelsim/work/generic_freq_div/behavioral.dat (nonexistent) +++ tags/ver/modelsim/work/generic_freq_div/behavioral.dat (revision 3) @@ -0,0 +1,2 @@ +p"0= 0^cx̋t5o>Gi)\&~2.Mȑ,g6 η}Ԛu8"/dxJ Mh A& a9 TX\+, +5|&{ r Vzu:m&gq-TdS?H9ߩҌ¼iW[-mQ ׁފJ!{E&]Ѣn+.2O|j|7C|CcE^J[垟(/Hzc ^b>e2nlނT VO>G~0gFsB \ No newline at end of file Index: tags/ver/modelsim/work/generic_freq_div/behavioral.dbs =================================================================== --- tags/ver/modelsim/work/generic_freq_div/behavioral.dbs (nonexistent) +++ tags/ver/modelsim/work/generic_freq_div/behavioral.dbs (revision 3) @@ -0,0 +1,5 @@ +pb7b7~S +" + + (tz;T&Q/Et?sk71WAi9>aL˞k71WAi#*8(l +Y&fk71WAi#*86z,qFfYK G p"Ij;N$ιU"GEV%N4 OtQ򯘡C^q! \ No newline at end of file Index: tags/ver/modelsim/work/generic_freq_div/_primary.dat =================================================================== --- tags/ver/modelsim/work/generic_freq_div/_primary.dat (nonexistent) +++ tags/ver/modelsim/work/generic_freq_div/_primary.dat (revision 3) @@ -0,0 +1 @@ +p45Q&"s0.ş$k2IZ:T3zd;58jRu9kIzuDUtj@kꍡ"~k{E++6g< \ No newline at end of file Index: tags/ver/modelsim/work/generic_freq_div/_primary.dbs =================================================================== --- tags/ver/modelsim/work/generic_freq_div/_primary.dbs (nonexistent) +++ tags/ver/modelsim/work/generic_freq_div/_primary.dbs (revision 3) @@ -0,0 +1,4 @@ +p4<'m4>do it<< to reload" + @echo " make use-vsim-gui : simulate with Modelsim and GUI" + @echo " make use-xst : synthesize with xst " + @echo " make implement : final step" + @echo " make ml : prints loaded modules. Use source bin/load_modules if modules are not loaded " + @echo " make files : prints info about the used files " + @echo " make vsim-help : prints appropriate steps for simulation" + @echo " make warnings-xst : prints warnings and info from the XST log file" + @echo " make warnings-implement : prints warnings and info from the PAR log file" + @echo " make clear : clears all XST output files" + @echo + +use-xst: $(VHDLSYNFILES) + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + @for i in $(VHDLSYNFILES); do bin/xstvhdl $$i >> $(PROJECTFILE); done + @echo run -ifn $(PROJECTFILE) -ifmt vhdl -ofn $(TOP).ngc -ofmt NGC -p $(DEVICE) -opt_mode $(OPTMODE) -opt_level $(OPTLEVEL) -top $(TOP) -rtlview yes > $(SCRIPTFILE) + @xst -ifn $(SCRIPTFILE) -ofn $(LOGFILE) + +implement: $(TOP).ngc + @mv -f src/*.ucf $(UCF)TMP + @mv -f $(UCF)TMP $(UCF) + @mv -f src/*.ut $(BITGEN)TMP + @mv -f $(BITGEN)TMP $(BITGEN) + bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) + +ml: + @/home/4all/packages/modules-2.0/sun5/bin/modulecmd tcsh list + +use-vsim: it $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run -all > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) + vsim -c work.$(TOPSIM) -do $(DOFILE) + +use-vsim-gui: $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run 1000 ns > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) +# vsim -gui work.$(TOPSIM) -do $(DOFILE) & + vsim -gui work.$(TOPSIM) -do it & + +clear: + @rm -f $(TOP).ngr $(TOP).msd $(TOP).msk $(TOP).rbt $(TOP).twr $(TOP).xpi $(TOP)_pad.csv $(TOP)_pad.txt $(TOP).bld + @rm -f $(TOP).ngc $(TOP).ncd $(TOP).ngd $(TOP).rba $(TOP).rbd $(TOP).rbb netlist.lst $(TOP).mrp $(TOP).ll $(TOP).bit + @rm -f $(TOP).lso $(TOP).ngm $(TOP).ngr $(TOP).pad $(TOP).par $(TOP).pcf transcript vsim.wlf $(TOP).log $(TOP).bgn *.twr *.xml *.map *.unroutes + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + +files: + @echo + @echo $(TOP)".ngc : netlist output from XST" + @echo $(TOP)".ngr : netlist output from XST for RTL and Technology viewers" + @echo $(TOP)".scr : script file for XST, generated by Makefile" + @echo $(TOP)".prj : contains the vhdl source files, generated by Makefile." + @echo $(TOP)".log : log file, output from XST" + @echo $(TOP)".ucf : user constraints file with pins description, write yourself" + @echo $(TOP)".ut : config. script for BITGEN, write yourself" + @echo "it : do-script for Modelsim in batchmode, write yourself" + @echo $(TOP)".do : do-script for Modelsim in GUI-mode, write yourself" + @echo $(TOP)".par : PAR report file, generated by make implement" + @echo + +vsim-help: + @echo + @echo " mkdir modelsim : create main directoriy for simulation" + @echo " vlib modelsim/work : create work library for simulation" + @echo " vmap : prints all logical mapped librarys" + @echo " vmap -del work : delete actual mapping for work library" + @echo " vmap work modelsim/work : map logical library work to modelsim/work" + @echo " vcom -93 -check_synthesis -work work : compile source vhdl files" + @echo " vcom -93 -work work : compile top level testbench" + @echo " do it : use in batch mode to recompile the testbench and the top entity and to restart the simulation" + @echo + +warnings-xst: + @grep -n -i warning *.log + @grep -n -i info *.log + +warnings-implement: + @grep -n -i warning *.par *.twr + @grep -n -i info *.par *.twr Index: tags/ver/xst/work/hdpdeps.ref =================================================================== --- tags/ver/xst/work/hdpdeps.ref (nonexistent) +++ tags/ver/xst/work/hdpdeps.ref (revision 3) @@ -0,0 +1,26 @@ +V3 17 +FL /export/jack/dimo/vhdl/lcd/src/asci_types.vhd 2008/06/16.12:38:20 J.40 +PH work/asci_types 1213627949 FL /export/jack/dimo/vhdl/lcd/src/asci_types.vhd \ + PB ieee/std_logic_1164 1192821031 +FL /export/jack/dimo/vhdl/lcd/src/components.vhd 2008/06/16.12:39:38 J.40 +PH work/components 1213627950 FL /export/jack/dimo/vhdl/lcd/src/components.vhd \ + PB ieee/std_logic_1164 1192821031 CD generic_freq_div CD lcd1 +FL /export/jack/dimo/vhdl/lcd/src/generic_freq_div.vhd 2008/06/16.12:51:57 J.40 +EN work/generic_freq_div 1213627951 \ + FL /export/jack/dimo/vhdl/lcd/src/generic_freq_div.vhd \ + PB ieee/std_logic_1164 1192821031 PH ieee/NUMERIC_STD 1192821033 +AR work/generic_freq_div/behavioral 1213627952 \ + FL /export/jack/dimo/vhdl/lcd/src/generic_freq_div.vhd \ + EN work/generic_freq_div 1213627951 +FL /export/jack/dimo/vhdl/lcd/src/lcd1.vhd 2008/06/16.16:51:04 J.40 +EN work/lcd1 1213627953 FL /export/jack/dimo/vhdl/lcd/src/lcd1.vhd \ + PB ieee/std_logic_1164 1192821031 PH ieee/NUMERIC_STD 1192821033 \ + PH work/asci_types 1213627949 +AR work/lcd1/behavioral 1213627954 \ + FL /export/jack/dimo/vhdl/lcd/src/lcd1.vhd EN work/lcd1 1213627953 +FL /export/jack/dimo/vhdl/lcd/src/topEntity.vhd 2008/06/16.12:53:58 J.40 +EN work/topEntity 1213627955 FL /export/jack/dimo/vhdl/lcd/src/topEntity.vhd \ + PB ieee/std_logic_1164 1192821031 PH work/components 1213627950 +AR work/topEntity/structural 1213627956 \ + FL /export/jack/dimo/vhdl/lcd/src/topEntity.vhd EN work/topEntity 1213627955 \ + CP generic_freq_div CP lcd1 Index: tags/ver/xst/work/hdllib.ref =================================================================== --- tags/ver/xst/work/hdllib.ref (nonexistent) +++ tags/ver/xst/work/hdllib.ref (revision 3) @@ -0,0 +1,8 @@ +AR generic_freq_div behavioral /export/jack/dimo/vhdl/lcd/src/generic_freq_div.vhd sub00/vhpl03 1213627952 +AR lcd1 behavioral /export/jack/dimo/vhdl/lcd/src/lcd1.vhd sub00/vhpl05 1213627954 +EN topentity NULL /export/jack/dimo/vhdl/lcd/src/topEntity.vhd sub00/vhpl06 1213627955 +PH asci_types NULL /export/jack/dimo/vhdl/lcd/src/asci_types.vhd sub00/vhpl00 1213627949 +EN generic_freq_div NULL /export/jack/dimo/vhdl/lcd/src/generic_freq_div.vhd sub00/vhpl02 1213627951 +PH components NULL /export/jack/dimo/vhdl/lcd/src/components.vhd sub00/vhpl01 1213627950 +EN lcd1 NULL /export/jack/dimo/vhdl/lcd/src/lcd1.vhd sub00/vhpl04 1213627953 +AR topentity structural /export/jack/dimo/vhdl/lcd/src/topEntity.vhd sub00/vhpl07 1213627956 Index: tags/ver/xst/work/sub00/vhpl00.vho =================================================================== --- tags/ver/xst/work/sub00/vhpl00.vho (nonexistent) +++ tags/ver/xst/work/sub00/vhpl00.vho (revision 3) @@ -0,0 +1,140 @@ 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=================================================================== --- tags/ver/xst/work/sub00/vhpl07.vho (nonexistent) +++ tags/ver/xst/work/sub00/vhpl07.vho (revision 3) @@ -0,0 +1,18 @@ +FHHV~4q: +structural +q*rY.'  +vY:clk_400Y p +q \#,#*'\*q'*6A#) :div1000. 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