URL
https://opencores.org/ocsvn/m16c5x/m16c5x/trunk
Subversion Repositories m16c5x
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- This comparison shows the changes necessary to convert path
/
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/m16c5x/trunk/Utils/IH2MEM.EXE
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/m16c5x/trunk/Utils/IH2MEM.C
219,7 → 219,8
i = 4; |
j = 0; |
|
fprintf(stdout, "%c%c%c\n", rdat[1], rdat[0], rdat[3]); |
//fprintf(stdout, "%c%c%c\n", rdat[1], rdat[0], rdat[3]); |
fprintf(stdout, "%c%c%c\n", rdat[3], rdat[0], rdat[1]); |
|
rlen -= 1; // Decrement record length |
|
/m16c5x/trunk/RTL/Src/M16C5x.bmm
7,9 → 7,9
ADDRESS_SPACE PROM RAMB16 [0x00000000:0x000017FF] |
|
BUS_BLOCK |
Mram_PROM1 [ 3:0] LOC = X0Y0; |
Mram_PROM3 [ 3:0] LOC = X0Y0; |
Mram_PROM2 [ 7:4] LOC = X0Y1; |
Mram_PROM3 [11:8] LOC = X0Y2; |
Mram_PROM1 [11:8] LOC = X0Y2; |
END_BUS_BLOCK; |
|
END_ADDRESS_SPACE; |
/m16c5x/trunk/RTL/Src/M16C5x_Tst4.mem
1,81 → 1,81
@0000 |
FFC |
500 |
600 |
E1C |
A20 |
700 |
80C |
F20 |
CFF |
005 |
006 |
C1E |
02A |
007 |
C08 |
02F |
@000C |
FE2 |
80A |
31C |
720 |
00C |
720 |
03C |
720 |
2EF |
A08 |
C13 |
027 |
C00 |
027 |
C30 |
027 |
@0018 |
10C |
720 |
507 |
21A |
A05 |
A02 |
700 |
06C |
C01 |
027 |
705 |
A12 |
50A |
20A |
007 |
C60 |
@0024 |
720 |
FFC |
720 |
507 |
B1A |
702 |
C20 |
546 |
027 |
CFF |
027 |
705 |
A1B |
207 |
02C |
645 |
@0030 |
F1A |
702 |
D20 |
C47 |
71A |
C06 |
71A |
DE6 |
A1F |
207 |
02D |
74C |
A17 |
60C |
A17 |
6ED |
@003C |
B3A |
B7C |
D80 |
306 |
B3A |
16C |
D80 |
306 |
A3B |
C7B |
08D |
603 |
A3B |
C61 |
08D |
603 |
@0048 |
93A |
B5C |
D80 |
306 |
B3A |
14C |
D80 |
307 |
A39 |
C5B |
08D |
603 |
A3B |
C41 |
08D |
703 |
@0054 |
B3A |
02C |
DA1 |
A04 |
A02 |
700 |
05C |
720 |
A3B |
C20 |
1AD |
40A |
20A |
007 |
C50 |
027 |
@0060 |
D02 |
720 |
507 |
24A |
41A |
20D |
027 |
705 |
A42 |
A14 |
@0BFD |
000 |
00A |
A00 |
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.asm
166,7 → 166,7
|
MOVLW 0x30 ; UART BRR (Hi) PS[3:0] |
MOVWF PortC ; Output to SPI and to UART |
MOVLW 0x0F ; UART BRR (Lo) Div[7:0] (115.2k baud) |
MOVLW 0x01 ; UART BRR (Lo) Div[7:0] (921.6k baud) |
MOVWF PortC |
|
WaitLp1 BTFSS PortA,SPI_SR_TF_EF ; Wait for UART UCR, BRR output |
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.lst
1,4 → 1,4
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 1 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 1 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT |
57,7 → 57,7
00051 |
00000000 00052 SPI_CR_REn EQU 0 ; Enable MISO Data Capture |
00000001 00053 SPI_CR_SSel EQU 1 ; Slv Select: 0 - Ext SEEPROM, 1 - SSP_UART |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 2 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 2 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT |
116,7 → 116,7
00104 ;------------------------------------------------------------------------------- |
00105 |
00000004 00106 UART_BR_PS EQU 4 ; Bits 11:8 : Baud rate prescaler - (M - 1) |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 3 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 3 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT |
175,7 → 175,7
00156 |
0006 0C08 00157 MOVLW 0x08 ; Delay before using SPI I/F |
0007 002F 00158 MOVWF DlyCntr |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 4 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 4 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT |
191,7 → 191,7
00166 |
000E 0C30 00167 MOVLW 0x30 ; UART BRR (Hi) PS[3:0] |
000F 0027 00168 MOVWF PortC ; Output to SPI and to UART |
0010 0C0F 00169 MOVLW 0x0F ; UART BRR (Lo) Div[7:0] (115.2k baud) |
0010 0C01 00169 MOVLW 0x01 ; UART BRR (Lo) Div[7:0] (921.6k baud) |
0011 0027 00170 MOVWF PortC |
00171 |
0012 0705 00172 WaitLp1 BTFSS PortA,SPI_SR_TF_EF ; Wait for UART UCR, BRR output |
234,7 → 234,7
0028 0A3B 00209 GOTO Wr_UART_TF ; Transmit Extended ASCII as is |
00210 |
0029 0C7B 00211 Tst_LowerCase MOVLW 0x7B ; Test against 'z' + 1 |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 5 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 5 |
|
|
LOC OBJECT CODE LINE SOURCE TEXT |
281,7 → 281,7
00250 ;------------------------------------------------------------------------------- |
00251 |
00252 END |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 6 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 6 |
|
|
SYMBOL TABLE |
340,7 → 340,7
UART_CR_RA 00000003 |
UART_CR_RTSo 00000001 |
UART_CR_WnR 00000001 |
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 7 |
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 7 |
|
|
SYMBOL TABLE |
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.HEX
1,7 → 1,7
:020000040000FA |
:10000000FF0C050006001E0C2A000700080C2F003C |
:10001000EF02080A130C2700000C2700300C270001 |
:100020000F0C27000507120A0A050A020700600CD8 |
:10002000010C27000507120A0A050A020700600CE6 |
:100030002700FF0C270005071B0A07022C004506B6 |
:100040001F0A07022D004C07170A0C06170AED06B7 |
:100050003B0A7B0C8D0003063B0A610C8D000306F6 |
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.O
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.cof
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/m16c5x/trunk/Code/MPLAB/M16C5x_Tst4.map
1,5 → 1,5
MPLINK 4.48, Linker |
Linker Map File - Created Sun Jul 28 12:14:22 2013 |
Linker Map File - Created Thu Dec 05 08:25:31 2013 |
|
Section Info |
Section Type Address Location Size(Bytes) |
/m16c5x/trunk/README.txt
10,15 → 10,15
------------------- |
|
This project demonstrates the use of a PIC16C5x-compatible core as an FPGA- |
based processor. The core provided is instruction set compatible, but it is |
not a cycle accurate model of any particular PIC microcomputer. It implements |
the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog |
timer. |
based processor. It implements the 12-bit instruction set, the timer 0 module, |
the pre-scaler, and the watchdog timer. The core provided here is compatible |
with instruction set, but it is not a cycle accurate model of any particular |
PIC microcomputer. |
|
As configured, the core supports single cycle (1) operation with internal |
block RAM serving as program memory. In addition to the block RAM program |
store, a 4x clock generator and reset controller is included as part of the in |
the demonstration. |
store, a 4x clock generator and reset controller is included as part of the |
demonstration. |
|
Three I/O ports are supported, but they are accessed as external registers and |
buffers using a bidirectional data bus. The TRIS I/O control registers are |
134,58 → 134,10
Status |
------ |
|
Design and initial verification is complete. Verification using ISim, MPLAB, |
Design and verification is complete. Verification performed using ISim, MPLAB, |
and a board with an XC3S200AN-4VQG100I FPGA, various oscillators, SEEPROMs, |
and RS-232/RS-485 transceivers is underway. |
and RS-232/RS-485 transceivers. |
|
In circuit testing of the M16C5x soft-core microcomputer has demonstrated that |
the M16C5x can operate to **147.4560 MHz**. At this internal system clock |
frequency, a 10x multiplication of the external reference oscillator, the SPI |
shift clock divider must be set to divide the system clock by 4, which |
generates an SPI shift clock frequency of 36.864 MHz. Various combinations of |
the DCM multiplier have been generated at tested in the XC3S200A-4VQG100I |
FPGA. The following table shows the system clock frequencies tested, the SPI |
shift clock frequencies tested, and the maximum achievable standard UART bit |
rate: |
|
DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz) |
4x 58.9824 29.4912 3.6864 |
5x 73.7280 36.8640 0.9216 |
6x 88.4736 44.2368 0.9216 |
6.5x 95.8464 47.9232 0.4608 |
7x 103.2192 51.6096 0.9216 |
7.5x 110.5920 55.2960 0.4608 |
8x 117.9648 58.9824 7.3728 |
8.5x 125.3376 62.6688 0.4608 |
10x 147.4560 36.8640 1.8432 |
|
These results are only applicable to this particular configuration. The period |
constraint for the system clock is set for 12.5 ns, or 80 MHz. The |
relationship between the clock enable, 0.5 of the system clock, does not seem |
to be accomodated by the reported performance values. Further investigation is |
needed to establish if the results provided in the previous table should be |
accepted as the performance limits of the M16C5x core in this FPGA family. |
|
A board has been configured with an XC3S50A-4VQG100I components, and it |
operates as expected at 80 MHz. A new internal resource configuration makes |
the UART clock, Clk_UART, a fixed output of the DCM. The UART clock is fixed |
at 2x ClkIn, or as is the case in this test configuration, 29.4912 MHz. |
|
Testing like that performed above with the XC3S200A-4VQG100I is shown below. |
It indicates that the upper operating frequency is limited to **140.0832 |
MHz**. This upper limit is most likely imposed by the reduction in routing |
resources. The utilization factor in an XC3S50A-4VQG100I FPGA is **99%**, and _~50%_ |
in an XC3S200A-4VQG100I FPGA. The larger number of LUTs/Slices and routing |
resources allows Map and Place greater flexibility to satisfy the timing |
constraints. |
|
DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz) |
4x 58.9824 29.4912 1.8432 |
8x 117.9648 58.9824 1.8432 |
8.5x 125.3376 62.6688 1.8432 |
9x 132.7104 66.3552 1.8432 |
9.5x 140.0832 70.0461 1.8432 |
|
Release Notes |
------------- |
|
326,3 → 278,12
P16C5x, by using wired-OR bus connections rather than explicit multiplexers. |
These improvements also provided some reductions in the resource utilization |
of the project. |
|
####Release 2.5.1 |
|
Modified the BMM file to allow the MEM file data fields to be represented in |
natural order. In other words, unlike the previous release, the most |
significant nibble is the first (leftmost) character of each data word, and |
the least significant nibble is the last (rightmost) character in a data word. |
Also modified the utility provided that converts Intel Hex programming files |
into files compatible with the Xilinx Data2MEM utility program. |