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/modbus/trunk/enlace/rs232_receiver.vhd
0,0 → 1,374
-------------------------------------------------------------------------------- |
-- Company: University of Vigo |
-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda |
-- |
-- Create Date: 10:26:09 10/18/06 |
-- Design Name: |
-- Module Name: rs232_receiver - Behavioral. |
-- The parity can be selected through the signal even_odd (0: odd/impar; 1: even/par) |
-- The error flags (start_error, discrepancy_error and stop_error) keep activated only one clock cycle except the parity error flag, that holds its state |
-- until a new data is received. |
-- The busy signal keeps activated during the whole receiving process of a data (start bit, 8 data bits, parity bit and stop bit) |
-- The receive clock must have a frequency of each times faster than the baud rate |
-- The activation of "new_data" during one clock cycle indicates the arriving of a new character. |
-- Project Name: |
-- Target Device: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
-------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity rs232_receiver is |
Port ( clk : in std_logic; -- global clock |
reset : in std_logic; -- global reset |
receive_clk : in std_logic; -- this clock must have a frequency of eight times faster than the baud rate |
even_odd: in std_logic; -- it selects the desired parity (0: odd/impar; 1: even/par) |
rxd : in std_logic; -- The RS232 RXD line |
data_out : out std_logic_vector(7 downto 0); -- The data received, in parallel |
parity_error : out std_logic; -- it indicates a parity error in the received data |
start_error : out std_logic; -- it indicates an error in the start bit (false start). The receiver will wait for a new complete start bit |
stop_error : out std_logic; -- it indicates an error in the stop bit (though the data could have been received correctly and it is presented at the outputs). |
discrepancy_error: out std_logic; -- it indicates an error because the three samples of the same bit have different values. |
busy : out std_logic; -- it indicates that the receiver is busy receiving one character |
new_data : out std_logic); -- it indicates that the receiving process has ended and a new character is available |
end rs232_receiver; |
|
architecture Behavioral of rs232_receiver is |
|
-- Component declaration |
|
-- 9 bits shift register declaration |
COMPONENT shift9_r |
PORT( |
clk : IN std_logic; |
reset : IN std_logic; |
msb_in : IN std_logic; |
shift_enable : IN std_logic; |
q_shift : OUT std_logic_vector(8 downto 0) |
); |
END COMPONENT; |
|
-- BCD counter declaration. This is the bit counter |
COMPONENT ctr_bcd |
PORT( |
clk : IN std_logic; |
reset : IN std_logic; |
sync_reset : IN std_logic; |
gctr : IN std_logic; |
qctr : OUT std_logic_vector(3 downto 0); |
ctr_eq_9 : OUT std_logic |
); |
END COMPONENT; |
|
-- Receiver clock counter declaration. This is the counter for the "receive_clock" cycles |
COMPONENT ctr_receiver_clock |
PORT( |
clk : IN std_logic; |
reset : IN std_logic; |
sync_reset : IN std_logic; |
gctr : IN std_logic; |
ctr_eq_2 : OUT std_logic; |
ctr_eq_4 : OUT std_logic; |
ctr_eq_6 : OUT std_logic; |
ctr_eq_8 : OUT std_logic; |
qctr : OUT std_logic_vector(3 downto 0) |
); |
END COMPONENT; |
|
-- Voting circuit declaration |
COMPONENT voting_circuit_2_of_3 |
PORT( |
clk : IN std_logic; |
reset : IN std_logic; |
load_sample_1 : IN std_logic; |
load_sample_2 : IN std_logic; |
load_sample_3 : IN std_logic; |
bit_input : IN std_logic; |
sampled_bit : OUT std_logic; |
discrepancy : OUT std_logic |
); |
END COMPONENT; |
|
-- Receiver control state machine declaration |
COMPONENT rx_ctrl |
PORT( |
CLK : IN std_logic; |
ctr_bits_eq_9 : IN std_logic; |
last_sample : IN std_logic; |
RESET : IN std_logic; |
fd_rxd : IN std_logic; |
sampled_bit : IN std_logic; |
incr_ctr_bits : OUT std_logic; |
ld_parity_error : OUT std_logic; |
load_data : OUT std_logic; |
load_discrepancy : OUT std_logic; |
new_data : OUT std_logic; |
reset_busy : OUT std_logic; |
reset_capture : OUT std_logic; |
reset_ctr_bits : OUT std_logic; |
reset_ctr_clock : OUT std_logic; |
rst_ce_ctr_clock : OUT std_logic; |
rst_discrepancy : OUT std_logic; |
set_busy : OUT std_logic; |
set_capture : OUT std_logic; |
set_ce_ctr_clock : OUT std_logic; |
shift_enable : OUT std_logic; |
start_error : OUT std_logic; |
stop_error : OUT std_logic |
); |
END COMPONENT; |
|
-- Signals declaration |
-- Edge detector for receive_clk |
signal receive_clk_t_1 , receive_clk_s, fa_receive_clk, fd_receive_clk: std_logic; |
|
-- Shift register |
signal shift_enable: std_logic; |
signal q_shift : std_logic_vector(8 downto 0); |
|
-- BCD counter |
signal reset_ctr_bits, incr_ctr_bits, ctr_bits_eq_9: std_logic; |
signal q_ctr_bits: std_logic_vector (3 downto 0); |
|
-- Receiver clock cycles counter |
signal reset_ctr_clock, incr_ctr_clock, ctr_clock_eq_2, ctr_clock_eq_4, ctr_clock_eq_6, ctr_clock_eq_8: std_logic; |
signal q_ctr_clock: std_logic_vector (3 downto 0); |
|
-- Busy register |
signal set_busy, reset_busy: std_logic; |
|
-- Parity error register |
signal load_parity_error, parity_error_aux: std_logic; |
|
-- Synchonization register and edge detector for RXD line |
signal rxd_s, rxd_t_1, fd_rxd: std_logic; |
|
-- Capture samples register |
signal reset_capture, set_capture, capture_samples: std_logic; |
|
-- Enable receive clock counter register |
signal reset_ce_ctr_clock, set_ce_ctr_clock, ce_ctr_clock: std_logic; |
|
-- Voting circuit for rxd samples |
signal load_sample_1, load_sample_2, load_sample_3, sampled_bit, discrepancy: std_logic; |
|
-- Discrepancy error register |
signal load_discrepancy_error, reset_discrepancy_error: std_logic; |
|
-- Data received register |
signal load_data: std_logic; |
|
-- Receiver control state machine |
signal last_sample: std_logic; |
|
begin |
|
-- Edge detector for receive_clk |
process (reset,clk,receive_clk_s,receive_clk_t_1) |
begin |
if reset = '1' then receive_clk_s <= '0'; |
receive_clk_t_1 <= '0'; |
elsif clk = '1' and clk'event then receive_clk_t_1 <= receive_clk_s; |
receive_clk_s <= receive_clk; |
end if; |
|
fa_receive_clk <= receive_clk_s and not receive_clk_t_1; |
fd_receive_clk <= not receive_clk_s and receive_clk_t_1; |
end process; |
|
-- Synchonization register and edge detector for RXD line |
process (reset,clk,rxd_s,rxd_t_1) |
begin |
if reset = '1' then rxd_s <= '1'; |
rxd_t_1 <= '1'; |
elsif clk = '1' and clk'event then rxd_t_1 <= rxd_s; |
rxd_s <= rxd; |
end if; |
|
-- fa_rxd <= rxd_s and not rxd_t_1; |
fd_rxd <= not rxd_s and rxd_t_1; |
end process; |
|
-- Busy register |
Busy_register: process (clk, reset, reset_busy, set_busy) |
begin |
if reset = '1' then |
busy <= '0'; |
elsif clk'event and clk ='1' then |
if reset_busy = '1' then busy <= '0'; |
elsif set_busy ='1' then busy <= '1'; |
end if; |
end if; |
end process; |
|
-- Capture samples register |
Capture_register: process (clk, reset, reset_capture, set_capture) |
begin |
if reset = '1' then |
capture_samples <= '0'; |
elsif clk'event and clk ='1' then |
if reset_capture = '1' then capture_samples <= '0'; |
elsif set_capture ='1' then capture_samples <= '1'; |
end if; |
end if; |
end process; |
|
-- Enable receive clock counter register |
Enable_receive_clock_counter_register: process (clk, reset, reset_ce_ctr_clock, set_ce_ctr_clock) |
begin |
if reset = '1' then |
ce_ctr_clock <= '0'; |
elsif clk'event and clk ='1' then |
if reset_ce_ctr_clock = '1' then ce_ctr_clock <= '0'; |
elsif set_ce_ctr_clock ='1' then ce_ctr_clock <= '1'; |
end if; |
end if; |
end process; |
|
-- Parity error register |
Parity_error_register: process (clk, reset, load_parity_error) |
begin |
if reset = '1' then |
parity_error <= '0'; |
elsif clk'event and clk ='1' then |
if load_parity_error = '1' then parity_error <= parity_error_aux; |
end if; |
end if; |
end process; |
|
-- Parity calculator |
parity_calculator: process(even_odd, q_shift) |
begin |
if even_odd = '0' then -- odd parity (the 9 bits has an odd number of ones) |
-- 9 bits XNOR. If it is 1, there is an error because there is an even number of ones |
parity_error_aux <= not (q_shift(8) xor q_shift(7) xor q_shift(6) xor q_shift(5) xor q_shift(4) xor q_shift(3) xor q_shift(2) xor q_shift(1) xor q_shift(0)); |
|
elsif even_odd = '1' then -- even parity (the 9 bits has an even number of ones) |
-- 9 bits XOR. If it is 1, there is an error because there is an odd number of ones |
parity_error_aux <= q_shift(8) xor q_shift(7) xor q_shift(6) xor q_shift(5) xor q_shift(4) xor q_shift(3) xor q_shift(2) xor q_shift(1) xor q_shift(0); |
end if; |
end process; |
|
-- Discrepancy error register |
Discrepancy_error_register: process (clk, reset, load_discrepancy_error) |
begin |
if reset = '1' then |
discrepancy_error <= '0'; |
elsif clk'event and clk ='1' then |
if reset_discrepancy_error = '1' then discrepancy_error <= '0'; |
elsif load_discrepancy_error = '1' then discrepancy_error <= discrepancy; |
end if; |
end if; |
end process; |
|
|
-- Data received register |
Data_received_register: process (clk, reset, load_data) |
begin |
if reset = '1' then |
data_out <= "00000000"; |
elsif clk'event and clk ='1' then |
if load_data = '1' then data_out <= q_shift (7 downto 0); |
end if; |
end if; |
end process; |
|
|
-- Component instantiation |
|
-- 9 bits shift register instantiation |
Inst_shift9_r: shift9_r PORT MAP( |
clk => clk, |
reset => reset, |
msb_in => sampled_bit, |
shift_enable => shift_enable, |
q_shift => q_shift |
); |
|
-- BCD counter instantiation. This is the bit counter |
Inst_ctr_bcd: ctr_bcd PORT MAP( |
clk => clk, |
reset => reset, |
sync_reset => reset_ctr_bits, |
gctr => incr_ctr_bits, |
qctr => q_ctr_bits, |
ctr_eq_9 => ctr_bits_eq_9 |
); |
|
-- Receiver clock counter instantiation. This is the counter for the "receive_clock" cycles |
Inst_ctr_receiver_clock: ctr_receiver_clock PORT MAP( |
clk => clk, |
reset => reset, |
sync_reset => reset_ctr_clock, |
ctr_eq_2 => ctr_clock_eq_2, |
ctr_eq_4 => ctr_clock_eq_4, |
ctr_eq_6 => ctr_clock_eq_6, |
ctr_eq_8 => ctr_clock_eq_8, |
gctr => incr_ctr_clock, |
qctr => q_ctr_clock |
); |
|
-- Increment order for receiver clock counter |
incr_ctr_clock <= ce_ctr_clock and fa_receive_clk; |
|
-- Voting circuit instantiation |
Inst_voting_circuit_2_of_3: voting_circuit_2_of_3 PORT MAP( |
clk => clk, |
reset => reset, |
load_sample_1 => load_sample_1, |
load_sample_2 => load_sample_2, |
load_sample_3 => load_sample_3, |
bit_input => rxd_s, |
sampled_bit => sampled_bit, |
discrepancy => discrepancy |
); |
|
-- Capture sample orders for voting circuit |
load_sample_1 <= fd_receive_clk and ctr_clock_eq_2 and capture_samples; |
load_sample_2 <= fd_receive_clk and ctr_clock_eq_4 and capture_samples; |
load_sample_3 <= fd_receive_clk and ctr_clock_eq_6 and capture_samples; |
last_sample <= fd_receive_clk and ctr_clock_eq_6; |
|
-- Receiver control state machine instantiation |
Inst_rx_ctrl: rx_ctrl PORT MAP( |
CLK => clk, |
ctr_bits_eq_9 => ctr_bits_eq_9, |
last_sample => last_sample, |
RESET => reset, |
fd_rxd => fd_rxd, |
sampled_bit => sampled_bit, |
incr_ctr_bits => incr_ctr_bits, |
ld_parity_error => load_parity_error, |
load_data => load_data, |
load_discrepancy => load_discrepancy_error, |
new_data => new_data, |
reset_busy => reset_busy, |
reset_capture => reset_capture, |
reset_ctr_bits => reset_ctr_bits, |
reset_ctr_clock => reset_ctr_clock, |
rst_ce_ctr_clock => reset_ce_ctr_clock, |
rst_discrepancy => reset_discrepancy_error, |
set_busy => set_busy, |
set_capture => set_capture, |
set_ce_ctr_clock => set_ce_ctr_clock, |
shift_enable => shift_enable, |
start_error => start_error, |
stop_error => stop_error |
); |
|
end Behavioral; |
modbus/trunk/enlace/rs232_receiver.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/uart_TB.vhd
===================================================================
--- modbus/trunk/enlace/uart_TB.vhd (nonexistent)
+++ modbus/trunk/enlace/uart_TB.vhd (revision 3)
@@ -0,0 +1,293 @@
+
+-- VHDL Test Bench Created from source file uart_rs232.vhd -- 21:28:36 07/21/2010
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY uart_rs232_uart_TB_vhd_tb IS
+END uart_rs232_uart_TB_vhd_tb;
+
+ARCHITECTURE behavior OF uart_rs232_uart_TB_vhd_tb IS
+
+ COMPONENT uart_rs232
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ send_data : IN std_logic;
+ data_in : IN std_logic_vector(7 downto 0);
+ even_odd : IN std_logic;
+ rxd : IN std_logic;
+ txd : OUT std_logic;
+ transmitter_busy : OUT std_logic;
+ send_done : OUT std_logic;
+ data_out : OUT std_logic_vector(7 downto 0);
+ parity_error : OUT std_logic;
+ start_error : OUT std_logic;
+ stop_error : OUT std_logic;
+ discrepancy_error : OUT std_logic;
+ receiver_busy : OUT std_logic;
+ new_data : OUT std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ SIGNAL reset : std_logic;
+ SIGNAL send_data : std_logic;
+ SIGNAL data_in : std_logic_vector(7 downto 0);
+ SIGNAL even_odd : std_logic;
+ SIGNAL rxd : std_logic;
+ SIGNAL txd : std_logic:='1';
+ SIGNAL transmitter_busy : std_logic;
+ SIGNAL send_done : std_logic;
+ SIGNAL data_out : std_logic_vector(7 downto 0);
+ SIGNAL parity_error : std_logic;
+ SIGNAL start_error : std_logic;
+ SIGNAL stop_error : std_logic;
+ SIGNAL discrepancy_error : std_logic;
+ SIGNAL receiver_busy : std_logic;
+ SIGNAL new_data : std_logic;
+
+
+ signal comiezo : std_logic_vector(7 downto 0):= "01010101";
+ signal segundo : std_logic_vector(7 downto 0):= "11100111";
+ signal dospuntos : std_logic_vector(7 downto 0):= "00111010"; --: ascii
+ signal cero : std_logic_vector(7 downto 0):= "00110000"; --0 ascii
+ signal siete : std_logic_vector(7 downto 0):="00110111"; --7 ascii
+ signal uno : std_logic_vector(7 downto 0):="00110001"; --1 ascii
+ signal ocho :std_logic_vector(7 downto 0):= "00111000"; --8 ascii
+ signal la_a :std_logic_vector(7 downto 0):= "01000001"; --A ascii
+ signal cinco :std_logic_vector(7 downto 0):= "00110101"; --5 ascii
+ signal la_f :std_logic_vector(7 downto 0):= "01000110"; --F ascii
+ signal cr :std_logic_vector(7 downto 0):= "00001101"; --CR ascii
+ signal lf :std_logic_vector(7 downto 0):= "00001010"; --LF ascii
+
+
+
+ -- Clock period definitions
+ constant clk_period : time := 20ns;
+
+
+BEGIN
+
+ uut: uart_rs232 PORT MAP(
+ clk => clk,
+ reset => reset,
+ send_data => send_data,
+ data_in => data_in,
+ even_odd => even_odd,
+ rxd => rxd,
+ txd => txd,
+ transmitter_busy => transmitter_busy,
+ send_done => send_done,
+ data_out => data_out,
+ parity_error => parity_error,
+ start_error => start_error,
+ stop_error => stop_error,
+ discrepancy_error => discrepancy_error,
+ receiver_busy => receiver_busy,
+ new_data => new_data
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+
+ wait for 100ns;
+ reset <= '1';
+ send_data <='0';
+ data_in <= "00000000";
+ even_odd <= '1';
+ wait for 100ns;
+ reset <= '0';
+
+--trama 1
+ wait for 300us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= comiezo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+--trama 2
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= segundo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dos puntos
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dospuntos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire bajo 7 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= siete(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama función alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama función bajo 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= uno(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama dato1 alto 8 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= ocho(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato1 bajo A ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_a(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 alto 5 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 bajo f ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_f(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama cr
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cr(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lf
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= lf(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ data_in <= "10101101";
+ wait for 200us;
+ send_data <= '1';
+ wait for 120us;
+ send_data <= '0';
+
+
+
+ wait; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
modbus/trunk/enlace/uart_TB.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/ctr_bcd.vhd
===================================================================
--- modbus/trunk/enlace/ctr_bcd.vhd (nonexistent)
+++ modbus/trunk/enlace/ctr_bcd.vhd (revision 3)
@@ -0,0 +1,62 @@
+------------------------------------------------------------------
+-- ctr_bcd.vhd --
+-- BCD counter
+------------------------------------------------------------------
+-- Luis Jacobo Alvarez Ruiz de Ojeda
+-- Dpto. Tecnologia Electronica
+-- University of Vigo
+-- 24, March, 2006
+------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity ctr_bcd is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ sync_reset : in std_logic;
+ gctr : in std_logic;
+ qctr : out std_logic_vector(3 downto 0);
+ ctr_eq_9 : out std_logic);
+end ctr_bcd;
+
+architecture Behavioral of ctr_bcd is
+
+------------------------------------------------------------------
+-- Signal Declarations and Constants
+------------------------------------------------------------------
+signal qctr_aux: std_logic_vector (3 downto 0);
+
+begin
+
+-- Outputs assignment
+qctr <= qctr_aux;
+
+process (clk, reset, gctr, qctr_aux)
+begin
+ if (reset ='1') then
+ -- Counter initialization
+ qctr_aux <= "0000";
+ elsif (clk'event and clk='1') then
+ if sync_reset = '1' then
+ qctr_aux <= "0000";
+ elsif (gctr='1') then
+ if qctr_aux = 9 then
+ qctr_aux <= "0000";
+ else
+ -- Increment counter
+ qctr_aux <= qctr_aux + 1;
+ end if;
+ end if;
+ end if;
+
+ if qctr_aux = 9 then
+ -- Last state
+ ctr_eq_9 <= '1';
+ else ctr_eq_9 <='0';
+ end if;
+end process;
+
+end Behavioral;
modbus/trunk/enlace/ctr_bcd.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/shift9_LR.vhd
===================================================================
--- modbus/trunk/enlace/shift9_LR.vhd (nonexistent)
+++ modbus/trunk/enlace/shift9_LR.vhd (revision 3)
@@ -0,0 +1,76 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 17:58:19 10/17/06
+-- Design Name:
+-- Module Name: shift9_LR - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description: 9 bits shift register with parallel load of the 8 least significant bits, independent load
+-- for the 9th bit, shift_enable control signal and right shifting (through LSB output).
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity shift9_LR is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ load_8_lsb_bits : in std_logic;
+ load_msb_bit : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ msb_in: in std_logic;
+ shift_enable : in std_logic;
+ q_shift: out std_logic_vector(8 downto 0);
+ lsb_out : out std_logic
+ );
+end shift9_LR;
+
+architecture Behavioral of shift9_LR is
+
+signal q_shift_aux: std_logic_vector (8 downto 0);
+
+begin
+
+-- Signal assignment
+q_shift <= q_shift_aux;
+
+process (clk, reset, load_8_lsb_bits, load_msb_bit, shift_enable, q_shift_aux)
+begin
+ if reset ='1' then
+ q_shift_aux <= "000000000";
+ elsif clk'event and clk='1' then
+ if shift_enable = '0' then
+
+ if load_8_lsb_bits = '1' then
+ q_shift_aux (7 downto 0) <= data_in;
+ end if;
+
+ if load_msb_bit = '1' then
+ q_shift_aux (8) <= msb_in;
+ end if;
+
+ else
+ q_shift_aux <= '0' & q_shift_aux (8 downto 1);
+ end if;
+ end if;
+lsb_out <= q_shift_aux (0);
+
+end process;
+
+end Behavioral;
modbus/trunk/enlace/shift9_LR.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/contro_ram.vhd
===================================================================
--- modbus/trunk/enlace/contro_ram.vhd (nonexistent)
+++ modbus/trunk/enlace/contro_ram.vhd (revision 3)
@@ -0,0 +1,82 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity contro_ram is
+ generic(
+ addr_bits : integer := 8); -- 2^addr_bits = numero bits de direccionamiento
+ port(
+--entradas y salidas de la RAM
+ clk :in std_logic;
+ reset :in std_logic;
+ Eram :out std_logic;
+ Eram_write :out std_logic;
+ ram_addr :out std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram :out std_logic_vector(7 downto 0);
+ data_out_ram :in std_logic_vector(7 downto 0);
+--entradas y salidas del pico blaze
+ Eram_picoB :in std_logic;
+ WEram_picoB :in std_logic;
+ addr_picoB :in std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram_picoB:in std_logic_vector(7 downto 0);
+ data_out_ram_picoB:out std_logic_vector(7 downto 0);
+--entradas y salidas del componente detector
+ Eram_det :in std_logic;
+ Eram_write_det :in std_logic;
+ ram_addr_det :in std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram_det:in std_logic_vector(7 downto 0);
+--entradas y salidas del componente generador trama
+ E_ram_gen :in std_logic;
+ WE_ram_gen :in std_logic;
+ addr_ram_gen :in std_logic_vector(addr_bits-1 downto 0);
+ data_out_ram_gen:out std_logic_vector(7 downto 0)
+ );
+end contro_ram;
+
+architecture Behavioral of contro_ram is
+
+--signal Senable_ram : std_logic_vector (2 downto 0):="000";
+begin
+
+--Senable_ram <= Eram_det & E_ram_gen & Eram_picoB;
+
+enable_ram: process(clk, Eram_det,E_ram_gen,Eram_picoB)
+variable Venable_ram : std_logic_vector (2 downto 0):="000";
+begin
+Venable_ram := Eram_det & E_ram_gen & Eram_picoB;
+if clk'event and clk = '1' then
+ case (Venable_ram) is
+-- case (Senable_ram) is
+ when "001" =>
+ Eram <= Eram_picoB;
+ Eram_write <= WEram_picoB;
+ ram_addr <= addr_picoB;
+ data_in_ram <= data_in_ram_picoB;
+ data_out_ram_picoB <= data_out_ram;
+ when "010" =>
+ Eram <= E_ram_gen;
+ Eram_write <= WE_ram_gen;
+ ram_addr <= addr_ram_gen;
+ data_in_ram <= (others=>'0');
+ data_out_ram_gen <= data_out_ram;
+ when "100" =>
+ Eram <= Eram_det;
+ Eram_write <= Eram_write_det;
+ ram_addr <= ram_addr_det;
+ data_in_ram <= data_in_ram_det;
+ when others =>
+ Eram <= '0';
+ Eram_write <= '0';
+ ram_addr <= (others=>'0');
+ data_in_ram <= (others=>'0');
+ end case;
+end if;
+end process;
+
+end Behavioral;
modbus/trunk/enlace/contro_ram.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/bin2ascii_pkg.vhd
===================================================================
--- modbus/trunk/enlace/bin2ascii_pkg.vhd (nonexistent)
+++ modbus/trunk/enlace/bin2ascii_pkg.vhd (revision 3)
@@ -0,0 +1,61 @@
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package bin2ascii_pkg is
+
+
+ type is
+ record
+ : std_logic_vector( 7 downto 0);
+ : std_logic;
+ end record;
+
+-- Declare constants
+
+ constant : time := ns;
+ constant : integer := ;
+
+-- Declare functions and procedure
+
+ function (signal : in ) return ;
+ procedure ( : in );
+
+end bin2ascii_pkg;
+
+
+package body is
+
+-- Example 1
+ function (signal : in ) return is
+ variable : ;
+ begin
+ := xor );
+ return ;
+ end ;
+
+
+-- Example 2
+ function (signal : in ;
+ signal : in ) return is
+ begin
+ if ( = '1') then
+ return ;
+ else
+ return 'Z';
+ end if;
+ end ;
+
+-- Procedure Example
+ procedure ( : in ) is
+
+ begin
+
+ end ;
+
+end bin2ascii_pkg;
modbus/trunk/enlace/bin2ascii_pkg.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/bin_ascii_TB.vhd
===================================================================
--- modbus/trunk/enlace/bin_ascii_TB.vhd (nonexistent)
+++ modbus/trunk/enlace/bin_ascii_TB.vhd (revision 3)
@@ -0,0 +1,69 @@
+
+-- VHDL Test Bench Created from source file bin_ascii.vhd -- 14:56:18 11/03/2010
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY bin_ascii_bin_ascii_TB_vhd_tb IS
+END bin_ascii_bin_ascii_TB_vhd_tb;
+
+ARCHITECTURE behavior OF bin_ascii_bin_ascii_TB_vhd_tb IS
+
+ COMPONENT bin_ascii
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ bin : IN std_logic_vector(7 downto 0);
+ ascii_h : OUT std_logic_vector(7 downto 0);
+ ascii_l : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ SIGNAL reset : std_logic;
+ SIGNAL bin : std_logic_vector(7 downto 0);
+ SIGNAL ascii_h : std_logic_vector(7 downto 0);
+ SIGNAL ascii_l : std_logic_vector(7 downto 0);
+ -- Clock period definitions
+ constant clk_period : time := 20ns;
+
+
+BEGIN
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ uut: bin_ascii PORT MAP(
+ clk => clk,
+ reset => reset,
+ bin => bin,
+ ascii_h => ascii_h,
+ ascii_l => ascii_l
+ );
+
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+ reset <= '1';
+ wait for 100ns;
+ reset <= '0';
+ wait for 100ns;
+-- bin <= "11101110"; -- hex
+ wait; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
modbus/trunk/enlace/bin_ascii_TB.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/uart_rs232.vhd
===================================================================
--- modbus/trunk/enlace/uart_rs232.vhd (nonexistent)
+++ modbus/trunk/enlace/uart_rs232.vhd (revision 3)
@@ -0,0 +1,208 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 17:27:44 10/18/06
+-- Design Name:
+-- Module Name: uart_rs232 - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+
+-- TRANSMITTER:
+-- The transmitter_busy signal keeps activated during the whole transmitting process of a data (start bit, 8 data bits, parity bit and stop bit)
+-- The activation of "send_data" during one "clk" clock cycle orders this circuit to capture the character present
+-- at the "data_in" inputs and to send it through the RS232 TXD line
+-- The activation of the "send_done" signal during one "clk" clock cycle indicates that the character has been sent
+
+-- RECEIVER:
+-- The error flags for the received data (start_error, discrepancy_error and stop_error) keep activated only one clock cycle except the parity error flag, that holds its state
+-- until a new data is received.
+-- The receiver_busy signal keeps activated during the whole receiving process of a data (start bit, 8 data bits, parity bit and stop bit)
+
+-- The activation of "new_data" during one clock cycle indicates the arriving of a new character.
+
+-- BOTH TRANSMITTER AND RECEIVER
+-- The uart_clock must have a frequency of eight times faster than the desired baud rate
+-- The parity can be selected through the signal even_odd (0: odd/impar; 1: even/par)
+
+-- CLOCK DIVIDER
+-- The use of a counter to generate the output clock makes the first period of the output clock only 7 times slower, because
+-- the first time, the counter counts from 0 to 3 (3 cycles) and the following times it counts from 3 to 3 (4 cycles)
+-- This is not important, since the UART detects the rising edges of this output clock and
+-- there are always 8 input clock cycles between two consecutive output clock rising edges.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity uart_rs232 is
+ Port ( clk : in std_logic; -- global clock
+ reset : in std_logic; -- global reset
+-- uart_clk : in std_logic; -- this clock must have a frequency of each times faster than the desired baud rate
+ send_data : in std_logic; -- this signal orders to send the data present at the data_in inputs through the TXD line
+ data_in : in std_logic_vector(7 downto 0); -- data to be sent
+ even_odd: in std_logic; -- it selects the desired parity (0: odd/impar; 1: even/par)
+ rxd : in std_logic; -- The RS232 RXD line
+ txd : out std_logic; -- The RS232 TXD line
+ transmitter_busy : out std_logic; -- it indicates that the transmitter is busy sending one character
+ send_done : out std_logic; -- it indicates that the character has been sent
+ data_out : out std_logic_vector(7 downto 0); -- The data received, in parallel
+ parity_error : out std_logic; -- it indicates a parity error in the received data
+ start_error : out std_logic; -- it indicates an error in the start bit (false start) of the received data. The receiver will wait for a new complete start bit
+ stop_error : out std_logic; -- it indicates an error in the stop bit of the received data (though the data could have been received correctly and it is presented at the outputs).
+ discrepancy_error: out std_logic; -- it indicates an error because the three samples of the same bit of the data being currently received have different values.
+ receiver_busy : out std_logic; -- it indicates that the receiver is busy receiving one character
+ new_data : out std_logic -- it indicates that the receiving process has ended and a new character is available
+ );
+end uart_rs232;
+
+architecture Behavioral of uart_rs232 is
+
+-- Component declaration
+
+-- RS232 transmitter declaration
+ COMPONENT rs232_transmitter
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ send_clk : IN std_logic;
+ send_data : IN std_logic;
+ data_in : IN std_logic_vector(7 downto 0);
+ even_odd : IN std_logic;
+ txd : OUT std_logic;
+ busy : OUT std_logic;
+ send_done : OUT std_logic
+ );
+ END COMPONENT;
+
+-- RS232 receiver declaration
+ COMPONENT rs232_receiver
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ receive_clk : IN std_logic;
+ even_odd : IN std_logic;
+ rxd : IN std_logic;
+ data_out : OUT std_logic_vector(7 downto 0);
+ parity_error : OUT std_logic;
+ start_error : OUT std_logic;
+ stop_error : OUT std_logic;
+ discrepancy_error : OUT std_logic;
+ busy : OUT std_logic;
+ new_data : OUT std_logic
+ );
+ END COMPONENT;
+
+-- Clock divider for transmitter declaration
+ COMPONENT divider8_uart
+ PORT(
+ clk_in : IN std_logic;
+ reset : IN std_logic;
+ clk_out_8_times_slow : OUT std_logic
+ );
+ END COMPONENT;
+
+-- Divisor de clock de la placa 50 Mhz
+ COMPONENT clock_generator_for_uart_rs232
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ uart_clk : out std_logic);
+ END COMPONENT;
+
+-- Signals declaration
+
+-- Transmitter
+signal send_clk: std_logic;
+-- Receiver
+signal receive_clk: std_logic;
+
+-- el clk en función de la velocidad
+signal uart_clk: std_logic;
+
+-- discriminadorde pulso
+signal Q1, Q2, Q3 : std_logic;
+signal Ssend_data : std_logic;
+
+begin
+
+-- Signals assignment
+receive_clk <= uart_clk;
+
+-- Component instantiation
+
+-- RS232 transmitter instantiation
+ Inst_rs232_transmitter: rs232_transmitter PORT MAP(
+ clk => clk,
+ reset => reset,
+ send_clk => send_clk,
+ send_data => Ssend_data,
+ data_in => data_in,
+ even_odd => even_odd,
+ txd => txd,
+ busy => transmitter_busy,
+ send_done => send_done
+ );
+
+-- RS232 receiver instantiation
+ Inst_rs232_receiver: rs232_receiver PORT MAP(
+ clk => clk,
+ reset => reset,
+ receive_clk => receive_clk,
+ even_odd => even_odd,
+ rxd => rxd,
+ data_out => data_out,
+ parity_error => parity_error,
+ start_error => start_error,
+ stop_error => stop_error,
+ discrepancy_error => discrepancy_error,
+ busy => receiver_busy,
+ new_data => new_data
+ );
+
+-- Clock divider for transmitter instantiation
+ Inst_divider8_uart: divider8_uart PORT MAP(
+ clk_in => uart_clk,
+ clk_out_8_times_slow => send_clk,
+ reset => reset
+ );
+
+-- Clock divider desde el clock general
+ Inst_clock_generator: clock_generator_for_uart_rs232 PORT MAP(
+ clk => clk,
+ uart_clk => uart_clk,
+ reset => reset
+ );
+
+-- Descripción Pulso
+process(clk)
+begin
+ if (clk'event and clk = '1') then
+ if (reset = '1') then
+ Q1 <= '0';
+ Q2 <= '0';
+ Q3 <= '0';
+ else
+ Q1 <= send_data;
+ Q2 <= Q1;
+ Q3 <= Q2;
+ end if;
+ end if;
+end process;
+Ssend_data <= Q1 and Q2 and (not Q3);
+
+end Behavioral;
modbus/trunk/enlace/uart_rs232.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/rs232_transmitter.vhd
===================================================================
--- modbus/trunk/enlace/rs232_transmitter.vhd (nonexistent)
+++ modbus/trunk/enlace/rs232_transmitter.vhd (revision 3)
@@ -0,0 +1,215 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 18:26:28 10/17/06
+-- Design Name:
+-- Module Name: rs232_transmitter - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+-- The parity can be selected through the signal even_odd (0: odd/impar; 1: even/par)
+-- The busy signal keeps activated during the whole transmitting process of a data (start bit, 8 data bits, parity bit and stop bit)
+-- The send clock must have a frequency equal to the desired baud rate
+-- The activation of "send_data" during one "clk" clock cycle orders this circuit to capture the character present
+-- at the "data_in" inputs and to send it through the RS232 TXD line
+-- The activation of the "send_done" signal during one "clk" clock cycle indicates that the character has been sent
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232_transmitter is
+ Port ( clk : in std_logic; -- global clock
+ reset : in std_logic; -- global reset
+ send_clk : in std_logic; -- this clock gives the duration of each bit in the transmission, that is, the baud rate
+ send_data : in std_logic; -- this signal orders to send the data present at the data_in inputs
+ data_in : in std_logic_vector(7 downto 0); -- data to be sent
+ even_odd: in std_logic; -- it selects the desired parity (0: odd/impar; 1: even/par)
+ txd : out std_logic; -- The RS232 TXD line
+ busy : out std_logic; -- it indicates that the transmitter is busy sending one character
+ send_done : out std_logic); -- it indicates that the sending process has ended
+end rs232_transmitter;
+
+architecture Behavioral of rs232_transmitter is
+
+-- Component declaration
+
+-- 9 bits shift register declaration
+ COMPONENT shift9_lr
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ load_8_lsb_bits : IN std_logic;
+ load_msb_bit : IN std_logic;
+ data_in : IN std_logic_vector(7 downto 0);
+ msb_in : IN std_logic;
+ shift_enable : IN std_logic;
+ q_shift : OUT std_logic_vector(8 downto 0);
+ lsb_out : OUT std_logic
+ );
+ END COMPONENT;
+
+-- BCD counter declaration
+ COMPONENT ctr_bcd
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ sync_reset : IN std_logic;
+ gctr : IN std_logic;
+ qctr : OUT std_logic_vector(3 downto 0);
+ ctr_eq_9 : OUT std_logic
+ );
+ END COMPONENT;
+
+-- Transmitter control state machine declaration
+ COMPONENT tx_ctrl
+ PORT(
+ CLK : IN std_logic;
+ ctr_eq_9 : IN std_logic;
+ fa_send_clk : IN std_logic;
+ RESET : IN std_logic;
+ send_data : IN std_logic;
+ incr_ctr : OUT std_logic;
+ load_parity_bit : OUT std_logic;
+ load_txd : OUT std_logic;
+ reset_busy : OUT std_logic;
+ reset_ctr : OUT std_logic;
+ reset_txd : OUT std_logic;
+ send_done : OUT std_logic;
+ set_busy : OUT std_logic;
+ set_txd : OUT std_logic;
+ shift_enable : OUT std_logic
+ );
+ END COMPONENT;
+
+-- Signals declaration
+-- Edge detector for send_clk
+signal send_clk_t_1 , send_clk_s, fa_send_clk: std_logic;
+
+-- Shift register
+signal parity_bit, load_parity_bit, shift_enable, lsb_out: std_logic;
+signal q_shift : std_logic_vector(8 downto 0);
+
+-- BCD counter
+signal incr_ctr, ctr_eq_9, reset_ctr: std_logic;
+signal q_ctr: std_logic_vector (3 downto 0);
+
+-- Busy register
+signal set_busy, reset_busy: std_logic;
+
+-- TXD register
+signal set_txd, reset_txd, load_txd: std_logic;
+
+begin
+
+-- Edge detector for send_clk
+process (reset,clk,send_clk_s,send_clk_t_1)
+begin
+ if reset = '1' then send_clk_s <= '0';
+ send_clk_t_1 <= '0';
+ elsif clk = '1' and clk'event then send_clk_t_1 <= send_clk_s;
+ send_clk_s <= send_clk;
+ end if;
+
+ fa_send_clk <= send_clk_s and not send_clk_t_1;
+-- fd_send_clk <= not send_clk_s and send_clk_t_1;
+end process;
+
+-- Busy register
+Busy_register: process (clk, reset, reset_busy, set_busy)
+begin
+if reset = '1' then
+ busy <= '0';
+elsif clk'event and clk ='1' then
+ if reset_busy = '1' then busy <= '0';
+ elsif set_busy ='1' then busy <= '1';
+ end if;
+end if;
+end process;
+
+-- TXD register
+TXD_register: process (clk, reset, reset_txd, set_txd)
+begin
+if reset = '1' then
+ txd <= '1';
+elsif clk'event and clk ='1' then
+ if set_txd = '1' then txd <= '1';
+ elsif reset_txd ='1' then txd <= '0';
+ elsif load_txd = '1' then txd <= lsb_out;
+ end if;
+end if;
+end process;
+
+-- Parity calculator
+parity_calculator: process(even_odd, q_shift)
+begin
+if even_odd = '0' then -- odd parity (the 9 bits has an odd number of ones)
+ -- 8 bits XNOR
+ parity_bit <= not (q_shift(7) xor q_shift(6) xor q_shift(5) xor q_shift(4) xor q_shift(3) xor q_shift(2) xor q_shift(1) xor q_shift(0));
+
+elsif even_odd = '1' then -- even parity (the 9 bits has an even number of ones)
+ -- 8 bits XOR
+ parity_bit <= q_shift(7) xor q_shift(6) xor q_shift(5) xor q_shift(4) xor q_shift(3) xor q_shift(2) xor q_shift(1) xor q_shift(0);
+end if;
+end process;
+
+-- Component instantiation
+
+-- 9 bits shift register instantiation
+ Inst_shift9_lr: shift9_lr PORT MAP(
+ clk => clk,
+ reset => reset,
+ load_8_lsb_bits => send_data,
+ load_msb_bit => load_parity_bit,
+ data_in => data_in,
+ msb_in => parity_bit,
+ shift_enable => shift_enable,
+ q_shift => q_shift,
+ lsb_out => lsb_out
+ );
+
+-- BCD counter instantiation
+ Inst_ctr_bcd: ctr_bcd PORT MAP(
+ clk => clk,
+ reset => reset,
+ sync_reset => reset_ctr,
+ gctr => incr_ctr,
+ qctr => q_ctr,
+ ctr_eq_9 => ctr_eq_9
+ );
+
+-- Transmitter control state machine instantiation
+ Inst_tx_ctrl: tx_ctrl PORT MAP(
+ CLK => clk,
+ ctr_eq_9 => ctr_eq_9,
+ fa_send_clk => fa_send_clk,
+ RESET => reset,
+ send_data => send_data,
+ incr_ctr => incr_ctr,
+ load_parity_bit => load_parity_bit,
+ load_txd => load_txd,
+ reset_busy => reset_busy,
+ reset_ctr => reset_ctr,
+ reset_txd => reset_txd,
+ send_done => send_done,
+ set_busy => set_busy,
+ set_txd => set_txd,
+ shift_enable => shift_enable
+ );
+
+end Behavioral;
modbus/trunk/enlace/rs232_transmitter.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/gen_lrc.vhd
===================================================================
--- modbus/trunk/enlace/gen_lrc.vhd (nonexistent)
+++ modbus/trunk/enlace/gen_lrc.vhd (revision 3)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity gen_lrc is
+ port(
+ clk :in std_logic; --clk
+ reset :in std_logic; --reset
+ new_data :in std_logic; --nuevo valor a leer
+ trama :in std_logic; --suma válida
+ dato_trama:in std_logic_vector(7 downto 0); --dato desde la ram
+ lrc_bin :out std_logic_vector(7 downto 0));--valor del lrc calculado
+end gen_lrc;
+
+architecture Behavioral of gen_lrc is
+signal acumulador :std_logic_vector(7 downto 0):=(others=>'0');
+begin
+SUMADOR:process (clk)
+begin
+ if reset='1' then
+ acumulador <= (others => '0');
+ elsif (clk'event and clk='1') then
+ if new_data='1' and trama = '1' then --tener presente que data_ok debe permanecer SOLO 1 clk
+ acumulador <= acumulador + dato_trama;
+ end if;
+ end if;
+end process SUMADOR;
+lrc_bin <= (not acumulador + 1) when trama = '0' else
+ "00000000";
+end Behavioral;
modbus/trunk/enlace/gen_lrc.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/divider8_uart.vhd
===================================================================
--- modbus/trunk/enlace/divider8_uart.vhd (nonexistent)
+++ modbus/trunk/enlace/divider8_uart.vhd (revision 3)
@@ -0,0 +1,50 @@
+------------------------------------------------------------------
+-- divider8_uart.vhd --
+-- This circuit generates a clock signal with a frequency 8 times slower
+-- than the input clock frequency.
+-- The use of a counter to generate the output clock makes the first period of the output clock only 7 times slower, because
+-- the first time, the counter counts from 0 to 3 (3 cycles) and the following times it counts from 3 to 3 (4 cycles)
+-- This is not important, since the UART detects the rising edges of this output clock and
+-- there are always 8 input clock cycles between two consecutive output clock rising edges.
+
+------------------------------------------------------------------
+-- Luis Jacobo Alvarez Ruiz de Ojeda
+-- Dpto. Tecnologia Electronica
+-- University of Vigo
+-- 18, October, 2006
+------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity divider8_uart is
+ Port ( clk_in : in std_logic;
+ clk_out_8_times_slow : out std_logic;
+ reset: in std_logic
+ );
+end divider8_uart;
+
+architecture Behavioral of divider8_uart is
+signal count: integer range 0 to 3;
+signal clk_out_aux: std_logic;
+
+begin
+
+clk_out_8_times_slow <= clk_out_aux;
+
+process (reset, clk_in, count, clk_out_aux)
+begin
+ if reset = '1' then clk_out_aux <='0';
+ count <= 0;
+ elsif (clk_in='1' and clk_in'event) then
+ if count = 3 then clk_out_aux <= not clk_out_aux;
+ count <= 0;
+ else count <= count+1;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
modbus/trunk/enlace/divider8_uart.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/top_enlace.vhd
===================================================================
--- modbus/trunk/enlace/top_enlace.vhd (nonexistent)
+++ modbus/trunk/enlace/top_enlace.vhd (revision 3)
@@ -0,0 +1,434 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_enlace is
+ generic ( bits : integer := 8; -- ancho de datos de la memoria
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ Port (
+--nexys2
+ Led : out std_logic_vector (7 downto 0);
+ an : out std_logic_vector (3 downto 0);
+
+-- analizar lógico
+ canalA :out std_logic_vector (7 downto 0);
+ canalB :out std_logic_vector (7 downto 0);
+
+--++++++++++++++++
+ clk : in std_logic; -- clock global
+ reset : in std_logic; -- reset global
+-- send_ram : in std_logic; -- orden para sacar dato de ram por RS232
+ rxd : in std_logic; -- linea de recepcion del RS232
+ error_uart : out std_logic;
+ error_lrc : out std_logic;
+ txd : out std_logic; -- linea de transmision del RS232
+-- puertos comunicacin con pico Blaze
+ picoB_ok :in std_logic;
+ addr_picoB : in std_logic_vector (addr_bits-1 downto 0);
+ Eram_picoB : in std_logic;
+ WEram_picoB : in std_logic;
+ data_in_ram_picoB : in std_logic_vector (7 downto 0);
+ data_out_ram_picoB : out std_logic_vector (7 downto 0);
+ cant_datos_picoB : in std_logic_vector (7 downto 0);
+ det_trama_ok_PB : out std_logic; --avisa cuando una trama est lista para usar
+ gen_trama_ok_PB : out std_logic --avisa cuando una trama fue enviada por la uart
+ );
+
+end top_enlace;
+
+architecture Behavioral of top_enlace is
+
+--*******************************************************************
+-- DECLARACION COMPONENTE UART_RS232
+--*******************************************************************
+component uart_rs232
+ Port ( clk : in std_logic; -- global clock
+ reset : in std_logic; -- global reset
+ send_data : in std_logic; -- this signal orders to send the data present at the data_in inputs through the TXD line
+ data_in : in std_logic_vector(7 downto 0); -- data to be sent
+ even_odd : in std_logic; -- it selects the desired parity (0: odd/impar; 1: even/par)
+ rxd : in std_logic; -- The RS232 RXD line
+ txd : out std_logic; -- The RS232 TXD line
+ transmitter_busy : out std_logic; -- it indicates that the transmitter is busy sending one character
+ send_done : out std_logic; -- it indicates that the character has been sent
+ data_out : out std_logic_vector(7 downto 0); -- The data received, in parallel
+ parity_error : out std_logic; -- it indicates a parity error in the received data
+ start_error : out std_logic; -- it indicates an error in the start bit (false start) of the received data. The receiver will wait for a new complete start bit
+ stop_error : out std_logic; -- it indicates an error in the stop bit of the received data (though the data could have been received correctly and it is presented at the outputs).
+ discrepancy_error : out std_logic; -- it indicates an error because the three samples of the same bit of the data being currently received have different values.
+ receiver_busy : out std_logic; -- it indicates that the receiver is busy receiving one character
+ new_data : out std_logic -- it indicates that the receiving process has ended and a new character is available
+ );
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE Detector (mquina de estado)
+--*******************************************************************
+component det_top
+ generic (
+ DIRE_LOCAL_ALTO : std_logic_vector(7 downto 0) := "00110001"; -- 1 ASCII
+ DIRE_LOCAL_BAJO : std_logic_vector(7 downto 0) := "00110001"; -- 1 ASCII
+ bits : integer := 8; -- ancho de datos de la memoria
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ Port (
+ clk :in std_logic;
+ reset :in std_logic;
+ data :in std_logic_vector(7 downto 0);
+ new_data :in std_logic;
+ error :out std_logic;
+ end_det :out std_logic;
+--para escritura de ram:
+ E :out std_logic; -- habilitador de la ram
+ WE :out std_logic; -- habilitador de escritura
+ ADDR :out std_logic_vector(addr_bits-1 downto 0);
+ data_ram :out std_logic_vector(bits-1 downto 0) --dato a guardar en ram
+ );
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE BLOQUE RAM
+--*******************************************************************
+component ram2_top
+ generic (
+ bits : integer := 8; -- ancho de datos de la memoria
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ E :in std_logic; -- habilitador de la ram
+ WE :in std_logic; -- habilitador de escritura
+ ADDR :in std_logic_vector(addr_bits-1 downto 0);
+ data_in :in std_logic_vector(bits-1 downto 0);
+ data_out :out std_logic_vector(bits-1 downto 0)
+ );
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE generador trama (maquina de estado)
+--*******************************************************************
+component gen_trama_top
+ generic(
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ end_gen :out std_logic;
+-- PicoBlaze
+ cant_datos_picoB :in std_logic_vector(7 downto 0); -- cantidad de datos cargados en ram
+ picoB_ok :in std_logic; -- arrancar transmision (tomando datos desde ram)
+-- ram
+ data_out_ram :in std_logic_vector(7 downto 0); --dato leido desde ram
+ addr_ram :out std_logic_vector(addr_bits-1 downto 0); --dato leido desde ram
+ E_ram :out std_logic; -- habilitador de ram
+ WE_ram :out std_logic; -- habilitador de escritura ram: 0-lectura 1-escritura
+-- uart
+ send_done_uart :in std_logic; -- aviso de dato enviado (por uart), seal habilitadora para obtener nuevo dato de ram
+ data_in_uart :out std_logic_vector(7 downto 0); --dato leido desde ram
+ send_data_uart :out std_logic
+ );
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE generador trama (maquina de estado)
+--*******************************************************************
+component contro_ram
+ generic(
+ addr_bits : integer := 8); -- 2^addr_bits = numero bits de direccionamiento
+ port(
+--entradas y salidas de la RAM
+ clk :in std_logic;
+ reset :in std_logic;
+ Eram :out std_logic;
+ Eram_write :out std_logic;
+ ram_addr :out std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram :out std_logic_vector(7 downto 0);
+ data_out_ram :in std_logic_vector(7 downto 0);
+--entradas y salidas del pico blaze
+ Eram_picoB :in std_logic;
+ WEram_picoB :in std_logic;
+ addr_picoB :in std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram_picoB:in std_logic_vector(7 downto 0);
+ data_out_ram_picoB:out std_logic_vector(7 downto 0);
+--entradas y salidas del componente detector
+ Eram_det :in std_logic;
+ Eram_write_det :in std_logic;
+ ram_addr_det :in std_logic_vector(addr_bits-1 downto 0);
+ data_in_ram_det:in std_logic_vector(7 downto 0);
+--entradas y salidas del componente generador trama
+ E_ram_gen :in std_logic;
+ WE_ram_gen :in std_logic;
+ addr_ram_gen :in std_logic_vector(addr_bits-1 downto 0);
+ data_out_ram_gen:out std_logic_vector(7 downto 0)
+ );
+end component;
+signal Q1,Q2,Q3 : std_logic:='0';
+signal picoB_ok_pulso : std_logic:='0';
+signal Stxd : std_logic:='1';
+--*******************************************************************
+-- SEALES DE COMPONENTE UART_RS232
+--*******************************************************************
+signal Sdata_out : std_logic_vector(7 downto 0):= (others=>'0');
+signal Snew_data : std_logic:='0';
+signal Ssend_done : std_logic:='1';
+signal Ssend_data_uart : std_logic:='0';
+signal Sdata_in_uart: std_logic_vector(7 downto 0):= (others=>'0');
+signal Stransmitter_busy : std_logic := '0';
+signal Sparity_error : std_logic := '0';
+signal Sstart_error : std_logic := '0';
+signal Sstop_error : std_logic := '0';
+signal Sdiscrepancy_error: std_logic := '0';
+signal Sreceiver_busy : std_logic := '0';
+
+--*******************************************************************
+-- SEALES DE COMPONENTE DET_TOP
+--*******************************************************************
+
+signal Serror_det : std_logic := '0';
+signal SEram_det : std_logic := '0';
+signal Sram_addr_det: std_logic_vector (addr_bits-1 downto 0):=(others=>'0') ;
+signal SEram_write_det: std_logic := '0';-- habilitador de escritura
+signal Sdata_in_ram_det: std_logic_vector (7 downto 0):=(others=>'0') ;
+signal Send_det : std_logic:='0';
+
+--*******************************************************************
+-- SEALES DE COMPONENTE BLOQUE RAM
+--*******************************************************************
+
+ signal SEram : std_logic; -- habilitador de la ram
+ signal SEram_write : std_logic; -- habilitador de escritura
+ signal Sram_addr :std_logic_vector(addr_bits-1 downto 0):=(others=>'0') ;
+ signal Sdata_in_ram :std_logic_vector(bits-1 downto 0):=(others=>'0') ;
+ signal Sdata_out_ram:std_logic_vector(bits-1 downto 0):=(others=>'0') ;
+
+--*******************************************************************
+-- SEALES DE COMPONENTE generador trama (maquina de estado)
+--*******************************************************************
+ signal Send_gen : std_logic:='0';
+ signal Sdata_out_ram_gen:std_logic_vector(bits-1 downto 0):=(others=>'0'); --dato leido desde ram
+ signal Saddr_ram_gen:std_logic_vector(addr_bits-1 downto 0):=(others=>'0') ; --dato leido desde ram
+ signal SE_ram_gen : std_logic:='0'; -- habilitador de ram
+ signal SWE_ram_gen : std_logic:='0';
+
+
+-- *********************Señales para CE **************
+ signal cont_div :std_logic_vector(20 downto 0):=(others=> '0');
+ signal CE_clock :std_logic:='0';
+
+ signal contador_canalA : std_logic_vector(7 downto 0) := (others=>'0');
+ signal RAM_trucha :std_logic_vector(7 downto 0) := (others=>'0');
+begin
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE UART_RS232
+--*******************************************************************
+IC_uart : uart_rs232
+ Port map (
+ clk => clk, -- global clock
+ reset => reset, -- global reset
+ send_data => Ssend_data_uart,--send_ram, -- this signal orders to send the data present at the data_in inputs through the TXD line
+ data_in => Sdata_in_uart,--Sdata_out_ram, -- data to be sent
+ even_odd => '0',--Seven_odd, -- it selects the desired parity (0: odd/impar; 1: even/par)
+ rxd => rxd, -- The RS232 RXD line
+ txd => Stxd, -- The RS232 TXD line
+ transmitter_busy => Stransmitter_busy, -- it indicates that the transmitter is busy sending one character
+ send_done => Ssend_done, -- it indicates that the character has been sent
+ data_out => Sdata_out, -- The data received, in parallel
+ parity_error => Sparity_error, -- it indicates a parity error in the received data
+ start_error => Sstart_error, -- it indicates an error in the start bit (false start) of the received data. The receiver will wait for a new complete start bit
+ stop_error => Sstop_error, -- it indicates an error in the stop bit of the received data (though the data could have been received correctly and it is presented at the outputs).
+ discrepancy_error => Sdiscrepancy_error, -- it indicates an error because the three samples of the same bit of the data being currently received have different values.
+ receiver_busy => Sreceiver_busy, -- it indicates that the receiver is busy receiving one character
+ new_data => Snew_data -- it indicates that the receiving process has ended and a new character is available
+ );
+
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE Detector (mquina de estado)
+--*******************************************************************
+IC_det: det_top
+ generic map (
+ DIRE_LOCAL_ALTO => "00110001", -- 0 ASCII
+ DIRE_LOCAL_BAJO => "00110001", -- 7 ASCII
+ bits => 8, -- ancho de datos de la memoria
+ addr_bits => 8 -- 2^addr_bits = numero bits de direccionamiento
+ )
+ Port map (
+ clk => clk,
+ reset => reset,
+ data => Sdata_out, --datos recibidos por la UART en 8bit
+ new_data => Snew_data, --bandera que detecta cuando se recibe un dato en la UART
+ error => Serror_det,
+ end_det => Send_det,
+--para escritura de ram:
+ E => SEram_det, -- habilitador de la ram
+ WE => SEram_write_det,-- habilitador de escritura
+ ADDR => Sram_addr_det, -- direccion de ram donde quiero escribir
+ data_ram => Sdata_in_ram_det -- dato a guardar en ram
+ );
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE BLOQUE RAM (mquina de estado)
+--*******************************************************************
+bloque_ram: ram2_top
+ generic map(
+ bits => 8, -- ancho de datos de la memoria
+ addr_bits => 8 -- 2^addr_bits = numero bits de direccionamiento
+ )
+ port map (
+ clk => clk,
+ reset => reset,
+ E => SEram, -- habilitador de la ram
+ WE => SEram_write, -- habilitador de escritura
+ ADDR => Sram_addr,
+ data_in => Sdata_in_ram,
+ data_out => Sdata_out_ram
+ );
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE generador trama (maquina de estado)
+--*******************************************************************
+gen_top: gen_trama_top
+ generic map(
+ addr_bits => 8 -- 2^addr_bits = numero bits de direccionamiento
+ )
+ port map(
+ clk => clk,
+ reset => reset,
+ end_gen => Send_gen,
+-- PicoBlaze
+ cant_datos_picoB => cant_datos_picoB,-- cantidad de datos cargados en ram
+ picoB_ok => picoB_ok_pulso, -- arrancar transmision (tomando datos desde ram)
+-- ram
+ data_out_ram => Sdata_out_ram_gen, --dato leido desde ram
+ addr_ram => Saddr_ram_gen, --dato leido desde ram
+ E_ram => SE_ram_gen, -- habilitador de ram
+ WE_ram => SWE_ram_gen, -- habilitador de escritura ram: 0-lectura 1-escritura
+-- uart
+ send_done_uart => Ssend_done, -- aviso de dato enviado (por uart), seal habilitadora para obtener nuevo dato de ram
+ data_in_uart => Sdata_in_uart, --dato leido desde ram
+ send_data_uart => Ssend_data_uart
+ );
+
+
+--*******************************************************************
+-- ESCRITURA / LECTURA EN RAM
+--*******************************************************************
+
+
+control_RAM: contro_ram
+ generic map(
+ addr_bits => 8) -- 2^addr_bits = numero bits de direccionamiento
+ port map(
+--entradas y salidas de la RAM
+ clk => clk,
+ reset => reset,
+ Eram => SEram, -- habilitador de la ram
+ Eram_write => SEram_write, -- habilitador de escritura
+ ram_addr => Sram_addr,
+ data_in_ram => Sdata_in_ram,
+ data_out_ram => Sdata_out_ram,
+--entradas y salidas del pico blaze
+ Eram_picoB => Eram_picoB,
+ WEram_picoB => WEram_picoB,
+ addr_picoB => addr_picoB,
+ data_in_ram_picoB=> data_in_ram_picoB,
+ data_out_ram_picoB=> data_out_ram_picoB,
+--entradas y salidas del componente detector
+ Eram_det => SEram_det, -- habilitador de la ram
+ Eram_write_det => SEram_write_det,-- habilitador de escritura
+ ram_addr_det => Sram_addr_det, -- direccion de ram donde quiero escribir
+ data_in_ram_det=> Sdata_in_ram_det, -- dato a guardar en ram
+--entradas y salidas del componente generador trama
+ E_ram_gen => SE_ram_gen, -- habilitador de ram:in std_logic;
+ WE_ram_gen => SWE_ram_gen, -- habilitador de escritura ram: 0-lectura 1-escritura
+ addr_ram_gen => Saddr_ram_gen, --dato leido desde ram
+ data_out_ram_gen=> Sdata_out_ram_gen --dato leido desde ram
+ );
+
+--*******************************************************************
+-- SEALES DE ERROR
+--*******************************************************************
+error_uart <= Stransmitter_busy or Sparity_error or Sstart_error or Sstop_error or Sdiscrepancy_error or Sreceiver_busy;
+error_lrc <= Serror_det;
+
+--*******************************************************************
+-- SEALES QUE AVISAN EL ESTADO DE LA INFORMACION ENVIADO/RECIBIDO
+--*******************************************************************
+det_trama_ok_PB <= Send_det;
+gen_trama_ok_PB <= Send_gen;
+--nexys2
+an <= "1111";
+--Led(6 downto 0) <= Sram_addr(6 downto 0);
+--Led(7) <= SEram;
+Led(3 downto 0) <= (others=>'0');--contador_canalA(4 downto 0);
+Led(4) <= Serror_det;
+Led(5) <=SEram;
+Led(6) <=SE_ram_gen;
+Led(7) <=SEram_det;
+canalA <= contador_canalA;--Sdata_in_uart;
+
+canalB(0) <= SEram; -- habilitador de la ram
+canalB(1) <= SEram_write;
+canalB(2) <= Stxd;
+txd <= Stxd;
+canalB(7 downto 3) <= Sram_addr(4 downto 0);
+
+--**Insert the following after the 'begin' keyword**
+process(clk)
+begin
+ if (clk'event and clk = '1') then
+ if (reset = '1') then
+ Q1 <= '0';
+ Q2 <= '0';
+ Q3 <= '0';
+ else--if CE_clock = '1' then
+ Q1 <= picoB_ok;
+ Q2 <= Q1;
+ Q3 <= Q2;
+ end if;
+ end if;
+end process;
+
+picoB_ok_pulso <= Q1 and Q2 and (not Q3);
+
+process(clk)
+begin
+ if CE_clock = '1' then
+ cont_div <= (others=>'0');
+ elsif clk'event and clk = '1' then
+ cont_div <= cont_div + 1;
+ end if;
+end process;
+
+process(clk)
+begin
+ if clk'event and clk = '1' then
+ if cont_div > "111111111111111111100" then
+ CE_clock <= '1';
+ else
+ CE_clock <= '0';
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if clk='1' and clk'event then
+ if CE_clock='1' then
+ contador_canalA <= contador_canalA + 1;
+ end if;
+ end if;
+end process;
+
+RAM_trucha <= "00110101";
+end Behavioral;
modbus/trunk/enlace/top_enlace.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/pondera_top.vhd
===================================================================
--- modbus/trunk/enlace/pondera_top.vhd (nonexistent)
+++ modbus/trunk/enlace/pondera_top.vhd (revision 3)
@@ -0,0 +1,104 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pondera_top is
+ port(
+ clk: in std_logic;
+ reset: in std_logic;
+ bin_HL: in std_logic_vector(7 downto 0);
+ new_data: in std_logic;
+ trama_ok: in std_logic;
+ bin: out std_logic_vector(7 downto 0);
+ bin_ok: out std_logic
+ );
+end pondera_top;
+
+
+architecture Behavioral of pondera_top is
+
+signal Sdata_H :std_logic_vector(7 downto 0):=(others=>'0');
+signal Sdata_L :std_logic_vector(7 downto 0):=(others=>'0');
+
+--Insert the following in the architecture before the begin keyword
+ --Use descriptive names for the states, like st1_reset, st2_search
+ type state_type is (st1_espera, st2_data_H, st3_data_L, st4_calculo);
+ signal state, next_state : state_type;
+ --Declare internal signals for all outputs of the state machine
+ signal Sbin_ok: std_logic:='0';
+begin
+
+-- This is a sample state machine using enumerated types.
+-- This will allow the synthesis tool to select the appropriate
+-- encoding style and will make the code more readable.
+
+
+ --other outputs
+
+--Insert the following in the architecture after the begin keyword
+ SYNC_PROC: process (clk, reset)
+ begin
+ if (reset='1') then
+ state <= st1_espera;
+ elsif (clk'event and clk = '1') then
+ state <= next_state;
+ --bin <= Sbin;
+ bin_ok <= Sbin_ok;
+ -- assign other outputs to internal signals"
+ end if;
+ end process;
+
+ --MOORE State Machine - Outputs based on state only
+ OUTPUT_DECODE: process (state)
+ begin
+ --insert statements to decode internal output signals
+ --below is simple example
+ if state = st1_espera then
+ Sbin_ok <= '0';
+ end if;
+
+ if state = st2_data_H then
+ Sdata_H <= bin_HL; --almacena el primer dato en una señal para ser ponderada
+ end if;
+
+ if state = st3_data_L then
+ Sdata_L <= bin_HL; --almacena el segundo dato en una señal para ser ponderada
+ end if;
+
+ if state = st4_calculo then
+ bin <= Sdata_H(3 downto 0)&"0000" + Sdata_L;
+ Sbin_ok <= '1';
+ end if;
+ end process;
+
+ NEXT_STATE_DECODE: process (state, new_data)
+ begin
+ --declare default state for next_state to avoid latches
+ next_state <= state; --default is to stay in current state
+ --insert statements to decode next_state
+ --below is a simple example
+ case (state) is
+ when st1_espera =>
+ if new_data = '1' and trama_ok = '1' then
+ next_state <= st2_data_H;
+ end if;
+ when st2_data_H =>
+ if new_data = '1' then
+ next_state <= st3_data_L;
+ end if;
+ when st3_data_L=>
+ next_state <= st4_calculo;
+ when st4_calculo =>
+ next_state <= st1_espera;
+ when others =>
+ next_state <= st1_espera;
+ end case;
+ end process;
+
+end Behavioral;
modbus/trunk/enlace/pondera_top.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/enlace_TB.vhd
===================================================================
--- modbus/trunk/enlace/enlace_TB.vhd (nonexistent)
+++ modbus/trunk/enlace/enlace_TB.vhd (revision 3)
@@ -0,0 +1,769 @@
+
+-- VHDL Test Bench Created from source file top_enlace.vhd -- 18:01:39 07/21/2010
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY top_enlace_enlace_TB_vhd_tb IS
+END top_enlace_enlace_TB_vhd_tb;
+
+ARCHITECTURE behavior OF top_enlace_enlace_TB_vhd_tb IS
+
+ COMPONENT top_enlace
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ send_ram : IN std_logic;
+ rxd : IN std_logic;
+ error_uart : OUT std_logic;
+ error_lrc : OUT std_logic;
+ leds : OUT std_logic_vector(7 downto 0);
+ txd : OUT std_logic;
+ picoB_ok :in std_logic;
+ addr_picoB : in std_logic_vector (3 downto 0);
+ Eram_picoB : in std_logic;
+ WEram_picoB : in std_logic;
+ data_in_ram_picoB : in std_logic_vector (7 downto 0);
+ data_out_ram_picoB : in std_logic_vector (7 downto 0);
+ cant_datos_picoB : in std_logic_vector (7 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ SIGNAL reset : std_logic;
+ SIGNAL send_ram : std_logic;
+ SIGNAL rxd : std_logic:='1';
+ SIGNAL picoB_ok : std_logic;
+ SIGNAL addr_picoB : std_logic_vector (3 downto 0);
+ SIGNAL Eram_picoB : std_logic;
+ SIGNAL WEram_picoB : std_logic;
+ SIGNAL data_in_ram_picoB : std_logic_vector (7 downto 0);
+ SIGNAL data_out_ram_picoB: std_logic_vector (7 downto 0);
+ SIGNAL cant_datos_picoB : std_logic_vector (7 downto 0);
+ SIGNAL error_uart : std_logic;
+ SIGNAL error_lrc : std_logic;
+ SIGNAL leds : std_logic_vector(7 downto 0);
+ SIGNAL txd : std_logic;
+ signal comiezo : std_logic_vector(7 downto 0):= "01010101";
+ signal segundo : std_logic_vector(7 downto 0):= "11100111";
+ signal dospuntos : std_logic_vector(7 downto 0):= "00111010"; --: ascii
+ signal cero : std_logic_vector(7 downto 0):= "00110000"; --0 ascii
+ signal uno : std_logic_vector(7 downto 0):= "00110001"; --1 ascii
+ signal dos : std_logic_vector(7 downto 0):= "00110010"; --2 ascii
+ signal tres : std_logic_vector(7 downto 0):= "00110011"; --3 ascii
+ signal cuatro : std_logic_vector(7 downto 0):= "00110100"; --4 ascii
+ signal cinco : std_logic_vector(7 downto 0):= "00110101"; --5 ascii
+ signal seis : std_logic_vector(7 downto 0):= "00110110"; --6 ascii
+ signal siete : std_logic_vector(7 downto 0):= "00110111"; --7 ascii
+ signal ocho : std_logic_vector(7 downto 0):= "00111000"; --8 ascii
+ signal nueve : std_logic_vector(7 downto 0):= "00111001"; --9 ascii
+ signal la_a : std_logic_vector(7 downto 0):= "01000001"; --A ascii
+ signal la_b : std_logic_vector(7 downto 0):= "01000010"; --B ascii
+ signal la_e : std_logic_vector(7 downto 0):= "01000101"; --E ascii
+ signal la_f : std_logic_vector(7 downto 0):= "01000110"; --F ascii
+ signal cr : std_logic_vector(7 downto 0):= "00001101"; --CR ascii
+ signal lf : std_logic_vector(7 downto 0):= "00001010"; --LF ascii
+
+
+ -- Clock period definitions
+ constant clk_period : time := 20ns;
+
+
+BEGIN
+
+ uut: top_enlace
+ PORT MAP(
+ clk => clk,
+ reset => reset,
+ send_ram => send_ram,
+ rxd => rxd,
+ error_uart => error_uart,
+ leds => leds,
+ txd => txd,
+ picoB_ok => picoB_ok,
+ addr_picoB => addr_picoB,
+ Eram_picoB => Eram_picoB,
+ WEram_picoB => WEram_picoB,
+ cant_datos_picoB => cant_datos_picoB,
+ data_in_ram_picoB => data_in_ram_picoB,
+ data_out_ram_picoB => data_out_ram_picoB
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+
+ wait for 100ns;
+ reset <= '1';
+ send_ram <='0';
+ addr_picoB <= "0011";
+ Eram_picoB <= '0';
+ wait for 100ns;
+ reset <= '0';
+
+--caracter erroneo 1
+ wait for 300us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= comiezo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+--caracter erroneo 2
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= segundo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+--*************************************************
+-- trama MODBUS 1
+--*************************************************
+ --trama dos puntos
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dospuntos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire alto 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= uno(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire bajo 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= uno(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama función alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama función bajo 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= tres(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama dato1 alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato1 bajo 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 alto 6 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= seis(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 bajo b ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_b(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato3 alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato3 bajo 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato4 alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato4 bajo 3 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= tres(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama lrc alto 7 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <=siete(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lrc bajo e ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_e(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama cr
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cr(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lf
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= lf(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+--*************************************************
+-- trama MODBUS 2
+--*************************************************
+ --trama dos puntos
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dospuntos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dire bajo 7 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= siete(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama función alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama función bajo 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama dato1 alto 5 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato1 bajo 8 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= ocho(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 alto F ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_f(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 bajo a ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_a(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama cr
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cr(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lf
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= lf(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+--*************************************************
+-- trama MODBUS 3
+--*************************************************
+ --trama dos puntos
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dospuntos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+-- direccion ***************************************
+ --trama dire alto 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= uno(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+--trama dire bajo 1 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= uno(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+-- funcion ***************************************
+
+ --trama función alto 0 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cero(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama función bajo 6 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= seis(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama dato1 alto 7 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= siete(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato1 bajo 2 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 alto 4 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cuatro(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato2 bajo 5 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato3 alto 2 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= dos(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato3 bajo 6 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= seis(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato4 alto 5 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato4 bajo 5ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato5 alto 7 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= siete(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato5 bajo 8 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= ocho(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato6 alto 8 ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= ocho(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama dato6 bajo 5 ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cinco(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+
+ --trama lrc alto B ascii ********************************
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_b(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lrc bajo A ascii
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= la_a(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama cr
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= cr(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+ --trama lf
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= lf(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+--**********************************************************
+
+--enviar datos de la ram al TX
+ wait for 5ms; -- antes 500us, os parece poco tiempo éste valor
+ Eram_picoB <= '1';
+ wait for 100us;
+ addr_picoB <= "0011";
+ wait for 100us;
+ send_ram <= '1';
+ wait for 120us;
+ send_ram <= '0';
+ wait for 2ms;
+ wait; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
modbus/trunk/enlace/enlace_TB.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/rs232_receive_control.vhd
===================================================================
--- modbus/trunk/enlace/rs232_receive_control.vhd (nonexistent)
+++ modbus/trunk/enlace/rs232_receive_control.vhd (revision 3)
@@ -0,0 +1,331 @@
+-- C:\USER\XILINX_2006\UART_RS232\RX_CTRL.vhd
+-- VHDL code created by Xilinx's StateCAD 7.1i
+-- Thu Oct 19 16:59:23 2006
+
+-- This VHDL code (for use with Xilinx XST) was generated using:
+-- enumerated state assignment with structured code format.
+-- Minimization is enabled, implied else is disabled,
+-- and outputs are area optimized.
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY RX_CTRL IS
+ PORT (CLK,ctr_bits_eq_9,fd_rxd,last_sample,RESET,sampled_bit: IN std_logic;
+ incr_ctr_bits,ld_parity_error,load_data,load_discrepancy,new_data,
+ reset_busy,reset_capture,reset_ctr_bits,reset_ctr_clock,rst_ce_ctr_clock,
+ rst_discrepancy,set_busy,set_capture,set_ce_ctr_clock,shift_enable,
+ start_error,stop_error : OUT std_logic);
+END;
+
+ARCHITECTURE BEHAVIOR OF RX_CTRL IS
+ TYPE type_sreg IS (IDLE,CHECK_9_BITS,CHECK_START_BIT,CHECK_STOP_BIT,END_RECEIVING,
+ SHIFT_BIT,START_BIT_ERROR,START_RECEIVING,STOP_BIT_ERROR,STORE_DATA,
+ WAIT_NEXT_BIT,WAIT_STOP_BIT);
+ SIGNAL sreg, next_sreg : type_sreg;
+BEGIN
+ PROCESS (CLK, RESET, next_sreg)
+ BEGIN
+ IF ( RESET='1' ) THEN
+ sreg <= IDLE;
+ ELSIF CLK='1' AND CLK'event THEN
+ sreg <= next_sreg;
+ END IF;
+ END PROCESS;
+
+ PROCESS (sreg,ctr_bits_eq_9,fd_rxd,last_sample,sampled_bit)
+ BEGIN
+ incr_ctr_bits <= '0'; ld_parity_error <= '0'; load_data <= '0';
+ load_discrepancy <= '0'; new_data <= '0'; reset_busy <= '0'; reset_capture <=
+ '0'; reset_ctr_bits <= '0'; reset_ctr_clock <= '0'; rst_ce_ctr_clock <= '0';
+ rst_discrepancy <= '0'; set_busy <= '0'; set_capture <= '0';
+ set_ce_ctr_clock <= '0'; shift_enable <= '0'; start_error <= '0'; stop_error
+ <= '0';
+
+ next_sreg<=IDLE;
+
+ IF NOT ( (sreg=CHECK_9_BITS) OR (sreg=CHECK_START_BIT) OR (
+ sreg=CHECK_STOP_BIT) OR (sreg=END_RECEIVING) OR (sreg=IDLE) OR (
+ sreg=SHIFT_BIT) OR (sreg=START_BIT_ERROR) OR (sreg=START_RECEIVING) OR (
+ sreg=STOP_BIT_ERROR) OR (sreg=STORE_DATA) OR (sreg=WAIT_NEXT_BIT) OR (
+ sreg=WAIT_STOP_BIT)) THEN next_sreg<=IDLE;
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ ELSE
+ CASE sreg IS
+ WHEN CHECK_9_BITS =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ rst_discrepancy<='1';
+ IF ( ctr_bits_eq_9='1' ) THEN
+ next_sreg<=STORE_DATA;
+ ELSE
+ next_sreg<=WAIT_NEXT_BIT;
+ END IF;
+ WHEN CHECK_START_BIT =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ IF ( sampled_bit='0' ) THEN
+ next_sreg<=WAIT_NEXT_BIT;
+ ELSE
+ next_sreg<=START_BIT_ERROR;
+ END IF;
+ WHEN CHECK_STOP_BIT =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ IF ( sampled_bit='1' ) THEN
+ next_sreg<=END_RECEIVING;
+ ELSE
+ next_sreg<=STOP_BIT_ERROR;
+ END IF;
+ WHEN END_RECEIVING =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ reset_capture<='1';
+ rst_ce_ctr_clock<='1';
+ reset_ctr_clock<='1';
+ reset_ctr_bits<='1';
+ new_data<='1';
+ reset_busy<='1';
+ next_sreg<=IDLE;
+ WHEN IDLE =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ IF ( fd_rxd='1' ) THEN
+ next_sreg<=START_RECEIVING;
+ ELSE
+ next_sreg<=IDLE;
+ END IF;
+ WHEN SHIFT_BIT =>
+ ld_parity_error<='0';
+ load_data<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ start_error<='0';
+ stop_error<='0';
+ shift_enable<='1';
+ incr_ctr_bits<='1';
+ load_discrepancy<='1';
+ next_sreg<=CHECK_9_BITS;
+ WHEN START_BIT_ERROR =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_ctr_bits<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ stop_error<='0';
+ reset_capture<='1';
+ rst_ce_ctr_clock<='1';
+ reset_ctr_clock<='1';
+ start_error<='1';
+ reset_busy<='1';
+ next_sreg<=IDLE;
+ WHEN START_RECEIVING =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ set_capture<='1';
+ set_ce_ctr_clock<='1';
+ set_busy<='1';
+ IF ( last_sample='1' ) THEN
+ next_sreg<=CHECK_START_BIT;
+ ELSE
+ next_sreg<=START_RECEIVING;
+ END IF;
+ WHEN STOP_BIT_ERROR =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='1';
+ next_sreg<=END_RECEIVING;
+ WHEN STORE_DATA =>
+ incr_ctr_bits<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ ld_parity_error<='1';
+ load_data<='1';
+ next_sreg<=WAIT_STOP_BIT;
+ WHEN WAIT_NEXT_BIT =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ IF ( last_sample='1' ) THEN
+ next_sreg<=SHIFT_BIT;
+ ELSE
+ next_sreg<=WAIT_NEXT_BIT;
+ END IF;
+ WHEN WAIT_STOP_BIT =>
+ incr_ctr_bits<='0';
+ ld_parity_error<='0';
+ load_data<='0';
+ load_discrepancy<='0';
+ new_data<='0';
+ reset_busy<='0';
+ reset_capture<='0';
+ reset_ctr_bits<='0';
+ reset_ctr_clock<='0';
+ rst_ce_ctr_clock<='0';
+ rst_discrepancy<='0';
+ set_busy<='0';
+ set_capture<='0';
+ set_ce_ctr_clock<='0';
+ shift_enable<='0';
+ start_error<='0';
+ stop_error<='0';
+ IF ( last_sample='1' ) THEN
+ next_sreg<=CHECK_STOP_BIT;
+ ELSE
+ next_sreg<=WAIT_STOP_BIT;
+ END IF;
+ WHEN OTHERS =>
+ END CASE;
+ END IF;
+ END PROCESS;
+END BEHAVIOR;
modbus/trunk/enlace/rs232_receive_control.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/voting_circuit_2_of_3.vhd
===================================================================
--- modbus/trunk/enlace/voting_circuit_2_of_3.vhd (nonexistent)
+++ modbus/trunk/enlace/voting_circuit_2_of_3.vhd (revision 3)
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 10:57:05 10/18/06
+-- Design Name:
+-- Module Name: voting_circuit_2_of_3 - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity voting_circuit_2_of_3 is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ load_sample_1 : in std_logic;
+ load_sample_2 : in std_logic;
+ load_sample_3 : in std_logic;
+ bit_input : in std_logic;
+ sampled_bit : out std_logic;
+ discrepancy : out std_logic);
+end voting_circuit_2_of_3;
+
+architecture Behavioral of voting_circuit_2_of_3 is
+
+-- Signals declaration
+signal sample_1, sample_2, sample_3: std_logic;
+signal sample_vector: std_logic_vector (2 downto 0);
+
+begin
+
+-- Vector of samples
+sample_vector <= sample_3 & sample_2 & sample_1;
+
+-- Sample 1 register
+Sample_1_register: process (clk, reset, load_sample_1)
+begin
+if reset = '1' then
+ sample_1 <= '0';
+elsif clk'event and clk ='1' then
+ if load_sample_1 = '1' then sample_1 <= bit_input;
+ end if;
+end if;
+end process;
+
+-- Sample 2 register
+Sample_2_register: process (clk, reset, load_sample_2)
+begin
+if reset = '1' then
+ sample_2 <= '0';
+elsif clk'event and clk ='1' then
+ if load_sample_2 = '1' then sample_2 <= bit_input;
+ end if;
+end if;
+end process;
+
+-- Sample 3 register
+Sample_3_register: process (clk, reset, load_sample_3)
+begin
+if reset = '1' then
+ sample_3 <= '0';
+elsif clk'event and clk ='1' then
+ if load_sample_3 = '1' then sample_3 <= bit_input;
+ end if;
+end if;
+end process;
+
+-- Voting circuit (2 of 3)
+with sample_vector select
+ sampled_bit <= '1' when "011"|"101"|"110"|"111",
+ '0' when others;
+
+with sample_vector select
+ discrepancy <= '0' when "000"|"111",
+ '1' when others;
+
+end Behavioral;
modbus/trunk/enlace/voting_circuit_2_of_3.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/gen_trama_top.vhd
===================================================================
--- modbus/trunk/enlace/gen_trama_top.vhd (nonexistent)
+++ modbus/trunk/enlace/gen_trama_top.vhd (revision 3)
@@ -0,0 +1,335 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity gen_trama_top is
+ generic(
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ end_gen :out std_logic;
+-- PicoBlaze
+ cant_datos_picoB :in std_logic_vector(7 downto 0); -- cantidad de datos cargados en ram
+ picoB_ok :in std_logic; -- arrancar transmision (tomando datos desde ram)
+-- ram
+ data_out_ram :in std_logic_vector(7 downto 0); --dato leido desde ram
+ addr_ram :out std_logic_vector(addr_bits-1 downto 0); --dato leido desde ram
+ E_ram :out std_logic; -- habilitador de ram
+ WE_ram :out std_logic; -- habilitador de escritura ram: 0-lectura 1-escritura
+-- uart
+ send_done_uart :in std_logic; -- aviso de dato enviado (por uart), seal habilitadora para obtener nuevo dato de ram
+ data_in_uart :out std_logic_vector(7 downto 0); --dato leido desde ram
+ send_data_uart :out std_logic
+ );
+end gen_trama_top;
+
+architecture Behavioral of gen_trama_top is
+
+-- ********************* DECLARACION DE SEALES Y ESTADOS *****************************
+ type state_type is (st1_espera, st2_dos_puntos, st3_lectura_ram, st4_ascii_H, st4_ascii_H_conver, st5_ascii_L, st5_ascii_L_conver, st6_fin_datos,st7_LRC_H, st7_LRC_H_conver, st8_LRC_L, st8_LRC_L_conver, st9_CR, st10_LF);
+ signal state, next_state : state_type;
+ signal Saddr :std_logic_vector (addr_bits-1 downto 0):=(others =>'0');
+ signal SE_ram :std_logic:='0';
+ signal SWE_ram :std_logic:='0';
+-- signal Sdata_in_uart :std_logic_vector (7 downto 0):=(others =>'0');
+ signal Ssend_data_uart :std_logic:='0';
+ signal Sst4_cont :std_logic_vector(1 downto 0):="00";
+ signal Sst5_cont :std_logic_vector(1 downto 0):="00";
+ signal Sst7_cont :std_logic_vector(1 downto 0):="00";
+ signal Sst8_cont :std_logic_vector(1 downto 0):="00";
+
+-- Seales CONVERSOR
+ signal Sbin :std_logic_vector (7 downto 0):=(others =>'0');
+ signal Sascii_H :std_logic_vector (7 downto 0):=(others =>'0');
+ signal Sascii_L :std_logic_vector (7 downto 0):=(others =>'0');
+-- Seales LRC
+ signal Slrc_bin : std_logic_vector (7 downto 0):=(others =>'0');
+ signal Strama : std_logic:='0';
+ signal Q1, Q2, Q3, Q4, Q5 : std_logic:='0'; -- seales auxiliares para obtener Snew_data e funcion de send_done (cadena Flip Flops)
+ signal Snew_data_pre : std_logic:='0';
+ signal Snew_data : std_logic:='0';
+
+
+-- ***************** DECLARACION COMPONENTE GENERADOR LRC ****************************
+component gen_lrc
+ port(
+ clk :in std_logic; --clk
+ reset :in std_logic; --reset
+ new_data :in std_logic; --nuevo valor a leer
+ trama :in std_logic; --suma vlida
+ dato_trama:in std_logic_vector(7 downto 0); --dato desde la ram
+ lrc_bin :out std_logic_vector(7 downto 0) --valor del lrc calculado
+ );
+end component;
+-- ***************** DECLARACION COMPONENTE CONVERSOR BIN A ASCII ****************************
+component bin_ascii
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ bin :in std_logic_vector(7 downto 0);
+ ascii_h :out std_logic_vector(7 downto 0);
+ ascii_l :out std_logic_vector(7 downto 0)
+ );
+end component;
+
+
+begin
+-- ***************** INSTANCIACION COMPONENTE GEN_LRC ****************************
+generador_lrc: gen_lrc
+ port map(
+ clk => clk,
+ reset => reset,
+ new_data => Snew_data,
+ trama => Strama, --suma vlida (trama = '1')
+ dato_trama => data_out_ram, --dato desde la ram
+ lrc_bin => Slrc_bin --valor del lrc calculado
+ );
+-- ***************** INSTANCIACION COMPONENTE CONVERSOR ****************************
+conv_bin2ascii: bin_ascii
+ port map(
+ clk => clk,
+ reset => reset,
+ bin => Sbin, -- entrada del conversor
+ ascii_h => Sascii_H,
+ ascii_l => Sascii_L
+ );
+--************ MAQUINA ESTADO: DESCRIPCION SINCRONIZAR CAMBIOS DE ESTADO **************
+SYNC_PROC: process (clk,reset)
+ begin
+ if (reset='1') then
+ state <= st1_espera;
+ elsif (clk'event and clk = '1') then
+ state <= next_state;
+ E_ram <= SE_ram;
+ WE_ram <= SWE_ram;
+-- data_in_uart <= Sdata_in_uart;
+-- send_data_uart <= Ssend_data_uart;
+ end if;
+ end process;
+
+
+-- data_in_uart <= Sdata_in_uart;
+--************ MAQUINA ESTADO: DESCRIPCION EJECUCION EN LOS ESTADOS (SALIDAS) ***********
+-- En los distintos estados se envian los caracteres de comienzo y fin de trama, lrc, y datos obtenidos de la RAM.
+-- En el estos estados se usa send_done_uart solo para poder resetar las seales de "enviar dato" (send_data_uart) y las de RAM,
+-- siempre que se cambia de estado es porque el dato anterior ya termino de enviarse.
+OUTPUT_DECODE: process (state,send_done_uart) --send_done_uart = 1 == "envio realizado"
+ begin
+ if state = st2_dos_puntos then
+ if send_done_uart = '0' then
+ data_in_uart <= "00111010"; -- carga en la entrada de uart el dato a enviar: ':'
+ end if;
+ end if;
+
+ if state = st3_lectura_ram then --no se envian datos, se direcciona el elemento de la RAM
+ if send_done_uart = '0' then
+ addr_ram <= Saddr; -- direccion del elemento a enviar
+ SE_ram <= '1'; -- hablita la RAM
+ SWE_ram <= '0'; -- habilita la Lectura
+ Saddr <= Saddr + 1; -- se incrementa el contador para luego acceder al proximo elemeto de RAM
+ end if;
+ Strama <= '1';
+ end if;
+
+ if state = st4_ascii_H then
+ if send_done_uart = '0' then
+ data_in_uart <= Sascii_H; -- parte alta del dato covertido
+ Snew_data_pre <= '1';
+ end if;
+ end if;
+
+ if state = st5_ascii_L then
+ if send_done_uart = '0' then
+ data_in_uart <= Sascii_L; -- parte alta del dato covertido
+ Snew_data_pre <= '0';
+ end if;
+ end if;
+
+ if state = st6_fin_datos then
+ Strama <= '0';
+ SE_ram <= '0'; -- deshabilita la RAM
+ SWE_ram <= '0'; -- (se mantiene siempre habilitada la lectura de la RAM)
+ end if;
+
+ if state = st7_LRC_H then
+ data_in_uart <= Sascii_H; -- parte alta del dato covertido
+ end if;
+
+ if state = st8_LRC_L then
+ data_in_uart <= Sascii_L; -- parte alta del dato covertido
+ end if;
+
+ if state = st9_CR then
+ data_in_uart <= "01000010";--"00001101"; -- carga en la entrada de uart el dato a enviar: CR
+ end if;
+ if state = st10_LF then
+ data_in_uart <= "01000001";--"00001010";
+ end_gen <= '1';
+ else
+ end_gen <= '0';
+ end if;
+
+
+end process;
+
+send_232:process(clk,state,send_done_uart)
+begin
+ if clk'event and clk = '1' then
+ if (state=st2_dos_puntos or state = st4_ascii_H or state = st5_ascii_L or state = st7_LRC_H or state = st8_LRC_L or state = st9_CR or state = st10_LF) then
+ if send_done_uart = '0' then
+ Ssend_data_uart <= '1'; -- seal que da la orden a la uart para enviar el dato
+ else
+ Ssend_data_uart <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+send_data_uart <= Ssend_data_uart;
+
+--************ MAQUINA ESTADO: DESCRIPCION ESTADO SIGUIENTE ***********************
+NEXT_STATE_DECODE: process (Saddr, Sst4_cont,Sst5_cont, state, send_done_uart, picoB_ok)
+begin
+ next_state <= state; --default is to stay in current state
+ case (state) is
+ when st1_espera => --estado de espera, comienza la secuencia de estados cuado
+ if picoB_ok = '1' then -- el pico blaze termina de cargar RAM
+ next_state <= st2_dos_puntos; -- se pasa a los estados que envan la trama
+ end if;
+ when st2_dos_puntos =>
+ if send_done_uart = '1' then --cuando se termina de enviar ":" se pasa al estado 3
+ next_state <= st3_lectura_ram;
+ end if;
+ when st3_lectura_ram => -- se pasa a otro estado independientemente de send_done_uart ya que st3 no se envia ningn dato
+ if Saddr < cant_datos_picoB then -- se recorre la RAM hasta el ltimo elemento dispuesto por pico blaze
+ next_state <= st4_ascii_H_conver; -- se va a enviar la parte alta del correspondiente elemento de RAM
+ else
+ next_state <= st6_fin_datos;-- cuando se termina de recorrer los elementos de la RAM se envia el LRC
+ end if;
+ when st4_ascii_H_conver =>
+ if Sst4_cont > "10" then
+ next_state <= st4_ascii_H;
+ end if;
+ when st4_ascii_H =>
+ if send_done_uart = '1' then -- cuando se termina de enviar la parte alta del correspondiente elemento, pasa a enviar la parte baja
+ next_state <= st5_ascii_L_conver;
+ end if;
+ when st5_ascii_L_conver =>
+ if Sst5_cont > "10" then
+ next_state <= st5_ascii_L;
+ end if;
+ when st5_ascii_L =>
+ if send_done_uart = '1' then -- cuando se envi la parte baja volvemos al st3 a buscar otro elemento a enviar
+ next_state <= st3_lectura_ram;
+ end if;
+ when st6_fin_datos =>
+ next_state <= st7_LRC_H_conver;
+ when st7_LRC_H_conver =>
+ next_state <= st7_LRC_H;
+ when st7_LRC_H =>
+ if send_done_uart = '1' then
+ next_state <= st8_LRC_L_conver;
+ end if;
+ when st8_LRC_L_conver =>
+ next_state <= st8_LRC_L;
+ when st8_LRC_L =>
+ if send_done_uart = '1' then
+ next_state <= st9_CR; -- cuando se termina de enviar el LRC se envia caracteres de fin de trama
+ end if;
+ when st9_CR =>
+ if send_done_uart = '1' then
+ next_state <= st10_LF;
+ end if;
+ when st10_LF =>
+ if send_done_uart = '1' then -- cuando se termina de enviar trama se vuelve a st1_espera
+ next_state <= st1_espera;
+ end if;
+ when others =>
+ next_state <= st1_espera;
+ end case;
+end process;
+
+
+
+process(clk)
+begin
+ if clk'event and clk = '1' then
+ if state = st4_ascii_H_conver then
+ Sst4_cont <= Sst4_cont + 1;
+ else
+ Sst4_cont <= "00";
+ end if;
+ end if;
+end process;
+
+
+process(clk)
+begin
+ if clk'event and clk = '1' then
+ if state = st5_ascii_L_conver then
+ Sst5_cont <= Sst5_cont + 1;
+ else
+ Sst5_cont <= "00";
+ end if;
+ end if;
+end process;
+
+process(clk)
+begin
+ if clk'event and clk = '1' then
+ if state = st7_LRC_H_conver then
+ Sst7_cont <= Sst7_cont + 1;
+ else
+ Sst7_cont <= "00";
+ end if;
+ end if;
+end process;
+
+process(clk)
+begin
+ if clk'event and clk = '1' then
+ if state = st8_LRC_L_conver then
+ Sst8_cont <= Sst8_cont + 1;
+ else
+ Sst8_cont <= "00";
+ end if;
+ end if;
+end process;
+
+
+-- ************** FLIP FLOPS PARA GENERAR Snew_data *******************
+-- Snew_data es la seal que le idica al componente "generar LRC", que tome y sume un
+-- nuevo dato que tiene presente en la entrada. Sigue a Send_done pero retrasado
+-- tres pulsos de clock, tiempo suficiente para que aparezca el dato a la entrada del
+-- componente gen_LRC.
+
+process(clk, reset)
+begin
+ if (reset = '1') then
+ Q1 <= '0';
+ Q2 <= '0';
+ Q3 <= '0';
+ Q4 <= '0';
+ Q5 <= '0';
+ elsif (clk'event and clk = '1') then
+ Q1 <= Snew_data_pre;
+ Q2 <= Q1;
+ Q3 <= Q2;
+ Q4 <= Q3;
+ Q5 <= Q4;
+ end if;
+end process;
+
+Snew_data <= Q1 and Q2 and Q3 and Q4 and (not Q5);
+
+--******************************************************************
+
+--************ MUX *************************
+Sbin <= data_out_ram when Strama = '1' else
+ Slrc_bin;
+--******************************************
+
+end Behavioral;
\ No newline at end of file
modbus/trunk/enlace/gen_trama_top.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/ascii_bin.vhd
===================================================================
--- modbus/trunk/enlace/ascii_bin.vhd (nonexistent)
+++ modbus/trunk/enlace/ascii_bin.vhd (revision 3)
@@ -0,0 +1,112 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:17:44 03/31/2010
+-- Design Name:
+-- Module Name: ascii_bin - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ascii_bin is
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ ascii :in std_logic_vector(7 downto 0);
+ new_data :in std_logic;
+ Nnew_data :out std_logic;
+ bin :out std_logic_vector(7 downto 0));
+end ascii_bin;
+
+architecture Behavioral of ascii_bin is
+signal Sa :std_logic:='0';
+signal Sb :std_logic:='0';
+signal Sc :std_logic:='0';
+signal Sd :std_logic:='0';
+signal Ssustraendo:std_logic_vector(7 downto 0):=(others => '0');
+signal Sconvinacional:std_logic:='0';
+signal Q1 :std_logic:='0';
+
+begin
+
+mayor_cero:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( ascii >= "00110000" ) then --si es mayor que 0 (ASCII)
+ Sa <= '1';
+ else
+ Sa <= '0';
+ end if;
+ end if;
+end process;
+
+menor_nueve:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( ascii <= "00111001" ) then --si es menor que 9 (ASCII)
+ Sb <= '1';
+ else
+ Sb <= '0';
+ end if;
+ end if;
+end process;
+
+mayor_A:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( ascii >= "01000001" ) then --si es mayor que A (ASCII)
+ Sc <= '1';
+ else
+ Sc <= '0';
+ end if;
+ end if;
+end process;
+
+menor_F:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( ascii <= "01000110" ) then --si es menor que 9 (ASCII)
+ Sd <= '1';
+ else
+ Sd <= '0';
+ end if;
+ end if;
+end process;
+
+Sconvinacional<= (not(Sa and not Sb and Sc and Sd)) or (Sa and Sb and not Sc and Sd); --controla cual es el sustraendo (0 o A-10)
+
+Ssustraendo<= "00110000" WHEN Sconvinacional ='1' ELSE --es el mutiplexor controlado por Sconvinacional para definir el sustraendo en la resta
+ "00110111";
+bin <= ascii - Ssustraendo;
+
+process(clk, reset)
+begin
+ if (reset = '1') then
+ Q1 <= '0';
+ elsif (clk'event and clk = '1') then
+ Q1 <= new_data;
+ Nnew_data <= Q1;
+ end if;
+end process;
+
+end Behavioral;
+
modbus/trunk/enlace/ascii_bin.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/bin_ascii.vhd
===================================================================
--- modbus/trunk/enlace/bin_ascii.vhd (nonexistent)
+++ modbus/trunk/enlace/bin_ascii.vhd (revision 3)
@@ -0,0 +1,161 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity bin_ascii is
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ bin :in std_logic_vector(7 downto 0);
+ ascii_h :out std_logic_vector(7 downto 0);
+ ascii_l :out std_logic_vector(7 downto 0));
+end bin_ascii;
+
+architecture Behavioral of bin_ascii is
+
+signal Sa_L :std_logic;
+signal Sb_L :std_logic;
+signal Sc_L :std_logic;
+signal Sd_L :std_logic;
+signal Sconvinacional_L :std_logic;
+signal Ssuma_L :std_logic_vector(7 downto 0);
+
+signal Sa_H :std_logic;
+signal Sb_H :std_logic;
+signal Sc_H :std_logic;
+signal Sd_H :std_logic;
+signal Sconvinacional_H :std_logic;
+signal Ssuma_H :std_logic_vector(7 downto 0);
+
+begin
+
+
+--**************************************************************
+-- Obtención código ascii de la parte baja
+--**************************************************************
+mayor_cero_L:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(3 downto 0) >= "0000" ) then --si es mayor que 0 binario
+ Sa_L <= '1';
+ else
+ Sa_L <= '0';
+ end if;
+ end if;
+end process;
+
+menor_nueve_L:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(3 downto 0) <= "1001" ) then --si es menor que 9 binario
+ Sb_L <= '1';
+ else
+ Sb_L <= '0';
+ end if;
+ end if;
+end process;
+
+mayor_10_L:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(3 downto 0) >= "1010" ) then --si es mayor que 10 binario
+ Sc_L <= '1';
+ else
+ Sc_L <= '0';
+ end if;
+ end if;
+end process;
+
+menor_F_L:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(3 downto 0) <= "1111" ) then --si es menor que 15 binario
+ Sd_L <= '1';
+ else
+ Sd_L <= '0';
+ end if;
+ end if;
+end process;
+
+--**************************************************************
+-- Obtención código ascii de la parte alta
+--**************************************************************
+mayor_cero_H:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(7 downto 4) >= "0000" ) then --si es mayor que 0 binario
+ Sa_H <= '1';
+ else
+ Sa_H <= '0';
+ end if;
+ end if;
+end process;
+
+menor_nueve_H:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(7 downto 4) <= "1001" ) then --si es menor que 9 binario
+ Sb_H <= '1';
+ else
+ Sb_H <= '0';
+ end if;
+ end if;
+end process;
+
+mayor_10_H:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(7 downto 4) >= "1010" ) then --si es mayor que 10 binario
+ Sc_H <= '1';
+ else
+ Sc_H <= '0';
+ end if;
+ end if;
+end process;
+
+menor_15_H:process(clk)
+begin
+ if (clk'event and clk ='1') then
+ if ( bin(7 downto 4) <= "1111" ) then --si es menor que 15 binario
+ Sd_H <= '1';
+ else
+ Sd_H <= '0';
+ end if;
+ end if;
+end process;
+
+
+--**************************************************************
+-- Logica convinacional para la obtención del código ascii bajo
+--**************************************************************
+Sconvinacional_L<= (not(Sa_L and not Sb_L and Sc_L and Sd_L)) or (Sa_L and Sb_L and not Sc_L and Sd_L); --controla cual es el sustraendo (0 o A-10)
+
+Ssuma_L <= "00110000" WHEN Sconvinacional_L ='1' ELSE --es el mutiplexor controlado por Sconvinacional para definir lo sumado
+ "00110111"; -- valor equivalente a el ascii 'A'
+
+ascii_L <= bin(3 downto 0) + Ssuma_L;
+
+--**************************************************************
+-- Logica convinacional para la obtención del código ascii alto
+--**************************************************************
+Sconvinacional_H<= (not(Sa_H and not Sb_H and Sc_H and Sd_H)) or (Sa_H and Sb_H and not Sc_H and Sd_H); --controla cual es el sustraendo (0 o A-10)
+
+Ssuma_H <= "00110000" WHEN Sconvinacional_H ='1' ELSE --es el mutiplexor controlado por Sconvinacional para definir lo sumado
+ "00110111"; -- valor equivalente a el ascii 'A'
+
+ascii_H <= bin(7 downto 4) + Ssuma_H;
+
+
+
+
+
+
+
+
+end Behavioral;
modbus/trunk/enlace/bin_ascii.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/lrc.vhd
===================================================================
--- modbus/trunk/enlace/lrc.vhd (nonexistent)
+++ modbus/trunk/enlace/lrc.vhd (revision 3)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:41:27 03/30/2010
+-- Design Name:
+-- Module Name: lrc - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lrc is
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ trama :in std_logic;
+ dato_ok :in std_logic;
+ dato :in std_logic_vector(7 downto 0);
+ lrc_ok :out std_logic);
+end lrc;
+
+architecture Behavioral of lrc is
+
+signal acumulador : std_logic_vector(7 downto 0);
+begin
+
+SUMADOR:process (clk,reset)
+begin
+ if reset='1' then
+ acumulador <= (others=>'0');
+ elsif clk ='1' and clk'event then
+ if trama = '1' then
+ if dato_ok='1'then --tener presente que data_ok debe permanecer SOLO 1 clk
+ acumulador <= acumulador + dato;
+ end if;
+ elsif acumulador = "00000000" then
+ lrc_ok <= '1';
+ else
+ lrc_ok <= '0';
+ end if;
+ end if;
+end process SUMADOR;
+
+end Behavioral;
+
modbus/trunk/enlace/lrc.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/ram2_top.vhd
===================================================================
--- modbus/trunk/enlace/ram2_top.vhd (nonexistent)
+++ modbus/trunk/enlace/ram2_top.vhd (revision 3)
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- La mayoría de las familias de las FPGA Spartan poseen bloques de RAM.
+-- para hacer uso de los mismos se debe realizar una descripción adecuada
+-- que se obtiene de los templates proporcionados por el fabricante.
+-- El módulo descripto a continuación hace uso de ésta característica para
+-- almacenar los datos que son adquiridos de la red MODBUS en un nivel de enlace.
+
+
+
+entity ram2_top is
+ generic ( bits : integer := 8; -- ancho de datos de la memoria
+ addr_bits : integer := 8); -- 2^addr_bits = numero bits de direccionamiento
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ E :in std_logic; -- habilitador de la ram
+ WE :in std_logic; -- habilitador de escritura
+ ADDR :in std_logic_vector(addr_bits-1 downto 0);
+ data_in :in std_logic_vector(bits-1 downto 0);
+ data_out :out std_logic_vector(bits-1 downto 0));
+end ram2_top;
+
+architecture Behavioral of ram2_top is
+
+type tipo_ram is array (2**addr_bits-1 downto 0) of std_logic_vector (bits-1 downto 0);
+signal RAM : tipo_ram;
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (E = '1') then
+ if (WE = '1') then
+ RAM(conv_integer(ADDR)) <= data_in;
+ else
+ data_out <= RAM(conv_integer(ADDR));
+ end if;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
modbus/trunk/enlace/ram2_top.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/shift9_r.vhd
===================================================================
--- modbus/trunk/enlace/shift9_r.vhd (nonexistent)
+++ modbus/trunk/enlace/shift9_r.vhd (revision 3)
@@ -0,0 +1,59 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 10:00:00 10/18/06
+-- Design Name:
+-- Module Name: shift9_R - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description: 9 bits shift register with serial in and parallel out, shift_enable control signal
+-- and right shifting.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity shift9_r is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ msb_in : in std_logic;
+ shift_enable : in std_logic;
+ q_shift : out std_logic_vector(8 downto 0));
+end shift9_r;
+
+architecture Behavioral of shift9_r is
+
+signal q_shift_aux: std_logic_vector (8 downto 0);
+
+begin
+
+-- Signal assignment
+q_shift <= q_shift_aux;
+
+process (clk, reset, msb_in, shift_enable, q_shift_aux)
+begin
+ if reset ='1' then
+ q_shift_aux <= "000000000";
+ elsif clk'event and clk='1' then
+ if shift_enable = '1' then
+ q_shift_aux <= msb_in & q_shift_aux (8 downto 1);
+ end if;
+ end if;
+end process;
+
+end Behavioral;
modbus/trunk/enlace/shift9_r.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/ctr_receiver_clock.vhd
===================================================================
--- modbus/trunk/enlace/ctr_receiver_clock.vhd (nonexistent)
+++ modbus/trunk/enlace/ctr_receiver_clock.vhd (revision 3)
@@ -0,0 +1,98 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 11:21:57 10/18/06
+-- Design Name:
+-- Module Name: ctr_receiver_clock - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description: It counts the cycles of the receive clock and indicates the reception of 2, 4, 6 and 8 receive clock cycles
+-- This counter starts at state 0, counts until state 8, then goes to state 1 and keep on counting, until it is reset to the initial state 0.
+-- This is necessary to count the receive clock cycles correctly, starting with the first receive clock cycle later than
+-- the first RXD falling edge (which corresponds to the start bit)
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ctr_receiver_clock is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ sync_reset : in std_logic;
+ ctr_eq_2 : out std_logic;
+ ctr_eq_4 : out std_logic;
+ ctr_eq_6 : out std_logic;
+ ctr_eq_8 : out std_logic;
+ gctr : in std_logic;
+ qctr : out std_logic_vector(3 downto 0));
+end ctr_receiver_clock;
+
+architecture Behavioral of ctr_receiver_clock is
+
+signal qctr_aux: std_logic_vector (3 downto 0);
+
+begin
+
+-- Outputs assignment
+qctr <= qctr_aux;
+
+process (clk, reset, gctr, qctr_aux)
+begin
+ if (reset ='1') then
+ -- Counter initialization
+ qctr_aux <= "0000";
+ elsif (clk'event and clk='1') then
+ if sync_reset = '1' then
+ qctr_aux <= "0000";
+ elsif (gctr='1') then
+ if qctr_aux = 8 then
+ qctr_aux <= "0001";
+ else
+ -- Increment counter
+ qctr_aux <= qctr_aux + 1;
+ end if;
+ end if;
+ end if;
+
+ if qctr_aux = 2 then
+ -- 2 cycles of receive clock.
+ ctr_eq_2 <= '1';
+ else ctr_eq_2 <='0';
+ end if;
+
+ if qctr_aux = 4 then
+ -- 4 cycles of receive clock
+ ctr_eq_4 <= '1';
+ else ctr_eq_4 <='0';
+ end if;
+
+ if qctr_aux = 6 then
+ -- 6 cycles of receive clock
+ ctr_eq_6 <= '1';
+ else ctr_eq_6 <='0';
+ end if;
+
+ if qctr_aux = 8 then
+ -- 8 cycles of receive clock. Last state
+ ctr_eq_8 <= '1';
+ else ctr_eq_8 <='0';
+ end if;
+end process;
+
+
+end Behavioral;
modbus/trunk/enlace/ctr_receiver_clock.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/.lso
===================================================================
--- modbus/trunk/enlace/.lso (nonexistent)
+++ modbus/trunk/enlace/.lso (revision 3)
@@ -0,0 +1 @@
+work
Index: modbus/trunk/enlace/rs232_transmit_control.vhd
===================================================================
--- modbus/trunk/enlace/rs232_transmit_control.vhd (nonexistent)
+++ modbus/trunk/enlace/rs232_transmit_control.vhd (revision 3)
@@ -0,0 +1,180 @@
+-- C:\USER\XILINX_2006\UART_RS232\TX_CTRL.vhd
+-- VHDL code created by Xilinx's StateCAD 7.1i
+-- Thu Oct 19 16:58:46 2006
+
+-- This VHDL code (for use with Xilinx XST) was generated using:
+-- enumerated state assignment with structured code format.
+-- Minimization is enabled, implied else is disabled,
+-- and outputs are area optimized.
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY TX_CTRL IS
+ PORT (CLK,ctr_eq_9,fa_send_clk,RESET,send_data: IN std_logic;
+ incr_ctr,load_parity_bit,load_txd,reset_busy,reset_ctr,reset_txd,send_done,
+ set_busy,set_txd,shift_enable : OUT std_logic);
+END;
+
+ARCHITECTURE BEHAVIOR OF TX_CTRL IS
+ TYPE type_sreg IS (IDLE,END_SENDING,LOAD_PARITY,SEND_BIT,SHIFT_BIT,START_BIT
+ ,STOP_BIT,WAIT_SEND_CLK);
+ SIGNAL sreg, next_sreg : type_sreg;
+BEGIN
+ PROCESS (CLK, RESET, next_sreg)
+ BEGIN
+ IF ( RESET='1' ) THEN
+ sreg <= IDLE;
+ ELSIF CLK='1' AND CLK'event THEN
+ sreg <= next_sreg;
+ END IF;
+ END PROCESS;
+
+ PROCESS (sreg,ctr_eq_9,fa_send_clk,send_data)
+ BEGIN
+ incr_ctr <= '0'; load_parity_bit <= '0'; load_txd <= '0'; reset_busy <=
+ '0'; reset_ctr <= '0'; reset_txd <= '0'; send_done <= '0'; set_busy <= '0';
+ set_txd <= '0'; shift_enable <= '0';
+
+ next_sreg<=IDLE;
+
+ IF NOT ( (sreg=END_SENDING) OR (sreg=IDLE) OR (sreg=LOAD_PARITY) OR (
+ sreg=SEND_BIT) OR (sreg=SHIFT_BIT) OR (sreg=START_BIT) OR (sreg=STOP_BIT) OR
+ (sreg=WAIT_SEND_CLK)) THEN next_sreg<=IDLE;
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ ELSE
+ CASE sreg IS
+ WHEN END_SENDING =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_txd<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ reset_ctr<='1';
+ send_done<='1';
+ reset_busy<='1';
+ next_sreg<=IDLE;
+ WHEN IDLE =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ IF ( send_data='1' ) THEN
+ next_sreg<=LOAD_PARITY;
+ ELSE
+ next_sreg<=IDLE;
+ END IF;
+ WHEN LOAD_PARITY =>
+ incr_ctr<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ load_parity_bit<='1';
+ set_busy<='1';
+ next_sreg<=WAIT_SEND_CLK;
+ WHEN SEND_BIT =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ IF ( fa_send_clk='1' AND ctr_eq_9='0' ) THEN
+ next_sreg<=SHIFT_BIT;
+ END IF;
+ IF ( fa_send_clk='1' AND ctr_eq_9='1' ) THEN
+ next_sreg<=STOP_BIT;
+ END IF;
+ IF ( fa_send_clk='0' ) THEN
+ next_sreg<=SEND_BIT;
+ END IF;
+ WHEN SHIFT_BIT =>
+ load_parity_bit<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ load_txd<='1';
+ shift_enable<='1';
+ incr_ctr<='1';
+ next_sreg<=SEND_BIT;
+ WHEN START_BIT =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ reset_txd<='1';
+ IF ( fa_send_clk='1' ) THEN
+ next_sreg<=SHIFT_BIT;
+ ELSE
+ next_sreg<=START_BIT;
+ END IF;
+ WHEN STOP_BIT =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ shift_enable<='0';
+ set_txd<='1';
+ IF ( fa_send_clk='1' ) THEN
+ next_sreg<=END_SENDING;
+ ELSE
+ next_sreg<=STOP_BIT;
+ END IF;
+ WHEN WAIT_SEND_CLK =>
+ incr_ctr<='0';
+ load_parity_bit<='0';
+ load_txd<='0';
+ reset_busy<='0';
+ reset_ctr<='0';
+ reset_txd<='0';
+ send_done<='0';
+ set_busy<='0';
+ set_txd<='0';
+ shift_enable<='0';
+ IF ( fa_send_clk='1' ) THEN
+ next_sreg<=START_BIT;
+ ELSE
+ next_sreg<=WAIT_SEND_CLK;
+ END IF;
+ WHEN OTHERS =>
+ END CASE;
+ END IF;
+ END PROCESS;
+END BEHAVIOR;
modbus/trunk/enlace/rs232_transmit_control.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/clock_generator_for_uart_rs232.vhd
===================================================================
--- modbus/trunk/enlace/clock_generator_for_uart_rs232.vhd (nonexistent)
+++ modbus/trunk/enlace/clock_generator_for_uart_rs232.vhd (revision 3)
@@ -0,0 +1,86 @@
+--------------------------------------------------------------------------------
+-- Company: University of Vigo
+-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
+--
+-- Create Date: 10:07:16 10/20/06
+-- Design Name:
+-- Module Name: clock_generator_for_uart_rs232 - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+-- This is a clock generator useful for the RS232 UART
+-- The uart_clock must have a frequency of eight times faster than the desired baud rate
+-- This clock generator obtains the uart_clock from a 50 MHz clock input
+-- Below are some values for the constant "divide_by", which allow to obtain some of the RS232 standard
+-- baud rates. Put the desired value in the definition of the constant or adapt this value if
+-- you need another baud rate or if your clock input frequency is other than 50 MHz.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_generator_for_uart_rs232 is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ uart_clk : out std_logic);
+end clock_generator_for_uart_rs232;
+
+architecture Behavioral of clock_generator_for_uart_rs232 is
+
+constant divide_by: integer := 651;
+
+-- For 1200 bps, divide_by = 5208;
+-- For 2400 bps, divide_by = 2604;
+-- For 4800 bps, divide_by = 1302;
+-- For 9600 bps, divide_by = 651;
+-- For 19200 bps, divide_by = 325;
+-- For 38400 bps, divide_by = 163;
+-- For 57600 bps, divide_by = 108;
+-- For 115200 bps, divide_by = 54;
+-- For 230400 bps, divide_by = 27;
+-- For 460800 bps, divide_by = 13;
+-- For 921600 bps, divide_by = 7;
+-- For 1 Mbps, divide_by = 6;
+
+-- At the higher frequencies, the resulting frequency of the clock output has less accuracy, so maybe
+-- there will be some problems with bit snchronization. If this is the case, it is recommended to obtain
+-- the needed frequency through another tupe of circuit, like a DLL or PLL
+
+signal count: integer range 0 to ((divide_by / 2) - 1);
+signal clk_out: std_logic;
+
+begin
+
+uart_clk <= clk_out;
+
+process (clk, reset, count, clk_out)
+begin
+ if reset = '1' then
+ clk_out <='0';
+ count <= 0;
+ elsif
+ clk='1' and clk'event then
+ if count = ((divide_by / 2) - 1) then
+ clk_out <= not clk_out;
+ count <= 0;
+ else count <= count+1;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
modbus/trunk/enlace/clock_generator_for_uart_rs232.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/enlace2_TB.vhd
===================================================================
--- modbus/trunk/enlace/enlace2_TB.vhd (nonexistent)
+++ modbus/trunk/enlace/enlace2_TB.vhd (revision 3)
@@ -0,0 +1,254 @@
+-- VHDL Test Bench Created from source file top_enlace.vhd -- 17:30:35 09/15/2010
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY top_enlace_enlace2_TB_vhd_tb IS
+END top_enlace_enlace2_TB_vhd_tb;
+
+ARCHITECTURE behavior OF top_enlace_enlace2_TB_vhd_tb IS
+
+ COMPONENT top_enlace
+ PORT(
+ clk : IN std_logic;
+ reset : IN std_logic;
+ Led : out std_logic_vector(7 downto 0); --nexys2
+ an : out std_logic_vector(3 downto 0); --nexys2
+ canalA: out std_logic_vector(7 downto 0); --nexys2
+ canalB: out std_logic_vector(7 downto 0); --nexys2
+ rxd : IN std_logic;
+ picoB_ok : IN std_logic;
+ addr_picoB : IN std_logic_vector(7 downto 0);
+ Eram_picoB : IN std_logic;
+ WEram_picoB : IN std_logic;
+ data_in_ram_picoB : IN std_logic_vector(7 downto 0);
+ cant_datos_picoB : IN std_logic_vector(7 downto 0);
+ error_uart : OUT std_logic;
+ error_lrc : OUT std_logic;
+ txd : OUT std_logic;
+ data_out_ram_picoB : OUT std_logic_vector(7 downto 0);
+ det_trama_ok_PB : out std_logic; --avisa cuando una trama est lista para usar
+ gen_trama_ok_PB : out std_logic --avisa cuando una trama fue enviada por la uart
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ signal Led : std_logic_vector(7 downto 0);
+ signal an : std_logic_vector(3 downto 0);
+ signal canalA: std_logic_vector(7 downto 0);
+ signal canalB: std_logic_vector(7 downto 0);
+ SIGNAL reset : std_logic;
+-- SIGNAL send_ram : std_logic;
+ SIGNAL rxd : std_logic;
+ SIGNAL error_uart : std_logic;
+ SIGNAL error_lrc : std_logic;
+-- SIGNAL leds : std_logic_vector(7 downto 0);
+ SIGNAL txd : std_logic;
+ SIGNAL picoB_ok : std_logic;
+ SIGNAL addr_picoB : std_logic_vector(7 downto 0);
+ SIGNAL Eram_picoB : std_logic;
+ SIGNAL WEram_picoB : std_logic;
+ SIGNAL data_in_ram_picoB : std_logic_vector(7 downto 0);
+ SIGNAL data_out_ram_picoB : std_logic_vector(7 downto 0);
+ SIGNAL cant_datos_picoB : std_logic_vector(7 downto 0);
+ SIGNAL det_trama_ok_PB : std_logic; --avisa cuando una trama est lista para usar
+ SIGNAL gen_trama_ok_PB : std_logic; --avisa cuando una trama fue enviada por la uart
+
+ signal comiezo : std_logic_vector(7 downto 0):= "01010101";
+ signal segundo : std_logic_vector(7 downto 0):= "11100111";
+ signal punto : std_logic_vector(7 downto 0):= "00101110";
+ signal dospuntos : std_logic_vector(7 downto 0):= "00111010"; --: ascii
+ signal cero : std_logic_vector(7 downto 0):= "00110000"; --0 ascii
+ signal uno : std_logic_vector(7 downto 0):= "00110001"; --1 ascii
+ signal dos : std_logic_vector(7 downto 0):= "00110010"; --2 ascii
+ signal tres : std_logic_vector(7 downto 0):= "00110011"; --3 ascii
+ signal cuatro : std_logic_vector(7 downto 0):= "00110100"; --4 ascii
+ signal cinco : std_logic_vector(7 downto 0):= "00110101"; --5 ascii
+ signal seis : std_logic_vector(7 downto 0):= "00110110"; --6 ascii
+ signal siete : std_logic_vector(7 downto 0):= "00110111"; --7 ascii
+ signal ocho : std_logic_vector(7 downto 0):= "00111000"; --8 ascii
+ signal nueve : std_logic_vector(7 downto 0):= "00111001"; --9 ascii
+ signal la_a : std_logic_vector(7 downto 0):= "01000001"; --A ascii
+ signal la_b : std_logic_vector(7 downto 0):= "01000010"; --B ascii
+ signal la_c : std_logic_vector(7 downto 0):= "01000011"; --C ascii
+ signal la_d : std_logic_vector(7 downto 0):= "01000100"; --D ascii
+ signal la_e : std_logic_vector(7 downto 0):= "01000101"; --E ascii
+ signal la_f : std_logic_vector(7 downto 0):= "01000110"; --F ascii
+ signal cr : std_logic_vector(7 downto 0):= "00001101"; --CR ascii
+ signal lf : std_logic_vector(7 downto 0):= "00001010"; --LF ascii
+
+ signal buffer_rx : std_logic_vector(7 downto 0):= "00000000";
+ type arreglo_datos is array (60 downto 0) of std_logic_vector (7 downto 0);
+ signal datos : arreglo_datos;
+
+ -- Clock period definitions
+ constant clk_period : time := 20ns;
+
+
+
+BEGIN
+
+ uut: top_enlace PORT MAP(
+ clk => clk,
+ reset => reset,
+ Led => Led,
+ an => an,
+ canalA => canalA,
+ canalB => canalB,
+ rxd => rxd,
+ error_uart => error_uart,
+ error_lrc => error_lrc,
+ txd => txd,
+ picoB_ok => picoB_ok,
+ addr_picoB => addr_picoB,
+ Eram_picoB => Eram_picoB,
+ WEram_picoB => WEram_picoB,
+ data_in_ram_picoB => data_in_ram_picoB,
+ data_out_ram_picoB => data_out_ram_picoB,
+ cant_datos_picoB => cant_datos_picoB,
+ det_trama_ok_PB => det_trama_ok_PB,
+ gen_trama_ok_PB => gen_trama_ok_PB
+ );
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+
+ wait for 100ns;
+ reset <= '1';
+ addr_picoB <= "00000011";
+ Eram_picoB <= '0';
+ picoB_ok <= '0';
+ wait for 100ns;
+ reset <= '0';
+
+--caracter erroneo 1
+ wait for 300us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= comiezo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+
+--caracter erroneo 2
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= segundo(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+--*************************************************
+-- RECEPCION
+--*************************************************
+ for j in 0 to 10 loop
+ --trama dos puntos
+ buffer_rx <= datos(j);
+ wait for 500us;
+ rxd <= '0';
+ wait for 104us;
+ for i in 0 to 7 loop
+ rxd <= buffer_rx(i);
+ wait for 104us;
+ end loop;
+ rxd <= '0';
+ wait for 104us;
+ rxd <= '1';
+ end loop;
+--*************************************************
+-- RESPUESTA PICOBLAZE
+--*************************************************
+ wait for 4ms;
+ cant_datos_picoB <= "00100000";--"00010000";
+ picoB_ok <= '1';
+ wait for 500ms;
+ picoB_ok <= '0';
+wait; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+datos(0) <= dospuntos;
+datos(1) <= uno;
+datos(2) <= uno;
+
+datos(3) <= cero;
+datos(4) <= uno;
+
+datos(5) <= cinco;--seis;
+datos(6) <= cinco;--siete;
+
+datos(7) <= siete;
+datos(8) <= la_d;
+
+datos(9) <= punto;
+datos(10) <= la_a;
+
+
+--datos(0) <= dospuntos;
+--datos(1) <= uno;
+--datos(2) <= uno;
+--
+--datos(3) <= cero;
+--datos(4) <= siete;
+--
+--datos(5) <= cuatro;
+--datos(6) <= seis;
+--
+--datos(7) <= la_a;
+--datos(8) <= la_b;
+--
+--datos(9) <= la_e;
+--datos(10) <= siete;
+--
+--datos(11) <= uno;
+--datos(12) <= seis;
+--
+--datos(13) <= uno;
+--datos(14) <= ocho;
+--
+--datos(15) <= siete;
+--datos(16) <= la_e;
+--
+--datos(17) <= cinco;
+--datos(18) <= la_f;
+--
+--datos(19) <= ocho;
+--datos(20) <= siete;
+--
+--datos(21) <= cero;
+--datos(22) <= cero;
+--
+--datos(23) <= uno;
+--datos(24) <= cero;
+--
+--datos(25) <= seis;
+--datos(26) <= la_d;
+--
+--datos(27) <= lf;
+--datos(20) <= la_a;--cr;
+
+END;
+
+
modbus/trunk/enlace/enlace2_TB.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modbus/trunk/enlace/det_top.vhd
===================================================================
--- modbus/trunk/enlace/det_top.vhd (nonexistent)
+++ modbus/trunk/enlace/det_top.vhd (revision 3)
@@ -0,0 +1,368 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 00:19:21 06/04/2010
+-- Design Name:
+-- Module Name: det_top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- TRAMA:
+-- The allowable characters transmitted for all other fields are hexadecimal 09, AF (ASCII coded). The devices monitor the bus
+-- continuously for the colon character(:). When this character is received, each device decodes the next character until it detects the
+-- End-Of-Frame(CR Y LF) --> (en ese orden).
+
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity det_top is
+ generic (
+ DIRE_LOCAL_ALTO : std_logic_vector(7 downto 0) := "00110001"; -- 1 ASCII
+ DIRE_LOCAL_BAJO : std_logic_vector(7 downto 0) := "00110001"; -- 1 ASCII
+ bits : integer := 8; -- ancho de datos de la memoria
+ addr_bits : integer := 8 -- 2^addr_bits = numero bits de direccionamiento
+ );
+ Port (
+ clk :in std_logic;
+ reset :in std_logic;
+ data :in std_logic_vector(7 downto 0);
+ new_data :in std_logic;
+ error :out std_logic;
+ end_det :out std_logic;
+--para escritura de ram:
+ E :out std_logic; -- habilitador de la ram
+ WE :out std_logic; -- habilitador de escritura
+ ADDR :out std_logic_vector(addr_bits-1 downto 0);
+ data_ram :out std_logic_vector(bits-1 downto 0)); --dato a guardar en ram
+end det_top;
+
+architecture Behavioral of det_top is
+
+--*******************************************************************
+-- DECLARACION COMPONENTE ASCII a BIN
+--*******************************************************************
+component ascii_bin
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ new_data :in std_logic;
+ Nnew_data :out std_logic;
+ ascii :in std_logic_vector(7 downto 0);
+ bin :out std_logic_vector(7 downto 0));
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE PONDERA
+--*******************************************************************
+component pondera_top
+ port(
+ clk: in std_logic;
+ reset: in std_logic;
+ bin_HL: in std_logic_vector(7 downto 0);
+ new_data: in std_logic;
+ trama_ok: in std_logic;
+ bin: out std_logic_vector(7 downto 0);
+ bin_ok: out std_logic
+ );
+end component;
+
+--*******************************************************************
+-- DECLARACION COMPONENTE CALCULO LRC
+--*******************************************************************
+component lrc
+ port(
+ clk :in std_logic;
+ reset :in std_logic;
+ trama :in std_logic;
+ dato_ok :in std_logic;
+ dato :in std_logic_vector(7 downto 0);
+ lrc_ok :out std_logic);
+end component;
+
+--*******************************************************************
+-- SEALES MAQUINA DE ESTADO
+--*******************************************************************
+
+ type state_type is (st1_det, st2_dire_alto, st3_dire_bajo, st4_comp, st5_func_alto, st6_func_bajo, st7_CR, st8_dato_y_LRC_rec, st9_LF);
+ signal state, next_state : state_type;
+
+ signal Scomp : std_logic:='0';
+ signal Serror : std_logic:='0';
+ signal SCR : std_logic_vector(7 downto 0):=(others => '0');
+ signal SLF : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sdire_bajo : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sdire_alto : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sfunc_bajo : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sfunc_alto : std_logic_vector(7 downto 0):=(others => '0');
+
+--*******************************************************************
+-- SEALES BLOQUE RAM
+--*******************************************************************
+ signal SEram : std_logic; -- habilitador de la ram
+ signal SEram_write : std_logic; -- habilitador de escritura
+ signal Sram_addr :std_logic_vector(addr_bits-1 downto 0):=(others=>'0') ;
+ signal Sdata_in_ram :std_logic_vector(bits-1 downto 0):=(others=>'0') ;
+--*************************************************************************
+-- seales para el detector de lrc bajo y alto
+--*************************************************************************
+ signal SQ1 : std_logic_vector(7 downto 0):=(others => '0');
+ signal SQ2 : std_logic_vector(7 downto 0):=(others => '0');
+
+ signal SsQ1 : std_logic:='0';
+ signal SsQ2 : std_logic:='0';
+ signal SsQ3 : std_logic:='0';
+ signal Sstate_bin : std_logic:='0';
+--*************************************************************************
+-- seales componente ascii a binario
+--*************************************************************************
+ signal Sascii : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sbin : std_logic_vector(7 downto 0):=(others => '0');
+ signal SNnew_data :std_logic:='0';
+
+--*************************************************************************
+-- seales componente pondera
+--*************************************************************************
+ signal Sbin_pond : std_logic_vector(7 downto 0):=(others => '0');
+ signal Sbin_ok_pond : std_logic:='0';
+ signal Strama_ok : std_logic:='0';
+
+--*************************************************************************
+-- seales componente calculador lrc
+--*************************************************************************
+
+ signal Sdata_ram :std_logic_vector(bits-1 downto 0):=(others=>'0');
+ signal Slrc_ok :std_logic :='0';
+
+begin
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE ASCII BINARIO
+--*******************************************************************
+ascii2bin: ascii_bin
+ port map(
+ clk => clk,
+ reset => reset,
+ new_data => new_data,
+ Nnew_data => SNnew_data,
+ ascii => Sascii,
+ bin => Sbin
+ );
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE PONDERA
+--*******************************************************************
+ponderacion: pondera_top
+ port map(
+ clk => clk,
+ reset => reset,
+ bin_HL => Sbin,
+ new_data => SNnew_data,
+ bin => Sdata_ram,
+ trama_ok => Strama_ok,
+ bin_ok => Sbin_ok_pond
+ );
+--*******************************************************************
+
+
+--*******************************************************************
+-- INSTANCIACION COMPONENTE CALCULAR LRC
+--*******************************************************************
+cal_lrc: lrc
+ port map(
+ clk => clk,
+ reset => reset,
+ trama => Strama_ok,
+ dato_ok => Sbin_ok_pond,
+ dato => Sdata_ram,
+ lrc_ok => Slrc_ok
+ );
+--*******************************************************************
+
+
+--*******************************************************************
+-- SINCRONIZMO DE LAS SALIDAS
+--*******************************************************************
+ SYNC_PROC: process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (reset = '1') then
+ state <= st1_det;
+ error <= '0';
+ else
+ state <= next_state;
+ error <= Serror;
+ -- assign other outputs to internal signals
+ end if;
+ end if;
+ end process;
+
+--*******************************************************************
+-- CODIFICACION ACCION EN LOS ESTADOS
+--*******************************************************************
+
+ --MEALY State-Machine - Outputs based on state and inputs
+ OUTPUT_DECODE: process (state, new_data)
+ begin
+ --insert statements to decode internal output signals
+ --below is simple example
+ if (state = st2_dire_alto and new_data = '1') then
+ Sdire_alto <= data;
+ Sascii <= data; -- a convertir y LRC
+ end if;
+
+ if (state = st3_dire_bajo and new_data = '1') then
+ Sdire_bajo <= data;
+ Sascii <= data; -- a convertir y LRC
+ end if;
+
+ if (state = st4_comp and Sdire_alto = DIRE_LOCAL_ALTO and Sdire_bajo = DIRE_LOCAL_BAJO) then -- direccin del esclavo
+ Scomp <= '1';
+ else
+ Scomp <= '0';
+ end if;
+
+ if (state = st5_func_alto and new_data = '1') then
+ Sfunc_alto <= data;
+ Sascii <= data; -- a convertir y LRC luego: Sdata_in_ram <= data;
+
+ end if;
+
+ if (state = st6_func_bajo and new_data = '1') then
+ Sfunc_bajo <= data;
+ Sascii <= data; -- a convertir y LRC luego: Sdata_in_ram <= data;
+ end if;
+
+ if (state = st7_CR and data = "01000110") then --"." ascii --CR en ASCII
+ SCR <= data;
+ end if;
+
+ if (state = st8_dato_y_LRC_rec and new_data = '1') then
+ Sascii <= data; -- a convertir y LRC luego: Sdata_in_ram <= data;
+ end if;
+
+ if (state = st9_LF and data = "01000001") then --A ascii--LF en ASCII
+ SLF <= data;
+ Serror <= Slrc_ok;
+ end_det <= '1';
+ else
+ end_det <= '0';
+ end if;
+
+ end process;
+
+--*******************************************************************
+-- CONDICION DE LOS ESTADOS A SEGUIR
+--*******************************************************************
+
+ NEXT_STATE_DECODE: process (state, new_data)
+ begin
+ --declare default state for next_state to avoid latches
+ next_state <= state; --default is to stay in current state
+ --insert statements to decode next_state
+ --below is a simple example
+ case (state) is
+ when st1_det =>
+ if new_data = '1' and data = "00111010" then -- : ASCII
+ next_state <= st2_dire_alto;
+ end if;
+ when st2_dire_alto =>
+ if new_data = '1' then
+ next_state <= st3_dire_bajo;
+ end if;
+ when st3_dire_bajo =>
+ if new_data = '1' then
+ next_state <= st4_comp;
+ end if;
+ when st4_comp =>
+ if Sdire_alto = DIRE_LOCAL_ALTO and Sdire_bajo = DIRE_LOCAL_BAJO then
+ next_state <= st5_func_alto;
+ else
+ next_state <= st1_det;
+ end if;
+ when st5_func_alto =>
+ if new_data = '1' then
+ next_state <= st6_func_bajo;
+ end if;
+ when st6_func_bajo =>
+ if new_data = '1' then
+ next_state <= st7_CR;
+ end if;
+ when st7_CR =>
+ if data = "00101110" then -- "." ascii --"00001010" then -- LF ASCII
+ next_state <= st9_LF;
+ else
+ next_state <= st8_dato_y_LRC_rec;
+ end if;
+ when st8_dato_y_LRC_rec =>
+ if new_data = '1' then
+ next_state <= st7_CR;
+ end if;
+ when st9_LF =>
+ if data = "01000001" then --A asci --"00001101" then -- CR ASCII
+ next_state <= st1_det;
+ end if;
+ when others =>
+ next_state <= st1_det;
+ end case;
+ end process;
+
+--**************Escritura en bloque ram*****************************
+SEram <= '1' when state = st8_dato_y_LRC_rec or state = st5_func_alto or state = st6_func_bajo else
+ '0';
+ADDR <= Sram_addr;
+data_ram <= Sdata_ram;
+
+
+
+--**************Escritura en bloque ram*****************************
+guardar_en_ram: process(clk,reset)
+begin
+ if reset = '1' or state = st1_det then
+ Sram_addr <= (others=>'0');
+ elsif clk'event and clk = '1' then
+ if Sbin_ok_pond = '1' then
+ Sram_addr <= Sram_addr +1;
+ end if;
+ end if;
+end process guardar_en_ram;
+WE <= Sbin_ok_pond;
+--*************************************************************************
+
+
+Strama_ok <= '1' when state /= st1_det and state /= st9_LF and data /= "00111010" else
+ '0';
+E <= Strama_ok;
+
+process(clk, reset)
+begin
+ if (reset = '1') then
+ SsQ1 <= '0';
+ SsQ2 <= '0';
+ SsQ3 <= '0';
+ elsif (clk'event and clk = '1') then
+ SsQ1 <= Sstate_bin;
+ SsQ2 <= SsQ1;
+ SsQ3 <= SsQ2;
+ end if;
+end process;
+Sstate_bin <= '1' when state = st9_LF else
+ '0';
+end Behavioral;
+
modbus/trunk/enlace/det_top.vhd
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+*
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