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URL https://opencores.org/ocsvn/or1200gct/or1200gct/trunk

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/tags/arelease/or1200.tk
0,0 → 1,2105
#//////////////////////////////////////////////////////////////////////
#//// ////
#//// OR1200 graphic configuration tool ////
#//// ////
#//// Description ////
#//// Graphic configuration tool for OR1200 core ////
#//// ////
#//// To Do: ////
#//// - find bugs ////
#//// ////
#//// Author(s): ////
#//// - Javier Castillo, jcastillo@opencores.org ////
#//// ////
#//////////////////////////////////////////////////////////////////////
#//// ////
#//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
#//// ////
#//// This source file may be used and distributed without ////
#//// restriction provided that this copyright statement is not ////
#//// removed from the file and that any derivative work contains ////
#//// the original copyright notice and the associated disclaimer. ////
#//// ////
#//// This source file is free software; you can redistribute it ////
#//// and/or modify it under the terms of the GNU Lesser General ////
#//// Public License as published by the Free Software Foundation; ////
#//// either version 2.1 of the License, or (at your option) any ////
#//// later version. ////
#//// ////
#//// This source is distributed in the hope that it will be ////
#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
#//// PURPOSE. See the GNU Lesser General Public License for more ////
#//// details. ////
#//// ////
#//// You should have received a copy of the GNU Lesser General ////
#//// Public License along with this source; if not, download it ////
#//// from http://www.opencores.org/lgpl.shtml ////
#//// ////
#//////////////////////////////////////////////////////////////////////
#//
#// CVS Revision History
#//
#// $Log: not supported by cvs2svn $
 
 
#Defines variables for parameters and its default values
 
 
proc defaultvals { } {
global ASIC
global VCD_DUMP
global VERBOSE
global targetFPGA
global targetASIC
global ASIC_MULTP2_32X32
global BIST
global RF_RAM
 
#Wishbone defines
global REGISTERED_OUTPUTS
global REGISTERED_INPUTS
global NO_BURSTS
global WB_RETRY
global WB_CAB
global WB_B3
global CLKDIV2_SUPPORT
global CLKDIV4_SUPPORT
#Misc
global ADDITIONAL_SYNOPSYS_DIRECTIVES
global CASE_DEFAULT
global IMPL_MEM2REG
 
#IU defines
global SR_EPH_DEF
global IMPL_ADDC
global IMPL_CY
global ADDITIONAL_FLAG_MODIFIERS
global IMPL_DIV
global IMPL_ALU_ROTATE
global MULT_IMPLEMENTED
global LWPWR_MULT
global ALU_COMP
#PM defines
global PM_IMPLEMENTED
global PM_READREGS
global PM_UNUSED_ZERO
global PM_PARTIAL_DECODING
 
#DU defines
global DU_IMPLEMENTED
global DU_HWBKPTS
global DU_TB_IMPLEMENTED
global DU_READREGS
global DU_UNUSED_ZERO
global DU_STATUS_UNIMPLEMENTED
 
#PIC defines
global PIC_IMPLEMENTED
global PIC_READREGS
global PIC_UNUSED_ZERO
global PIC_PICMR
global PIC_PICSR
global PIC_INTS
#TT defines
global TT_IMPLEMENTED
global TT_TTMR
global TT_TTSR
global TT_READREGS
#IC CACHES
global NO_IC
global IC_WAYS
global IC_SIZE
global ICLS
#DC defines
global NO_DC
global DC_WAYS
global DC_SIZE
global DCLS
global SB_IMPLEMENTED
global SB_ENTRIES
global SB_LOG
#MMU defines
global NO_IMMU
global NO_DMMU
#QMEM defines
global QMEM_IMPLEMENTED
global QMEM_BSEL
global QMEM_ACK
#MISC defines
global MAC_IMPLEMENTED
global MAC_SPR_WE
global CFGR_IMPLEMENTED
global SYS_FULL_DECODE
#Target defines
set ASIC 0
set VCD_DUMP 0
set VERBOSE 0
set targetFPGA XILINX_RAMB4
set targetASIC VIRTUALSILICON_SSP
set ASIC_MULTP2_32X32 0
set BIST 0
set RF_RAM 2
 
#Wishbone defines
set REGISTERED_OUTPUTS 1
set REGISTERED_INPUTS 0
set NO_BURSTS 0
set WB_RETRY 0
set WB_CAB 1
set WB_B3 0
set CLKDIV2_SUPPORT 1
set CLKDIV4_SUPPORT 0
#Misc
set ADDITIONAL_SYNOPSYS_DIRECTIVES 0
set CASE_DEFAULT 1
set IMPL_MEM2REG 1
 
#IU defines
set SR_EPH_DEF 0
set IMPL_ADDC 1
set IMPL_CY 1
set ADDITIONAL_FLAG_MODIFIERS 0
set IMPL_DIV 0
set IMPL_ALU_ROTATE 0
set MULT_IMPLEMENTED 1
set LWPWR_MULT 0
set ALU_COMP 2
 
#PM defines
set PM_IMPLEMENTED 1
set PM_READREGS 1
set PM_UNUSED_ZERO 1
set PM_PARTIAL_DECODING 1
 
#DU defines
set DU_IMPLEMENTED 1
set DU_HWBKPTS 0
if { $ASIC==0 && ( $targetFPGA=="XILINX_RAMB4" || $targetFPGA=="XILINX_RAM32x1D" ) } {
set DU_TB_IMPLEMENTED 1
} else {
set DU_TB_IMPLEMENTED 0
}
set DU_READREGS 1
set DU_UNUSED_ZERO 1
set DU_STATUS_UNIMPLEMENTED 1
 
#PIC defines
set PIC_IMPLEMENTED 1
set PIC_READREGS 1
set PIC_UNUSED_ZERO 1
set PIC_PICMR 1
set PIC_PICSR 1
set PIC_INTS 20
 
#TT defines
set TT_IMPLEMENTED 1
set TT_TTMR 1
set TT_TTSR 1
set TT_READREGS 1
 
#IC defines
set NO_IC 0
set IC_WAYS 1
set IC_SIZE 8KB
set ICLS 16
 
#DC defines
set NO_DC 0
set DC_WAYS 1
set DC_SIZE 8KB
set DCLS 16
set SB_IMPLEMENTED 0
set SB_ENTRIES 4
set SB_LOG 2
#MMU defines
set NO_IMMU 0
set NO_DMMU 0
 
#QMEM defines
set QMEM_IMPLEMENTED 0
set QMEM_BSEL 0
set QMEM_ACK 0
 
#MISC defines
set MAC_IMPLEMENTED 1
set MAC_SPR_WE 1
set CFGR_IMPLEMENTED 1
set SYS_FULL_DECODE 1
}
 
 
#Target memories
lappend memFPGA "GENERIC" "ALTERA_LPM" "XILINX_RAMB4" "XILINX_RAM32x1D" "USE_RAM16x1D_FOR_RAM32X1D"
lappend memASIC "GENERIC" "ARTISAN_SSP" "ARTISAN_SDP" "ARTISAN_STP" "VIRTUALSILICON_SSP" "VIRTUALSILICON_STP_T1" "VIRTUALSILICON_STP_T2"
 
 
 
 
proc confFPGA { } {
 
global memFPGA
global ASIC_MULTP2_32X32
global targetFPGA
global RF_RAM
 
destroy .screen.memframe
destroy .screen.multframe
destroy .screen.bistframe
destroy .screen.rfframe
 
#Create a frame for the memory type selection
frame .screen.memframe -bd 2 -relief groove
pack .screen.memframe -side left -padx 2m -pady 2m
label .screen.memframe.meml -text "Target FPGA memories"
pack .screen.memframe.meml -side top
 
#Create the list for memories
set i 1
 
foreach mem $memFPGA {
radiobutton .screen.memframe.b$i -text $mem -variable targetFPGA -value $mem
pack .screen.memframe.b$i -side top -anchor w
incr i 1
}
 
#Create a frame for Register File memory type
frame .screen.rfframe -bd 2 -relief groove
pack .screen.rfframe -side top -padx 2m -pady 2m
label .screen.rfframe.rflab1 -text "Type of Register File RAM"
pack .screen.rfframe.rflab1 -side top
radiobutton .screen.rfframe.rf1 -text "Generic (flip-flop based) " -variable RF_RAM -value 0
radiobutton .screen.rfframe.rf2 -text "Two port RAM" -variable RF_RAM -value 1
radiobutton .screen.rfframe.rf3 -text "Dual port RAM" -variable RF_RAM -value 2
pack .screen.rfframe.rf1 .screen.rfframe.rf2 .screen.rfframe.rf3 -side top -anchor w
 
 
#Create a frame for the multiplier type selection
set ASIC_MULTP2_32X32 0
frame .screen.multframe -bd 2 -relief groove
pack .screen.multframe -side left -padx 2m -pady 2m
label .screen.multframe.multl -text "Multiplier"
pack .screen.multframe.multl -side top
radiobutton .screen.multframe.rmul1 -text "GENERIC 32x32 MULTIPLIER" -variable ASIC_MULTP2_32X32 -value 0
pack .screen.multframe.rmul1 -side top -anchor w
 
 
 
}
 
 
proc confASIC { } {
#Global var with all the posible target memories for ASIC
global memASIC
global targetASIC
global ASIC_MULTP2_32X32
global RF_RAM
 
destroy .screen.memframe
destroy .screen.multframe
destroy .screen.bistframe
destroy .screen.rfframe
 
#Create a frame for the memory type selection
frame .screen.memframe -bd 2 -relief groove
pack .screen.memframe -side left -padx 2m -pady 2m
label .screen.memframe.meml -text "Target ASIC memories"
pack .screen.memframe.meml -side top
 
#Create the list for memories
set i 1
 
foreach mem $memASIC {
radiobutton .screen.memframe.b$i -text $mem -variable targetASIC -value $mem
pack .screen.memframe.b$i -side top -anchor w
incr i 1
}
 
#Create a frame for Register File memory type
frame .screen.rfframe -bd 2 -relief groove
pack .screen.rfframe -side top -padx 2m -pady 2m
label .screen.rfframe.rflab1 -text "Type of Register File RAM"
pack .screen.rfframe.rflab1 -side top
radiobutton .screen.rfframe.rf1 -text "Generic (flip-flop based) " -variable RF_RAM -value 0
radiobutton .screen.rfframe.rf2 -text "Two port RAM" -variable RF_RAM -value 1
radiobutton .screen.rfframe.rf3 -text "Dual port RAM" -variable RF_RAM -value 2
pack .screen.rfframe.rf1 .screen.rfframe.rf2 .screen.rfframe.rf3 -side top -anchor w
 
 
#Create a frame for the multiplier type selection
frame .screen.multframe -bd 2 -relief groove
pack .screen.multframe -side top -padx 2m -pady 2m
label .screen.multframe.multl -text "Multiplier"
pack .screen.multframe.multl -side top
radiobutton .screen.multframe.rmul1 -text "GENERIC 32x32 MULTIPLIER" -variable ASIC_MULTP2_32X32 -value 0
radiobutton .screen.multframe.rmul2 -text "ASIC 32x32 MULTIPLIER" -variable ASIC_MULTP2_32X32 -value 1
pack .screen.multframe.rmul1 -side top -anchor w
pack .screen.multframe.rmul2 -side top -anchor w
 
 
}
 
 
 
proc about { } {
toplevel .dabout -class Dialog
wm title .dabout About
wm iconname .dabout Dialog
frame .dabout.top -relief raised -bd 1
pack .dabout.top -side top -fill both
frame .dabout.bot -relief raised -bd 1
pack .dabout.bot -side bottom -fill both
message .dabout.top.msg -width 5i -font -Adobe-Times-Medium-R-Normal-*-180-* -text "OpenRisc 1200 graphic configuration tool"
message .dabout.top.msg2 -width 5i -font -Adobe-Times-Medium-R-Normal-*-180-* -text "jcastillo@opensocdesign.com"
message .dabout.top.msg3 -width 5i -font -Adobe-Times-Medium-R-Normal-*-180-* -text "Version 0.1"
pack .dabout.top.msg .dabout.top.msg2 .dabout.top.msg3 -side top -expand 1 -fill both -padx 3m -pady 3m
}
proc confOR1200 { } {
 
destroy .d
 
toplevel .d -class Dialog
wm title .d "OpenRISC 1200 Core Configuration"
frame .d.left -relief raised -bd 1 -relief flat
frame .d.right -relief raised -bd 1 -relief flat
pack .d.left -side left -fill both
pack .d.right -side right -fill both
#Add buttons
button .d.left.iub -text "Integer Unit" -command { confIU }
button .d.left.icb -text "Instruction Cache" -command { confIC }
button .d.left.dcb -text "Data Cache" -command { confDC }
button .d.left.mmub -text "MMU" -command { confMMU }
button .d.left.dub -text "Debug Unit" -command { confDU }
button .d.left.pmb -text "Power Management" -command { confPM }
button .d.right.picb -text "PIC" -command { confPIC }
button .d.right.ttb -text "Tick Timer" -command { confTT }
button .d.right.qmb -text "Quick Embedded Memory" -command { confQM }
button .d.right.mcb -text "Misc" -command { confMISC }
button .d.right.exb -text "Exit" -command { destroy .d }
pack .d.left.iub .d.left.icb .d.left.dcb .d.left.mmub -padx 10m -fill x
pack .d.left.dub .d.left.pmb .d.right.picb -padx 10m -fill x
pack .d.right.ttb .d.right.qmb .d.right.mcb .d.right.exb -padx 10m -fill x
 
}
proc confIU { } {
 
destroy .diu
destroy .dmi
 
toplevel .diu -class Dialog
wm title .diu "Integer Unit"
frame .diu.top -relief raised -bd 1 -relief flat
frame .diu.top2 -relief raised -bd 1 -relief groove
frame .diu.top3 -relief raised -bd 1 -relief groove
frame .diu.top4 -relief raised -bd 1 -relief groove
frame .diu.top5 -relief raised -bd 1 -relief groove
frame .diu.top6 -relief raised -bd 1 -relief groove
frame .diu.top7 -relief raised -bd 1 -relief groove
frame .diu.top8 -relief raised -bd 1 -relief groove
frame .diu.top9 -relief raised -bd 1 -relief groove
frame .diu.top10 -relief raised -bd 1 -relief groove
frame .diu.top11 -relief raised -bd 1 -relief groove
 
pack .diu.top -side top -fill both
pack .diu.top2 -side top -fill both
pack .diu.top3 -side top -fill both
pack .diu.top4 -side top -fill both
pack .diu.top5 -side top -fill both
pack .diu.top6 -side top -fill both
pack .diu.top7 -side top -fill both
pack .diu.top8 -side top -fill both
pack .diu.top9 -side top -fill both
pack .diu.top10 -side top -fill both
pack .diu.top11 -side top -fill both
 
label .diu.top.opl -text "OpenRISC 1200 Integer Unit Configuration" -relief raised
pack .diu.top.opl -side top -pady 5m -padx 10m
 
radiobutton .diu.top2.flashy -text y -variable SR_EPH_DEF -value 1
radiobutton .diu.top2.flashn -text n -variable SR_EPH_DEF -value 0
pack .diu.top2.flashy .diu.top2.flashn -side left
 
radiobutton .diu.top3.addcy -text y -variable IMPL_ADDC -value 1
radiobutton .diu.top3.addcn -text n -variable IMPL_ADDC -value 0
pack .diu.top3.addcy .diu.top3.addcn -side left
 
radiobutton .diu.top4.cyy -text y -variable IMPL_CY -value 1
radiobutton .diu.top4.cyn -text n -variable IMPL_CY -value 0
pack .diu.top4.cyy .diu.top4.cyn -side left
 
radiobutton .diu.top5.addcompy -text y -variable ADDITIONAL_FLAG_MODIFIERS -value 1
radiobutton .diu.top5.addcompn -text n -variable ADDITIONAL_FLAG_MODIFIERS -value 0
pack .diu.top5.addcompy .diu.top5.addcompn -side left
 
radiobutton .diu.top6.divy -text y -variable IMPL_DIV -value 1
radiobutton .diu.top6.divn -text n -variable IMPL_DIV -value 0
pack .diu.top6.divy .diu.top6.divn -side left
 
radiobutton .diu.top7.roty -text y -variable IMPL_ALU_ROTATE -value 1
radiobutton .diu.top7.rotn -text n -variable IMPL_ALU_ROTATE -value 0
pack .diu.top7.roty .diu.top7.rotn -side left
 
radiobutton .diu.top8.muly -text y -variable MULT_IMPLEMENTED -value 1
radiobutton .diu.top8.muln -text n -variable MULT_IMPLEMENTED -value 0
pack .diu.top8.muly .diu.top8.muln -side left
radiobutton .diu.top9.lpmuly -text y -variable LWPWR_MULT -value 1
radiobutton .diu.top9.lpmuln -text n -variable LWPWR_MULT -value 0
pack .diu.top9.lpmuly .diu.top9.lpmuln -side left
 
radiobutton .diu.top10.comp1 -text 1 -variable ALU_COMP -value 1
radiobutton .diu.top10.comp2 -text 2 -variable ALU_COMP -value 2
pack .diu.top10.comp1 .diu.top10.comp2 -side left
label .diu.top2.flashl -text " Exception vectors in FLASH"
label .diu.top3.addcl -text " Implement l.addc instruction"
label .diu.top4.cyl -text " Implement carry bit SR\[CY\]"
label .diu.top5.fml -text " Add operations set compare flag when result is zero"
label .diu.top6.divl -text " Implement optional l.div/l.divu operations"
label .diu.top7.rotl -text " Implement rotate in the ALU"
label .diu.top8.mull -text " Implement multiplier"
label .diu.top9.lpmull -text " Low power multiplier"
label .diu.top10.compl -text " Type of ALU compare to implement"
 
pack .diu.top2.flashl .diu.top3.addcl .diu.top4.cyl .diu.top5.fml .diu.top6.divl .diu.top7.rotl .diu.top8.mull .diu.top9.lpmull .diu.top10.compl -side left
 
 
frame .diu.top11.left -relief raised -bd 1 -relief flat
frame .diu.top11.right -relief raised -bd 1 -relief flat
pack .diu.top11.left -side left -fill both
pack .diu.top11.right -side right -fill both
button .diu.top11.left.nextb -text "Next" -command { confIC }
button .diu.top11.right.exitb -text "Exit" -command { destroy .diu }
 
pack .diu.top11.left.nextb -side top -padx 10m -pady 5m -fill x
pack .diu.top11.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
proc confPM { } {
 
destroy .dpm
destroy .ddu
toplevel .dpm -class Dialog
wm title .dpm "Power Management"
wm iconname .dpm Dialog
frame .dpm.top -relief raised -bd 1 -relief flat
frame .dpm.top2 -relief raised -bd 1 -relief groove
frame .dpm.top3 -relief raised -bd 1 -relief groove
frame .dpm.top4 -relief raised -bd 1 -relief groove
frame .dpm.top5 -relief raised -bd 1 -relief groove
frame .dpm.top6 -relief raised -bd 1 -relief groove
 
pack .dpm.top -side top -fill both
pack .dpm.top2 -side top -fill both
pack .dpm.top3 -side top -fill both
pack .dpm.top4 -side top -fill both
pack .dpm.top5 -side top -fill both
pack .dpm.top6 -side top -fill both
 
label .dpm.top.opl -text "OpenRISC 1200 Power Management Configuration" -relief raised
pack .dpm.top.opl -side top -pady 5m -padx 10m
radiobutton .dpm.top2.imply -text y -variable PM_IMPLEMENTED -value 1
radiobutton .dpm.top2.impln -text n -variable PM_IMPLEMENTED -value 0
pack .dpm.top2.imply .dpm.top2.impln -side left
 
radiobutton .dpm.top3.ready -text y -variable PM_READREGS -value 1
radiobutton .dpm.top3.readn -text n -variable PM_READREGS -value 0
pack .dpm.top3.ready .dpm.top3.readn -side left
 
radiobutton .dpm.top4.unusedy -text y -variable PM_UNUSED_ZERO -value 1
radiobutton .dpm.top4.unusedn -text n -variable PM_UNUSED_ZERO -value 0
pack .dpm.top4.unusedy .dpm.top4.unusedn -side left
radiobutton .dpm.top5.pary -text y -variable PM_PARTIAL_DECODING -value 1
radiobutton .dpm.top5.parn -text n -variable PM_PARTIAL_DECODING -value 0
pack .dpm.top5.pary .dpm.top5.parn -side left
label .dpm.top2.impll -text " Power Management Unit Implemented"
label .dpm.top3.readl -text " Read PMR is allowed"
label .dpm.top4.unusedl -text " Unused PMR bits should be zero"
label .dpm.top5.parl -text " PMR can be read/written at any address inside PM group"
pack .dpm.top2.impll -side left
pack .dpm.top3.readl -side left
pack .dpm.top4.unusedl -side left
pack .dpm.top5.parl -side left
 
frame .dpm.top6.left -relief raised -bd 1 -relief flat
frame .dpm.top6.right -relief raised -bd 1 -relief flat
pack .dpm.top6.left -side left -fill both
pack .dpm.top6.right -side right -fill both
button .dpm.top6.left.nextb -text "Next" -command { confPIC }
button .dpm.top6.right.exitb -text "Exit" -command { destroy .dpm }
 
pack .dpm.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dpm.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
proc confDU { } {
 
global ASIC
global targetFPGA
 
 
destroy .dmu
destroy .ddu
toplevel .ddu -class Dialog
wm title .ddu "Debug Unit"
wm iconname .ddu Dialog
frame .ddu.top -relief raised -bd 1 -relief flat
frame .ddu.top2 -relief raised -bd 1 -relief groove
frame .ddu.top3 -relief raised -bd 1 -relief groove
frame .ddu.top4 -relief raised -bd 1 -relief groove
frame .ddu.top5 -relief raised -bd 1 -relief groove
frame .ddu.top6 -relief raised -bd 1 -relief groove
frame .ddu.top7 -relief raised -bd 1 -relief groove
frame .ddu.top8 -relief raised -bd 1 -relief groove
 
pack .ddu.top -side top -fill both
pack .ddu.top2 -side top -fill both
pack .ddu.top3 -side top -fill both
pack .ddu.top4 -side top -fill both
pack .ddu.top5 -side top -fill both
pack .ddu.top6 -side top -fill both
pack .ddu.top7 -side top -fill both
pack .ddu.top8 -side top -fill both
 
label .ddu.top.opl -text "OpenRISC 1200 Debug Unit Configuration" -relief raised
pack .ddu.top.opl -side top -pady 5m -padx 10m
radiobutton .ddu.top2.imply -text y -variable DU_IMPLEMENTED -value 1
radiobutton .ddu.top2.impln -text n -variable DU_IMPLEMENTED -value 0
pack .ddu.top2.imply .ddu.top2.impln -side left
 
radiobutton .ddu.top3.hwby -text y -variable DU_HWBKPTS -value 1
radiobutton .ddu.top3.hwbn -text n -variable DU_HWBKPTS -value 0
pack .ddu.top3.hwby .ddu.top3.hwbn -side left
 
 
#Trace buffer option only if Virtex FPGA selected
if { $ASIC==0 && ( $targetFPGA=="XILINX_RAMB4" || $targetFPGA=="XILINX_RAM32x1D" ) } {
radiobutton .ddu.top4.tby -text y -variable DU_TB_IMPLEMENTED -value 1
radiobutton .ddu.top4.tbn -text n -variable DU_TB_IMPLEMENTED -value 0
pack .ddu.top4.tby .ddu.top4.tbn -side left
 
label .ddu.top4.bufl -text " Trace Buffer implemented (Only for Xilinx FPGA)"
pack .ddu.top4.bufl -side left
} else {
set DU_TB_IMPLEMENTED 0
}
radiobutton .ddu.top5.ready -text y -variable DU_READREGS -value 1
radiobutton .ddu.top5.readn -text n -variable DU_READREGS -value 0
pack .ddu.top5.ready .ddu.top5.readn -side left
 
radiobutton .ddu.top6.unusedy -text y -variable DU_UNUSED_ZERO -value 1
radiobutton .ddu.top6.unusedn -text n -variable DU_UNUSED_ZERO -value 0
pack .ddu.top6.unusedy .ddu.top6.unusedn -side left
 
radiobutton .ddu.top7.ifstaty -text y -variable DU_STATUS_UNIMPLEMENTED -value 1
radiobutton .ddu.top7.ifstatn -text n -variable DU_STATUS_UNIMPLEMENTED -value 0
pack .ddu.top7.ifstaty .ddu.top7.ifstatn -side left
 
label .ddu.top2.impll -text " Debug Unit Implemented"
label .ddu.top3.hwbl -text " Hardware breakpoints implemented"
label .ddu.top5.readl -text " Read DU registers is allowed"
label .ddu.top6.unusedl -text " Unused DU registers bits should be zero"
label .ddu.top7.ifstatl -text " IF/LSU status is not needed by devel I/F"
pack .ddu.top2.impll -side left
pack .ddu.top3.hwbl -side left
pack .ddu.top5.readl -side left
pack .ddu.top6.unusedl -side left
pack .ddu.top7.ifstatl -side left
 
 
frame .ddu.top8.left -relief raised -bd 1 -relief flat
frame .ddu.top8.right -relief raised -bd 1 -relief flat
pack .ddu.top8.left -side left -fill both
pack .ddu.top8.right -side right -fill both
button .ddu.top8.left.nextb -text "Next" -command { confPM }
button .ddu.top8.right.exitb -text "Exit" -command { destroy .ddu }
 
pack .ddu.top8.left.nextb -side top -padx 10m -pady 5m -fill x
pack .ddu.top8.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
proc confPIC { } {
destroy .dpic
destroy .dpm
 
toplevel .dpic -class Dialog
wm title .dpic "PIC"
wm iconname .dpic Dialog
frame .dpic.top -relief raised -bd 1 -relief flat
frame .dpic.top2 -relief raised -bd 1 -relief groove
frame .dpic.top3 -relief raised -bd 1 -relief groove
frame .dpic.top4 -relief raised -bd 1 -relief groove
frame .dpic.top5 -relief raised -bd 1 -relief groove
frame .dpic.top6 -relief raised -bd 1 -relief groove
frame .dpic.top7 -relief raised -bd 1 -relief groove
frame .dpic.top8 -relief raised -bd 1 -relief groove
 
pack .dpic.top -side top -fill both
pack .dpic.top2 -side top -fill both
pack .dpic.top3 -side top -fill both
pack .dpic.top4 -side top -fill both
pack .dpic.top5 -side top -fill both
pack .dpic.top6 -side top -fill both
pack .dpic.top7 -side top -fill both
pack .dpic.top8 -side top -fill both
 
 
label .dpic.top.opl -text "OpenRISC 1200 PIC Configuration" -relief raised
pack .dpic.top.opl -side top -pady 5m -padx 10m
radiobutton .dpic.top2.imply -text y -variable PIC_IMPLEMENTED -value 1
radiobutton .dpic.top2.impln -text n -variable PIC_IMPLEMENTED -value 0
pack .dpic.top2.imply .dpic.top2.impln -side left
 
entry .dpic.top3.entry1 -width 3 -relief sunken -bd 2 -textvariable PIC_INTS
pack .dpic.top3.entry1 -side left
 
radiobutton .dpic.top4.ready -text y -variable PIC_READREGS -value 1
radiobutton .dpic.top4.readn -text n -variable PIC_READREGS -value 0
pack .dpic.top4.ready .dpic.top4.readn -side left
 
radiobutton .dpic.top5.unusedy -text y -variable PIC_UNUSED_ZERO -value 1
radiobutton .dpic.top5.unusedn -text n -variable PIC_UNUSED_ZERO -value 0
pack .dpic.top5.unusedy .dpic.top5.unusedn -side left
radiobutton .dpic.top6.mry -text y -variable PIC_PICMR -value 1
radiobutton .dpic.top6.mrn -text n -variable PIC_PICMR -value 0
pack .dpic.top6.mry .dpic.top6.mrn -side left
radiobutton .dpic.top7.sry -text y -variable PIC_PICSR -value 1
radiobutton .dpic.top7.srn -text n -variable PIC_PICSR -value 0
pack .dpic.top7.sry .dpic.top7.srn -side left
label .dpic.top2.impll -text " PIC Implemented"
label .dpic.top3.numl -text " Number of interrupt inputs (2-31)"
label .dpic.top4.unusedl -text " Read PIC registers is allowed"
label .dpic.top5.parl -text " Unused PIC bits should be zero"
label .dpic.top6.mrl -text " Implement PICMR register"
label .dpic.top7.srl -text " Implement PICSR register"
pack .dpic.top2.impll -side left
pack .dpic.top3.numl -side left
pack .dpic.top4.unusedl -side left
pack .dpic.top5.parl -side left
pack .dpic.top6.mrl -side left
pack .dpic.top7.srl -side left
 
frame .dpic.top8.left -relief raised -bd 1 -relief flat
frame .dpic.top8.right -relief raised -bd 1 -relief flat
pack .dpic.top8.left -side left -fill both
pack .dpic.top8.right -side right -fill both
button .dpic.top8.left.nextb -text "Next" -command { confTT }
button .dpic.top8.right.exitb -text "Exit" -command { destroy .dpic }
 
pack .dpic.top8.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dpic.top8.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
 
proc confTT { } {
 
destroy .dpic
destroy .dtt
toplevel .dtt -class Dialog
wm title .dtt "Tick Timer"
wm iconname .dtt Dialog
frame .dtt.top -relief raised -bd 1 -relief flat
frame .dtt.top2 -relief raised -bd 1 -relief groove
frame .dtt.top3 -relief raised -bd 1 -relief groove
frame .dtt.top4 -relief raised -bd 1 -relief groove
frame .dtt.top5 -relief raised -bd 1 -relief groove
frame .dtt.top6 -relief raised -bd 1 -relief groove
 
pack .dtt.top -side top -fill both
pack .dtt.top2 -side top -fill both
pack .dtt.top3 -side top -fill both
pack .dtt.top4 -side top -fill both
pack .dtt.top5 -side top -fill both
pack .dtt.top6 -side top -fill both
 
 
label .dtt.top.opl -text "OpenRISC 1200 Tick Timer Configuration" -relief raised
pack .dtt.top.opl -side top -pady 5m -padx 10m
radiobutton .dtt.top2.imply -text y -variable TT_IMPLEMENTED -value 1
radiobutton .dtt.top2.impln -text n -variable TT_IMPLEMENTED -value 0
pack .dtt.top2.imply .dtt.top2.impln -side left
 
radiobutton .dtt.top3.mry -text y -variable TT_TTMR -value 1
radiobutton .dtt.top3.mrn -text n -variable TT_TTMR -value 0
pack .dtt.top3.mry .dtt.top3.mrn -side left
radiobutton .dtt.top4.sry -text y -variable TT_TTSR -value 1
radiobutton .dtt.top4.srn -text n -variable TT_TTSR -value 0
pack .dtt.top4.sry .dtt.top4.srn -side left
 
radiobutton .dtt.top5.ready -text y -variable TT_READREGS -value 1
radiobutton .dtt.top5.readn -text n -variable TT_READREGS -value 0
pack .dtt.top5.ready .dtt.top5.readn -side left
 
label .dtt.top2.impll -text " Tick Timer Implemented"
label .dtt.top3.mrl -text " Implement TTMR register"
label .dtt.top4.srl -text " Implement TTSR register"
label .dtt.top5.readl -text " Read TT registers is allowed"
pack .dtt.top2.impll -side left
pack .dtt.top3.mrl -side left
pack .dtt.top4.srl -side left
pack .dtt.top5.readl -side left
 
 
frame .dtt.top6.left -relief raised -bd 1 -relief flat
frame .dtt.top6.right -relief raised -bd 1 -relief flat
pack .dtt.top6.left -side left -fill both
pack .dtt.top6.right -side right -fill both
button .dtt.top6.left.nextb -text "Next" -command { confQM }
button .dtt.top6.right.exitb -text "Exit" -command { destroy .dtt }
 
pack .dtt.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dtt.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
proc confIC { } {
 
global IC_WAYS
global IC_SIZE
global ICLS
 
destroy .diu
destroy .dic
toplevel .dic -class Dialog
wm title .dic "Instruction Cache"
wm iconname .dic Dialog
frame .dic.top -relief raised -bd 1 -relief flat
frame .dic.top2 -relief raised -bd 1 -relief groove
frame .dic.top3 -relief raised -bd 1 -relief groove
frame .dic.top4 -relief raised -bd 1 -relief groove
frame .dic.top5 -relief raised -bd 1 -relief groove
frame .dic.top6 -relief raised -bd 1 -relief groove
 
pack .dic.top -side top -fill both
pack .dic.top2 -side top -fill both
pack .dic.top3 -side top -fill both
pack .dic.top4 -side top -fill both
pack .dic.top5 -side top -fill both
pack .dic.top6 -side top -fill both
 
 
label .dic.top.opl -text "OpenRISC 1200 Instruction Cache Configuration" -relief raised
pack .dic.top.opl -side top -pady 5m -padx 10m
radiobutton .dic.top2.imply -text y -variable NO_IC -value 0
radiobutton .dic.top2.impln -text n -variable NO_IC -value 1
pack .dic.top2.imply .dic.top2.impln -side left
 
menubutton .dic.top3.ways -text Ways -menu .dic.top3.ways.menu -relief raised
pack .dic.top3.ways -side left -fill both
menu .dic.top3.ways.menu
.dic.top3.ways.menu add radiobutton -label "1" -variable IC_WAYS -value 1
tk_menuBar .dic.top3.ways
menubutton .dic.top4.size -text Size -menu .dic.top4.size.menu -relief raised
pack .dic.top4.size -side left -fill both
menu .dic.top4.size.menu
.dic.top4.size.menu add radiobutton -label "512B" -variable IC_SIZE -value 512B
.dic.top4.size.menu add radiobutton -label "4KB" -variable IC_SIZE -value 4KB
.dic.top4.size.menu add radiobutton -label "8KB" -variable IC_SIZE -value 8KB
tk_menuBar .dic.top4.size
menubutton .dic.top5.lcls -text "Line Size" -menu .dic.top5.lcls.menu -relief raised
pack .dic.top5.lcls -side left -fill both
menu .dic.top5.lcls.menu
.dic.top5.lcls.menu add radiobutton -label "8" -variable ICLS -value 8
.dic.top5.lcls.menu add radiobutton -label "16" -variable ICLS -value 16
tk_menuBar .dic.top5.lcls
label .dic.top2.impll -text " Instruction Cache Implemented"
label .dic.top3.wayl -text " Instruction Cache Ways"
label .dic.top4.sizel -text " Instruction Cache Size"
label .dic.top5.lclsl -text " Instruction Cache Line Size in bytes"
pack .dic.top2.impll -side left
pack .dic.top3.wayl -side left
pack .dic.top4.sizel -side left
pack .dic.top5.lclsl -side left
 
frame .dic.top6.left -relief raised -bd 1 -relief flat
frame .dic.top6.right -relief raised -bd 1 -relief flat
pack .dic.top6.left -side left -fill both
pack .dic.top6.right -side right -fill both
button .dic.top6.left.nextb -text "Next" -command { confDC }
button .dic.top6.right.exitb -text "Exit" -command { destroy .dic }
 
pack .dic.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dic.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
 
proc confDC { } {
 
global DC_WAYS
global DC_SIZE
global DCLS
 
destroy .ddc
destroy .dic
toplevel .ddc -class Dialog
wm title .ddc "Data Cache"
wm iconname .ddc Dialog
frame .ddc.top -relief raised -bd 1 -relief flat
frame .ddc.top2 -relief raised -bd 1 -relief groove
frame .ddc.top3 -relief raised -bd 1 -relief groove
frame .ddc.top4 -relief raised -bd 1 -relief groove
frame .ddc.top5 -relief raised -bd 1 -relief groove
frame .ddc.top6 -relief raised -bd 1 -relief groove
frame .ddc.top7 -relief raised -bd 1 -relief groove
frame .ddc.top8 -relief raised -bd 1 -relief groove
frame .ddc.top9 -relief raised -bd 1 -relief groove
frame .ddc.top10 -relief raised -bd 1 -relief groove
 
 
pack .ddc.top -side top -fill both
pack .ddc.top2 -side top -fill both
pack .ddc.top3 -side top -fill both
pack .ddc.top4 -side top -fill both
pack .ddc.top5 -side top -fill both
pack .ddc.top6 -side top -fill both
pack .ddc.top7 -side top -fill both
pack .ddc.top8 -side top -fill both
pack .ddc.top9 -side top -fill both
pack .ddc.top10 -side top -fill both
 
label .ddc.top.opl -text "OpenRISC 1200 Data Cache Configuration" -relief raised
pack .ddc.top.opl -side top -pady 5m -padx 10m
radiobutton .ddc.top2.imply -text y -variable NO_DC -value 0
radiobutton .ddc.top2.impln -text n -variable NO_DC -value 1
pack .ddc.top2.imply .ddc.top2.impln -side left
 
menubutton .ddc.top3.ways -text Ways -menu .ddc.top3.ways.menu -relief raised
pack .ddc.top3.ways -side left -fill both
menu .ddc.top3.ways.menu
.ddc.top3.ways.menu add radiobutton -label "1" -variable DC_WAYS -value 1
tk_menuBar .ddc.top3.ways
menubutton .ddc.top4.size -text Size -menu .ddc.top4.size.menu -relief raised
pack .ddc.top4.size -side left -fill both
menu .ddc.top4.size.menu
.ddc.top4.size.menu add radiobutton -label "4KB" -variable DC_SIZE -value 4KB
.ddc.top4.size.menu add radiobutton -label "8KB" -variable DC_SIZE -value 8KB
tk_menuBar .ddc.top4.size
menubutton .ddc.top5.lcls -text "Line Size" -menu .ddc.top5.lcls.menu -relief raised
pack .ddc.top5.lcls -side left -fill both
menu .ddc.top5.lcls.menu
.ddc.top5.lcls.menu add radiobutton -label "8" -variable DCLS -value 8
.ddc.top5.lcls.menu add radiobutton -label "16" -variable DCLS -value 16
tk_menuBar .ddc.top5.lcls
label .ddc.top6.opl -text "OpenRISC 1200 Store Buffer Configuration" -relief raised
pack .ddc.top6.opl -side top -pady 5m -padx 10m
radiobutton .ddc.top7.imply -text y -variable SB_IMPLEMENTED -value 1
radiobutton .ddc.top7.impln -text n -variable SB_IMPLEMENTED -value 0
pack .ddc.top7.imply .ddc.top7.impln -side left
menubutton .ddc.top8.sbs -text "Store Buffer Size" -menu .ddc.top8.sbs.menu -relief raised
pack .ddc.top8.sbs -side left -fill both
menu .ddc.top8.sbs.menu
.ddc.top8.sbs.menu add radiobutton -label "4" -variable SB_ENTRIES -value 4 -command { set SB_LOG 2 }
.ddc.top8.sbs.menu add radiobutton -label "8" -variable SB_ENTRIES -value 8 -command { set SB_LOG 3 }
tk_menuBar .ddc.top8.sbs
label .ddc.top2.impll -text " Data Cache Implemented"
label .ddc.top3.wayl -text " Data Cache Ways"
label .ddc.top4.sizel -text " Data Cache Size"
label .ddc.top5.lclsl -text " Data Cache Line Size in bytes"
label .ddc.top7.impl -text " Enable Store Buffer"
label .ddc.top8.sbel -text " Store Buffer Entries"
pack .ddc.top2.impll -side left
pack .ddc.top3.wayl -side left
pack .ddc.top4.sizel -side left
pack .ddc.top5.lclsl -side left
pack .ddc.top7.impl -side left
pack .ddc.top8.sbel -side left
 
frame .ddc.top10.left -relief raised -bd 1 -relief flat
frame .ddc.top10.right -relief raised -bd 1 -relief flat
pack .ddc.top10.left -side left -fill both
pack .ddc.top10.right -side right -fill both
button .ddc.top10.left.nextb -text "Next" -command { confMMU }
button .ddc.top10.right.exitb -text "Exit" -command { destroy .ddc }
 
pack .ddc.top10.left.nextb -side top -padx 10m -pady 5m -fill x
pack .ddc.top10.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
 
proc confQM { } {
 
destroy .dqm
destroy .dtt
toplevel .dqm -class Dialog
wm title .dqm "Quick Embedded Memory"
wm iconname .dqm Dialog
frame .dqm.top -relief raised -bd 1 -relief flat
frame .dqm.top2 -relief raised -bd 1 -relief groove
frame .dqm.top3 -relief raised -bd 1 -relief groove
frame .dqm.top4 -relief raised -bd 1 -relief groove
frame .dqm.top6 -relief raised -bd 1 -relief groove
 
pack .dqm.top -side top -fill both
pack .dqm.top2 -side top -fill both
pack .dqm.top3 -side top -fill both
pack .dqm.top4 -side top -fill both
pack .dqm.top6 -side top -fill both
 
 
label .dqm.top.opl -text "OpenRISC 1200 Quick Embedded Memory Configuration" -relief raised
pack .dqm.top.opl -side top -pady 5m -padx 10m
radiobutton .dqm.top2.imply -text y -variable QMEM_IMPLEMENTED -value 1
radiobutton .dqm.top2.impln -text n -variable QMEM_IMPLEMENTED -value 0
pack .dqm.top2.imply .dqm.top2.impln -side left
 
radiobutton .dqm.top3.sely -text y -variable QMEM_BSEL -value 1
radiobutton .dqm.top3.seln -text n -variable QMEM_BSEL -value 0
pack .dqm.top3.sely .dqm.top3.seln -side left
radiobutton .dqm.top4.acky -text y -variable QMEM_ACK -value 1
radiobutton .dqm.top4.ackn -text n -variable QMEM_ACK -value 0
pack .dqm.top4.acky .dqm.top4.ackn -side left
label .dqm.top2.impll -text " Implement Quick Embedded Memory"
label .dqm.top3.sell -text " Enable qmem_sel* ports"
label .dqm.top4.ackl -text " Enable qmem_ack port"
pack .dqm.top2.impll -side left
pack .dqm.top3.sell -side left
pack .dqm.top4.ackl -side left
 
frame .dqm.top6.left -relief raised -bd 1 -relief flat
frame .dqm.top6.right -relief raised -bd 1 -relief flat
pack .dqm.top6.left -side left -fill both
pack .dqm.top6.right -side right -fill both
button .dqm.top6.left.nextb -text "Next" -command { confMISC }
button .dqm.top6.right.exitb -text "Exit" -command { destroy .dqm }
 
pack .dqm.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dqm.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
 
proc confMMU { } {
 
destroy .dmu
destroy .ddc
toplevel .dmu -class Dialog
wm title .dmu "MMU"
wm iconname .dmu Dialog
frame .dmu.top -relief raised -bd 1 -relief flat
frame .dmu.top2 -relief raised -bd 1 -relief groove
frame .dmu.top3 -relief raised -bd 1 -relief groove
frame .dmu.top6 -relief raised -bd 1 -relief groove
 
pack .dmu.top -side top -fill both
pack .dmu.top2 -side top -fill both
pack .dmu.top3 -side top -fill both
pack .dmu.top6 -side top -fill both
 
 
label .dmu.top.opl -text "OpenRISC 1200 MMU Configuration" -relief raised
pack .dmu.top.opl -side top -pady 5m -padx 10m
radiobutton .dmu.top2.imply -text y -variable NO_IMMU -value 0
radiobutton .dmu.top2.impln -text n -variable NO_IMMU -value 1
pack .dmu.top2.imply .dmu.top2.impln -side left
 
 
radiobutton .dmu.top3.imply -text y -variable NO_DMMU -value 0
radiobutton .dmu.top3.impln -text n -variable NO_DMMU -value 1
pack .dmu.top3.imply .dmu.top3.impln -side left
label .dmu.top2.impll -text " Implement Instruction MMU"
label .dmu.top3.impll -text " Implement Data MMU"
pack .dmu.top2.impll -side left
pack .dmu.top3.impll -side left
 
 
frame .dmu.top6.left -relief raised -bd 1 -relief flat
frame .dmu.top6.right -relief raised -bd 1 -relief flat
pack .dmu.top6.left -side left -fill both
pack .dmu.top6.right -side right -fill both
button .dmu.top6.left.nextb -text "Next" -command { confDU }
button .dmu.top6.right.exitb -text "Exit" -command { destroy .dmu }
 
pack .dmu.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dmu.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
 
proc confMISC { } {
 
destroy .dmi
destroy .dqm
toplevel .dmi -class Dialog
wm title .dmi "Misc"
wm iconname .dmi Dialog
frame .dmi.top -relief raised -bd 1 -relief flat
frame .dmi.top2 -relief raised -bd 1 -relief groove
frame .dmi.top3 -relief raised -bd 1 -relief groove
frame .dmi.top4 -relief raised -bd 1 -relief groove
frame .dmi.top5 -relief raised -bd 1 -relief groove
frame .dmi.top6 -relief raised -bd 1 -relief groove
 
pack .dmi.top -side top -fill both
pack .dmi.top2 -side top -fill both
pack .dmi.top3 -side top -fill both
pack .dmi.top4 -side top -fill both
pack .dmi.top5 -side top -fill both
pack .dmi.top6 -side top -fill both
 
 
label .dmi.top.opl -text "OpenRISC 1200 Miscellaneous Configuration" -relief raised
pack .dmi.top.opl -side top -pady 5m -padx 10m
radiobutton .dmi.top2.imply -text y -variable MAC_IMPLEMENTED -value 1
radiobutton .dmi.top2.impln -text n -variable MAC_IMPLEMENTED -value 0
pack .dmi.top2.imply .dmi.top2.impln -side left
 
radiobutton .dmi.top3.macwey -text y -variable MAC_SPR_WE -value 1
radiobutton .dmi.top3.macwen -text n -variable MAC_SPR_WE -value 0
pack .dmi.top3.macwey .dmi.top3.macwen -side left
radiobutton .dmi.top4.imply -text y -variable CFGR_IMPLEMENTED -value 1
radiobutton .dmi.top4.impln -text n -variable CFGR_IMPLEMENTED -value 0
pack .dmi.top4.imply .dmi.top4.impln -side left
radiobutton .dmi.top5.sysy -text y -variable SYS_FULL_DECODE -value 1
radiobutton .dmi.top5.sysn -text n -variable SYS_FULL_DECODE -value 0
pack .dmi.top5.sysy .dmi.top5.sysn -side left
 
label .dmi.top2.impll -text " Implement Multiply and Accumulate (MAC) Unit"
label .dmi.top3.macwel -text " MACLO/MACHI registers are writable"
label .dmi.top4.impll -text " Implement configuration registers"
label .dmi.top5.sysl -text " Full address decode inside SYS group"
pack .dmi.top2.impll -side left
pack .dmi.top3.macwel -side left
pack .dmi.top4.impll -side left
pack .dmi.top5.sysl -side left
 
frame .dmi.top6.left -relief raised -bd 1 -relief flat
frame .dmi.top6.right -relief raised -bd 1 -relief flat
pack .dmi.top6.left -side left -fill both
pack .dmi.top6.right -side right -fill both
button .dmi.top6.left.nextb -text "Next" -command { confIU }
button .dmi.top6.right.exitb -text "Exit" -command { destroy .dmi }
 
pack .dmi.top6.left.nextb -side top -padx 10m -pady 5m -fill x
pack .dmi.top6.right.exitb -side top -padx 10m -pady 5m -fill x
 
}
proc saveconfdialog { } {
 
destroy .dsaveconf
toplevel .dsaveconf -class Dialog
wm title .dsaveconf "Save Configuration"
wm iconname .dsaveconf Dialog
frame .dsaveconf.top -relief raised -bd 1
pack .dsaveconf.top -side top -fill both
frame .dsaveconf.bot -relief raised -bd 1
pack .dsaveconf.bot -side top -fill both
 
 
label .dsaveconf.top.fn -text "Enter Filename" -relief raised
pack .dsaveconf.top.fn -side left -pady 5m -padx 10m
 
entry .dsaveconf.top.entry1 -width 20 -relief sunken -bd 2 -textvariable savefilename
pack .dsaveconf.top.entry1 -side left -pady 5m -padx 10m
frame .dsaveconf.bot.left -relief raised -bd 1 -relief flat
frame .dsaveconf.bot.right -relief raised -bd 1 -relief flat
pack .dsaveconf.bot.left -side left -fill both
pack .dsaveconf.bot.right -side right -fill both
button .dsaveconf.bot.left.okb -text "OK" -command { saveconf $savefilename }
button .dsaveconf.bot.right.cancelb -text "Cancel" -command { destroy .dsaveconf }
 
pack .dsaveconf.bot.left.okb -side top -padx 10m -pady 5m -fill x
pack .dsaveconf.bot.right.cancelb -side top -padx 10m -pady 5m -fill x
 
 
}
 
proc saveconf { file } {
 
global ASIC
global VCD_DUMP
global VERBOSE
global targetFPGA
global targetASIC
global ASIC_MULTP2_32X32
global BIST
global RF_RAM
#Wishbone defines
global REGISTERED_OUTPUTS
global REGISTERED_INPUTS
global NO_BURSTS
global WB_RETRY
global WB_CAB
global WB_B3
global CLKDIV2_SUPPORT
global CLKDIV4_SUPPORT
#Misc
global ADDITIONAL_SYNOPSYS_DIRECTIVES
global CASE_DEFAULT
global IMPL_MEM2REG
#IU defines
global SR_EPH_DEF
global IMPL_ADDC
global IMPL_CY
global ADDITIONAL_FLAG_MODIFIERS
global IMPL_DIV
global IMPL_ALU_ROTATE
global MULT_IMPLEMENTED
global LWPWR_MULT
global ALU_COMP
#PM defines
global PM_IMPLEMENTED
global PM_READREGS
global PM_UNUSED_ZERO
global PM_PARTIAL_DECODING
#DU defines
global DU_IMPLEMENTED
global DU_HWBKPTS
global DU_TB_IMPLEMENTED
global DU_READREGS
global DU_UNUSED_ZERO
global DU_STATUS_UNIMPLEMENTED
#PIC defines
global PIC_IMPLEMENTED
global PIC_READREGS
global PIC_UNUSED_ZERO
global PIC_PICMR
global PIC_PICSR
global PIC_INTS
#TT defines
global TT_IMPLEMENTED
global TT_TTMR
global TT_TTSR
global TT_READREGS
#IC CACHES
global NO_IC
global IC_WAYS
global IC_SIZE
global ICLS
#DC defines
global NO_DC
global DC_WAYS
global DC_SIZE
global DCLS
global SB_IMPLEMENTED
global SB_ENTRIES
global SB_LOG
#MMU defines
global NO_IMMU
global NO_DMMU
#QMEM defines
global QMEM_IMPLEMENTED
global QMEM_BSEL
global QMEM_ACK
#MISC defines
global MAC_IMPLEMENTED
global MAC_SPR_WE
global CFGR_IMPLEMENTED
global SYS_FULL_DECODE
 
set errorno [catch { set f [open $file w] } errorname ]
 
if { $errorno != 0 } {
errorfile
return
}
 
 
puts $f $ASIC
puts $f $VCD_DUMP
puts $f $VERBOSE
puts $f $targetFPGA
puts $f $targetASIC
puts $f $ASIC_MULTP2_32X32
puts $f $BIST
puts $f $RF_RAM
 
#Wishbone defines
puts $f $REGISTERED_OUTPUTS
puts $f $REGISTERED_INPUTS
puts $f $NO_BURSTS
puts $f $WB_RETRY
puts $f $WB_CAB
puts $f $WB_B3
puts $f $CLKDIV2_SUPPORT
puts $f $CLKDIV4_SUPPORT
#Misc
puts $f $ADDITIONAL_SYNOPSYS_DIRECTIVES
puts $f $CASE_DEFAULT
puts $f $IMPL_MEM2REG
 
#IU defines
puts $f $SR_EPH_DEF
puts $f $IMPL_ADDC
puts $f $IMPL_CY
puts $f $ADDITIONAL_FLAG_MODIFIERS
puts $f $IMPL_DIV
puts $f $IMPL_ALU_ROTATE
puts $f $MULT_IMPLEMENTED
puts $f $LWPWR_MULT
puts $f $ALU_COMP
#PM defines
puts $f $PM_IMPLEMENTED
puts $f $PM_READREGS
puts $f $PM_UNUSED_ZERO
puts $f $PM_PARTIAL_DECODING
 
#DU defines
puts $f $DU_IMPLEMENTED
puts $f $DU_HWBKPTS
puts $f $DU_TB_IMPLEMENTED
puts $f $DU_READREGS
puts $f $DU_UNUSED_ZERO
puts $f $DU_STATUS_UNIMPLEMENTED
 
#PIC defines
puts $f $PIC_IMPLEMENTED
puts $f $PIC_READREGS
puts $f $PIC_UNUSED_ZERO
puts $f $PIC_PICMR
puts $f $PIC_PICSR
puts $f $PIC_INTS
#TT defines
puts $f $TT_IMPLEMENTED
puts $f $TT_TTMR
puts $f $TT_TTSR
puts $f $TT_READREGS
#IC CACHES
puts $f $NO_IC
puts $f $IC_WAYS
puts $f $IC_SIZE
puts $f $ICLS
#DC defines
puts $f $NO_DC
puts $f $DC_WAYS
puts $f $DC_SIZE
puts $f $DCLS
puts $f $SB_IMPLEMENTED
puts $f $SB_ENTRIES
puts $f $SB_LOG
#MMU defines
puts $f $NO_IMMU
puts $f $NO_DMMU
#QMEM defines
puts $f $QMEM_IMPLEMENTED
puts $f $QMEM_BSEL
puts $f $QMEM_ACK
#MISC defines
puts $f $MAC_IMPLEMENTED
puts $f $MAC_SPR_WE
puts $f $CFGR_IMPLEMENTED
puts $f $SYS_FULL_DECODE
 
 
 
close $f
destroy .dsaveconf
 
}
 
proc loadconfdialog { } {
 
destroy .dloadconf
toplevel .dloadconf -class Dialog
wm title .dloadconf "Load Configuration"
wm iconname .dloadconf Dialog
frame .dloadconf.top -relief raised -bd 1
pack .dloadconf.top -side top -fill both
frame .dloadconf.bot -relief raised -bd 1
pack .dloadconf.bot -side top -fill both
 
 
label .dloadconf.top.fn -text "Enter Filename" -relief raised
pack .dloadconf.top.fn -side left -pady 5m -padx 10m
 
entry .dloadconf.top.entry1 -width 20 -relief sunken -bd 2 -textvariable loadfilename
pack .dloadconf.top.entry1 -side left -pady 5m -padx 10m
frame .dloadconf.bot.left -relief raised -bd 1 -relief flat
frame .dloadconf.bot.right -relief raised -bd 1 -relief flat
pack .dloadconf.bot.left -side left -fill both
pack .dloadconf.bot.right -side right -fill both
button .dloadconf.bot.left.okb -text "OK" -command { loadconf $loadfilename }
button .dloadconf.bot.right.cancelb -text "Cancel" -command { destroy .dloadconf }
 
pack .dloadconf.bot.left.okb -side top -padx 10m -pady 5m -fill x
pack .dloadconf.bot.right.cancelb -side top -padx 10m -pady 5m -fill x
 
 
}
 
proc loadconf { file } {
 
global ASIC
global VCD_DUMP
global VERBOSE
global targetFPGA
global targetASIC
global ASIC_MULTP2_32X32
global BIST
global RF_RAM
#Wishbone defines
global REGISTERED_OUTPUTS
global REGISTERED_INPUTS
global NO_BURSTS
global WB_RETRY
global WB_CAB
global WB_B3
global CLKDIV2_SUPPORT
global CLKDIV4_SUPPORT
#Misc
global ADDITIONAL_SYNOPSYS_DIRECTIVES
global CASE_DEFAULT
global IMPL_MEM2REG
#IU defines
global SR_EPH_DEF
global IMPL_ADDC
global IMPL_CY
global ADDITIONAL_FLAG_MODIFIERS
global IMPL_DIV
global IMPL_ALU_ROTATE
global MULT_IMPLEMENTED
global LWPWR_MULT
global ALU_COMP
#PM defines
global PM_IMPLEMENTED
global PM_READREGS
global PM_UNUSED_ZERO
global PM_PARTIAL_DECODING
#DU defines
global DU_IMPLEMENTED
global DU_HWBKPTS
global DU_TB_IMPLEMENTED
global DU_READREGS
global DU_UNUSED_ZERO
global DU_STATUS_UNIMPLEMENTED
#PIC defines
global PIC_IMPLEMENTED
global PIC_READREGS
global PIC_UNUSED_ZERO
global PIC_PICMR
global PIC_PICSR
global PIC_INTS
#TT defines
global TT_IMPLEMENTED
global TT_TTMR
global TT_TTSR
global TT_READREGS
#IC CACHES
global NO_IC
global IC_WAYS
global IC_SIZE
global ICLS
#DC defines
global NO_DC
global DC_WAYS
global DC_SIZE
global DCLS
global SB_IMPLEMENTED
global SB_ENTRIES
global SB_LOG
#MMU defines
global NO_IMMU
global NO_DMMU
#QMEM defines
global QMEM_IMPLEMENTED
global QMEM_BSEL
global QMEM_ACK
#MISC defines
global MAC_IMPLEMENTED
global MAC_SPR_WE
global CFGR_IMPLEMENTED
global SYS_FULL_DECODE
 
set errorno [catch { set f [open $file r] } errorname ]
 
if { $errorno != 0 } {
errorfile
return
}
 
 
set ASIC [gets $f]
set VCD_DUMP [gets $f]
set VERBOSE [gets $f]
set targetFPGA [gets $f]
set targetASIC [gets $f]
set ASIC_MULTP2_32X32 [gets $f]
set BIST [gets $f]
set RF_RAM [gets $f]
 
#Wishbone defines
set REGISTERED_OUTPUTS [gets $f]
set REGISTERED_INPUTS [gets $f]
set NO_BURSTS [gets $f]
set WB_RETRY [gets $f]
set WB_CAB [gets $f]
set WB_B3 [gets $f]
set CLKDIV2_SUPPORT [gets $f]
set CLKDIV4_SUPPORT [gets $f]
#Misc
set ADDITIONAL_SYNOPSYS_DIRECTIVES [gets $f]
set CASE_DEFAULT [gets $f]
set IMPL_MEM2REG [gets $f]
 
#IU defines
set SR_EPH_DEF [gets $f]
set IMPL_ADDC [gets $f]
set IMPL_CY [gets $f]
set ADDITIONAL_FLAG_MODIFIERS [gets $f]
set IMPL_DIV [gets $f]
set IMPL_ALU_ROTATE [gets $f]
set MULT_IMPLEMENTED [gets $f]
set LWPWR_MULT [gets $f]
set ALU_COMP [gets $f]
#PM defines
set PM_IMPLEMENTED [gets $f]
set PM_READREGS [gets $f]
set PM_UNUSED_ZERO [gets $f]
set PM_PARTIAL_DECODING [gets $f]
 
#DU defines
set DU_IMPLEMENTED [gets $f]
set DU_HWBKPTS [gets $f]
set DU_TB_IMPLEMENTED [gets $f]
set DU_READREGS [gets $f]
set DU_UNUSED_ZERO [gets $f]
set DU_STATUS_UNIMPLEMENTED [gets $f]
 
#PIC defines
set PIC_IMPLEMENTED [gets $f]
set PIC_READREGS [gets $f]
set PIC_UNUSED_ZERO [gets $f]
set PIC_PICMR [gets $f]
set PIC_PICSR [gets $f]
set PIC_INTS [gets $f]
#TT defines
set TT_IMPLEMENTED [gets $f]
set TT_TTMR [gets $f]
set TT_TTSR [gets $f]
set TT_READREGS [gets $f]
#IC CACHES
set NO_IC [gets $f]
set IC_WAYS [gets $f]
set IC_SIZE [gets $f]
set ICLS [gets $f]
#DC defines
set NO_DC [gets $f]
set DC_WAYS [gets $f]
set DC_SIZE [gets $f]
set DCLS [gets $f]
set SB_IMPLEMENTED [gets $f]
set SB_ENTRIES [gets $f]
set SB_LOG [gets $f]
#MMU defines
set NO_IMMU [gets $f]
set NO_DMMU [gets $f]
#QMEM defines
set QMEM_IMPLEMENTED [gets $f]
set QMEM_BSEL [gets $f]
set QMEM_ACK [gets $f]
#MISC defines
set MAC_IMPLEMENTED [gets $f]
set MAC_SPR_WE [gets $f]
set CFGR_IMPLEMENTED [gets $f]
set SYS_FULL_DECODE [gets $f]
 
 
 
close $f
destroy .dloadconf
 
}
proc export { } {
 
 
global ASIC
global VCD_DUMP
global VERBOSE
global targetFPGA
global targetASIC
global ASIC_MULTP2_32X32
global BIST
global RF_RAM
#Wishbone defines
global REGISTERED_OUTPUTS
global REGISTERED_INPUTS
global NO_BURSTS
global WB_RETRY
global WB_CAB
global WB_B3
global CLKDIV2_SUPPORT
global CLKDIV4_SUPPORT
#Misc
global ADDITIONAL_SYNOPSYS_DIRECTIVES
global CASE_DEFAULT
global IMPL_MEM2REG
#IU defines
global SR_EPH_DEF
global IMPL_ADDC
global IMPL_CY
global ADDITIONAL_FLAG_MODIFIERS
global IMPL_DIV
global IMPL_ALU_ROTATE
global MULT_IMPLEMENTED
global LWPWR_MULT
global ALU_COMP
#PM defines
global PM_IMPLEMENTED
global PM_READREGS
global PM_UNUSED_ZERO
global PM_PARTIAL_DECODING
#DU defines
global DU_IMPLEMENTED
global DU_HWBKPTS
global DU_TB_IMPLEMENTED
global DU_READREGS
global DU_UNUSED_ZERO
global DU_STATUS_UNIMPLEMENTED
#PIC defines
global PIC_IMPLEMENTED
global PIC_READREGS
global PIC_UNUSED_ZERO
global PIC_PICMR
global PIC_PICSR
global PIC_INTS
#TT defines
global TT_IMPLEMENTED
global TT_TTMR
global TT_TTSR
global TT_READREGS
#IC CACHES
global NO_IC
global IC_WAYS
global IC_SIZE
global ICLS
#DC defines
global NO_DC
global DC_WAYS
global DC_SIZE
global DCLS
global SB_IMPLEMENTED
global SB_ENTRIES
global SB_LOG
#MMU defines
global NO_IMMU
global NO_DMMU
#QMEM defines
global QMEM_IMPLEMENTED
global QMEM_BSEL
global QMEM_ACK
#MISC defines
global MAC_IMPLEMENTED
global MAC_SPR_WE
global CFGR_IMPLEMENTED
global SYS_FULL_DECODE
set errorno [catch { set f [open "or1200_config.v" w] } errorname ]
 
if { $errorno != 0 } {
errorfile
return
}
 
if { $ASIC == 1 } {
puts $f {`define OR1200_ASIC}
}
if { $VCD_DUMP == 1 } {
puts $f {`define OR1200_VCD_DUMP }
}
if { $VERBOSE == 1 } {
puts $f {`define OR1200_VERBOSE }
}
 
 
puts $f "`define OR1200_$targetFPGA "
puts $f "`define OR1200_$targetASIC "
 
if { $ASIC_MULTP2_32X32 == 1 } {
puts $f {`define OR1200_ASIC_MULTP2_32X32 }
} else {
puts $f {`define OR1200_GENERIC_MULTP2_32X32 }
}
 
if {$ASIC == 1 && ($targetASIC=="VIRTUALSILICON_SSP" | $targetASIC=="VIRTUALSILICON_STP_T1" | $targetASIC=="VIRTUALSILICON_STP_T2")} {
if { $BIST == 1 } {
puts $f {`define OR1200_BIST }
}
}
 
if { $RF_RAM == 0 } {
puts $f {`define OR1200_RFRAM_GENERIC }
} elseif { $RF_RAM == 1 } {
puts $f {`define OR1200_RFRAM_TWOPORT }
} else {
puts $f {`define OR1200_RFRAM_DUALPORT }
}
 
 
#Wishbone defines
if { $REGISTERED_OUTPUTS==1 } {
puts $f {`define OR1200_REGISTERED_OUTPUTS }
}
if { $REGISTERED_INPUTS==1 } {
puts $f {`define OR1200_REGISTERED_INPUTS }
}
if { $NO_BURSTS==1 } {
puts $f {`define OR1200_NO_BURSTS }
}
if { $WB_RETRY==1 } {
puts $f {`define OR1200_WB_RETRY }
}
if { $WB_CAB==1 } {
puts $f {`define OR1200_WB_CAB }
}
if { $WB_B3==1 } {
puts $f {`define OR1200_WB_B3 }
}
if { $CLKDIV2_SUPPORT==1 } {
puts $f {`define OR1200_CLKDIV2_SUPPORT }
}
if { $CLKDIV4_SUPPORT==1 } {
puts $f {`define OR1200_CLKDIV4_SUPPORT }
}
 
#Misc
if { $ADDITIONAL_SYNOPSYS_DIRECTIVES==1 } {
puts $f {`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES }
}
if { $CASE_DEFAULT==1 } {
puts $f {`define OR1200_CASE_DEFAULT }
}
if { $IMPL_MEM2REG==1 } {
puts $f {`define OR1200_IMPL_MEM2REG1 }
} else {
puts $f {`define OR1200_IMPL_MEM2REG2 }
}
 
#IU defines
 
if { $SR_EPH_DEF==1 } {
puts $f {`define OR1200_SR_EPH_DEF }
}
if { $IMPL_ADDC==1 } {
puts $f {`define OR1200_IMPL_ADDC }
}
if { $IMPL_CY==1 } {
puts $f {`define OR1200_IMPL_CY }
}
if { $ADDITIONAL_FLAG_MODIFIERS==1 } {
puts $f {`define OR1200_ADDITIONAL_FLAG_MODIFIERS }
}
if { $IMPL_DIV==1 } {
puts $f {`define OR1200_IMPL_DIV }
}
if { $IMPL_ALU_ROTATE==1 } {
puts $f {`define OR1200_IMPL_ALU_ROTATE }
}
if { $MULT_IMPLEMENTED==1 } {
puts $f {`define OR1200_MULT_IMPLEMENTED }
}
if { $LWPWR_MULT==1 } {
puts $f {`define OR1200_LWPWR_MULT }
}
if { $ALU_COMP==1 } {
puts $f {`define OR1200_ALU_COMP }
}
#PM defines
if { $PM_IMPLEMENTED==1 } {
puts $f {`define OR1200_PM_IMPLEMENTED }
}
if { $PM_READREGS==1 } {
puts $f {`define OR1200_PM_READREGS }
}
if { $PM_UNUSED_ZERO==1 } {
puts $f {`define OR1200_PM_UNUSED_ZERO }
}
if { $PM_PARTIAL_DECODING==1 } {
puts $f {`define OR1200_PM_PARTIAL_DECODING }
}
 
#DU defines
if { $DU_IMPLEMENTED==1 } {
puts $f {`define OR1200_DU_IMPLEMENTED }
}
if { $DU_HWBKPTS==1 } {
puts $f {`define OR1200_DU_HWBKPTS }
}
if { $DU_TB_IMPLEMENTED==1 } {
puts $f {`define OR1200_DU_TB_IMPLEMENTED }
}
if { $DU_READREGS==1 } {
puts $f {`define OR1200_DU_READREGS }
}
if { $DU_UNUSED_ZERO==1 } {
puts $f {`define OR1200_DU_UNUSED_ZERO }
}
if { $DU_STATUS_UNIMPLEMENTED==1 } {
puts $f {`define OR1200_DU_STATUS_UNIMPLEMENTED }
}
 
 
#PIC defines
if { $PIC_IMPLEMENTED==1 } {
puts $f {`define OR1200_PIC_IMPLEMENTED }
}
if { $PIC_READREGS==1 } {
puts $f {`define OR1200_PIC_READREGS }
}
if { $PIC_UNUSED_ZERO==1 } {
puts $f {`define OR1200_PIC_UNUSED_ZERO }
}
if { $PIC_PICMR==1 } {
puts $f {`define OR1200_PIC_PICMR }
}
if { $PIC_PICSR==1 } {
puts $f {`define OR1200_PIC_PICSR }
}
 
puts $f "`define OR1200_PIC_INTS $PIC_INTS"
 
 
#TT defines
if { $TT_IMPLEMENTED==1 } {
puts $f {`define OR1200_TT_IMPLEMENTED }
}
if { $TT_TTMR==1 } {
puts $f {`define OR1200_TT_TTMR }
}
if { $TT_TTSR==1 } {
puts $f {`define OR1200_TT_TTSR }
}
if { $TT_READREGS==1 } {
puts $f {`define OR1200_TT_READREGS }
}
#IC CACHES
if { $NO_IC==1 } {
puts $f {`define OR1200_NO_IC }
}
 
puts $f "`define OR1200_IC_$IC_WAYS\W_$IC_SIZE"
 
if { $ICLS==8 } {
puts $f {`define OR1200_ICLS 3 }
} else {
puts $f {`define OR1200_ICLS 4 }
}
 
#DC defines
if { $NO_DC==1 } {
puts $f {`define OR1200_NO_DC }
}
 
puts $f "`define OR1200_DC_$DC_WAYS\W_$DC_SIZE"
 
if { $DCLS==8 } {
puts $f {`define OR1200_DCLS 3 }
} else {
puts $f {`define OR1200_DCLS 4 }
}
 
if { $SB_IMPLEMENTED==1 } {
puts $f {`define OR1200_SB_IMPLEMENTED }
}
 
puts $f "`define OR1200_SB_ENTRIES $SB_ENTRIES"
 
puts $f "`define OR1200_SB_LOG $SB_LOG"
 
#MMU defines
if { $NO_IMMU==1 } {
puts $f {`define OR1200_NO_IMMU }
}
if { $NO_DMMU==1 } {
puts $f {`define OR1200_NO_DMMU }
}
 
#QMEM defines
if {$QMEM_IMPLEMENTED == 1} {
puts $f {`define OR1200_QMEM_IMPLEMENTED }
}
if {$QMEM_BSEL == 1} {
puts $f {`define OR1200_QMEM_BSEL }
}
if {$QMEM_ACK == 1} {
puts $f {`define OR1200_QMEM_ACK }
}
#MISC defines
if {$MAC_IMPLEMENTED == 1} {
puts $f {`define OR1200_MAC_IMPLEMENTED }
}
if {$MAC_SPR_WE == 1} {
puts $f {`define OR1200_MAC_SPR_WE }
}
if {$CFGR_IMPLEMENTED == 1} {
puts $f {`define OR1200_CFGR_IMPLEMENTED }
}
if {$SYS_FULL_DECODE == 1} {
puts $f {`define OR1200_SYS_FULL_DECODE }
}
 
close $f
 
 
}
proc errorfile { } {
 
destroy .derror
toplevel .derror -class Dialog
wm title .derror "Error in File Access"
wm iconname .derror Dialog
frame .derror.top -relief raised -bd 1
pack .derror.top -side top -fill both
frame .derror.bot -relief raised -bd 1
pack .derror.bot -side top -fill both
 
 
label .derror.top.fn -text "ERROR IN FILE ACCESS"
pack .derror.top.fn -side top -pady 5m -padx 10m
button .derror.bot.okb -text "OK" -command { destroy .derror }
pack .derror.bot.okb -side top -padx 10m -pady 5m -fill x
 
 
}
 
wm title . "OR1200 Graphic Configuration Tool"
#wm minsize . 1000 600
 
 
defaultvals
 
frame .mbar -relief raised -bd 2
frame .screen -width 15c -height 10c
 
pack .mbar .screen -side top -fill x
 
menubutton .mbar.file -text File -underline 0 -menu .mbar.file.menu
menubutton .mbar.synthesis -text Target -underline 0 -menu .mbar.synthesis.menu
menubutton .mbar.processor -text "Processor Settings" -underline 0 -menu .mbar.processor.menu
menubutton .mbar.wishbone -text Wishbone -underline 0 -menu .mbar.wishbone.menu
menubutton .mbar.misc -text Misc -underline 0 -menu .mbar.misc.menu
menubutton .mbar.simulation -text Simulation -underline 0 -menu .mbar.simulation.menu
menubutton .mbar.help -text Help -underline 0 -menu .mbar.help.menu
 
pack .mbar.file .mbar.synthesis .mbar.processor .mbar.wishbone .mbar.misc .mbar.simulation -side left
pack .mbar.help -side right
 
menu .mbar.file.menu
 
.mbar.file.menu add command -label "Load configuration" -command {loadconfdialog}
.mbar.file.menu add command -label "Save configuration" -command {saveconfdialog}
.mbar.file.menu add separator
.mbar.file.menu add command -label "Generate verilog configuration file" -command { export }
.mbar.file.menu add separator
.mbar.file.menu add command -label "Default values" -command {defaultvals}
.mbar.file.menu add separator
.mbar.file.menu add command -label "Exit" -command {exit}
 
menu .mbar.help.menu
 
.mbar.help.menu add command -label "About ..." -command about
 
 
menu .mbar.simulation.menu
 
.mbar.simulation.menu add checkbutton -label "Dump VCD file" -variable VCD_DUMP
.mbar.simulation.menu add separator
.mbar.simulation.menu add checkbutton -label "Generate debug messages" -variable VERBOSE
 
menu .mbar.synthesis.menu
 
.mbar.synthesis.menu add radiobutton -label "ASIC" -variable ASIC -value 1 -command {confASIC}
.mbar.synthesis.menu add radiobutton -label "FPGA" -variable ASIC -value 0 -command {confFPGA}
confFPGA
 
menu .mbar.processor.menu
.mbar.processor.menu add command -label "Configure OpenRISC" -command {confOR1200}
 
menu .mbar.wishbone.menu
 
.mbar.wishbone.menu add checkbutton -label "Register WB outputs" -variable REGISTERED_OUTPUTS
.mbar.wishbone.menu add checkbutton -label "Register WB inputs" -variable REGISTERED_INPUTS
.mbar.wishbone.menu add separator
.mbar.wishbone.menu add checkbutton -label "Disable memory bursts" -variable NO_BURSTS
.mbar.wishbone.menu add checkbutton -label "Remove CAB signals" -variable WB_CAB
.mbar.wishbone.menu add separator
.mbar.wishbone.menu add checkbutton -label "Wishbone B3 compatibility" -variable WB_B3
.mbar.wishbone.menu add separator
.mbar.wishbone.menu add checkbutton -label "WB:RISC 1:2 clock ratio" -variable CLKDIV2_SUPPORT
.mbar.wishbone.menu add checkbutton -label "WB:RISC 1:4 clock ratio" -variable CLKDIV4_SUPPORT
.mbar.wishbone.menu add separator
.mbar.wishbone.menu add checkbutton -label "Retry counter enabled" -variable WB_RETRY
 
menu .mbar.misc.menu
 
.mbar.misc.menu add checkbutton -label "Additional Synopsys directives" -variable ADDITIONAL_SYNOPSYS_DIRECTIVES
.mbar.misc.menu add checkbutton -label "Enable default statement in case blocks" -variable CASE_DEFAULT
.mbar.misc.menu add separator
.mbar.misc.menu add radiobutton -label "Type of mem2reg aligner 1" -variable IMPL_MEM2REG -value 1
.mbar.misc.menu add radiobutton -label "Type of mem2reg aligner 2" -variable IMPL_MEM2REG -value 2
.mbar.misc.menu add separator
.mbar.misc.menu add checkbutton -label "Enable BIST (only for VIRTUAL SILICON memories)" -variable BIST
tk_menuBar .mbar .mbar.file .mbar.synthesis .mbar.processor .mbar.misc .mbar.simulation .mbar.help
 
focus .mbar
/tags/arelease/or1200_defines.v
0,0 → 1,1041
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Parameters of the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/06/30 17:37:38 cvsadmin
// Initial import
//
 
 
//Configuration file from graphic configuration tool
`include "or1200_config.v"
 
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
 
 
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4
/* Order defined by arith insns that have two source operands both in regs
(see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD 4'd0
`define OR1200_ALUOP_ADDC 4'd1
`define OR1200_ALUOP_SUB 4'd2
`define OR1200_ALUOP_AND 4'd3
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
 
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 2
`define OR1200_MACOP_NOP 2'b00
`define OR1200_MACOP_MAC 2'b01
`define OR1200_MACOP_MSB 2'b10
 
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 2
`define OR1200_SHROTOP_NOP 2'd0
`define OR1200_SHROTOP_SLL 2'd0
`define OR1200_SHROTOP_SRL 2'd1
`define OR1200_SHROTOP_SRA 2'd2
`define OR1200_SHROTOP_ROR 2'd3
 
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE 2'd0
`define OR1200_TWO_CYCLES 2'd1
 
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
 
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
 
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
 
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
 
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH 3
`define OR1200_RFWBOP_NOP 3'b000
`define OR1200_RFWBOP_ALU 3'b001
`define OR1200_RFWBOP_LSU 3'b011
`define OR1200_RFWBOP_SPRS 3'b101
`define OR1200_RFWBOP_LR 3'b111
 
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
 
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
 
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
 
 
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
 
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
 
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS 9:8
 
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
//`define OR1200_OR32_CUST5 6'b111100
 
 
/////////////////////////////////////////////////////
//
// Exceptions
//
 
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
 
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
 
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
 
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
 
 
/////////////////////////////////////////////////////
//
// SPR groups
//
 
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
 
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
 
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
 
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
 
 
/////////////////////////////////////////////////////
//
// System group
//
 
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
 
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
 
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
 
 
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
 
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
 
// PM group
`define OR1200_SPRGRP_PM 5'd8
 
 
 
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
 
// Number of DVR/DCR pairs if HW breakpoints enabled
`define OR1200_DU_DVRDCR_PAIRS 8
 
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, do not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`endif
 
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
 
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
 
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
 
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
 
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
 
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_BE 12
`define OR1200_DU_DSR_TE 13
 
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_BE 12
`define OR1200_DU_DRR_TE 13
 
 
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
 
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
 
 
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
 
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
 
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
 
 
 
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
 
 
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
 
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
 
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
 
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
 
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
 
 
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
 
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
 
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
 
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
 
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
 
 
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
 
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
 
 
/////////////////////////////////////////////////
//
// Data cache (DC)
//
 
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
 
 
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
 
 
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
 
 
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
 
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
 
// VR values
`define OR1200_VR_REV 6'h01
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
 
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_RES1_BITS 23:11
`define OR1200_UPR_CUP_BITS 31:24
 
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`define OR1200_UPR_MP 1'b1 // MAC always present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`define OR1200_UPR_RES1 13'h0000
`define OR1200_UPR_CUP 8'h00
 
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
 
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`define OR1200_CPUCFGR_HGF 1'b0
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`define OR1200_CPUCFGR_OF32S 1'b0
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
 
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
 
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
 
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
 
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
 
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
 
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`define OR1200_DCCFGR_RES1 17'h00000
`endif
 
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
 
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
 
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 2:0
`define OR1200_DCFGR_WPCI_BITS 3
`define OR1200_DCFGR_RES1_BITS 31:4
 
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
/tags/arelease/or1200_config.v
0,0 → 1,41
`define OR1200_XILINX_RAMB4
`define OR1200_VIRTUALSILICON_SSP
`define OR1200_GENERIC_MULTP2_32X32
`define OR1200_RFRAM_DUALPORT
`define OR1200_REGISTERED_OUTPUTS
`define OR1200_WB_CAB
`define OR1200_CLKDIV2_SUPPORT
`define OR1200_CASE_DEFAULT
`define OR1200_IMPL_MEM2REG1
`define OR1200_IMPL_ADDC
`define OR1200_IMPL_CY
`define OR1200_MULT_IMPLEMENTED
`define OR1200_PM_IMPLEMENTED
`define OR1200_PM_READREGS
`define OR1200_PM_UNUSED_ZERO
`define OR1200_PM_PARTIAL_DECODING
`define OR1200_DU_IMPLEMENTED
`define OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_READREGS
`define OR1200_DU_UNUSED_ZERO
`define OR1200_DU_STATUS_UNIMPLEMENTED
`define OR1200_PIC_IMPLEMENTED
`define OR1200_PIC_READREGS
`define OR1200_PIC_UNUSED_ZERO
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
`define OR1200_PIC_INTS 20
`define OR1200_TT_IMPLEMENTED
`define OR1200_TT_TTMR
`define OR1200_TT_TTSR
`define OR1200_TT_READREGS
`define OR1200_IC_1W_8KB
`define OR1200_ICLS 4
`define OR1200_DC_1W_8KB
`define OR1200_DCLS 4
`define OR1200_SB_ENTRIES 4
`define OR1200_SB_LOG 2
`define OR1200_MAC_IMPLEMENTED
`define OR1200_MAC_SPR_WE
`define OR1200_CFGR_IMPLEMENTED
`define OR1200_SYS_FULL_DECODE
/tags/arelease/Makefile
0,0 → 1,3
all:
xconfig:
wish -f or1200.tk
/tags/arelease/README
0,0 → 1,12
This is the graphic configuration tool for OpenRisc 1200 core.
 
Copy all the files to the or1200/rtl/verilog directory overwritting or1200_defines.v.
 
In order to run the tool write:
 
$ make xconfig
 
 
The tool will generate a file called or1200_config.v with the selected configuration.
 
Please, be free of send comments, bugs, or contributions to jcastillo@opensocdesign.com

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