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URL https://opencores.org/ocsvn/ppx16/ppx16/trunk

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/trunk/bench/vhdl/TestBench55.vhd
0,0 → 1,30
library IEEE;
use IEEE.std_logic_1164.all;
use work.StimLog.all;
 
entity TestBench55 is
end TestBench55;
 
architecture behaviour of TestBench55 is
 
signal Clk : std_logic := '0';
signal Reset_n : std_logic := '0';
signal T0CKI : std_logic := '0';
signal Port_A : std_logic_vector(7 downto 0);
signal Port_B : std_logic_vector(7 downto 0);
signal Port_C : std_logic_vector(7 downto 0);
 
begin
 
p1 : entity work.P16C55 port map (Clk, Reset_n, T0CKI, Port_A, Port_B, Port_C);
 
as : AsyncStim generic map(FileName => "PPX16.vhd", InterCharDelay => 300 us, Baud => 48000, Bits => 8)
port map(Port_A(1));
 
al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 48000, Bits => 8)
port map(Port_A(0));
 
Clk <= not Clk after 50 ns;
Reset_n <= '1' after 200 ns;
 
end;
/trunk/bench/vhdl/TestBench84.vhd
0,0 → 1,23
library IEEE;
use IEEE.std_logic_1164.all;
 
entity TestBench84 is
end TestBench84;
 
architecture behaviour of TestBench84 is
 
signal Clk : std_logic := '0';
signal Reset_n : std_logic := '0';
signal T0CKI : std_logic := '0';
signal INT : std_logic := '0';
signal Port_A : std_logic_vector(7 downto 0);
signal Port_B : std_logic_vector(7 downto 0);
 
begin
 
p1 : entity work.P16F84 port map (Clk, Reset_n, T0CKI, INT, Port_A, Port_B);
 
Clk <= not Clk after 50 ns;
Reset_n <= '1' after 200 ns;
 
end;
/trunk/rtl/vhdl/P16C55.vhd
0,0 → 1,237
--
-- PIC16C55 compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.PPX_Pack.all;
 
entity P16C55 is
generic(
SyncReset : boolean := true);
port(
Clk : in std_logic;
Reset_n : in std_logic;
T0CKI : in std_logic;
Port_A : inout std_logic_vector(7 downto 0);
Port_B : inout std_logic_vector(7 downto 0);
Port_C : inout std_logic_vector(7 downto 0)
);
end P16C55;
 
architecture rtl of P16C55 is
 
constant InstructionLength : integer := 12;
constant ROMAddressWidth : integer := 9;
constant StackAddrWidth : integer := 1;
constant TopBoot : boolean := true;
 
component ROM55
port(
Clk : in std_logic;
A : in std_logic_vector(8 downto 0);
D : out std_logic_vector(11 downto 0)
);
end component;
 
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(8 downto 0);
signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_CS : std_logic_vector(7 downto 5);
signal RAM_CS : std_logic;
signal TMR_CS : std_logic;
signal File_Rd : std_logic;
signal File_Wr : std_logic;
signal Tris_Rd : std_logic;
signal Tris_A_Wr : std_logic;
signal Tris_B_Wr : std_logic;
signal Tris_C_Wr : std_logic;
signal Op_Bus : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(5 downto 0);
signal Int_Trig : std_logic;
signal GIE : std_logic;
 
begin
 
Int_Trig <= '0';
GIE <= '0';
 
-- Synchronise reset
process (Reset_n, Clk)
variable Reset_v : std_logic;
begin
if Reset_n = '0' then
if SyncReset then
Reset_s_n <= '0';
Reset_v := '0';
end if;
elsif Clk'event and Clk = '1' then
if SyncReset then
Reset_s_n <= Reset_v;
Reset_v := '1';
end if;
end if;
end process;
 
g_reset : if not SyncReset generate
Reset_s_n <= Reset_n;
end generate;
 
-- Address decoder
Tris_Rd <= '0';
RAM_CS <= '1' when File_Addr_r(4 downto 3) /= "00" else '0';
TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 1 else '0';
Tris_A_Wr <= '1' when Instruction(11 downto 0) = "000000000101" else '0';
Tris_B_Wr <= '1' when Instruction(11 downto 0) = "000000000110" else '0';
Tris_C_Wr <= '1' when Instruction(11 downto 0) = "000000000111" else '0';
File_CS(5) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 5 else '0';
File_CS(6) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 6 else '0';
File_CS(7) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 else '0';
 
-- Register File
pr : PPX_RAM
generic map(Bottom => 8, Top => 31, AddrWidth => 5)
port map(
Clk => Clk,
CS => RAM_CS,
Wr => File_Wr,
Rd => File_Rd,
Addr => File_Addr(4 downto 0),
Data_In => Res_Bus,
Data_Out => Op_Bus);
 
-- Option Register
process (Clk)
begin
if Clk'event and Clk = '1' then
if Instruction(11 downto 0) = "000000000010" then
OPTION <= Res_Bus(5 downto 0);
end if;
end if;
end process;
 
rom : ROM55 port map(
Clk => Clk,
A => ROM_Addr,
D => ROM_Data);
 
ppx : PPX16
generic map(
InstructionLength => InstructionLength,
ROMAddressWidth => ROMAddressWidth,
StackAddrWidth => StackAddrWidth,
TopBoot => TopBoot)
port map(
Clk => Clk,
Reset_n => Reset_s_n,
ROM_Addr => ROM_Addr,
ROM_Data => ROM_Data,
Int_Trig => Int_Trig,
GIE => GIE,
File_Addr => File_Addr,
File_Addr_r => File_Addr_r,
File_Rd => File_Rd,
File_Wr => File_Wr,
Instruction => Instruction,
Op_Bus => Op_Bus,
Res_Bus => Res_Bus);
 
tmr0 : PPX_TMR port map(
Clk => Clk,
Reset_n => Reset_s_n,
CKI => T0CKI,
SE => OPTION(4),
CS => OPTION(5),
PS => OPTION(2 downto 0),
PSA => OPTION(3),
TMR_Sel => TMR_CS,
Rd => File_Rd,
Wr => File_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus);
 
porta : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(5),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Tris_Wr => Tris_A_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
IOPort => Port_A);
 
portb : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(6),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Tris_Wr => Tris_B_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
IOPort => Port_B);
 
portc : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(7),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Tris_Wr => Tris_C_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
IOPort => Port_C);
 
end;
/trunk/rtl/vhdl/PPX_Pack.vhd
0,0 → 1,194
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package PPX_Pack is
 
component PPX_ALU
generic(
InstructionLength : integer
);
port (
Clk : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : inout std_logic_vector(7 downto 0);
Skip : in std_logic;
Carry : in std_logic;
Z_Skip : out std_logic;
STATUS_d : out std_logic_vector(2 downto 0);
STATUS_Wr : out std_logic_vector(2 downto 0)
);
end component;
 
component PPX_Ctrl
generic(
InstructionLength : integer
);
port(
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
W_Rd : out std_logic;
Imm_Op : out std_logic;
B2Res : out std_logic;
Push : out std_logic;
Pop : out std_logic;
Goto : out std_logic;
IRet : out std_logic;
B_Skip : out std_logic;
Sleep : out std_logic
);
end component;
 
component PPX_PCS
generic(
PC_Width : integer;
StackAddrWidth : integer;
TopBoot : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
PCLATH : in std_logic_vector(4 downto 0);
STATUS : in std_logic_vector(6 downto 5);
NPC : out std_logic_vector(PC_Width - 1 downto 0);
Int : in std_logic;
Sleep : in std_logic;
Push : in std_logic;
Pop : in std_logic;
Goto : in std_logic
);
end component;
 
component PPX16
generic(
InstructionLength : integer;
ROMAddressWidth : integer;
StackAddrWidth : integer;
TopBoot : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Int_Trig : in std_logic;
GIE : in std_logic;
Int_Acc : out std_logic;
Int_Ret : out std_logic;
File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
Op_Bus : inout std_logic_vector(7 downto 0);
Res_Bus : inout std_logic_vector(7 downto 0)
);
end component;
 
component PPX_RAM
generic(
Bottom : integer;
Top : integer;
AddrWidth : integer
);
port(
Clk : in std_logic;
CS : in std_logic;
Wr : in std_logic;
Rd : in std_logic;
Addr : in std_logic_vector(AddrWidth - 1 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end component;
 
component PPX_Port
port(
Clk : in std_logic;
Reset_n : in std_logic;
Port_CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Tris_Rd : in std_logic;
Tris_Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end component;
 
component PPX_TMR
port(
Clk : in std_logic;
Reset_n : in std_logic;
CKI : in std_logic;
SE : in std_logic;
CS : in std_logic;
PS : in std_logic_vector(2 downto 0);
PSA : in std_logic;
TMR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
TOF : out std_logic
);
end component;
 
end PPX_Pack;
/trunk/rtl/vhdl/PPX_RAM.vhd
0,0 → 1,102
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
-- other registers must be implemented externally including GPR
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity PPX_RAM is
generic(
Bottom : integer;
Top : integer;
AddrWidth : integer
);
port(
Clk : in std_logic;
CS : in std_logic;
Wr : in std_logic;
Rd : in std_logic;
Addr : in std_logic_vector(AddrWidth - 1 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end PPX_RAM;
 
architecture rtl of PPX_RAM is
 
type RAM_Image is array (Top downto Bottom) of std_logic_vector(7 downto 0);
signal RAM : RAM_Image;
signal AddrReg : std_logic_vector(AddrWidth - 1 downto 0);
signal Tmp_Data : std_logic_vector(7 downto 0);
 
begin
 
process (Clk)
begin
if Clk'event and Clk = '1' then
AddrReg <= Addr;
-- pragma translate_off
if to_integer(unsigned(Addr)) >= Bottom and to_integer(unsigned(Addr)) <= Top then
-- pragma translate_on
Tmp_Data <= RAM(to_integer(unsigned(Addr)));
-- pragma translate_off
end if;
-- pragma translate_on
if CS = '1' and Wr = '1' then
RAM(to_integer(unsigned(AddrReg))) <= Data_In;
if AddrReg = Addr then
Tmp_Data <= Data_In;
end if;
end if;
end if;
end process;
 
Data_Out <= Tmp_Data when CS = '1' and Rd = '1' ELSE "ZZZZZZZZ";
 
end;
/trunk/rtl/vhdl/P16F84.vhd
0,0 → 1,276
--
-- PIC16F84 compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- No port B pullup
-- No EEPROM
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.PPX_Pack.all;
 
entity P16F84 is
generic(
SyncReset : boolean := true);
port(
Clk : in std_logic;
Reset_n : in std_logic;
T0CKI : in std_logic;
INT : in std_logic;
Port_A : inout std_logic_vector(7 downto 0);
Port_B : inout std_logic_vector(7 downto 0)
);
end P16F84;
 
architecture rtl of P16F84 is
 
constant InstructionLength : integer := 14;
constant ROMAddressWidth : integer := 10;
constant StackAddrWidth : integer := 3;
constant TopBoot : boolean := false;
 
component ROM84
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(13 downto 0)
);
end component;
 
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(9 downto 0);
signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_CS : std_logic_vector(6 downto 5);
signal TMR_CS : std_logic;
signal RAM_CS : std_logic;
signal File_Rd : std_logic;
signal File_Wr : std_logic;
signal Tris_A_Rd : std_logic;
signal Tris_A_Wr : std_logic;
signal Tris_B_Rd : std_logic;
signal Tris_B_Wr : std_logic;
signal Op_Bus : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(7 downto 0);
signal INTCON : std_logic_vector(7 downto 0);
signal Int_Trig : std_logic;
signal Int_Acc : std_logic;
signal Int_Ret : std_logic;
signal TOF : std_logic;
signal Old_B : std_logic_vector(7 downto 4);
signal Old_INT : std_logic;
 
begin
 
-- Synchronise reset
process (Reset_n, Clk)
variable Reset_v : std_logic;
begin
if Reset_n = '0' then
if SyncReset then
Reset_s_n <= '0';
Reset_v := '0';
end if;
elsif Clk'event and Clk = '1' then
if SyncReset then
Reset_s_n <= Reset_v;
Reset_v := '1';
end if;
end if;
end process;
 
g_reset : if not SyncReset generate
Reset_s_n <= Reset_n;
end generate;
 
-- Address decoder
File_CS(5) <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 5 else '0';
File_CS(6) <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 6 else '0';
Tris_A_Rd <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Rd = '1' else '0';
Tris_B_Rd <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Rd = '1' else '0';
Tris_A_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Wr = '1') or
Instruction(13 downto 0) = "00000001100101" else '0';
Tris_B_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Wr = '1') or
Instruction(13 downto 0) = "00000001100110" else '0';
RAM_CS <= '1' when File_Addr_r(6 downto 4) /= "000" or File_Addr_r(3 downto 2) = "11" else '0';
TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 1 else '0';
 
-- Register File
pr : PPX_RAM
generic map(Bottom => 12, Top => 79, AddrWidth => 7)
port map(
Clk => Clk,
CS => RAM_CS,
Wr => File_Wr,
Rd => File_Rd,
Addr => File_Addr(6 downto 0),
Data_In => Res_Bus,
Data_Out => Op_Bus);
 
-- Option Register
Op_Bus <= OPTION when
to_integer(unsigned(File_Addr_r(7 downto 0))) = 129 and
File_Rd = '1' else "ZZZZZZZZ";
process (Clk)
begin
if Clk'event and Clk = '1' then
if Instruction(13 downto 0) = "00000001100010" or
to_integer(unsigned(File_Addr_r(7 downto 0))) = 129 then
OPTION <= Res_Bus;
end if;
Old_B <= Port_B(7 downto 4);
Old_INT <= INT;
end if;
end process;
 
-- Interrupt Register
Int_Trig <= (INTCON(0) and INTCON(3)) or
(INTCON(1) and INTCON(4)) or
(INTCON(2) and INTCON(5));
Op_Bus <= INTCON when
to_integer(unsigned(File_Addr_r(7 downto 0))) = 11 and
File_Rd = '1' else "ZZZZZZZZ";
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
INTCON <= (others => '0');
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_r(7 downto 0))) = 11 then
INTCON <= Res_Bus;
end if;
if Int_Acc = '1' then
INTCON(7) <= '0';
end if;
if Int_Ret = '1' then
INTCON(7) <= '0';
end if;
if TOF = '1' then
INTCON(2) <= '1';
end if;
if (OPTION(6) = '1' and INT = '1' and Old_INT = '0') or
(OPTION(6) = '0' and INT = '0' and Old_INT = '1') then
INTCON(1) <= '1';
end if;
if Old_B /= Port_B(7 downto 4) then
INTCON(0) <= '1';
end if;
end if;
end process;
 
rom : ROM84 port map(
Clk => Clk,
A => ROM_Addr,
D => ROM_Data);
 
ppx : PPX16
generic map(
InstructionLength => InstructionLength,
ROMAddressWidth => ROMAddressWidth,
StackAddrWidth => StackAddrWidth,
TopBoot => TopBoot)
port map(
Clk => Clk,
Reset_n => Reset_s_n,
ROM_Addr => ROM_Addr,
ROM_Data => ROM_Data,
Int_Trig => Int_Trig,
GIE => INTCON(7),
Int_Acc => Int_Acc,
Int_Ret => Int_Ret,
File_Addr => File_Addr,
File_Addr_r => File_Addr_r,
File_Rd => File_Rd,
File_Wr => File_Wr,
Instruction => Instruction,
Op_Bus => Op_Bus,
Res_Bus => Res_Bus);
 
tmr0 : PPX_TMR
port map(
Clk => Clk,
Reset_n => Reset_s_n,
CKI => T0CKI,
SE => OPTION(4),
CS => OPTION(5),
PS => OPTION(2 downto 0),
PSA => OPTION(3),
TMR_Sel => TMR_CS,
Rd => File_Rd,
Wr => File_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
TOF => TOF);
 
porta : PPX_Port
port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(5),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_A_Rd,
Tris_Wr => Tris_A_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
IOPort => Port_A);
 
portb : PPX_Port
port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(6),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_B_Rd,
Tris_Wr => Tris_B_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
IOPort => Port_B);
 
end;
/trunk/rtl/vhdl/PPX_ALU.vhd
0,0 → 1,318
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity PPX_ALU is
generic(
InstructionLength : integer
);
port (
Clk : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : inout std_logic_vector(7 downto 0);
Skip : in std_logic;
Carry : in std_logic;
Z_Skip : out std_logic;
STATUS_d : out std_logic_vector(2 downto 0);
STATUS_Wr : out std_logic_vector(2 downto 0)
);
end PPX_ALU;
 
architecture rtl of PPX_ALU is
 
procedure AddSub(A : std_logic_vector(3 downto 0);
B : std_logic_vector(3 downto 0);
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector(3 downto 0);
signal Carry : out std_logic) is
variable B_i : unsigned(4 downto 0);
variable Full_Carry : unsigned(4 downto 0);
variable Res_i : unsigned(4 downto 0);
begin
if Sub = '1' then
B_i := "0" & not unsigned(B);
else
B_i := "0" & unsigned(B);
end if;
if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
Full_Carry := "00001";
else
Full_Carry := "00000";
end if;
Res_i := unsigned("0" & A) + B_i + Full_Carry;
Carry <= Res_i(4);
Res <= std_logic_vector(Res_i(3 downto 0));
end;
 
signal Do_IDTEST : std_logic;
signal Do_ADD : std_logic;
signal Do_SUB : std_logic;
signal Do_DEC : std_logic;
signal Do_INC : std_logic;
signal Do_AND : std_logic;
signal Do_OR : std_logic;
signal Do_XOR : std_logic;
signal Do_COM : std_logic;
signal Do_RRF : std_logic;
signal Do_RLF : std_logic;
signal Do_SWAP : std_logic;
signal Do_BITCLR : std_logic;
signal Do_BITSET : std_logic;
signal Do_BITTESTCLR : std_logic;
signal Do_BITTESTSET : std_logic;
signal Do_CLR : std_logic;
signal Do_PASSA : std_logic;
 
signal Inst_Top : std_logic_vector(11 downto 0);
 
signal Bit_Pattern : std_logic_vector(7 downto 0);
signal Bit_Test : std_logic_vector(7 downto 0);
 
signal IDD : std_logic_vector(7 downto 0);
 
signal DC_i : std_logic;
signal AddSubRes : std_logic_vector(8 downto 0);
 
begin
 
Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
 
process (Clk)
begin
if Clk'event and Clk = '1' then
Do_ADD <= '0';
Do_SUB <= '0';
Do_AND <= '0';
Do_OR <= '0';
Do_XOR <= '0';
Do_IDTEST <= '0';
Do_INC <= '0';
Do_DEC <= '0';
Do_COM <= '0';
Do_RRF <= '0';
Do_RLF <= '0';
Do_SWAP <= '0';
Do_BITCLR <= '0';
Do_BITSET <= '0';
Do_BITTESTCLR <= '0';
Do_BITTESTSET <= '0';
Do_CLR <= '0';
Do_PASSA <= '0';
if Skip = '0' then
if InstructionLength = 12 then
if Inst_Top(11 downto 6) = "000111" then
-- ADDWF
Do_ADD <= '1';
end if;
if Inst_Top(11 downto 6) = "000010" then
-- SUBWF
Do_SUB <= '1';
end if;
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
-- ANDWF, ANDLW
Do_AND <= '1';
end if;
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
-- IORWF, IORLW
Do_OR <= '1';
end if;
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
-- XORWF, XORLW
Do_XOR <= '1';
end if;
else
if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
-- ADDWF, ADDLW
Do_ADD <= '1';
end if;
if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
-- SUBWF, SUBLW
Do_SUB <= '1';
end if;
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
-- ANDWF, ANDLW
Do_AND <= '1';
end if;
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
-- IORWF, IORLW
Do_OR <= '1';
end if;
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
-- XORWF, XORLW
Do_XOR <= '1';
end if;
end if;
 
if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
-- INC/DEC w conditional skip
Do_IDTEST <= '1';
end if;
if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
-- INCF, INCFSZ
Do_INC <= '1';
end if;
if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
-- DECF, DECFSZ,
Do_DEC <= '1';
end if;
if Inst_Top(11 downto 6) = "001001" then
-- COMF
Do_COM <= '1';
end if;
if Inst_Top(11 downto 6) = "001100" then
-- RRF
Do_RRF <= '1';
end if;
if Inst_Top(11 downto 6) = "001101" then
-- RLF
Do_RLF <= '1';
end if;
if Inst_Top(11 downto 6) = "001110" then
-- SWAPF
Do_SWAP <= '1';
end if;
if Inst_Top(11 downto 8) = "0100" then
-- BCF
Do_BITCLR <= '1';
end if;
if Inst_Top(11 downto 8) = "0101" then
-- BSF
Do_BITSET <= '1';
end if;
if Inst_Top(11 downto 8) = "0110" then
-- BTFSC
Do_BITTESTCLR <= '1';
end if;
if Inst_Top(11 downto 8) = "0111" then
-- BTFSS
Do_BITTESTSET <= '1';
end if;
if Inst_Top(11 downto 6) = "000001" then
-- CLRF, CLRW
Do_CLR <= '1';
end if;
if Inst_Top(11 downto 6) = "001000" then
-- MOVF
Do_PASSA <= '1';
end if;
end if;
 
case Inst_Top(7 downto 5) is
when "000" =>
Bit_Pattern <= "00000001";
when "001" =>
Bit_Pattern <= "00000010";
when "010" =>
Bit_Pattern <= "00000100";
when "011" =>
Bit_Pattern <= "00001000";
when "100" =>
Bit_Pattern <= "00010000";
when "101" =>
Bit_Pattern <= "00100000";
when "110" =>
Bit_Pattern <= "01000000";
when others =>
Bit_Pattern <= "10000000";
end case;
end if;
end process;
 
IDD <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
std_logic_vector(unsigned(A) - 1) when Do_DEC = '1' else "ZZZZZZZZ";
Q <= IDD when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
 
Q <= AddSubRes(7 downto 0) when (Do_ADD = '1' OR Do_SUB = '1') else "ZZZZZZZZ";
AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
 
Q <= (A and B) when Do_AND = '1' else
(A or B) when Do_OR = '1' else
(A xor B) when Do_XOR = '1' else "ZZZZZZZZ";
Q <= (not A) when Do_COM = '1' else "ZZZZZZZZ";
 
Q <= Carry & A(7 downto 1) when Do_RRF = '1' else "ZZZZZZZZ";
Q <= A(6 downto 0) & Carry when Do_RLF = '1' else "ZZZZZZZZ";
 
Q <= A(3 downto 0) & A(7 downto 4) when Do_SWAP = '1' else "ZZZZZZZZ";
 
Q <= ((not Bit_Pattern) and A) when Do_BITCLR = '1' else "ZZZZZZZZ";
Q <= (Bit_Pattern or A) when Do_BITSET = '1' else "ZZZZZZZZ";
 
Q <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
 
Q <= A when Do_PASSA = '1' else "ZZZZZZZZ";
 
Bit_Test <= Bit_Pattern and A;
 
Z_Skip <= '1' when (Do_IDTEST = '1' and IDD = "00000000") or
(Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
(Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
 
STATUS_d(2) <= '1' when Q(7 downto 0) = "00000000" else '0';
STATUS_d(1) <= DC_i;
STATUS_d(0) <= A(0) when Do_RRF = '1' else
A(7) when Do_RLF = '1' else
AddSubRes(8);
 
-- Z
STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
Do_CLR = '1' or Do_COM = '1' or Do_PASSA = '1' else '0';
-- DC
STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
-- C
STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
 
end;
/trunk/rtl/vhdl/PPX_TMR.vhd
0,0 → 1,157
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
-- other registers must be implemented externally including GPR
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity PPX_TMR is
port(
Clk : in std_logic;
Reset_n : in std_logic;
CKI : in std_logic;
SE : in std_logic;
CS : in std_logic;
PS : in std_logic_vector(2 downto 0);
PSA : in std_logic;
TMR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
TOF : out std_logic
);
end PPX_TMR;
 
architecture rtl of PPX_TMR is
 
signal TMR : std_logic_vector(7 downto 0);
 
signal Tick : std_logic;
 
begin
 
-- Registers and counter
Data_Out <= TMR when Rd = '1' and TMR_Sel = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
TMR <= "00000000";
TOF <= '0';
elsif Clk'event and Clk = '1' then
TOF <= '0';
if Tick = '1' then
TMR <= std_logic_vector(unsigned(TMR) + 1);
if TMR = "11111111" then
TOF <= '1';
end if;
end if;
if TMR_Sel = '1' and Wr = '1' then
TMR <= Data_In;
TOF <= '0';
end if;
end if;
end process;
 
-- Tick generator
process (Clk, Reset_n)
variable Prescaler : unsigned(7 downto 0);
variable CKI_r : std_logic_vector(1 downto 0);
variable P_r : std_logic_vector(1 downto 0);
variable Tick0 : std_logic;
begin
if Reset_n = '0' then
Prescaler := (others => '0');
Tick <= '0';
Tick0 := '0';
CKI_r := "00";
P_r := "00";
elsif Clk'event and Clk='1' then
P_r(1) := P_r(0);
case PS is
when "000" => P_r(0) := Prescaler(0);
when "001" => P_r(0) := Prescaler(1);
when "010" => P_r(0) := Prescaler(2);
when "011" => P_r(0) := Prescaler(3);
when "100" => P_r(0) := Prescaler(4);
when "101" => P_r(0) := Prescaler(5);
when "110" => P_r(0) := Prescaler(6);
when others => P_r(0) := Prescaler(7);
end case;
 
Tick0 := '0';
if SE = '0' then -- low-to-high
if CKI_r(1) = '1' and CKI_r(0) = '0' then
Tick0 := '1';
end if;
else
if CKI_r(1) = '0' and CKI_r(0) = '1' then
Tick0 := '1';
end if;
end if;
if CS = '0' then
Tick0 := '1';
end if;
CKI_r(1) := CKI_r(0);
CKI_r(0) := CKI;
 
Tick <= '0';
if PSA = '1' then
Tick <= Tick0;
elsif P_r(1) = '1' and P_r(0) = '0' then
Tick <= '1';
end if;
 
if Tick0 = '1' then
Prescaler := Prescaler + 1;
end if;
end if;
end process;
 
end;
/trunk/rtl/vhdl/PPX_Ctrl.vhd
0,0 → 1,116
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
-- other registers must be implemented externally including GPR
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity PPX_Ctrl is
generic(
InstructionLength : integer
);
port(
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
W_Rd : out std_logic;
Imm_Op : out std_logic;
B2Res : out std_logic;
Push : out std_logic;
Pop : out std_logic;
Goto : out std_logic;
IRet : out std_logic;
B_Skip : out std_logic;
Sleep : out std_logic
);
end PPX_Ctrl;
 
architecture rtl of PPX_Ctrl is
 
begin
 
File_Wr <= '1' when (Inst(InstructionLength - 1 downto InstructionLength - 2) = "00" and
Inst(InstructionLength - 7) = '1') or
Inst(InstructionLength - 1 downto InstructionLength - 3) = "010" else '0';
File_Rd <= not Inst(InstructionLength - 1);
W_Rd <= Inst(InstructionLength - 1);
Imm_Op <= Inst(InstructionLength - 1);
Goto <= '1' when Inst(InstructionLength - 1 downto InstructionLength - 3) = "101" else '0';
 
i12 : if InstructionLength = 12 generate
Push <= '1' when Inst(11 downto 8) = "1001" else '0'; -- CALL
Pop <= '1' when Inst(11 downto 8) = "1000" else '0'; -- RETLW
B_Skip <= '1' when Inst(11 downto 10) = "10" else '0';
Sleep <= '1' when Inst(11 downto 0) = "000000000011" else '0';
B2Res <= '1' when Inst(11 downto 8) = "1100" or -- MOVLW
Inst(11 downto 8) = "1000" or -- RETLW
Inst(11 downto 6) = "000000" else '0'; -- MOVWF/TRIS/OPTION and some others
W_Wr <= '1' when Inst(11 downto 8) = "1000" or
Inst(11 downto 10) = "11" or
(Inst(11 downto 10) = "00" and Inst(5) = '0' and Inst(9 downto 6) /= "0000") else '0';
IRet <= '0';
end generate;
 
i14 : if InstructionLength = 14 generate
Push <= '1' when Inst(13 downto 11) = "100" else '0'; -- CALL
Pop <= '1' when Inst(13 downto 10) = "1101" or -- RETLW
Inst(13 downto 1) = "0000000000100" else '0'; -- RETURN, RETFIE
B_Skip <= '1' when Inst(13 downto 12) = "10" or Inst(13 downto 10) = "1101" or
Inst(13 downto 1) = "0000000000100" else '0';
Sleep <= '1' when Inst(13 downto 0) = "00000001100011" else '0';
B2Res <= '1' when Inst(13 downto 10) = "1100" or -- MOVLW
Inst(13 downto 10) = "1101" or -- RETLW
Inst(13 downto 8) = "000000" else '0'; -- MOVWF/TRIS/OPTION and some others
W_Wr <= '1' when Inst(13 downto 12) = "11" or
(Inst(13 downto 12) = "00" and Inst(7) = '0' and Inst(11 downto 8) /= "0000") else '0';
IRet <= '1' when Inst(13 downto 0) = "00000000001001" else '0'; -- RETFIE
end generate;
 
end;
 
/trunk/rtl/vhdl/PPX_Port.vhd
0,0 → 1,111
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
-- other registers must be implemented externally including GPR
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity PPX_Port is
port(
Clk : in std_logic;
Reset_n : in std_logic;
Port_CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Tris_Rd : in std_logic;
Tris_Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end PPX_Port;
 
architecture rtl of PPX_Port is
 
signal Tris : std_logic_vector(7 downto 0);
signal Port_Output : std_logic_vector(7 downto 0);
signal Port_Input : std_logic_vector(7 downto 0);
 
begin
 
IOPort(0) <= Port_Output(0) when Tris(0) = '0' else 'Z';
IOPort(1) <= Port_Output(1) when Tris(1) = '0' else 'Z';
IOPort(2) <= Port_Output(2) when Tris(2) = '0' else 'Z';
IOPort(3) <= Port_Output(3) when Tris(3) = '0' else 'Z';
IOPort(4) <= Port_Output(4) when Tris(4) = '0' else 'Z';
IOPort(5) <= Port_Output(5) when Tris(5) = '0' else 'Z';
IOPort(6) <= Port_Output(6) when Tris(6) = '0' else 'Z';
IOPort(7) <= Port_Output(7) when Tris(7) = '0' else 'Z';
 
Data_Out <= Port_Input when Port_CS = '1' and Rd = '1' else "ZZZZZZZZ";
 
process (Clk)
begin
if Clk'event and Clk = '1' then
Port_Input <= IOPort; -- Synchronise input
if Port_CS = '1' and Wr = '1' then
Port_Output <= Data_In;
Port_Input <= Data_In;
end if;
end if;
end process;
 
Data_Out <= Tris when Tris_Rd = '1' else "ZZZZZZZZ";
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Tris <= "11111111";
elsif Clk'event and Clk = '1' then
if Tris_Wr = '1' then
Tris <= Data_In;
end if;
end if;
end process;
 
end;
/trunk/rtl/vhdl/PPX_PCS.vhd
0,0 → 1,171
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity PPX_PCS is
generic(
PC_Width : integer;
StackAddrWidth : integer;
TopBoot : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
PCLATH : in std_logic_vector(4 downto 0);
STATUS : in std_logic_vector(6 downto 5);
NPC : out std_logic_vector(PC_Width - 1 downto 0);
Int : in std_logic;
Sleep : in std_logic;
Push : in std_logic;
Pop : in std_logic;
Goto : in std_logic
);
end PPX_PCS;
 
architecture rtl of PPX_PCS is
 
signal PC_i : unsigned(PC_Width - 1 downto 0);
signal NPC_i : unsigned(PC_Width - 1 downto 0);
 
type Stack_Image is array (2 ** StackAddrWidth - 1 downto 0) of unsigned(PC_Width - 1 downto 0);
signal Stack : Stack_Image;
 
signal StackPtr : unsigned(StackAddrWidth -1 downto 0);
 
begin
 
Data_Out <= std_logic_vector(PC_i(7 downto 0)) when CS = '1' and Rd = '1' else "ZZZZZZZZ";
NPC <= std_logic_vector(NPC_i);
 
process (Clk)
begin
if Clk'event and Clk = '1' then
if Push = '1' or Int = '1' then
Stack(to_integer(StackPtr)) <= PC_i;
end if;
end if;
end process;
 
process (PC_i, Sleep, CS, Wr, PCLATH, STATUS, Push, Pop, Goto, Int, Data_In, Addr_In, Stack, StackPtr)
begin
NPC_i <= PC_i;
if Sleep = '0' then
NPC_i <= PC_i + 1;
end if;
if CS = '1' and Wr = '1' then
if PC_Width = 13 then
NPC_i(7 downto 0) <= unsigned(Data_In);
NPC_i(PC_Width - 1 downto PC_Width - 5) <= unsigned(PCLATH);
end if;
if PC_Width = 11 then
NPC_i(7 downto 0) <= unsigned(Data_In);
NPC_i(8) <= '0';
NPC_i(10 downto 9) <= unsigned(STATUS);
end if;
end if;
if Push = '1' then
if PC_Width = 13 then
NPC_i(10 downto 0) <= unsigned(Addr_In);
NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
end if;
if PC_Width = 11 then
NPC_i(7 downto 0) <= unsigned(Addr_In(7 downto 0));
NPC_i(8) <= '0';
NPC_i(10 downto 9) <= unsigned(STATUS);
end if;
end if;
if Pop = '1' then
NPC_i <= Stack(to_integer(StackPtr - 1));
end if;
if Goto = '1' then
if PC_Width = 13 then
NPC_i(10 downto 0) <= unsigned(Addr_In);
NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
end if;
if PC_Width = 11 then
NPC_i(8 downto 0) <= unsigned(Addr_In);
NPC_i(10 downto 9) <= unsigned(STATUS);
end if;
end if;
if Int = '1' then
NPC_i <= (others => '0');
NPC_i(2) <= '1';
end if;
end process;
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
PC_i <= (others => '1');
if TopBoot then
PC_i(0) <= '0';
end if;
StackPtr <= (others => '0');
elsif Clk'event and Clk = '1' then
PC_i <= NPC_i;
if Push = '1' then
StackPtr <= StackPtr + 1;
end if;
if Pop = '1' then
StackPtr <= StackPtr - 1;
end if;
if Int = '1' then
StackPtr <= StackPtr + 1;
end if;
end if;
end process;
 
end;
/trunk/rtl/vhdl/PPX16.vhd
0,0 → 1,324
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
-- other registers must be implemented externally including GPR
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.PPX_Pack.all;
 
entity PPX16 is
generic(
InstructionLength : integer;
ROMAddressWidth : integer;
StackAddrWidth : integer;
TopBoot : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Int_Trig : in std_logic;
GIE : in std_logic;
Int_Acc : out std_logic;
Int_Ret : out std_logic;
File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
Op_Bus : inout std_logic_vector(7 downto 0);
Res_Bus : inout std_logic_vector(7 downto 0)
);
end PPX16;
 
architecture rtl of PPX16 is
 
-- File control
signal File_Addr_i : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_i_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Rd_i : std_logic;
signal File_Wr_i : std_logic;
signal PC_CS : std_logic;
 
-- Registers
signal STATUS : std_logic_vector(7 downto 0);
signal W : std_logic_vector(7 downto 0);
signal FSR : std_logic_vector(7 downto 0);
signal PCLATH : std_logic_vector(4 downto 0);
signal NPC : std_logic_vector(InstructionLength - 2 downto 0);
 
-- Registered instruction word
 
-- Control signals
signal Inst : std_logic_vector(InstructionLength - 1 downto 0);
signal Op_Mux : std_logic_vector(7 downto 0);
signal STATUS_d : std_logic_vector(2 downto 0);
signal STATUS_Wr : std_logic_vector(2 downto 0);
signal Z_Skip : std_logic;
signal B_Skip : std_logic;
signal Inst_Skip : std_logic;
signal W_Wr : std_logic;
signal W_Rd : std_logic;
signal Imm_Op : std_logic;
signal Push : std_logic;
signal Pop : std_logic;
signal Goto : std_logic;
signal IRet : std_logic;
signal B2Res : std_logic;
signal Sleep : std_logic;
signal Sleep_r : std_logic;
signal Int : std_logic;
 
begin
 
-- Instruction register
Instruction <= Inst;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Inst <= (others => '0'); -- Force NOP at reset.
elsif Clk'event and Clk = '1' then
if Inst_Skip = '1' then
Inst <= (others => '0'); -- Flush (Force NOP)
else
Inst <= ROM_Data;
end if;
end if;
end process;
 
-- File address
File_Addr <= File_Addr_i;
i12 : if InstructionLength = 12 generate
File_Addr_i <= FSR(6 downto 0) when
-- pragma translate_off
is_x(ROM_Data) or
-- pragma translate_on
unsigned(ROM_Data(4 downto 0)) = 0 else
FSR(6 downto 5) & ROM_Data(4 downto 0);
end generate;
i14 : if InstructionLength = 14 generate
File_Addr_i <= STATUS(7) & FSR(7 downto 0) when
-- pragma translate_off
is_x(ROM_Data) or
-- pragma translate_on
unsigned(ROM_Data(6 downto 0)) = 0 else
STATUS(6 downto 5) & ROM_Data(6 downto 0);
Op_Bus(4 downto 0) <= PCLATH when
to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and
File_Rd_i = '1' else "ZZZZZ";
end generate;
process (Clk)
begin
if Clk'event and Clk = '1' then
File_Addr_r <= File_Addr_i;
File_Addr_i_r <= File_Addr_i;
end if;
end process;
 
-- PCLATH Register
process (Reset_n, Clk)
begin
if Reset_n = '0' then
PCLATH <= "00000";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and File_Wr_i = '1' then
PCLATH <= Res_Bus(4 downto 0);
end if;
end if;
end process;
 
-- Working register
Op_Bus <= W when W_Rd = '1' else "ZZZZZZZZ";
process (Clk)
begin
if Clk'event and Clk = '1' then
if W_Wr = '1' then
W <= Res_Bus;
end if;
end if;
end process;
 
-- Status register
Op_Bus <= STATUS when
to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and
File_Rd_i = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
STATUS <= "00011000";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and
File_Wr_i = '1' then
STATUS <= Res_Bus;
else
if STATUS_Wr(0) = '1' then
STATUS(0) <= STATUS_d(0);
end if;
if STATUS_Wr(1) = '1' then
STATUS(1) <= STATUS_d(1);
end if;
if STATUS_Wr(2) = '1' then
STATUS(2) <= STATUS_d(2);
end if;
end if;
end if;
end process;
 
-- FSR Register
Op_Bus <= FSR when
to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
File_Rd_i = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
FSR <= "11111111";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
File_Wr_i = '1' then
FSR <= Res_Bus;
end if;
end if;
end process;
 
-- Program counter
PC_CS <= '1' when to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 2 else '0';
ROM_Addr <= NPC(ROMAddressWidth - 1 downto 0);
pcs : PPX_PCS
generic map(
PC_Width => InstructionLength - 1,
StackAddrWidth => StackAddrWidth,
TopBoot => TopBoot)
port map(
Clk => Clk,
Reset_n => Reset_n,
CS => PC_CS,
Rd => File_Rd_i,
Wr => File_Wr_i,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Addr_In => Inst(InstructionLength - 4 downto 0),
PCLATH => PCLATH,
STATUS => STATUS(6 downto 5),
NPC => NPC,
Int => Int,
Sleep => Sleep_r,
Push => Push,
Pop => Pop,
Goto => Goto);
 
-- ALU
Op_Mux <= Inst(7 downto 0) when Imm_Op = '1' else W;
Res_Bus <= Op_Mux when B2Res = '1' else "ZZZZZZZZ";
alu : PPX_ALU
generic map(InstructionLength => InstructionLength)
port map(
Clk => Clk,
ROM_Data => ROM_Data,
A => Op_Bus,
B => Op_Mux,
Q => Res_Bus,
Skip => Inst_Skip,
Carry => STATUS(0),
Z_Skip => Z_Skip,
STATUS_d => STATUS_d,
STATUS_Wr => STATUS_Wr);
 
-- Instruction decoder
File_Rd <= File_Rd_i;
File_Wr <= File_Wr_i;
Inst_Skip <= Z_Skip or B_Skip or Sleep_r;
id : PPX_Ctrl
generic map(InstructionLength => InstructionLength)
port map(
Inst => Inst,
File_Rd => File_Rd_i,
File_Wr => File_Wr_i,
W_Wr => W_Wr,
W_Rd => W_Rd,
Imm_Op => Imm_Op,
B2Res => B2Res,
Push => Push,
Pop => Pop,
Goto => Goto,
IRet => IRet,
B_Skip => B_Skip,
Sleep => Sleep);
 
-- Interrupts and stuff
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Sleep_r <= '0';
Int <= '0';
Int_Acc <= '0';
Int_Ret <= '0';
elsif Clk'event and Clk = '1' then
if Sleep = '1' then
Sleep_r <= '1';
end if;
if Int_Trig = '1' then
Sleep_r <= '0';
end if;
if Int_Trig = '1' and GIE = '1' then -- extra check ???????????????
Int <= '1';
Int_Acc <= '1';
else
Int <= '0';
Int_Acc <= '0';
end if;
if IRet = '1' then
Int_Ret <= '1';
else
Int_Ret <= '0';
end if;
end if;
end process;
 
end;

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