URL
https://opencores.org/ocsvn/robust_reg/robust_reg/trunk
Subversion Repositories robust_reg
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Rev 2 → Rev 3
/robust_reg/run/run.sh
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/robust_reg/src/regfile.html
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/robust_reg/src/regfile.v
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/robust_reg/src/regfile.h
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/robust_reg/src/regs.xls
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robust_reg/src/regs.xls
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Index: robust_reg/src/def_regfile.txt
===================================================================
--- robust_reg/src/def_regfile.txt (revision 2)
+++ robust_reg/src/def_regfile.txt (nonexistent)
@@ -1,27 +0,0 @@
-INCLUDE def_reg.txt
-
-SWAP FFD 1 ##flip-flop delay
-
-## Types:
-## RW - read / write (output from block)
-## RO - read only (input to block)
-## WO - write only (output to block)
-## IW - internal write (output to block - logic is added especially)
-## IR - internal read (no port - logic is added especially)
-ENUM TYPE_RW TYPE_RO TYPE_WO TYPE_IW TYPE_IR
-
-SWAP TYPE_TYPE_RW Read and Write
-SWAP TYPE_TYPE_RO Read only
-SWAP TYPE_TYPE_WO Write only
-
-GROUP APB is {
- pclken 1 input
- psel 1 input
- penable 1 input
- paddr ADDR_BITS input
- pwrite 1 input
- pwdata 32 input
- prdata 32 output
- pslverr 1 output
- pready 1 output
-}
Index: robust_reg/src/def_reg.txt
===================================================================
--- robust_reg/src/def_reg.txt (revision 2)
+++ robust_reg/src/def_reg.txt (nonexistent)
@@ -1,24 +0,0 @@
-
-
- SWAP REGNAME DMA
- SWAP REG_NUM 6
-
-
- GROUP REGS is {
- CONFIG0 SON(ADDR 0) SON(TYPE TYPE_RW) SON(DESC Configuration register 0) ##reg number 0
- CONFIG1 SON(ADDR 4) SON(TYPE TYPE_RW) SON(DESC Configuration register 1) ##reg number 1
- CONFIG2 SON(ADDR 8) SON(TYPE TYPE_RW) SON(DESC Configuration register 2) ##reg number 2
- CONFIG3 SON(ADDR C) SON(TYPE TYPE_RW) SON(DESC Configuration register 3) ##reg number 3
- START SON(ADDR 20) SON(TYPE TYPE_WO) SON(DESC Start register) ##reg number 4
- STATUS SON(ADDR 30) SON(TYPE TYPE_RO) SON(DESC Status register) ##reg number 5
- }
-
- GROUP REG0 is { ;; rd_start_addr 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) SON(DESC Read start address) ;; }
- GROUP REG1 is { ;; wr_start_addr 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) SON(DESC Write start address) ;; }
- GROUP REG2 is { ;; buffer_size 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) SON(DESC Buffer size in bytes) ;; }
- GROUP REG3 is { ;; set_int 1 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RO) SON(DESC Interrupt was set on last command)
- cmd_last 1 SON(START 1) SON(DEFAULT 1) SON(TYPE TYPE_RW) SON(DESC Last command in list)
- next_addr 28 SON(START 4) SON(DEFAULT 0) SON(TYPE TYPE_RW) SON(DESC Address of next command) ;; }
- GROUP REG4 is { ;; ch_start 1 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_WO) SON(DESC Start channel) ;; }
- GROUP REG5 is { ;; buff_count 16 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RO) SON(DESC Number of buffers completed)
- int_count 6 SON(START 16) SON(DEFAULT 0) SON(TYPE TYPE_RO) SON(DESC Number of interrupts pending) ;; }
Index: robust_reg/trunk/run/README.txt
===================================================================
--- robust_reg/trunk/run/README.txt (nonexistent)
+++ robust_reg/trunk/run/README.txt (revision 3)
@@ -0,0 +1,36 @@
+
+------------------------------ Remark ----------------------------------------
+This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
+It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
+------------------------------------------------------------------------------
+
+RobustVerilog generic APB register file
+
+This register file generator uses an Excel worksheet and produces:
+1. Verilog register file
+2. C header file
+3. HTML documentation
+
+The Excel worksheet named Database holds the registers and their fields.
+
+Register and field types:
+RW - Read and Write
+RO - Read only
+WO - Write only
+
+The Excel worksheet automatically generates the RobustVerilog definition files in the RobustVerilog_regs and RobustVerilog_fields worksheets
+
+Creating the output files:
+1. Make changes as required in the Excel Database worksheet
+2. Save worksheet RobustVerilog_regs as text to def_regs.txt (space delimiters)
+3. Save worksheet RobustVerilog_fields as text to def_fields.txt (space delimiters)
+4. Run the run.sh script in the run dicertory
+5. Output files will be in run/out directory
+
+
+In order to create the design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
+
+For any questions / remarks / suggestions / bugs please contact info@provartec.com.
+
+
+
Index: robust_reg/trunk/run/run.sh
===================================================================
--- robust_reg/trunk/run/run.sh (nonexistent)
+++ robust_reg/trunk/run/run.sh (revision 3)
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+echo Starting RobustVerilog regfile run
+rm -rf out
+mkdir out
+
+../../../robust ../src/regfile.v -od out -header
+../../../robust ../src/regfile.h -od out -header
+../../../robust ../src/regfile.html -od out
+
+echo Completed RobustVerilog regfile run - results in run/out/
Index: robust_reg/trunk/src/regfile.html
===================================================================
--- robust_reg/trunk/src/regfile.html (nonexistent)
+++ robust_reg/trunk/src/regfile.html (revision 3)
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+OUTFILE REGNAME_regfile.html
+INCLUDE def_regfile.txt
+
+
+
+
+LOOP RX REG_NUM
+
-
+
- GROUP_REGS[RX]
+
-
+
- Offset: 0xGROUP_REGS[RX].ADDR +
- Access: TYPE_GROUP_REGS[RX].TYPE +
- Description: GROUP_REGS[RX].DESC +
- Fields:
+
-
+ GROUP_REGRX [EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START]
Description: GROUP_REGRX.DESC
Access: TYPE_GROUP_REGRX.TYPE
Default value: GROUP_REGRX.DEFAULT
robust_reg/trunk/src/regs.xls
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Index: robust_reg/trunk/src/def_regfile.txt
===================================================================
--- robust_reg/trunk/src/def_regfile.txt (nonexistent)
+++ robust_reg/trunk/src/def_regfile.txt (revision 3)
@@ -0,0 +1,28 @@
+INCLUDE def_regs.txt
+INCLUDE def_fields.txt
+
+SWAP FFD 1 ##flip-flop delay
+
+## Types:
+## RW - read / write (output from block)
+## RO - read only (input to block)
+## WO - write only (output to block)
+## IW - internal write (output to block - logic is added especially)
+## IR - internal read (no port - logic is added especially)
+ENUM TYPE_RW TYPE_RO TYPE_WO TYPE_IW TYPE_IR
+
+SWAP TYPE_TYPE_RW Read and Write
+SWAP TYPE_TYPE_RO Read only
+SWAP TYPE_TYPE_WO Write only
+
+GROUP APB is {
+ pclken 1 input
+ psel 1 input
+ penable 1 input
+ paddr ADDR_BITS input
+ pwrite 1 input
+ pwdata 32 input
+ prdata 32 output
+ pslverr 1 output
+ pready 1 output
+}
Index: robust_reg/trunk/src/def_regs.txt
===================================================================
--- robust_reg/trunk/src/def_regs.txt (nonexistent)
+++ robust_reg/trunk/src/def_regs.txt (revision 3)
@@ -0,0 +1,299 @@
+
+
+ SWAP REGNAME DMA
+ SWAP REG_NUM 6
+
+
+ GROUP REGS is {
+ CONFIG0 SON(ADDR 0) SON(TYPE TYPE_RW) ##reg number 0
+ CONFIG1 SON(ADDR 4) SON(TYPE TYPE_RW) ##reg number 1
+ CONFIG2 SON(ADDR 8) SON(TYPE TYPE_RW) ##reg number 2
+ CONFIG3 SON(ADDR C) SON(TYPE TYPE_RW) ##reg number 3
+ START SON(ADDR 20) SON(TYPE TYPE_WO) ##reg number 4
+ STATUS SON(ADDR 30) SON(TYPE TYPE_RO) ##reg number 5
+ }
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