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/rv01_riscv_core/trunk/SIM/ISIM/README.txt
0,0 → 1,14
--------------------------------------------------------------- |
-- RV01 self-test simulation with Xilinx isim |
--------------------------------------------------------------- |
|
The synthesis script RV01_selftest.tcl in ../SYN/XILINX includes |
in the project the simulation test-bench RV01_selftest_TB.vhd |
too, so that self-test module can be simulated by simply starting |
isim simulator inside the Vivado project (setting |
module RV01_SELFTEST_TB as top-level module, if needed). |
|
The selftest module simulation runs for ~1.1ms, when simulation |
stops, wave window should look like the snapshot in file |
waves_1d1ms_vivado.PNG (both DONE and PASS signals are '1'). |
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/rv01_riscv_core/trunk/SIM/ISIM/waves_1d1ms_isim.PNG
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rv01_riscv_core/trunk/SIM/ISIM/waves_1d1ms_isim.PNG
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