URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
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Rev 2 → Rev 3
/trunk/hdl/filelist.dc
0,0 → 1,233
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/u1_lib.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/m1_lib.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v |
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v |
|
/* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */ |
|
elaborate s1_top |
link |
uniquify |
/* check_design */ |
|
create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i") |
set_input_delay 1 -max -clock sys_clock_i all_inputs() - find(port, "sys_clock_i") |
set_output_delay 1 -max -clock sys_clock_i all_outputs() |
|
compile -map_effort high |
|
write -format db -hierarchy -output s1_top.db |
write -format verilog -hierarchy -output s1_top.v |
|
report_area > report_area.txt |
report_timing > report_timing.txt |
report_constraint -all_violators > report_constraint.txt |
|
quit |
|
/trunk/hdl/filelist.icarus
0,0 → 1,214
/usr/design/simplyrisc-s1/hdl/behav/sparc_libs/m1_lib.v |
/usr/design/simplyrisc-s1/hdl/behav/sparc_libs/u1_lib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v |
/usr/design/simplyrisc-s1/hdl/behav/testbench/mem_harness.v |
/usr/design/simplyrisc-s1/hdl/behav/testbench/testbench.v |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/include |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/s1_top |
/trunk/hdl/filelist.vcs
0,0 → 1,214
-v /usr/design/simplyrisc-s1/hdl/behav/sparc_libs/m1_lib.v |
-v /usr/design/simplyrisc-s1/hdl/behav/sparc_libs/u1_lib.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v |
-v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v |
/usr/design/simplyrisc-s1/hdl/behav/testbench/mem_harness.v |
/usr/design/simplyrisc-s1/hdl/behav/testbench/testbench.v |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/include |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/s1_top |
/trunk/hdl/filelist.fpga
0,0 → 1,213
/usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/u1_lib.v |
/usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/m1_lib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v |
/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v |
/usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/include |
+incdir+/usr/design/simplyrisc-s1/hdl/rtl/s1_top |
+define+FPGA_SYN |