OpenCores
URL https://opencores.org/ocsvn/simu_mem/simu_mem/trunk

Subversion Repositories simu_mem

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/trunk/bench/verilog/samsung/k7n643645m_R03.v
0,0 → 1,48
`define addr_bits 21
`define data_bits 36
 
module K7N643645M (
Dq,
Addr,
K,
CKEb,
Bwa_n,
Bwb_n,
Bwc_n,
Bwd_n,
WEb,
ADV,
OEb,
CS1b,
CS2,
CS2b,
LBOb,
ZZ);
 
parameter mem_sizes = 2 * 1024 * 1024 - 1;
 
inout [(`data_bits - 1) : 0] Dq;
input [(`addr_bits - 1) : 0] Addr;
 
input K;
input ADV;
input CKEb;
input WEb;
 
input Bwa_n;
input Bwb_n;
input Bwc_n;
input Bwd_n;
 
input CS1b;
input CS2;
input CS2b;
input OEb;
input ZZ;
input LBOb;
 
initial
begin
$display("Replace this file with the original file from Samsung. You can find it on the Samsung semiconductor home page under High Speed SRAM / NtRAM / K7N643645M");
end
endmodule
/trunk/bench/vhdl/misc/math_pkg.vhd
0,0 → 1,56
----------------------------------------------------------------------
---- ----
---- Auxiliary package with mathematical functions. ----
---- ----
---- This file is part of the simu_mem project ----
---- ----
---- Authors: ----
---- - Michael Geng, vhdl@MichaelGeng.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
PACKAGE math_pkg IS
-- linear congruential generator (a random number generator)
-- use result for the seed in the next call
-- preferably use bits 30...16
FUNCTION lcg (seed : IN NATURAL) RETURN NATURAL;
END PACKAGE math_pkg;
 
PACKAGE BODY math_pkg IS
FUNCTION lcg (seed : IN NATURAL) RETURN NATURAL IS
-- Constants from: http://en.wikipedia.org/wiki/Linear_congruential_generator
CONSTANT a : NATURAL := 16807;
CONSTANT c : NATURAL := 0;
CONSTANT m : NATURAL := 2 ** 31 - 1;
BEGIN
RETURN (a * seed + c) MOD m;
END FUNCTION;
END PACKAGE BODY math_pkg;
trunk/bench/vhdl/misc/math_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vhdl/zbt_ram/patgen_pkg.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/patgen_pkg.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/patgen_pkg.vhd (revision 3) @@ -0,0 +1,91 @@ +---------------------------------------------------------------------- +---- ---- +---- Package used by the test pattern generator for the ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model. ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY ieee, misc; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE misc.math_pkg.ALL; + +PACKAGE patgen_pkg IS + COMPONENT patgen IS + GENERIC ( + clk_periode : TIME); + port ( + Clk : IN STD_LOGIC; + Rst : IN STD_LOGIC; + Ena : IN STD_LOGIC; + A : OUT STD_LOGIC_VECTOR; + D : OUT STD_LOGIC_VECTOR; + CKE_n : OUT STD_LOGIC; + CS1_n : OUT STD_LOGIC; + CS2 : OUT STD_LOGIC; + CS2_n : OUT STD_LOGIC; + WE_n : OUT STD_LOGIC; + BW_n : OUT STD_LOGIC_VECTOR; + OE_n : OUT STD_LOGIC; + ADV : OUT STD_LOGIC; + ZZ : OUT STD_LOGIC; + LBO_n : OUT STD_LOGIC); + END COMPONENT patgen; + + PROCEDURE random_vector ( + SIGNAL D : OUT STD_LOGIC_VECTOR; + VARIABLE random : INOUT NATURAL); +END PACKAGE patgen_pkg; + +PACKAGE BODY patgen_pkg IS + PROCEDURE random_vector ( + SIGNAL D : OUT STD_LOGIC_VECTOR; + VARIABLE random : INOUT NATURAL) IS + BEGIN + IF (D'length >= 31) THEN + random := lcg (random); + D (30 DOWNTO 0) <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(30 DOWNTO 0)); + + random := lcg (random); + D (D'length - 1 DOWNTO 31) <= + STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D'length - 32 DOWNTO 0)); + else + random := lcg (random); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D'length - 1 DOWNTO 0)); + END IF; + END PROCEDURE random_vector; +END PACKAGE BODY patgen_pkg; Index: trunk/bench/vhdl/zbt_ram/testbench.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/testbench.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/testbench.vhd (revision 3) @@ -0,0 +1,201 @@ +---------------------------------------------------------------------- +---- ---- +---- Testbench for the ZBT_RAM simulation model ---- +---- ---- +---- This file is part of the simu_mem project ---- +---- ---- +---- Description ---- +---- This testbench checks if the output of the simulation model ---- +---- matches the output of the reference model. Every mismatch ---- +---- prints an error message. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY ieee, RAM, samsung; +USE ieee.std_logic_1164.ALL; +USE work.patgen_pkg.ALL; + +ENTITY testbench IS + GENERIC ( + -- Address bus width + A_width : POSITIVE := 21; + -- Data bus width + D_width : POSITIVE := 36; + + -- How many clock cycles shall be simulated? + N_simulation_cycles : POSITIVE := 100000); +END ENTITY testbench; + +ARCHITECTURE arch OF testbench IS + CONSTANT clk_periode : TIME := 4 ns; + CONSTANT reset_time : TIME := 100 ns; + + SIGNAL Clk, Rst : STD_LOGIC; + SIGNAL clk_ena : STD_LOGIC := '1'; + SIGNAL Count : INTEGER; + + SIGNAL A : STD_LOGIC_VECTOR (A_width - 1 DOWNTO 0); + SIGNAL D_DUT : STD_LOGIC_VECTOR (D_width - 1 DOWNTO 0); + SIGNAL D_Reference : STD_LOGIC_VECTOR (D_width - 1 DOWNTO 0); + SIGNAL D_Patgen : STD_LOGIC_VECTOR (D_width - 1 DOWNTO 0); + SIGNAL ADV : STD_LOGIC; + SIGNAL WE_n : STD_LOGIC; + SIGNAL CKE_n : STD_LOGIC; + SIGNAL CS1_n : STD_LOGIC; + SIGNAL CS2 : STD_LOGIC; + SIGNAL CS2_n : STD_LOGIC; + SIGNAL BW_n : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0); + SIGNAL OE_n : STD_LOGIC; + SIGNAL ZZ : STD_LOGIC; + SIGNAL LBO_n : STD_LOGIC; + SIGNAL ZZ_delayed_1 : STD_LOGIC; + SIGNAL ZZ_delayed_2 : STD_LOGIC; +BEGIN + ASSERT D_width mod 9 = 0 + REPORT "Error: D_width must be a multiple of 9" + SEVERITY FAILURE; + + iDUT : ENTITY RAM.ZBT_RAM + GENERIC MAP ( + Debug => 0) + PORT MAP ( + Clk => Clk, + D => D_DUT, + Q => D_DUT, + A => A, + CKE_n => CKE_n, + CS1_n => CS1_n, + CS2 => CS2, + CS2_n => CS2_n, + WE_n => WE_n, + BW_n => BW_n, + OE_n => OE_n, + ADV => ADV, + ZZ => ZZ, + LBO_n => LBO_n); + + iReference : ENTITY Samsung.K7N643645M + PORT MAP ( + Dq => D_Reference, + Addr => A, + K => Clk, + CKEb => CKE_n, + Bwa_n => BW_n (0), + Bwb_n => BW_n (1), + Bwc_n => BW_n (2), + Bwd_n => BW_n (3), + WEb => WE_n, + ADV => ADV, + OEb => OE_n, + CS1b => CS1_n, + CS2 => CS2, + CS2b => CS2_n, + LBOb => LBO_n, + ZZ => ZZ); + + pCheck : PROCESS (Rst, Clk) IS + BEGIN + IF (Rst = '0') AND rising_edge (Clk) THEN + FOR BankNoMinus1 in 0 to D_width / 9 - 1 LOOP + IF (ZZ_delayed_2 = '0') THEN + IF ((D_DUT ( 9 * (BankNoMinus1 + 1) - 1 DOWNTO 9 * BankNoMinus1) /= (8 DOWNTO 0 => 'U')) OR + (D_Reference (9 * (BankNoMinus1 + 1) - 1 DOWNTO 9 * BankNoMinus1) /= (8 DOWNTO 0 => 'X'))) THEN + ASSERT D_DUT ( 9 * (BankNoMinus1 + 1) - 1 DOWNTO 9 * BankNoMinus1) = + D_Reference (9 * (BankNoMinus1 + 1) - 1 DOWNTO 9 * BankNoMinus1) + REPORT "Error: DUT and reference model mismatch in Bank no " & + INTEGER'IMAGE (BankNoMinus1) + SEVERITY ERROR; + END IF; + END IF; + END LOOP; + END IF; + END PROCESS pCheck; + + iPatgen : patgen + GENERIC MAP ( + clk_periode => clk_periode) + PORT MAP ( + Clk => Clk, + Rst => Rst, + Ena => clk_ena, + A => A, + D => D_Patgen, + CKE_n => CKE_n, + CS1_n => CS1_n, + CS2 => CS2, + CS2_n => CS2_n, + WE_n => WE_n, + BW_n => BW_n, + OE_n => OE_n, + ADV => ADV, + ZZ => ZZ, + LBO_n => LBO_n); + + D_DUT <= D_Patgen; + D_Reference <= D_Patgen; + + pClk : PROCESS IS + BEGIN + Rst <= '1'; + Clk <= '1'; + WAIT FOR reset_time; + Rst <= '0'; + + WHILE (clk_ena = '1') LOOP + WAIT FOR clk_periode / 2; + Clk <= NOT Clk; + END LOOP; + + WAIT; + END PROCESS pClk; + + pCounter : PROCESS (Clk, Rst) IS + BEGIN + IF (Rst = '1') THEN + Count <= 0; + clk_ena <= '1'; + ZZ_delayed_1 <= '0'; + ZZ_delayed_2 <= '0'; + ELSIF rising_edge (Clk) THEN + IF (Count < N_simulation_cycles) THEN + Count <= Count + 1; + ELSE + clk_ena <= '0'; + END IF; + + ZZ_delayed_1 <= ZZ; + ZZ_delayed_2 <= ZZ_delayed_1; + END IF; + END PROCESS pCounter; +END ARCHITECTURE; Index: trunk/bench/vhdl/zbt_ram/testbench_random_conf.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/testbench_random_conf.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/testbench_random_conf.vhd (revision 3) @@ -0,0 +1,48 @@ +---------------------------------------------------------------------- +---- ---- +---- This configuration simulates a random pattern. ---- +---- ---- +---- This file is part of the simu_mem project ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +USE work.patgen_pkg.ALL; + +configuration random_conf OF testbench IS + FOR arch + FOR iPatgen : work.patgen_pkg.patgen USE + ENTITY work.patgen (random); + END FOR; + END FOR; +END configuration random_conf; Index: trunk/bench/vhdl/zbt_ram/testbench_deterministic_conf.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/testbench_deterministic_conf.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/testbench_deterministic_conf.vhd (revision 3) @@ -0,0 +1,48 @@ +---------------------------------------------------------------------- +---- ---- +---- This configuration simulates a deterministic pattern. ---- +---- ---- +---- This file is part of the simu_mem project ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +USE work.patgen_pkg.ALL; + +configuration deterministic_conf OF testbench IS + FOR arch + FOR iPatgen : work.patgen_pkg.patgen USE + ENTITY work.patgen (deterministic); + END FOR; + END FOR; +END configuration deterministic_conf; Index: trunk/bench/vhdl/zbt_ram/patgen_entity.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/patgen_entity.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/patgen_entity.vhd (revision 3) @@ -0,0 +1,78 @@ +---------------------------------------------------------------------- +---- ---- +---- Test pattern generator for the ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model. ---- +---- Entity declaration only. ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY ieee, misc, RAM; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE misc.math_pkg.ALL; +USE RAM.ZBT_RAM_pkg.ALL; +USE work.patgen_pkg.ALL; + +ENTITY patgen IS + GENERIC ( + clk_periode : TIME; + tOE : TIME := 2.7 ns; + tWS : TIME := 1.2 ns; + tWH : TIME := 0.3 ns); + PORT ( + -- system clock + Clk : IN STD_LOGIC; + + -- global reset + Rst : IN STD_LOGIC; + + -- clock enable + Ena : IN STD_LOGIC; + + A : OUT STD_LOGIC_VECTOR; + D : OUT STD_LOGIC_VECTOR; + CKE_n : BUFFER STD_LOGIC; + CS1_n : BUFFER STD_LOGIC; + CS2 : BUFFER STD_LOGIC; + CS2_n : BUFFER STD_LOGIC; + WE_n : BUFFER STD_LOGIC; + BW_n : BUFFER STD_LOGIC_VECTOR; + OE_n : BUFFER STD_LOGIC; + ADV : BUFFER STD_LOGIC; + ZZ : BUFFER STD_LOGIC; + LBO_n : BUFFER STD_LOGIC); +END ENTITY patgen; Index: trunk/bench/vhdl/zbt_ram/patgen_arch_random.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/patgen_arch_random.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/patgen_arch_random.vhd (revision 3) @@ -0,0 +1,230 @@ +---------------------------------------------------------------------- +---- ---- +---- Test pattern generator for the ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model. ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Description ---- +---- This architecture generates a random pattern. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +ARCHITECTURE random OF patgen IS + CONSTANT D_width : INTEGER := D'LENGTH; + CONSTANT A_width : INTEGER := A'LENGTH; + + SIGNAL next_state : state_type; + SIGNAL state : state_type; + SIGNAL last_state : state_type; + SIGNAL next_operation : state_type; + SIGNAL operation : state_type; + SIGNAL want_sleep : STD_LOGIC; + SIGNAL want_sleep_delayed_1 : STD_LOGIC; + SIGNAL want_sleep_delayed_2 : STD_LOGIC; + SIGNAL ZZ_delayed_1 : STD_LOGIC; +BEGIN + ASSERT A_width >= 5 + REPORT "Error: Address widths < 5 bits not supported by the test pattern generator" + SEVERITY FAILURE; + + D <= (D_width - 1 DOWNTO 0 => 'L'); + + next_state <= calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation) WHEN (CKE_n = '0'); + next_operation <= calc_operation (next_state, operation); + + pPatternGenerator : PROCESS (Clk, Rst) IS + VARIABLE random : NATURAL; + VARIABLE random_u : unsigned (31 DOWNTO 0); + VARIABLE OE_n_v : STD_LOGIC; + VARIABLE WE_n_v : STD_LOGIC; + VARIABLE nWE_next_rising_edge : STD_LOGIC; + VARIABLE ADV_v : STD_LOGIC; + VARIABLE CKE_n_v : STD_LOGIC; + VARIABLE nBW_v : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0); + VARIABLE nCS1_v : STD_LOGIC; + VARIABLE CS2_v : STD_LOGIC; + VARIABLE nCS2_v : STD_LOGIC; + VARIABLE ZZ_v : STD_LOGIC; + VARIABLE State_v : state_type; + BEGIN + IF (Rst = '1') THEN + random := 1; + WE_n_v := '0'; + D <= (D_width - 1 DOWNTO 0 => '0'); + A <= (A_width - 1 DOWNTO 0 => '0'); + ADV <= '0'; + WE_n <= '0'; + CKE_n <= '0'; + CS1_n <= '0'; + CS2 <= '0'; + CS2_n <= '0'; + CKE_n <= '0'; + OE_n <= '0'; + ZZ <= '0'; + ZZ_delayed_1 <= '0'; + LBO_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + last_state <= Deselect; + want_sleep <= '0'; + want_sleep_delayed_1 <= '0'; + want_sleep_delayed_2 <= '0'; + ELSIF RISING_EDGE (Clk) THEN + state <= next_state; + operation <= next_operation; + + IF ((WE_n_v = '1') OR (next_state = sleep) OR (state = sleep)) THEN + WE_n <= '1' AFTER tWH; + END IF; + + IF ((state = write) OR (state = write_continue)) THEN + OE_n_v := '1'; + ELSE + random := lcg (random); + OE_n_v := TO_UNSIGNED (random, 32)(0); + END IF; + OE_n <= OE_n_v AFTER clk_periode - tOE; + ELSIF FALLING_EDGE (Clk) THEN + IF (Ena = '1') THEN + random := lcg (random); + IF ((state = sleep) OR (last_state = sleep)) THEN + ADV_v := '0'; + ELSE + ADV_v := TO_UNSIGNED (random, 32)(0); + END IF; + WE_n_v := TO_UNSIGNED (random, 32)(1); + CKE_n_v := TO_UNSIGNED (random, 32)(2); + LBO_n <= TO_UNSIGNED (random, 32)(3); + nBW_v := STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + A <= TO_UNSIGNED (random, 32)(8) & (A_width - 5 DOWNTO 0 => '0') & + TO_UNSIGNED (random, 32)(9) & "00"; + + IF (last_state = write) OR (last_state = write_continue) THEN + random_vector (D, random); + ELSE + D <= (D_width - 1 DOWNTO 0 => 'Z'); + END IF; + + -- disable clock only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + CKE_n_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- deassert CS1_n only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + nCS1_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- deassert CS2 only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + CS2_v := random_u (0) OR random_u (1) OR random_u (2) OR random_u (3) OR random_u (4) OR + random_u (5) OR random_u (6) OR random_u (7) OR random_u (8) OR random_u (9); + + -- deassert CS2_n only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + nCS2_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- put RAM in sleep mode only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + want_sleep <= random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + want_sleep_delayed_1 <= want_sleep; + want_sleep_delayed_2 <= want_sleep_delayed_1; + ZZ_v := want_sleep_delayed_2; + ZZ_delayed_1 <= ZZ; + + IF (WE_n = '0') AND (WE_n_v = '1') THEN + nWE_next_rising_edge := '0'; + ELSE + nWE_next_rising_edge := WE_n_v; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (State_v = invalid_state) THEN + ADV_v := '0'; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (State_v = invalid_state) THEN + nBW_v (0) := '0'; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (((want_sleep = '1') OR (want_sleep_delayed_1 = '1') OR (want_sleep_delayed_2 = '1')) AND + ((State_v = write) OR (State_v = write_continue))) THEN + nCS1_v := '1'; + ADV_v := '0'; + END IF; + + IF (((ZZ = '1') OR (ZZ_delayed_1 = '1')) AND + ((State_v = write))) THEN + nCS1_v := '0'; + CS2_v := '1'; + nCS2_v := '0'; + WE_n_v := '1'; + ADV_v := '0'; + OE_n_v := '0'; + CKE_n_v := '0'; + END IF; + + ADV <= ADV_v; + CKE_n <= CKE_n_v; + BW_n <= nBW_v; + CKE_n <= CKE_n_v; + CS1_n <= nCS1_v; + CS2 <= CS2_v; + CS2_n <= nCS2_v; + ZZ <= ZZ_v; + + IF (WE_n_v = '0') THEN + WE_n <= '0' AFTER clk_periode * 0.5 - tWS; + END IF; + + IF (CKE_n = '0') THEN + last_state <= state; + END IF; + END IF; + END IF; + END PROCESS pPatternGenerator; +END ARCHITECTURE random; Index: trunk/bench/vhdl/zbt_ram/patgen.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/patgen.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/patgen.vhd (revision 3) @@ -0,0 +1,920 @@ +---------------------------------------------------------------------- +---- ---- +---- Test pattern generator for the ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model. ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY ieee, misc, RAM; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE misc.math_pkg.ALL; +USE RAM.ZBT_RAM_pkg.ALL; +USE work.patgen_pkg.ALL; + +ENTITY patgen IS + GENERIC ( + clk_periode : TIME; + tOE : TIME := 2.7 ns; + tWS : TIME := 1.2 ns; + tWH : TIME := 0.3 ns); + PORT ( + -- system clock + Clk : IN STD_LOGIC; + + -- global reset + Rst : IN STD_LOGIC; + + -- clock enable + Ena : IN STD_LOGIC; + + A : OUT STD_LOGIC_VECTOR; + D : OUT STD_LOGIC_VECTOR; + CKE_n : BUFFER STD_LOGIC; + CS1_n : BUFFER STD_LOGIC; + CS2 : BUFFER STD_LOGIC; + CS2_n : BUFFER STD_LOGIC; + WE_n : BUFFER STD_LOGIC; + BW_n : BUFFER STD_LOGIC_VECTOR; + OE_n : BUFFER STD_LOGIC; + ADV : BUFFER STD_LOGIC; + ZZ : BUFFER STD_LOGIC; + LBO_n : BUFFER STD_LOGIC); +END ENTITY patgen; + +ARCHITECTURE random OF patgen IS + CONSTANT D_width : INTEGER := D'LENGTH; + CONSTANT A_width : INTEGER := A'LENGTH; + + SIGNAL next_state : state_type; + SIGNAL state : state_type; + SIGNAL last_state : state_type; + SIGNAL next_operation : state_type; + SIGNAL operation : state_type; + SIGNAL want_sleep : STD_LOGIC; + SIGNAL want_sleep_delayed_1 : STD_LOGIC; + SIGNAL want_sleep_delayed_2 : STD_LOGIC; + SIGNAL ZZ_delayed_1 : STD_LOGIC; +BEGIN + ASSERT A_width >= 5 + REPORT "Error: Address widths < 5 bits not supported by the test pattern generator" + SEVERITY FAILURE; + + D <= (D_width - 1 DOWNTO 0 => 'L'); + + next_state <= calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation) WHEN (CKE_n = '0'); + next_operation <= calc_operation (next_state, operation); + + pPatternGenerator : PROCESS (Clk, Rst) IS + VARIABLE random : NATURAL; + VARIABLE random_u : unsigned (31 DOWNTO 0); + VARIABLE OE_n_v : STD_LOGIC; + VARIABLE WE_n_v : STD_LOGIC; + VARIABLE nWE_next_rising_edge : STD_LOGIC; + VARIABLE ADV_v : STD_LOGIC; + VARIABLE CKE_n_v : STD_LOGIC; + VARIABLE nBW_v : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0); + VARIABLE nCS1_v : STD_LOGIC; + VARIABLE CS2_v : STD_LOGIC; + VARIABLE nCS2_v : STD_LOGIC; + VARIABLE ZZ_v : STD_LOGIC; + VARIABLE State_v : state_type; + BEGIN + IF (Rst = '1') THEN + random := 1; + WE_n_v := '0'; + D <= (D_width - 1 DOWNTO 0 => '0'); + A <= (A_width - 1 DOWNTO 0 => '0'); + ADV <= '0'; + WE_n <= '0'; + CKE_n <= '0'; + CS1_n <= '0'; + CS2 <= '0'; + CS2_n <= '0'; + CKE_n <= '0'; + OE_n <= '0'; + ZZ <= '0'; + ZZ_delayed_1 <= '0'; + LBO_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + last_state <= Deselect; + want_sleep <= '0'; + want_sleep_delayed_1 <= '0'; + want_sleep_delayed_2 <= '0'; + ELSIF RISING_EDGE (Clk) THEN + state <= next_state; + operation <= next_operation; + + IF ((WE_n_v = '1') OR (next_state = sleep) OR (state = sleep)) THEN + WE_n <= '1' AFTER tWH; + END IF; + + IF ((state = write) OR (state = write_continue)) THEN + OE_n_v := '1'; + ELSE + random := lcg (random); + OE_n_v := TO_UNSIGNED (random, 32)(0); + END IF; + OE_n <= OE_n_v AFTER clk_periode - tOE; + ELSIF FALLING_EDGE (Clk) THEN + IF (Ena = '1') THEN + random := lcg (random); + IF ((state = sleep) OR (last_state = sleep)) THEN + ADV_v := '0'; + ELSE + ADV_v := TO_UNSIGNED (random, 32)(0); + END IF; + WE_n_v := TO_UNSIGNED (random, 32)(1); + CKE_n_v := TO_UNSIGNED (random, 32)(2); + LBO_n <= TO_UNSIGNED (random, 32)(3); + nBW_v := STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + A <= TO_UNSIGNED (random, 32)(8) & (A_width - 5 DOWNTO 0 => '0') & + TO_UNSIGNED (random, 32)(9) & "00"; + + IF (last_state = write) OR (last_state = write_continue) THEN + random_vector (D, random); + ELSE + D <= (D_width - 1 DOWNTO 0 => 'Z'); + END IF; + + -- disable clock only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + CKE_n_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- deassert CS1_n only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + nCS1_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- deassert CS2 only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + CS2_v := random_u (0) OR random_u (1) OR random_u (2) OR random_u (3) OR random_u (4) OR + random_u (5) OR random_u (6) OR random_u (7) OR random_u (8) OR random_u (9); + + -- deassert CS2_n only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + nCS2_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + + -- put RAM in sleep mode only about every 1024 cycles + random := lcg (random); + random_u := TO_UNSIGNED (random, 32); + want_sleep <= random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND + random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9); + want_sleep_delayed_1 <= want_sleep; + want_sleep_delayed_2 <= want_sleep_delayed_1; + ZZ_v := want_sleep_delayed_2; + ZZ_delayed_1 <= ZZ; + + IF (WE_n = '0') AND (WE_n_v = '1') THEN + nWE_next_rising_edge := '0'; + ELSE + nWE_next_rising_edge := WE_n_v; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (State_v = invalid_state) THEN + ADV_v := '0'; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (State_v = invalid_state) THEN + nBW_v (0) := '0'; + END IF; + + State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v, + ZZ_v, operation); + IF (((want_sleep = '1') OR (want_sleep_delayed_1 = '1') OR (want_sleep_delayed_2 = '1')) AND + ((State_v = write) OR (State_v = write_continue))) THEN + nCS1_v := '1'; + ADV_v := '0'; + END IF; + + IF (((ZZ = '1') OR (ZZ_delayed_1 = '1')) AND + ((State_v = write))) THEN + nCS1_v := '0'; + CS2_v := '1'; + nCS2_v := '0'; + WE_n_v := '1'; + ADV_v := '0'; + OE_n_v := '0'; + CKE_n_v := '0'; + END IF; + + ADV <= ADV_v; + CKE_n <= CKE_n_v; + BW_n <= nBW_v; + CKE_n <= CKE_n_v; + CS1_n <= nCS1_v; + CS2 <= CS2_v; + CS2_n <= nCS2_v; + ZZ <= ZZ_v; + + IF (WE_n_v = '0') THEN + WE_n <= '0' AFTER clk_periode * 0.5 - tWS; + END IF; + + IF (CKE_n = '0') THEN + last_state <= state; + END IF; + END IF; + END IF; + END PROCESS pPatternGenerator; +END ARCHITECTURE random; + +ARCHITECTURE Deterministic OF patgen IS + -- Patterns according to K7N643645M, 72Mb NtRAM Specification, Samsung, Rev. 1.3 September 2008 + + CONSTANT D_width : INTEGER := D'LENGTH; + CONSTANT A_width : INTEGER := A'LENGTH; +BEGIN + pPatternGenerator : PROCESS IS + VARIABLE random : NATURAL; + VARIABLE FirstTime : BOOLEAN := TRUE; + VARIABLE WE_n_v : STD_LOGIC; + BEGIN + -- initialisations + random := 1; + D <= (D_width - 1 DOWNTO 0 => '0'); + A <= (A_width - 1 DOWNTO 0 => '0'); + ADV <= '0'; + WE_n <= '0'; + CKE_n <= '0'; + CS1_n <= '0'; + CS2 <= '0'; + CS2_n <= '0'; + CKE_n <= '0'; + OE_n <= '0'; + ZZ <= '0'; + LBO_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + IF FirstTime THEN + WAIT UNTIL (Rst = '0'); + FirstTime := FALSE; + END IF; + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of write cycle", page 20 + --------------------------------------------------------------------------------------------- + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + CS2 <= '1'; + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D11#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= '1'; + random_vector (D, random); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D21#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D22#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + random_vector (D, random); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D23#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= '1'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D24#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D31#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D32#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D33#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D34#, D_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of read cycle", page 19 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random_vector (D, random); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + ADV <= '1'; + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random := lcg (random); + WE_n <= '1'; + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + ADV <= '1'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(1); + CS2 <= TO_UNSIGNED (random, 32)(2); + CS2_n <= TO_UNSIGNED (random, 32)(3); + ADV <= TO_UNSIGNED (random, 32)(4); + WE_n <= TO_UNSIGNED (random, 32)(5); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 5 DOWNTO 6)); + + --------------------------------------------------------------------------------------------- + -- write values to 0xA40, 0xA50, 0xA60, 0xA70, 0xA80 and 0xA90 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D4#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A70#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A80#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D6#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A90#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D7#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random := lcg (random); + WE_n <= '1'; + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D8#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D9#, D_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of single read/write", page 21 + --------------------------------------------------------------------------------------------- + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D2#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A70#, A_width)); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A80#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A90#, A_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of CKE_n operation", page 22 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D2#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of nCS operation", page 23 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL RISING_EDGE (Clk); + WE_n <= '1' AFTER tWH; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D3#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + END PROCESS pPatternGenerator; +END ARCHITECTURE Deterministic; Index: trunk/bench/vhdl/zbt_ram/patgen_arch_deterministic.vhd =================================================================== --- trunk/bench/vhdl/zbt_ram/patgen_arch_deterministic.vhd (nonexistent) +++ trunk/bench/vhdl/zbt_ram/patgen_arch_deterministic.vhd (revision 3) @@ -0,0 +1,701 @@ +---------------------------------------------------------------------- +---- ---- +---- Test pattern generator for the ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model. ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Description ---- +---- This architecture generates test patterns according to ---- +---- K7N643645M, 72Mb NtRAM Specification, Samsung, Rev. 1.3 ---- +---- September 2008 ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +ARCHITECTURE deterministic OF patgen IS + -- Patterns according to K7N643645M, 72Mb NtRAM Specification, Samsung, Rev. 1.3 September 2008 + + CONSTANT D_width : INTEGER := D'LENGTH; + CONSTANT A_width : INTEGER := A'LENGTH; +BEGIN + pPatternGenerator : PROCESS IS + VARIABLE random : NATURAL; + VARIABLE FirstTime : BOOLEAN := TRUE; + VARIABLE WE_n_v : STD_LOGIC; + BEGIN + -- initialisations + random := 1; + D <= (D_width - 1 DOWNTO 0 => '0'); + A <= (A_width - 1 DOWNTO 0 => '0'); + ADV <= '0'; + WE_n <= '0'; + CKE_n <= '0'; + CS1_n <= '0'; + CS2 <= '0'; + CS2_n <= '0'; + CKE_n <= '0'; + OE_n <= '0'; + ZZ <= '0'; + LBO_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + IF FirstTime THEN + WAIT UNTIL (Rst = '0'); + FirstTime := FALSE; + END IF; + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of write cycle", page 20 + --------------------------------------------------------------------------------------------- + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + CS2 <= '1'; + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D11#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= '1'; + random_vector (D, random); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D21#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D22#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + random_vector (D, random); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D23#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= '1'; + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D24#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D31#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D32#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D33#, D_width)); + + random := lcg (random); + OE_n <= TO_UNSIGNED (random, 32)(0) AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D34#, D_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of read cycle", page 19 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random_vector (D, random); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + ADV <= '1'; + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random := lcg (random); + WE_n <= '1'; + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + ADV <= '1'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + WE_n <= TO_UNSIGNED (random, 32)(3); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(1); + CS2 <= TO_UNSIGNED (random, 32)(2); + CS2_n <= TO_UNSIGNED (random, 32)(3); + ADV <= TO_UNSIGNED (random, 32)(4); + WE_n <= TO_UNSIGNED (random, 32)(5); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 5 DOWNTO 6)); + + --------------------------------------------------------------------------------------------- + -- write values to 0xA40, 0xA50, 0xA60, 0xA70, 0xA80 and 0xA90 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D4#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A70#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A80#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D6#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A90#, A_width)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D7#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random := lcg (random); + WE_n <= '1'; + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D8#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D9#, D_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of single read/write", page 21 + --------------------------------------------------------------------------------------------- + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D2#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A70#, A_width)); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A80#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A90#, A_width)); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of CKE_n operation", page 22 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D2#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '1'; + random_vector (A, random); + random := lcg (random); + CS1_n <= TO_UNSIGNED (random, 32)(0); + CS2 <= TO_UNSIGNED (random, 32)(1); + CS2_n <= TO_UNSIGNED (random, 32)(2); + ADV <= TO_UNSIGNED (random, 32)(3); + WE_n <= TO_UNSIGNED (random, 32)(4); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 4 DOWNTO 5)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + ADV <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + CKE_n <= '0'; + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A60#, A_width)); + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + + --------------------------------------------------------------------------------------------- + -- Pattern according to "Timing waveform of nCS operation", page 23 + --------------------------------------------------------------------------------------------- + OE_n <= '1' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A10#, A_width)); + WE_n <= '1'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A20#, A_width)); + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + + OE_n <= '0' AFTER clk_periode * 1.5 - tOE; + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A30#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL RISING_EDGE (Clk); + WE_n <= '1' AFTER tWH; + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A40#, A_width)); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + random := lcg (random); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 - 1 DOWNTO 0)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D3#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + A <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#A50#, A_width)); + WE_n <= '0'; + BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0'); + CS1_n <= '0'; + CS2 <= '1'; + CS2_n <= '0'; + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + CS1_n <= '1'; + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= STD_LOGIC_VECTOR (TO_UNSIGNED (16#D5#, D_width)); + + WAIT UNTIL FALLING_EDGE (Clk); + random_vector (A, random); + random := lcg (random); + CS2 <= TO_UNSIGNED (random, 32)(0); + CS2_n <= TO_UNSIGNED (random, 32)(1); + WE_n <= TO_UNSIGNED (random, 32)(2); + BW_n <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 2 DOWNTO 3)); + D <= (D_width - 1 DOWNTO 0 => 'Z'); + + WAIT UNTIL FALLING_EDGE (Clk); + END PROCESS pPatternGenerator; +END ARCHITECTURE deterministic; Index: trunk/rtl/vhdl/ZBT_RAM_pkg.vhd =================================================================== --- trunk/rtl/vhdl/ZBT_RAM_pkg.vhd (nonexistent) +++ trunk/rtl/vhdl/ZBT_RAM_pkg.vhd (revision 3) @@ -0,0 +1,135 @@ +---------------------------------------------------------------------- +---- ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model ---- +---- ---- +---- This file is part of the simu_mem project ---- +---- ---- +---- Description ---- +---- State definition and next state calculation function for ---- +---- the ZBT RAM model ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE ZBT_RAM_pkg IS + TYPE state_type IS ( + sleep, + deselect, + deselect_continue, + read, + read_continue, + dummy_read, + dummy_read_continue, + write, + write_continue, + write_abort, + write_abort_continue, + invalid_state); + + FUNCTION calc_state ( + CS1_n : STD_LOGIC; + CS2 : STD_LOGIC; + CS2_n : STD_LOGIC; + WE_n : STD_LOGIC; + BW_n : STD_LOGIC_VECTOR; + OE_n : STD_LOGIC; + ADV : STD_LOGIC; + ZZ : STD_LOGIC; + operation : state_type) RETURN state_type; + + FUNCTION calc_operation ( + state : state_type; + operation : state_type) RETURN state_type; +END PACKAGE ZBT_RAM_pkg; + +PACKAGE BODY ZBT_RAM_pkg IS + FUNCTION calc_state ( + CS1_n : STD_LOGIC; + CS2 : STD_LOGIC; + CS2_n : STD_LOGIC; + WE_n : STD_LOGIC; + BW_n : STD_LOGIC_VECTOR; + OE_n : STD_LOGIC; + ADV : STD_LOGIC; + ZZ : STD_LOGIC; + operation : state_type) RETURN state_type IS + VARIABLE selected : BOOLEAN; + BEGIN + selected := ((CS1_n = '0') AND (CS2 = '1') AND (CS2_n = '0')); + + IF (ZZ = '1') THEN + RETURN sleep; + ELSIF ((ADV = '0') AND (NOT selected)) THEN + RETURN deselect; + ELSIF ((ADV = '1') AND (operation = deselect)) THEN + RETURN deselect_continue; + ELSIF (selected AND (ADV = '0') AND (WE_n = '1') AND (OE_n = '0')) THEN + RETURN read; + ELSIF ((ADV = '1') AND (OE_n = '0') AND (operation = Read)) THEN + RETURN read_continue; + ELSIF (selected AND (ADV = '0') AND (WE_n = '1') AND (OE_n = '1')) THEN + RETURN dummy_read; + ELSIF ((ADV = '1') AND (OE_n = '1') AND (operation = Read)) THEN + RETURN dummy_read_continue; + ELSIF (selected AND (ADV = '0') AND (WE_n = '0') AND (BW_n /= (BW_n'range => '1'))) THEN + RETURN write; + ELSIF ((ADV = '1') AND (BW_n /= (BW_n'range => '1')) AND (operation = write)) THEN + RETURN write_continue; + ELSIF (selected AND (ADV = '0') AND (WE_n = '0') AND (BW_n = (BW_n'range => '1')) AND + (operation = Write)) THEN + RETURN write_abort; + ELSIF ((ADV = '1') AND (BW_n = (BW_n'range => '1')) AND (operation = write_abort)) THEN + RETURN write_abort_continue; + ELSE + RETURN invalid_state; + END IF; + END FUNCTION calc_state; + + FUNCTION calc_operation ( + state : state_type; + operation : state_type) RETURN state_type IS + BEGIN + CASE state IS + WHEN deselect | write | write_abort | read => + RETURN state; + WHEN dummy_read => + RETURN read; + WHEN OTHERS => + RETURN operation; + END CASE; + END FUNCTION calc_operation; +END PACKAGE BODY ZBT_RAM_pkg;
trunk/rtl/vhdl/ZBT_RAM_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/vhdl/linked_list_mem_pkg.vhd =================================================================== --- trunk/rtl/vhdl/linked_list_mem_pkg.vhd (nonexistent) +++ trunk/rtl/vhdl/linked_list_mem_pkg.vhd (revision 3) @@ -0,0 +1,166 @@ +---------------------------------------------------------------------- +---- ---- +---- Linked list based RAM simulation model ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Description ---- +---- This package implements functions to allocate, write, read ---- +---- and deallocate a linked list based memory. ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE linked_list_mem_pkg IS + -- pointer to one data word in the memory + -- The reason for using a pointer here is that it seems to be the only way to keep the model + -- independent of the data width + CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth + + TYPE operation_type is (read, write); + + -- data memory array type definition + TYPE data_ptr IS ACCESS BIT_VECTOR; + + -- Define memory page linked list cell. This cell contains + -- the mem_array, starting page address, valid data array and + -- the pointer to the next element in the linked list. + TYPE mem_array_type IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr; + + -- pointer to next item in the linked list. + TYPE mem_page_type; + + TYPE mem_page_ptr IS ACCESS mem_page_type; + + TYPE mem_page_type IS RECORD + mem_array : mem_array_type; -- data memory + page_address : NATURAL; + next_cell : mem_page_ptr; + END RECORD mem_page_type; + + PROCEDURE rw_mem ( + data : INOUT STD_LOGIC_VECTOR; + addr : IN NATURAL; + next_cell : INOUT mem_page_ptr; + CONSTANT operation : IN operation_type); + + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr); +END PACKAGE linked_list_mem_pkg; + +PACKAGE BODY linked_list_mem_pkg IS + -- -------------------------------------------------- + -- The purpose of this procedure is to read or write a memory location from + -- the linked list, if the particular page does not exist, create it. + -- -------------------------------------------------- + PROCEDURE rw_mem ( + data : INOUT STD_LOGIC_VECTOR; + addr : IN NATURAL; + next_cell : INOUT mem_page_ptr; + CONSTANT operation : IN operation_type) IS + VARIABLE current_cell_v : mem_page_ptr; -- current page pointer + VARIABLE page_address_v : NATURAL; -- calculated page address + VARIABLE index_v : INTEGER; -- address within the memory page + VARIABLE mem_array_v : mem_array_type; + BEGIN + -- Copy the top of the linked list pointer to a working pointer + current_cell_v := next_cell; + + -- Calculate the index within the page from the given address + index_v := addr MOD PAGEDEPTH; + + -- Calculate the page address from the given address + page_address_v := addr - index_v; + + -- Search through the memory to determine if the calculated + -- memory page exists. Stop searching when reach the end of + -- the linked list. + WHILE (current_cell_v /= NULL AND + current_cell_v.page_address /= page_address_v) LOOP + current_cell_v := current_cell_v.next_cell; + END LOOP; + + IF (operation = write) THEN + IF (current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v) THEN + -- Found the memory page the particular address belongs to + IF (current_cell_v.mem_array (index_v) /= NULL) THEN + current_cell_v.mem_array (index_v).ALL := TO_BITVECTOR(data); + ELSE + current_cell_v.mem_array (index_v) := NEW BIT_VECTOR'(TO_BITVECTOR (data)); + END IF; + ELSE + -- The memory page the address belongs to was not allocated in memory. + -- Allocate page here and assign data. + mem_array_v (index_v) := NEW BIT_VECTOR'(TO_BITVECTOR (data)); + next_cell := NEW mem_page_type'(mem_array => mem_array_v, + page_address => page_address_v, + next_cell => next_cell); + END IF; + ELSE -- Read memory + IF (current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v AND + current_cell_v.mem_array (index_v) /= NULL) THEN + -- Found the memory page the particular address belongs to, + -- and the memory location has valid data. + data := TO_STDLOGICVECTOR (current_cell_v.mem_array (index_v).ALL); + ELSE + -- Trying to read from unwritten or unallocated + -- memory location, return 'U'; + data := (data'RANGE => 'U'); + END IF; + END IF; + END PROCEDURE rw_mem; + + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr) IS + VARIABLE delete_cell_v : mem_page_ptr; + BEGIN + -- Deallocate the linked link memory from work station memory. + WHILE next_cell /= NULL LOOP -- while not reached the end of the LL + delete_cell_v := next_cell; -- Copy pointer to record for deleting + FOR i IN 0 TO PAGEDEPTH-1 LOOP + IF delete_cell_v.mem_array (i) /= NULL THEN + deallocate (delete_cell_v.mem_array (i)); + END IF; + END LOOP; + next_cell := next_cell.next_cell; -- set pointer to next cell in linked list + deallocate (delete_cell_v); -- Deallocate current cell from memory. + END LOOP; + END PROCEDURE deallocate_mem; +END PACKAGE BODY linked_list_mem_pkg;
trunk/rtl/vhdl/linked_list_mem_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/vhdl/ZBT_RAM.vhd =================================================================== --- trunk/rtl/vhdl/ZBT_RAM.vhd (nonexistent) +++ trunk/rtl/vhdl/ZBT_RAM.vhd (revision 3) @@ -0,0 +1,224 @@ +---------------------------------------------------------------------- +---- ---- +---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ---- +---- simulation model ---- +---- ---- +---- This file is part of the simu_mem project. ---- +---- ---- +---- Description ---- +---- This is a functional simulation model for single port ---- +---- synchronous static RAMs. Examples for applicable devices: ---- +---- ---- +---- Manufacturer Device ---- +---- Samsung K7N643645M ---- +---- ISSI IS61NLP51236 ---- +---- ---- +---- Advantages of this model: ---- +---- 1. Consumes few simulator memory if only few memory ---- +---- locations are accessed because it internally uses a ---- +---- linked list. ---- +---- 2. Simulates quickly because it does not contain timing ---- +---- information. Fast simulator startup time because of the ---- +---- linked list. ---- +---- 3. Usable for any data and address bus width. ---- +---- 4. Works at any clock frequency. ---- +---- 5. Programmed in VHDL. ---- +---- ---- +---- When this model will not be useful: ---- +---- 1. When it has to be synthesized. ---- +---- 2. When a timing model is required. Ask your RAM vendor for ---- +---- a timing model. ---- +---- 3. When all memory locations have to be accessed in one ---- +---- single simulation run. The linked list model will not ---- +---- be well suited then. ---- +---- 4. When your design is in Verilog. ---- +---- ---- +---- For above reasons a typical application is a functional ---- +---- simulation of a design which uses external synchronous ---- +---- static RAMs. ---- +---- ---- +---- Authors: ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2008 Authors ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.NUMERIC_STD.ALL; + + USE work.ZBT_RAM_pkg.ALL; + USE work.linked_list_mem_pkg.ALL; + +ENTITY ZBT_RAM IS + GENERIC ( + debug : INTEGER := 0); -- >= 1: print write operations + -- >= 2: print also read operations + PORT ( + Clk : IN STD_LOGIC; + D : IN STD_LOGIC_VECTOR; + Q : OUT STD_LOGIC_VECTOR; + A : IN STD_LOGIC_VECTOR; + CKE_n : IN STD_LOGIC; + CS1_n : IN STD_LOGIC; + CS2 : IN STD_LOGIC; + CS2_n : IN STD_LOGIC; + WE_n : IN STD_LOGIC; + BW_n : IN STD_LOGIC_VECTOR; + OE_n : IN STD_LOGIC; + ADV : IN STD_LOGIC; + ZZ : IN STD_LOGIC; + LBO_n : IN STD_LOGIC; + dealloc_mem : IN BOOLEAN := FALSE); -- control SIGNAL for deallocating memory +END ENTITY ZBT_RAM; + +ARCHITECTURE LinkedList OF ZBT_RAM IS + CONSTANT D_width : INTEGER := D'LENGTH; + CONSTANT A_width : INTEGER := A'LENGTH; + + TYPE mem_page_ptr_array IS ARRAY (0 TO D_width / 9 - 1) of mem_page_ptr; + + SIGNAL state, last_state : state_type := Deselect; + SIGNAL operation : state_type := Deselect; + SIGNAL DOut : STD_LOGIC_VECTOR (D_width - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL A_delayed_1 : NATURAL; + SIGNAL A_delayed_2 : NATURAL; + SIGNAL BW_n_delayed_1 : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0); + SIGNAL BW_n_delayed_2 : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0); + SIGNAL ADV_delayed : STD_LOGIC; + SIGNAL sleep_count : INTEGER RANGE 4 DOWNTO 0 := 0; +BEGIN + ASSERT BW_n'LENGTH = D'LENGTH / 9 + REPORT "Error: BW_n'length must be equal to D'length / 9" + SEVERITY FAILURE; + + mem_proc : PROCESS (Clk, dealloc_mem) IS + VARIABLE state_v : state_type; + VARIABLE mem_page_v : mem_page_ptr_array; + VARIABLE D_v : STD_LOGIC_VECTOR (8 DOWNTO 0); + BEGIN + IF dealloc_mem THEN + FOR i IN 0 TO D_width / 9 - 1 LOOP + deallocate_mem (mem_page_v (i)); + END LOOP; + ELSIF rising_edge (Clk) THEN + IF (CKE_n = '0') THEN + state_v := calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation); + operation <= calc_operation (state_v, operation); + + IF ((state_v = read) OR (state_v = dummy_read) OR (state_v = write)) THEN + A_delayed_1 <= to_INTEGER (UNSIGNED (A)); + END IF; + + IF ((state_v = write) OR (state_v = write_continue)) THEN + BW_n_delayed_1 <= BW_n; + END IF; + + IF (state_v = invalid_state) THEN + REPORT "Invalid state" SEVERITY ERROR; + END IF; + + state <= state_v; + last_state <= state; + ADV_delayed <= ADV; + BW_n_delayed_2 <= BW_n_delayed_1; + END IF; + + IF (ZZ = '1') THEN + sleep_count <= 4; + ELSIF (sleep_count > 0) THEN + sleep_count <= sleep_count - 1; + END IF; + + IF (sleep_count = 0) THEN + IF (((state = write) OR + (state = read) OR + (state = dummy_read) OR + (state = write_abort)) AND (CKE_n = '0')) THEN + A_delayed_2 <= A_delayed_1; + ELSIF (ADV_delayed = '1') AND (CKE_n = '0') THEN + IF (A_delayed_2 MOD (D_width / 9) < D_width / 9 - 1) THEN + A_delayed_2 <= A_delayed_2 + 1; + ELSE + A_delayed_2 <= A_delayed_1; + END IF; + END IF; + + IF ((CKE_n = '0') AND (BW_n_delayed_2 /= (D_width / 9 - 1 DOWNTO 0 => '1')) AND + ((last_state = write) OR (last_state = write_continue))) THEN + FOR i IN 0 TO D_width / 9 - 1 LOOP + IF (BW_n_delayed_2 (i) = '0') THEN + D_v := D (9 * (i + 1) - 1 DOWNTO 9 * i); + rw_mem (data => D_v, + addr => A_delayed_2, + next_cell => mem_page_v (i), + operation => write); + IF (Debug >= 1) THEN + REPORT ("DBG, " & TIME'IMAGE (now) & ": Write " & + INTEGER'IMAGE (to_INTEGER (UNSIGNED (D_v))) & " to address=" & + INTEGER'IMAGE (A_delayed_2) & ", bank=" & INTEGER'IMAGE (i)); + END IF; + END IF; + END LOOP; + END IF; + ELSIF (sleep_count = 3) THEN + A_delayed_2 <= 0; + END IF; + END IF; + + IF falling_edge (Clk) THEN + IF (sleep_count = 0) THEN + IF (CKE_n = '0') THEN + IF ((last_state = read) OR (last_state = read_continue) OR + (last_state = dummy_read) OR (last_state = dummy_read_continue)) THEN + FOR i IN 0 TO D_width / 9 - 1 LOOP + rw_mem (data => D_v, + addr => A_delayed_2, + next_cell => mem_page_v (i), + operation => read); + DOut (9 * (i + 1) - 1 DOWNTO 9 * i) <= D_v; + IF (Debug >= 2) THEN + REPORT ("DBG, " & TIME'IMAGE (now) & ": Read " & + INTEGER'IMAGE (to_INTEGER (UNSIGNED (D_v))) & " from address=" & + INTEGER'IMAGE (A_delayed_2) & ", bank=" & INTEGER'IMAGE (i)); + END IF; + END LOOP; + ELSE + DOut <= (OTHERS => 'Z'); + END IF; + END IF; + ELSE + DOut <= (OTHERS => 'Z'); + END IF; + END IF; + END PROCESS mem_proc; + + Q <= (Q'RANGE => 'Z') WHEN (OE_n = '1') ELSE DOut; +END LinkedList;
trunk/rtl/vhdl/ZBT_RAM.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/bin/modelsim.inc =================================================================== --- trunk/sim/rtl_sim/bin/modelsim.inc (nonexistent) +++ trunk/sim/rtl_sim/bin/modelsim.inc (revision 3) @@ -0,0 +1,13 @@ +function check_executable { + if [ ! -x $1 ]; then + echo "$1 does not exist or is not executable." + exit 0 + fi +} + +function map { + if [ ! -d ../out/$1 ] ; then + vlib ../out/$1 + vmap $1 $2 + fi; +}
trunk/sim/rtl_sim/bin/modelsim.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/bin/sim.sh =================================================================== --- trunk/sim/rtl_sim/bin/sim.sh (nonexistent) +++ trunk/sim/rtl_sim/bin/sim.sh (revision 3) @@ -0,0 +1,73 @@ +#!/bin/bash +# +# This script runs RTL simulation. +# Right now only Modelsim is supported. +# +# Author: Michael Geng +# + +# Number of clock cycles you want to run the simulations +N_simulation_cycles=100 + +# data bus width +D_width=36 + +# address bus width +A_width=21 + +. modelsim.inc + +if [ -z $MODEL_SIM ]; then + echo "The environment variable MODEL_SIM must point to your Modelsim installation." + exit 0 +fi + +vlib=$MODEL_SIM/win32pe/vlib +vcom=$MODEL_SIM/win32pe/vcom +vsim=$MODEL_SIM/win32pe/vsim + +for tool in $vlib $vcom $vsim +do + check_executable $tool +done + +touch modelsim.ini + +mkdir -p ../out + +# map libraries +map std "$MODEL_SIM/std" +map ieee "$MODEL_SIM/ieee" +map verilog "$MODEL_SIM/verilog" +map RAM ../out/RAM +map misc ../out/misc +map samsung ../out/samsung +map test_zbt ../out/test_zbt + +# compile +vcom -work ../out/misc ../../../bench/vhdl/misc/math_pkg.vhd + +vlog +define+hc25 -work ../out/samsung ../../../bench/verilog/samsung/k7n643645m_R03.v + +vcom -work ../out/RAM ../../../rtl/vhdl/linked_list_mem_pkg.vhd +vcom -work ../out/RAM ../../../rtl/vhdl/ZBT_RAM_pkg.vhd +vcom -work ../out/RAM ../../../rtl/vhdl/ZBT_RAM.vhd + +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_pkg.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_entity.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_arch_random.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_arch_deterministic.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench_random_conf.vhd +vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench_deterministic_conf.vhd + +mkdir -p ../log + +# simulate +echo "Simulate with deterministic pattern" +vsim -l ../log/zbt_deterministic.out -c -t 100ps -GD_width=$D_width -GA_width=$A_width \ + -GN_simulation_cycles=$N_simulation_cycles -do "run -all ; quit ;" test_zbt.deterministic_conf + +echo "Simulate with random pattern" +vsim -l ../log/zbt_random.out -c -t 100ps -GD_width=$D_width -GA_width=$A_width \ + -GN_simulation_cycles=$N_simulation_cycles -do "run -all ; quit ;" test_zbt.random_conf
trunk/sim/rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/bin/clean.sh =================================================================== --- trunk/sim/rtl_sim/bin/clean.sh (nonexistent) +++ trunk/sim/rtl_sim/bin/clean.sh (revision 3) @@ -0,0 +1,4 @@ +#!/bin/bash +rm -r ../out +rm -r ../log +rm modelsim.ini
trunk/sim/rtl_sim/bin/clean.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/README.txt =================================================================== --- trunk/README.txt (nonexistent) +++ trunk/README.txt (revision 3) @@ -0,0 +1,78 @@ +////////////////////////////////////////////////////////////////// +// // +// The simu_mem project provides functional simulation models // +// of commercially available RAMs. The following types are // +// presently supported: // +// // +// - asynchronous static SRAMs // +// - synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT // +// RAM) // +// // +// Author(s): // +// - Michael Geng (vhdl@MichaelGeng.de) // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2008 Authors // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +Advantages of the simu_mem models +================================= + +1. Consumes few simulator memory if only few memory + locations are accessed because it internally uses a + linked list. +2. Simulates quickly because it does not contain timing + information. Fast simulator startup time because of the + linked list. +3. Usable for any data and address bus width. +4. Works at any clock frequency. +5. Programmed in VHDL. + +When the simu_mem models will not be useful +=========================================== +1. When it has to be synthesized. +2. When a timing model is required. Ask your RAM vendor for + a timing model. +3. When your design is in Verilog. + +Where are the simulation models? +================================ + +The RAM simulation models are located in rtl/vhdl/. They were +tested only with the Modelsim simulator. + +How were the models tested? +=========================== + +A testbench exists for ZBT RAMs. sim/rtl_sim/bin/sim.sh will execute +the simulation. In order to run this test you must replace +bench/verilog/samsung/k7n643645m_R03.v with the original simulation +file from Samsung. You can find it on the Samsung semiconductor home +page under High Speed SRAM / NtRAM / K7N643645M.

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