OpenCores
URL https://opencores.org/ocsvn/tlc2/tlc2/trunk

Subversion Repositories tlc2

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Rev 2 → Rev 3

/tags/vers/wave.do
0,0 → 1,42
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tlc_tb/uut/clk
add wave -noupdate -format Logic /tlc_tb/uut/rst
add wave -noupdate -format Logic /tlc_tb/uut/j_left
add wave -noupdate -format Logic /tlc_tb/uut/j_right
add wave -noupdate -format Literal /tlc_tb/uut/led
add wave -noupdate -format Literal /tlc_tb/uut/pr_state
add wave -noupdate -format Literal /tlc_tb/uut/nxt_state
add wave -noupdate -format Logic /tlc_tb/uut/pr_state_mode
add wave -noupdate -format Logic /tlc_tb/uut/nxt_state_mode
add wave -noupdate -format Literal /tlc_tb/uut/led_int
add wave -noupdate -format Logic /tlc_tb/uut/one_sec
add wave -noupdate -format Logic /tlc_tb/uut/go
add wave -noupdate -format Logic /tlc_tb/uut/mode
add wave -noupdate -format Logic /tlc_tb/uut/green_period
add wave -noupdate -format Logic /tlc_tb/uut/orange_period
add wave -noupdate -format Logic /tlc_tb/uut/red_period
add wave -noupdate -format Logic /tlc_tb/uut/red_orange_period
add wave -noupdate -format Logic /tlc_tb/uut/stb_period
add wave -noupdate -format Logic /tlc_tb/uut/rst_int
add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp0
add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp1
add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp2
add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp3
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2053550 ns} 1}
configure wave -namecolwidth 208
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {2202166 ns} {2234934 ns}
/tags/vers/modelsim.ini
0,0 → 1,1058
; Copyright 1991-2007 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
work = modelsim/work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile=1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VcomZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VcomZeroInOptions = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageNoSub = 0
 
; Automatically exclude VHDL case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Turn on code coverage in VHDL generate blocks. Default is on.
CoverGenerate = 1
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
vlog95compat = 0
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal to or more than 1M are
; marked as sparse)
SparseMemThreshold = 1048576
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VlogZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VlogZeroInOptions = ""
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VoptZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VoptZeroInOptions = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Turn on code coverage in VLOG generate blocks. Default is on.
CoverGenerate = 1
 
; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is on.
CoverCells = 0
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
; 1 -- Turn off all optimizations that affect coverage reports.
; 2 -- Allow optimizations that allow large performance improvements
; by invoking sequential processes only when the data changes.
; Allow VHDL FF recognition. This may make major reductions in
; coverage counts.
; 3 -- In addition, allow optimizations that may change expressions or
; remove some statements. Allow constant propagation.
; 4 -- In addition, allow optimizations that may remove major regions of
; code by changing assignments to built-ins or removing unused
; signals. Allow VHDL subprogram inlining. Change Verilog gates to
; continuous assignments.
CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobeDefault".
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupPerInstanceDefault".
; SVCovergroupPerInstanceDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
[vsim]
 
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ns
 
; Enables certain code coverage exclusions automatically. Set AutoExclusions = none to disable.
AutoExclusions = fsm
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
; level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
 
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name: # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1
 
 
; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable System Verilog assertion messages
; Info and Warning are disabled by default
; IgnoreSVAInfo = 0
; IgnoreSVAWarning = 0
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify whether to enable SystemVerilog DPI out-of-the-blue call.
; Out-of-the-blue call refers to a SystemVerilog export function call
; directly from a C function that don't have the proper context setup
; as done in DPI-C import C functions. When this is enabled, one can
; call a DPI export function (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
 
; Should the tool conform to the 2001 or 2005 VPI object model
; Note that System Verilog objects are only available in the 2005 object model
; The tool default is the latest available LRM behavior
; Options here are: 2001 2005 latest
; PliCompatDefault = 2005
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
; This is necessary when C++ files have been compiled with aCC's -AA option.
; The default behavior is to use /usr/lib/libCsup.sl.
; UseCsupV2 = 1
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; Note: these ini variables can be overriden by the vsim command
; line switch "-onfinish <ask|stop|exit>".
OnFinish = ask
 
; Print "simstats" result at the end of simulation before shutdown.
; If this is enabled, the simstats result will be printed out before shutdown.
; The default is off.
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA concurrent assertion pass enable.
; For SVA, Default is on when the assertion has a pass action block or vsim switch -assertdebug is used and the visibility flag "+acc=a" is turned on in vopt.
; For PSL, Default is on only when vsim switch "-assertdebug" is used and the visibility flag "+acc=a" is turned on in vopt.
; AssertionPassEnable = 0
 
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0
 
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1
 
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1
 
; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to not include them.
; ToggleVlogIntegers = 1
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off.
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enable or disable generation of more detailed information about the sampling of covergroup,
; cross, and coverpoints. It provides the details of the number of times the covergroup
; instance and type were sampled, as well as details about why covergroup, cross and
; coverpoint were not covered. A non-zero value is to enable this feature. 0 is to
; disable this feature. Default is 0;
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Run the 0in tools from within the simulator.
; Default value set to 0. Please set it to 1 to invoke 0in.
; VsimZeroIn = 1
 
; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VsimZeroInOptions = ""
 
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0
 
; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000
 
; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; SolveFailSeverity = 0
 
; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
 
; When SolveFailDebug is enabled, this value specifies the algorithm used to
; discover conflicts between constraints for randomize() failures.
; The default is "many".
;
; Valid schemes are:
; "many" = best for determining conflicts due to many related constraints
; "few" = best for determining conflicts due to few related constraints
;
; SolveFailDebugScheme = many
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum number of constraint subsets that will be tested for
; conflicts.
; The default is 0 (no limit).
; SolveFailDebugLimit = 0
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum size of constraint subsets that will be tested for
; conflicts.
; The default value is 0 (no limit).
; SolveFailDebugMaxSet = 0
 
; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the complexity of
; the constraint scenario (both in memory and time spent during evaluation)
; exceeds the specified limit. This value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of
; the constraint solver for others.
; The default value is "" (no options).
;
; Valid flags are:
; i = disable bit interleaving for >, >=, <, <= constraints
; n = disable bit interleaving for all constraints
; r = reverse bit interleaving
;
; SolveFlags =
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; Note: To achieve the same random sequences, solver optimizations and/or
; bug fixes introduced since the specified release may be disabled -
; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
 
; Control transcripting of Verilog display system task messages.
; These system tasks include $display[bho], $strobe[bho],
; Smonitor{bho], and $write[bho]. They also include the analogous
; file I/O tasks that write to STDOUT (i.e. $fwrite or $fdisplay).
; The default is to have messages appear only in the transcript.
; The other settings are to send messages to the wlf file only
; (messages that are recorded in the wlf file can be viewed in the
; MsgViewer) or to both the transcript and the wlf file. The valid
; values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
/tags/vers/src/tlc2.ucf
0,0 → 1,34
#NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0)
#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1)
#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2)
#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3)
#NET "j_up" LOC = "AD4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick up low active
#NET "j_down" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low active
NET "j_left" LOC = "AE4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick left low active
NET "j_right" LOC = "AC6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick right low active
NET "rst" LOC = "AA7" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick push low active
 
#NET "turn_on" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) #dip switch low active
#NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk
 
#NET "out_vector(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0)
NET "led(0)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1)
NET "led(1)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2)
NET "led(2)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3)
#NET "out_vector(4)" LOC = "G21" | IOSTANDARD = LVCMOS33; #led(4)
#NET "out_vector(5)" LOC = "G23" | IOSTANDARD = LVCMOS33; #led(5)
#NET "out_vector(6)" LOC = "H23" | IOSTANDARD = LVCMOS33; #led(6)
#NET "out_vector(7)" LOC = "J21" | IOSTANDARD = LVCMOS33; #led(7)
 
#NET "in_vector(0)" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) dip switches are low-active
#NET "in_vector(1)" LOC = "AD15" | IOSTANDARD = LVCMOS25; #dip_sw(1)
#NET "in_vector(2)" LOC = "AD19" | IOSTANDARD = LVCMOS25; #dip_sw(2)
#NET "in_vector(3)" LOC = "AD23" | IOSTANDARD = LVCMOS25; #dip_sw(3)
#NET "in_vector(4)" LOC = "AF21" | IOSTANDARD = LVCMOS25; #dip_sw(4)
#NET "in_vector(5)" LOC = "AF22" | IOSTANDARD = LVCMOS25; #dip_sw(5)
#NET "in_vector(6)" LOC = "W15" | IOSTANDARD = LVCMOS25; #dip_sw(6)
#NET "in_vector(7)" LOC = "W16" | IOSTANDARD = LVCMOS25; #dip_sw(7)
 
#NET "enable" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low-active
NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk
 
/tags/vers/src/tlc2.vhd
0,0 → 1,219
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tlc2 is
generic( freq : integer := 1e8; -- 100 MHz, use 100 Hz (1e2) for simulation and run 5 ms
max_period_factor : INTEGER := 45; --the period of the longest signal (green)
idle_period_factor : integer := 1; -- 1 sec blinking interval
green_period_factor : integer := 45; -- 45 sec green interval
orange_period_factor : integer := 5; -- 5 sec orange interval
red_period_factor : integer := 30; -- 30 sec red interval
red_orange_period_factor : integer := 5); -- 5 sec red_orange interval
port( clk, rst : in std_logic; -- low - active reset
j_left, j_right : IN std_logic; -- j_right turns normal mode, j_left turns test mode, both signals are low active
led : out std_logic_vector (2 downto 0) ); -- {RED|ORANGE|GREEN}, RED is MSB
end tlc2;
 
architecture behavioral of tlc2 is
type state is (idle0, idle1, green, orange, red, red_orange, rst_before_idle1, rst_before_idle0, rst_before_green, rst_before_orange, rst_before_red, rst_before_red_orange);
signal pr_state, nxt_state : state;
signal pr_state_mode, nxt_state_mode : std_logic :='0'; -- state signals for the joystick encoder
signal led_int : std_logic_vector (2 downto 0); -- internal led signal used to invert the output if neccessary
SIGNAL one_sec : std_logic := '0'; -- signal with 1s period used as time basis
SIGNAL mode : std_logic := '0'; -- changes between test end normal mode, triggered by the joystick decoder
SIGNAL rst_int : STD_LOGIC := '1'; --used to reset the period-signals after state transition
SIGNAL counter : INTEGER RANGE 0 TO max_period_factor := 0;
constant one_sec_factor : integer := freq-1;
begin
 
-------------------------------------------------------------------------------
-- Simple FSM for the joystick encoder. Generats the mode - signal.
-------------------------------------------------------------------------------
mode_s_p: process(clk)
begin
if clk'event and clk='1' then
IF rst='0' THEN
pr_state_mode <= '0';
else
pr_state_mode <= nxt_state_mode;
END if;
end if;
end process;
 
mode_c_p: process(pr_state_mode,j_right,j_left)
begin
CASE pr_state_mode IS
WHEN '0' => IF j_right='0' and j_left='1' THEN
nxt_state_mode <= '1';
ELSE
nxt_state_mode <= '0';
END if;
mode <= '0';
WHEN OTHERS => IF j_left='0' THEN
nxt_state_mode <= '0';
ELSE
nxt_state_mode <= '1';
END if;
mode <= '1';
END CASE;
END process;
 
-------------------------------------------------------------------------------
-- period-signal generator
-------------------------------------------------------------------------------
time_p: process(clk)
variable temp0 : integer RANGE 0 TO max_period_factor;
VARIABLE flag : STD_LOGIC := '0';
BEGIN
IF clk'EVENT AND clk='1' THEN
IF rst_int='0' THEN -- a 0 level signal is needed by the current state of the main fsm
temp0 := 0;
else
IF one_sec='0' THEN
flag := '0';
END IF;
IF one_sec='1' AND flag='0' THEN --this part is executed only on a
--positive transition of the one_sec signal. The counter factors multiply the
--period of the one_sec signal. If you need to speed up the execution change
--the on_sec_factor to a lower value. This us usefull for simulation purposes
flag := '1';
IF
temp0=max_period_factor THEN
temp0 := 0;
ELSE
temp0 := temp0 + 1;
end if;
END if;
END if;
END if;
counter <= temp0;
END process;
 
-------------------------------------------------------------------------------
-- 1 sec time basis signal generator. Generate a signal with 2 sec period.
-------------------------------------------------------------------------------
one_sec_p: process(clk)
VARIABLE temp : integer RANGE 0 TO one_sec_factor;
begin
IF clk'event AND clk='1' THEN
IF rst_int='0' THEN
temp := 0;
one_sec <= '0';
else
iF temp>=one_sec_factor THEN
temp := 0;
one_sec <= '1';
else
temp := temp + 1;
one_sec <= '0';
END if;
END if;
END IF;
END process;
 
-------------------------------------------------------------------------------
-- main FSM
-------------------------------------------------------------------------------
main_s_p: process(clk)
begin
if clk'event and clk='1' then
IF rst='0' THEN
pr_state <= idle0;
else
pr_state <= nxt_state;
end if;
END if;
end process;
 
main_c_p: process(pr_state,mode,counter)
begin
case pr_state is
WHEN idle0 => IF mode='0' then
IF counter>=idle_period_factor THEN
nxt_state <= rst_before_idle1;
ELSE
nxt_state <= idle0;
END IF;
ELSE
nxt_state <= rst_before_green;
END if;
led_int <= "010";
rst_int <= '1';
when idle1 => if mode='0' then
IF counter>=idle_period_factor THEN
nxt_state <= rst_before_idle0;
ELSE
nxt_state <= idle1;
END IF;
ELSE
nxt_state <= rst_before_green;
END if;
led_int <= "000";
rst_int <= '1';
when green => if mode='1' then
if counter>=green_period_factor THEN
nxt_state <= rst_before_orange;
ELSE
nxt_state <= green;
END if;
ELSE
nxt_state <= rst_before_idle0;
end if;
led_int <= "001";
rst_int <= '1';
WHEN orange => if mode='1'then
if counter>=orange_period_factor THEN
nxt_state <= rst_before_red;
ELSE
nxt_state <= orange;
END if;
ELSE
nxt_state <= rst_before_idle0;
END if;
led_int <= "010";
rst_int <= '1';
WHEN red => if mode='1' THEN
if counter>=red_period_factor THEN
nxt_state <= rst_before_red_orange;
ELSE
nxt_state <= red;
END if;
ELSE
nxt_state <= rst_before_idle0;
END if;
led_int <= "100";
rst_int <= '1';
WHEN red_orange => if mode='1' THEN
if counter>=red_orange_period_factor THEN
nxt_state <= rst_before_green;
ELSE
nxt_state <= red_orange;
END if;
ELSE
nxt_state <= rst_before_idle0;
END if;
led_int <= "110";
rst_int <= '1';
WHEN rst_before_idle1 => nxt_state <= idle1;
led_int <= "000";
rst_int <= '0';
WHEN rst_before_green => nxt_state <= green;
led_int <= "001";
rst_int <= '0';
WHEN rst_before_orange => nxt_state <= orange;
led_int <= "010";
rst_int <= '0';
WHEN rst_before_red => nxt_state <= red;
led_int <= "100";
rst_int <= '0';
WHEN rst_before_red_orange => nxt_state <= red_orange;
led_int <= "110";
rst_int <= '0';
WHEN OTHERS => nxt_state <= idle0;
led_int <= "010";
rst_int <= '0';
END case;
END process;
led <= led_int;
END behavioral;
/tags/vers/src/tlc2.do
0,0 → 1,3
add wave *
run 1000 ns
restart -nowave
/tags/vers/src/tlc2_tb.vhd
0,0 → 1,100
 
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:44:54 03/26/2008
-- Design Name: counter
-- Module Name: counter_tb.vhd
-- Project Name: clk_tb
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: counter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY tlc2_tb IS
END tlc2_tb;
 
ARCHITECTURE behavior OF tlc2_tb IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT tlc2
PORT(
clk : IN std_logic;
rst, j_left, j_right : IN std_logic;
led : OUT std_logic_vector(2 downto 0) );
END COMPONENT;
 
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL j_right : std_logic := '1';
SIGNAL j_left : std_logic := '1';
--Outputs
SIGNAL led : std_logic_vector(2 downto 0);
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: tlc2 PORT MAP(
clk => clk,
rst => rst, j_left => j_left, j_right => j_right,
led => led
);
 
tb_clk : PROCESS
BEGIN
 
-- Wait 100 ns for global reset to finish
--wait for 100 ns;
 
clk <= not clk;
wait for 5 ns;
-- Place stimulus here
END PROCESS;
 
tb_s: PROCESS
BEGIN
wait for 15 ns;
rst <= '0';
wait for 25 ns;
rst <= '1';
wait for 15 ns;
j_left <= '0';
wait for 30 ns;
j_left <= '1';
wait for 13000 ns;
j_right <= '0';
wait for 100 ns;
j_right <= '1';
-- wait for 1000 ns;
-- j_left <= '0';
-- wait for 100 ns ;
-- j_left <= '1';
-- wait for 1500 ns;
-- j_right <= '0';
-- wait for 50 ns;
--- j_right <= '1';
wait;
 
END PROCESS;
END;
/tags/vers/src/tlc2.ut
0,0 → 1,30
-g DebugBitstream:No
-g Binary:no
-b
-g CRC:Enable
-g ConfigRate:6
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFF0001
-g DCMShutDown:Disable
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:NoWait
-g Security:None
-g Persist:No
-g ReadBack
-g DonePipe:No
-g DriveDone:No
/tags/vers/bin/route_ngc
0,0 → 1,15
#!/bin/sh
# route entity ucf-file device effort bitgen
#ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6
rm -f $1.ngd
echo ngdbuild $1.ngc -aul -uc $2 -p $3# -sd $6/xst -sd $6
ngdbuild $1.ngc -aul -uc $2 -p $3 #-sd $6/xst -sd $6
#ngdbuild $1.ngc -aul -uc $2 -p $3
echo map -pr b -p $3 $1
map -pr b -p $3 $1
echo par -ol $4 -w $1 $1.ncd
par -ol $4 -w $1 $1.ncd
echo trce -v 25 $1.ncd $1.pcf
trce -v 25 $1.ncd $1.pcf
echo bitgen $1 -l -m -w -d -f $5
bitgen $1 -l -m -w -d -f $5
tags/vers/bin/route_ngc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/vers/bin/load_modules =================================================================== --- tags/vers/bin/load_modules (nonexistent) +++ tags/vers/bin/load_modules (revision 3) @@ -0,0 +1,4 @@ +module load mentor/modelsim/6.3d-64 +module load xilinx/ise-9.2i-64 + + Index: tags/vers/bin/vscript =================================================================== --- tags/vers/bin/vscript (nonexistent) +++ tags/vers/bin/vscript (revision 3) @@ -0,0 +1 @@ +echo vcom $1
tags/vers/bin/vscript Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/vers/bin/xstvhdl =================================================================== --- tags/vers/bin/xstvhdl (nonexistent) +++ tags/vers/bin/xstvhdl (revision 3) @@ -0,0 +1 @@ +echo vhdl work $1 \ No newline at end of file
tags/vers/bin/xstvhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/vers/modelsim/work/_opt/voptdzqxgz =================================================================== --- tags/vers/modelsim/work/_opt/voptdzqxgz (nonexistent) +++ tags/vers/modelsim/work/_opt/voptdzqxgz (revision 3) @@ -0,0 +1,73 @@ +m255 +K3 +Z0 cModel Technology Builtin Library +13 +Z1 dD:\qa\buildsites\6.3d\builds\win32\modeltech +Penv +Z2 OL;C;6.3d;37 +32 +b1 +Z3 OP;C;6.3d;37 +Z4 w1196138599 +Z5 d$MODEL_TECH/.. +Z6 8vhdl_src/std/env.vhd +Z7 Fvhdl_src/std/env.vhd +l0 +L1 +VMSh;Gmh>9BN +@Jt +  + +  + +  +e +X  +Xe +H  +He +> + RSt +/Cn- H +(  +(e +  > + o +hZ +/  + +(  +( + > + | dt +  +  . +  + + He +  +e + e +> +nm` p   + +]]]!m +#m (  + +S ( 0#  + + +S^]]$m 8 0#  + + +S'm  +^]%m  +]ym 8 0#  + + +S|m  +^]zm  +]*m]]]],m +.mR/m  X 0#  + + +R"  H 0!# " +! +! +S!"]2m  +%^!]0m  +%]4m  + ^]5m# H 0$## % +$ +$ +S'8m  ++^']6m  ++]:m  +]<m-].]/] ]AmEm &(  +& +S3' ( 0(#' ) +( +( +R3Fm* +S1Im+ +R4Jm-4]Lm , +R3 - +R3 Pm-Rm. + +- +S-6Um/6 +/// +`-3^6]Sm/3^1]Gm/3]Zm  + +[m:];]<] +]`m +cm 0(  +0 +SG1 ( 02#1 3 +2 +2 +S=G^ ]=]dm4 +S? hm5 + +c +XcBlm66 +/66 +`cmm  +G^B]im/jm  +G^?]em/fm  +G]qmH]I]J] ]m +mx` Kyx_XM]m7 +SYm  +a^Y]m8 + + +X]m  +a^]]m  +a]m  - +m  +Lo^N]m9 +Sdm  +l^d]m: + + +Xhm  +l^h]m  +l]m  - +m  +L`^O]m; +Som  +w^o]m< + +- +X-sm  +w^s]m   +w]m  - +m  +LQ^P]m= +Szm  +^z]m> + + +X~m  +^~]m  + +]m 0 - +m  +LB^Q]m? +Sm  +^]m@ + + +Xm  +^]m   +]m H - +m  +L2^R]mA +Sm  +^]mB + + +Xm  +^]m  +]m ` - +m  +L#^S]m  +m x - +m  +L^T]m  +m  - +m  +L^U]m  +m  - +m  +L^V]m  +m  - +m  +L ^W]m  +m  - +m  +L^K]m  +m  - +m  +L]m]]]C +C +Sa + +a + 0 +a +` +a + +a + +a + +a +   +X + +D.0 +D +]E..J +E +]F/;.S +F +SVH +V +% +]G<I.Z +G +SV* +]HJ.d +H +]]`d--```c`freq``max_period_factor_facto``0idle_period_factor_fact```green_period_factor_fac`` orange_period_factor_fa`` +red_period_factor_facto`` red_orange_period_factor_factor``  clkctorLL +XrstctorLL +xj_leftrLLj_rightLLledghtLLidle0tidle1tgreentorangeredgered_orange_oranrst_before_idle1e_idle1rst_before_idle0e_idle0rst_before_greene_greenrst_before_orange_orangrst_before_redorst_before_red_orange_o + 1BSetpr_stater_stateLLnxt_statet_statLLpr_state_modeteLL@nxt_state_modetLLhled_intLLone_secLLmodeecLLrst_intLLcounterLL#MERGED#mode_s_p,main_s_pain_s_mode_c_pode_c_ptime_ppone_sec_pe_sec_main_c_pain_c_pline__218ne__21 XMNOPQRSKTUVW(@Xpbehavioralaviortlc2iorone_sec_factor_temp0_flag_temp_src/tlc2.vhdlc2/80b 3f9 {800 3f2 {630 42e {{t358 568 358 378 518 } {540 4f0 } {0 33}} 64a 42e {{t540 t3b8 t398 3b8 540 398 } {568 5d0 } {0 44}} 653 42e {{t358 5f0 358 5b0 } {610 } {0 65}} 65a 42e {{t358 5f0 358 } {5b0 } {0 96}} 664 42e {{t610 t5d0 t4f0 610 4f0 5d0 } {518 590 5f0 } {0 129}} 66d 42e {{t590 } {3d8 } {0 218}} }} 0~ \ No newline at end of file Index: tags/vers/modelsim/work/_opt/vopt6x1df4 =================================================================== --- tags/vers/modelsim/work/_opt/vopt6x1df4 (nonexistent) +++ tags/vers/modelsim/work/_opt/vopt6x1df4 (revision 3) @@ -0,0 +1,44 @@ +p +eez5sH`t&aLRWs3o#$e\b,nif%aӺ p +OP @W . +/ +Z8DC:eW2l.koiәkEm:oxZՏj1b.%TK>N8@Q\ٔٓ=(cj7mO5r4BGdZ9.`Yg +p@BWlZƸMeШ Pfhŕ!]N1p+Ju!qr"a'>w!rX9DFiZ#D]ԢJ&eC9P8>M[DIAэ_VKr}YS$4N~%ַy&7 +FAJiH[ν%՝&ƃxX.1 Wʭ{Pd(֐޼G!= :&I~g` 0 +ޭgP,|µ*RgmqZhwaB?p銘E!Jza%"3'x3V5x@,!Cz6(ԁ h?0 )?c\[eTDizm|!{"!߶ޠ(/;ë9a(W/PJe1A0:̳$ז)m#/g%W<9{x) +O$tU.AN)HV@˛a(=Wg(uA1 +WQv(p( +R +gmK1m)]Ϟ~E&Y_(Oq9@| +ڬ19^颜 s˿Frڼ%tB!_sL=C +`EYU7MZN 2Sp8ZAH?բ,*5Y/F3W$]o +|i + +fO$I'$.PJ)g|a +f(4}/eKb+!Rb W%Q4 +بP*/#5Ӓ*2-W.$eMzL92B颔 +~Ke{KMD@5MBOtDF`,(r>4"I34]W +X 6ŋC[r yhfLyٛJة +юţN +y7 +A&t=P*% +Q{=W7rz%,"3q /A _HuVzP0-+4)q' {wwF|O-ѯs2z P. w p +*/wYR%_Ω"y/ +MW٧}5 + /rG{r(ɡ ` +7pxZqn*'E!_X&e]^/(Ej%\cB: +i< +HwU{8ڧ'}(=)dV@R1I s٪WeIڑkǐRsCnⷊ +ƀ<օ"@Lބ[ ?ߞnlFx.G%nm3$}h˂ajf ^Kga3~?c걅\ + "E, +{y"3'QbSfDJ<8ݬ S谓@$TXPva)'45 +_·Kr.[c!dv#ZƊilƧTu_^= 43Pv0@]pW ׊\mΕt{) Dt- +_FuA2pR^N" + +鼐0Mj_8+xO"ňZz9kO%/+/RU]ֹ# + .k3oeJIϋ%9U{짘yL"8ڐbZ-ƪˎ NQqzb1B/y\559^uQ7&6[\SMȰL_O E6fl^z޺bH%}vÒC \ No newline at end of file Index: tags/vers/modelsim/work/_opt/vopt7gwyje =================================================================== --- tags/vers/modelsim/work/_opt/vopt7gwyje (nonexistent) +++ tags/vers/modelsim/work/_opt/vopt7gwyje (revision 3) @@ -0,0 +1,10 @@ +p +eez5sH$`t&aLRS-8x*c6/TC3<;JhiWn<%&XO' 40W}flʴc]tUZH:H(сI `C +9\& 7#r0 +g +yxJ]Z۪! ӟ>$OO T:L +e^ ҍm|tQaA @f\i _(iVoe_5 ?8QkWq.!4WN +YwcǓgVyڅV^:,LsmUm2x\NvaĩUdƁ щE` +i\y R k)m 6HD^r2G't +MNYxU~".( TaZ2;; Uе +\ =-d˲-g|z 9+m1Wv88qV@NqΠd=Ǽ Yce|AE"L4=HaaCypS\ U:0F9@!޷l|1nuHϋp)˛s3B"zC \ No newline at end of file Index: tags/vers/modelsim/work/_opt/vopthksh7h =================================================================== --- tags/vers/modelsim/work/_opt/vopthksh7h (nonexistent) +++ tags/vers/modelsim/work/_opt/vopthksh7h (revision 3) @@ -0,0 +1,3 @@ +p Ho-r Ho 0 O!!"Ȱx%Z޳ZH^=mGzxhva^fC=m +!!׊э=m +!K5׮ooKWNޅz \ No newline at end of file Index: tags/vers/modelsim/work/_opt/voptr6x661 =================================================================== --- tags/vers/modelsim/work/_opt/voptr6x661 (nonexistent) +++ tags/vers/modelsim/work/_opt/voptr6x661 (revision 3) @@ -0,0 +1,108 @@ +4%5] +/`mu + + + + +$ +! +/n-p + +d +0 0n- + +d + 0 1n(-( + +d +00 2n8-8 + +d +@0 5nH +H +d +X0  +S  ^];nh + + +  +<n + + +   +<n + + +@ @ +<n  + + +0 0 +=n +X X +49> +] +It +  + + > + Pt +  +  +@  +@ +0  +0 +> + +] ]]Am ]Fm +  + +Gm? + +Sw +]x +]Im ^]]] ]Lm]Mm ? + +Sw +]x +]Nm  +Om +? + + +Sw +]x +]Pm  +Qm ? + +Sw +]x +]Rm  +Sm "? + +S#w +#]x +""]Tm  +Um +&? + + +S'w +']2x +&&]Vm  +Wm*? + +S+w ++]dx +**]Xm  +am.? + +S/w +/]..]cm^0]1]]U + +S4 .I + +3]1.P + +4]5]`clklc2LL/hrstlc2LL0j_rightLL1j_leftLL2ledftLL5uutft>workttlc2tbehavioralaviortb_clkrtb_skrbehaviorehaviortlc2_tbsrc/tlc2_tb.vhdf15e 3f9 {155 3f2 {149 42e {{68 } {68 } {0 65}} 150 42e {{} {88 c8 a8 } {0 76}} }} ! \ No newline at end of file Index: tags/vers/modelsim/work/_opt/voptd7wnie =================================================================== --- tags/vers/modelsim/work/_opt/voptd7wnie (nonexistent) +++ tags/vers/modelsim/work/_opt/voptd7wnie (revision 3) @@ -0,0 +1,2 @@ +p Ho HoO? 0 t,LȹيDEK`p<:-ڢ'&SUq#=+ hLt0BL2jv"h\5sC +Sg̺6pՖ$tbL\ RTv +3[9f9ɛU} \ No newline at end of file Index: tags/vers/modelsim/work/_opt/_deps =================================================================== --- tags/vers/modelsim/work/_opt/_deps (nonexistent) +++ tags/vers/modelsim/work/_opt/_deps (revision 3) @@ -0,0 +1,12 @@ +k)99{]QK{9uL2j P)` 4R:;#1ܖ4)u`O_J ,dZIR\G>lcjl6@i!zG@ƯQ_^ΦGiΕf/l_; +_zf%FireKcl\-0i%,monr; 5B! I2r8FL[-pbGRDO7DG!qB +eykId]Cm+ySX&GOPixLmo .<ǾCq긒w)X'#(&RѠAVӖ? qA30S5r_Ga +kĩOgb&ɐ]PDX;1!̈$o{ۍgz8W8qh8+a]U#6mXAH@9{:<=e +k6$zPDӥ%7E{7w  86 +S.=۰`'E+EYI*{3&V|uWެ] +EK5֭CPMhQƆYc>Y§w9NnaIܪ?ߤyMҕۙTef)XPl?t9sd[cg(P4iP +|j6^𝽑.h=d7kH*pw\BxIT*e &hbJyES .1E%Oia$OxCPw*nBFU:EkMsjjm + +mnF7~Y):)njܧHcwv# -IEU\Ȣ!U;3bE  +|F~5[%%^?R!EEwØ4mex@·OH\7;ݰd"Hx%pT7x#9qEMڧ1r:ʯ~~wjM~'G&ϭS7,̦;, a\x36e'Sie͓jPs\]0gʿ3cIqZ/&b,*onf-PIkH2k(\p<@ts. +$쥺Z]%!cyG>0JWK2 P-g؛g']0Z"+h(H·nJDٟ#eFيB Cd?'</,>->p,*4BB īoȝoqb{@i쟸PY34x[l:eR2$Q7p2S(%p1aoj_sT (HJ ڣ++(8{T Z7S((g51%`jASͪ. \ No newline at end of file Index: tags/vers/modelsim/work/_opt/vopt2ry2s2 =================================================================== --- tags/vers/modelsim/work/_opt/vopt2ry2s2 (nonexistent) +++ tags/vers/modelsim/work/_opt/vopt2ry2s2 (revision 3) @@ -0,0 +1,40 @@ +p$l](&l]-Չ"           +  ! + +!# + +$ +%%('''(*,,, ,.// 00(22(44(566(88(::(<A + +AB B +C +E + +FGBIJCLLCPCRBR SBUBUBZ +ZBZ([` + +`a a + c + +de aff(!h ah i ajj("l al amm(#qv + +v$x + +y +zz(%|||(&  +' +(()(*(+(,(- +((.(/(0(1(2 +3 (4(5(6(7(8 +9 +(:(;(<(=(> +? (@(A(B(C(D +E (F(G(H(I(J(K(L(M(N(O(P(Q(R(S(T(U(V(W(X(Y(Z([(\](^yJW|0!, ~H2:ͤʃ|0!,7%NE`\KV |0!,7%N[~hʕ1+XSf#TM&H+]xf kQsY&,QQ⻗g5E2N +#kt? +LZ`n+ݹZ2+M@ tw?HY,ܧĪĺ:'flj9VrH+]xf kQsY&,QQ⻗g5E2N +#kt? +LZ`n+ݹZ2+M@ f6bʜ +tZ[NzqCVY|T#t'+x#R3Q| +EZUFf + uN'@[(^& qG +k' jƫ%{F_h$]wo_ Vs˙4|ղ_ 0RvGP)[ imXv+Z2LW*;̢*H?oW-9uTn8y̡Q8CPqɅPa-~us*rߛL\묮͜b*jj>,RJOqJ,Кmz3Q{}ēK>YskMug F2Cr%cB2 $pc+@1}ef 0PV)]U1X#\ @I`O%e w͙KGa +v9Sm;AZ} \ No newline at end of file Index: tags/vers/modelsim/work/_opt/voptzkwn46 =================================================================== --- tags/vers/modelsim/work/_opt/voptzkwn46 (nonexistent) +++ tags/vers/modelsim/work/_opt/voptzkwn46 (revision 3) @@ -0,0 +1,61 @@ +m255 +K3 +13 +Z0 cModel Technology +Z1 d/export/jack/dimo/vhdl/tlc2 +T_opt +Z2 V0>dXfFb=W24Q[dPk7mTFH3 +Z3 04 7 8 work tlc2_tb behavior 1 +Z4 =3-001636847494-4857da9b-3a2c3-66cb +Z5 o-quiet -auto_acc_if_foreign -work work +Z6 tExplicit 1 +Z7 OL;O;6.3d;37 +Etlc2 +Z8 w1213717120 +Z9 DPx17 __model_tech/ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4Fcgb0eea`gLaQP=1inVA2 +Z14 OL;C;6.3d;37 +R6 +Abehavioral +R9 +R10 +Z15 DEx41 /export/jack/dimo/vhdl/tlc2/modelsim/work 4 tlc2 0 22 z>cgb0eea`gLaQP=1inVA2 +32 +Z16 Mx2 17 __model_tech/ieee 14 std_logic_1164 +Z17 Mx1 17 __model_tech/ieee 11 numeric_std +l28 +L18 +Z18 VYDEJECD57LKz:[[od;1_V0 +R14 +R6 +Etlc2_tb +Z19 w1210753914 +R9 +R10 +32 +Z20 8src/tlc2_tb.vhd +Z21 Fsrc/tlc2_tb.vhd +l0 +L33 +Z22 VL6[DR2;]DnF7oV@jf8n4?2 +R14 +R6 +Abehavior +R15 +R9 +R10 +DEx41 /export/jack/dimo/vhdl/tlc2/modelsim/work 7 tlc2_tb 0 22 L6[DR2;]DnF7oV@jf8n4?2 +32 +R16 +R17 +l55 +L36 +Z23 V0C2SIHCb;J2KNV?ilnf[43 +R14 +R6 Index: tags/vers/modelsim/work/_opt/vopthqrmdi =================================================================== --- tags/vers/modelsim/work/_opt/vopthqrmdi (nonexistent) +++ tags/vers/modelsim/work/_opt/vopthqrmdi (revision 3) @@ -0,0 +1,9 @@ +p Ho-r Ho0 O!#A#A#A #A +#A #A #A + +  + ! Ȱx%Z:=mGzxhva^fC=m +!!׊э=m +!K5׮ooKWBP d!LQ} +2C,M_掓] +Ͽk[T1+쵍n$Pg,**;\E'.pYz\#kn0>f>)$'ԍou&VxJ=|0}N>4=vٍ \ No newline at end of file Index: tags/vers/modelsim/work/_opt/vopttzj1g5 =================================================================== --- tags/vers/modelsim/work/_opt/vopttzj1g5 (nonexistent) +++ tags/vers/modelsim/work/_opt/vopttzj1g5 (revision 3) @@ -0,0 +1,4 @@ +p Ho HoO> 0 t,LȹيDEK`p<:-ڢ'&SUq2I=QN|ZGddG/# ->I=QN|ZGdG/# ->I= QN|ZGdG +/# >I= QN|ZGdK+4Q  +A6mVhȇlo{aJ${AoFVboi6uVCd'wgu\D9R:2#IZo  +`*&57mf9'Jl03ItìlޏƦZ&Qʶ!#"6KRrS(ؠU^%#PV.b9 ;ya{޹8Ap\tȞ692.9=ά̱)ތUH6A/b"sXb 0EPR\ \ No newline at end of file Index: tags/vers/modelsim/work/_opt/voptz6h44f =================================================================== --- tags/vers/modelsim/work/_opt/voptz6h44f (nonexistent) +++ tags/vers/modelsim/work/_opt/voptz6h44f (revision 3) @@ -0,0 +1,393 @@ +m255 +K3 +Z0 cModel Technology Builtin Library +13 +Z1 dD:\qa\buildsites\6.3d\builds\win32\modeltech +Pmath_complex +Z2 DPx4 work 9 math_real 0 22 zjAF7SKfg_RPI0GT^n1N`1 +Z3 OL;C;6.3d;37 +31 +b1 +Z4 Mx1 4 work 9 math_real +Z5 OP;C;6.3d;37 +Z6 w877855682 +Z7 d$MODEL_TECH/.. +Z8 8vhdl_src/ieee/1076-2code.vhd +Z9 Fvhdl_src/ieee/1076-2code.vhd +l0 +L687 +V1a;R8Z_kc3Q7^>9;gKVIV0 +Z10 OE;C;6.3d;37 +Z11 o-93 -work ieee -dirpath $MODEL_TECH/.. +Z12 tExplicit 1 +Bbody +DBx4 work 12 math_complex 0 22 1a;R8Z_kc3Q7^>9;gKVIV0 +R2 +R3 +31 +R4 +R5 +l0 +L3719 +VIMmI^hXJEW@Uoa4kJFX:K1 +R10 +R11 +R12 +nbody +Pmath_real +R3 +31 +b1 +R5 +R6 +R7 +R8 +R9 +l0 +L55 +VzjAF7SKfg_RPI0GT^n1N`1 +R10 +R11 +R12 +Bbody +DBx4 work 9 math_real 0 22 zjAF7SKfg_RPI0GT^n1N`1 +R3 +31 +R5 +l0 +L1772 +V:TOmE?QHig?1Xi[gFIA[l1 +R10 +R11 +R12 +nbody +Pnumeric_bit +R3 +31 +b1 +R5 +Z13 w1196138599 +R7 +Z14 8vhdl_src/ieee/mti_numeric_bit.vhd +Z15 Fvhdl_src/ieee/mti_numeric_bit.vhd +l0 +L58 +VK1ChclJ;R]bj:k4Y1 +R10 +R16 +R12 +nbody +Pnumeric_std +Z17 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2 +R3 +31 +b1 +Z18 Mx1 4 ieee 14 std_logic_1164 +R5 +R13 +R7 +Z19 8vhdl_src/ieee/mti_numeric_std.vhd +Z20 Fvhdl_src/ieee/mti_numeric_std.vhd +l0 +L57 +V=NSdli^?T5OD8;4F6>65S7FR:e[I>ADUQO1 +R10 +R11 +R12 +nbody +Pstd_logic_textio +R17 +Z34 DPx3 std 6 textio 0 22 K]Z^fghZ6B=BjnK5NomDT3 +R3 +31 +b1 +Z35 Mx2 3 std 6 textio +R18 +R5 +R13 +R7 +Z36 8vhdl_src/synopsys/std_logic_textio.vhd +Z37 Fvhdl_src/synopsys/std_logic_textio.vhd +l0 +L22 +V8YS?iX`WD1REQG`ZRYQGB2 +R10 +R11 +R12 +Bbody +DBx4 work 16 std_logic_textio 0 22 8YS?iX`WD1REQG`ZRYQGB2 +R17 +R34 +R3 +31 +R35 +R18 +R5 +l0 +L70 +Vj9DSczGXI>dbiF;m2[GMa2 +R10 +R11 +R12 +nbody +Pstd_logic_unsigned +R30 +R17 +R3 +31 +b1 +R26 +R31 +R5 +R13 +R7 +Z38 8vhdl_src/synopsys/mti_std_logic_unsigned.vhd +Z39 Fvhdl_src/synopsys/mti_std_logic_unsigned.vhd +l0 +L34 +VhEMVMlaNCR^;kUYmkG[EMmIIzoCHn?@614I_=a3 +R10 +R42 +R12 +nbody +Pvital_timing +R17 +R3 +30 +b1 +R18 +R5 +Z44 w1196138601 +R7 +8vhdl_src/vital95/timing_p.vhd +Fvhdl_src/vital95/timing_p.vhd +l0 +L46 +VOBWK>;kUYmkG;kUYmkGN8@Q\ٔٓ=(cj7mO5r4BGdZ9.`Yg +p@BWlZƸMeШ Pfhŕ!]N1p+Ju!qr"a'>w!rX9DFiZ#D]ԢJ&eC9P8>M[DIAэ_VKr}YS$4N~%ַy&7 +FAJiH[ν%՝&ƃxX.1 Wʭ{Pd(֐޼G!= :&I~g` 0 +ޭgP,|µ*RgmqZhwaB?p銘E!Jza%"3'x3V5x@,!Cz6(ԁ h?0 )?c\[eTDizm|!{"!߶ޠ(/;ë9a(W/PJe1A0:̳$ז)m#/g%W<9{x) +O$tU.AN)HV@˛a(=Wg(uA1 +WQv(p( +R +gmK1m)]Ϟ~E&Y_(Oq9@| +ڬ19^颜 s˿Frڼ%tB!_sL=C +`EYU7MZN 2Sp8ZAH?բ,*5Y/F3W$]o +|i + +fO$I'$.PJ)g|a +f(4}/eKb+!Rb W%Q4 +بP*/#5Ӓ*2-W.$eMzL92B颔 +~Ke{KMD@5MBOtDF`,(r>4"I34]W +X 6ŋC[r yhfLyٛJة +юţN +y7 +A&t=P*% +Q{=W7rz%,"3q /A _HuVzP0-+4)q' {wwF|O-ѯs2z P. w p +*/wYR%_Ω"y/ +MW٧}5 + /rG{r(ɡ ` +7pxZqn*'E!_X&e]^/(Ej%\cB: +i< +HwU{8ڧ'}(=)dV@R1I s٪WeIڑkǐRsCnⷊ +ƀ<օ"@Lބ[ ?ߞnlFx.G%nm3$}h˂ajf ^Kga3~?c걅\ + "E, +{y"3'QbSfDJ<8ݬ S谓@$TXPva)'45 +_·Kr.[c!dv#ZƊilƧTu_^= 43Pv0@]pW ׊\mΕt{) Dt- +_FuA2pR^N" + +鼐0Mj_8+xO"ňZz9kO%/+/RU]ֹ# + .k3oeJIϋ%9U{짘yL"8ڐbZ-ƪˎ NQqzb1B/y\559^uQ7&6[\SMȰL_O E6fl^z޺bH%}vÒC \ No newline at end of file Index: tags/vers/modelsim/work/tlc2/behavioral.dbs =================================================================== --- tags/vers/modelsim/work/tlc2/behavioral.dbs (nonexistent) +++ tags/vers/modelsim/work/tlc2/behavioral.dbs (revision 3) @@ -0,0 +1,40 @@ +p$l](&l]-Չ"           +  ! + +!# + +$ +%%('''(*,,, ,.// 00(22(44(566(88(::(<A + +AB B +C +E + +FGBIJCLLCPCRBR SBUBUBZ +ZBZ([` + +`a a + c + +de aff(!h ah i ajj("l al amm(#qv + +v$x + +y +zz(%|||(&  +' +(()(*(+(,(- +((.(/(0(1(2 +3 (4(5(6(7(8 +9 +(:(;(<(=(> +? (@(A(B(C(D +E (F(G(H(I(J(K(L(M(N(O(P(Q(R(S(T(U(V(W(X(Y(Z([(\](^yJW|0!, ~H2:ͤʃ|0!,7%NE`\KV |0!,7%N[~hʕ1+XSf#TM&H+]xf kQsY&,QQ⻗g5E2N +#kt? +LZ`n+ݹZ2+M@ tw?HY,ܧĪĺ:'flj9VrH+]xf kQsY&,QQ⻗g5E2N +#kt? +LZ`n+ݹZ2+M@ f6bʜ +tZ[NzqCVY|T#t'+x#R3Q| +EZUFf + uN'@[(^& qG +k' jƫ%{F_h$]wo_ Vs˙4|ղ_ 0RvGP)[ imXv+Z2LW*;̢*H?oW-9uTn8y̡Q8CPqɅPa-~us*rߛL\묮͜b*jj>,RJOqJ,Кmz3Q{}ēK>YskMug F2Cr%cB2 $pc+@1}ef 0PV)]U1X#\ @I`O%e w͙KGa +v9Sm;AZ} \ No newline at end of file Index: tags/vers/modelsim/work/tlc2/_primary.dat =================================================================== --- tags/vers/modelsim/work/tlc2/_primary.dat (nonexistent) +++ tags/vers/modelsim/work/tlc2/_primary.dat (revision 3) @@ -0,0 +1,4 @@ +p Ho HoO> 0 t,LȹيDEK`p<:-ڢ'&SUq2I=QN|ZGddG/# ->I=QN|ZGdG/# ->I= QN|ZGdG +/# >I= QN|ZGdK+4Q  +A6mVhȇlo{aJ${AoFVboi6uVCd'wgu\D9R:2#IZo  +`*&57mf9'Jl03ItìlޏƦZ&Qʶ!#"6KRrS(ؠU^%#PV.b9 ;ya{޹8Ap\tȞ692.9=ά̱)ތUH6A/b"sXb 0EPR\ \ No newline at end of file Index: tags/vers/modelsim/work/tlc2/_primary.dbs =================================================================== --- tags/vers/modelsim/work/tlc2/_primary.dbs (nonexistent) +++ tags/vers/modelsim/work/tlc2/_primary.dbs (revision 3) @@ -0,0 +1,9 @@ +p Ho-r Ho0 O!#A#A#A #A +#A #A #A + +  + ! Ȱx%Z:=mGzxhva^fC=m +!!׊э=m +!K5׮ooKWBP d!LQ} +2C,M_掓] +Ͽk[T1+쵍n$Pg,**;\E'.pYz\#kn0>f>)$'ԍou&VxJ=|0}N>4=vٍ \ No newline at end of file Index: tags/vers/modelsim/work/tlc2_tb/behavior.dat =================================================================== --- tags/vers/modelsim/work/tlc2_tb/behavior.dat (nonexistent) +++ tags/vers/modelsim/work/tlc2_tb/behavior.dat (revision 3) @@ -0,0 +1,10 @@ +p +eez5sH$`t&aLRS-8x*c6/TC3<;JhiWn<%&XO' 40W}flʴc]tUZH:H(сI `C +9\& 7#r0 +g +yxJ]Z۪! ӟ>$OO T:L +e^ ҍm|tQaA @f\i _(iVoe_5 ?8QkWq.!4WN +YwcǓgVyڅV^:,LsmUm2x\NvaĩUdƁ щE` +i\y R k)m 6HD^r2G't +MNYxU~".( TaZ2;; Uе +\ =-d˲-g|z 9+m1Wv88qV@NqΠd=Ǽ Yce|AE"L4=HaaCypS\ U:0F9@!޷l|1nuHϋp)˛s3B"zC \ No newline at end of file Index: tags/vers/modelsim/work/tlc2_tb/behavior.dbs =================================================================== --- tags/vers/modelsim/work/tlc2_tb/behavior.dbs (nonexistent) +++ tags/vers/modelsim/work/tlc2_tb/behavior.dbs (revision 3) @@ -0,0 +1,4 @@ +p$l](&l]Չ$"/ 0 1 2 5 ;/;/<0<0<2<2< 1< 1=5=5:@F/F/F(IK N0N( +P0P( R2R( T2T( +V1V(X1X(cdyJ$1|0!, ~H2:ͤʃ|0!,7%NE`\KV |0!,7%N[~hʕ1+XSf#TGt(E|㲒M;VͿ0Z%~y}Np&>g̺6pՖ$tbL\ RTv +3[9f9ɛU} \ No newline at end of file Index: tags/vers/modelsim/work/tlc2_tb/_primary.dat =================================================================== --- tags/vers/modelsim/work/tlc2_tb/_primary.dat (nonexistent) +++ tags/vers/modelsim/work/tlc2_tb/_primary.dat (revision 3) @@ -0,0 +1,2 @@ +p Ho HoO? 0 t,LȹيDEK`p<:-ڢ'&SUq#=+ hLt0BL2jv"h\5sC +SdXfFb=W24Q[dPk7mTFH3 +04 7 8 work tlc2_tb behavior 1 +Z2 =3-001636847494-4857da9b-3a2c3-66cb +Z3 o-quiet -auto_acc_if_foreign -work work +Z4 tExplicit 1 +Z5 OL;O;6.3d;37 +Etlc2 +Z6 w1213717120 +Z7 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4Fcgb0eea`gLaQP=1inVA2 +Z12 OL;C;6.3d;37 +32 +R4 +Abehavioral +R7 +R8 +Z13 DEx4 work 4 tlc2 0 22 z>cgb0eea`gLaQP=1inVA2 +l28 +L18 +Z14 VYDEJECD57LKz:[[od;1_V0 +R12 +32 +Z15 Mx2 4 ieee 14 std_logic_1164 +Z16 Mx1 4 ieee 11 numeric_std +R4 +Etlc2_tb +Z17 w1210753914 +R7 +R8 +Z18 8src/tlc2_tb.vhd +Z19 Fsrc/tlc2_tb.vhd +l0 +L33 +Z20 VL6[DR2;]DnF7oV@jf8n4?2 +R12 +32 +R4 +Abehavior +R7 +R8 +Z21 DEx4 work 7 tlc2_tb 0 22 L6[DR2;]DnF7oV@jf8n4?2 +l55 +L36 +Z22 V0C2SIHCb;J2KNV?ilnf[43 +R12 +32 +R15 +R16 +R4 Index: tags/vers/it =================================================================== --- tags/vers/it (nonexistent) +++ tags/vers/it (revision 3) @@ -0,0 +1,4 @@ +vcom src/tlc2.vhd +vcom src/tlc2_tb.vhd +restart +run 1000 ns Index: tags/vers/Makefile =================================================================== --- tags/vers/Makefile (nonexistent) +++ tags/vers/Makefile (revision 3) @@ -0,0 +1,136 @@ +############################################################################################## +# In order to create a new project, change the first three macros in this file, the content # +# of the UCF file and the name and content of the VHD files in src # +# Don't forget to execute "source bin/load_modules" manual from the shell # +############################################################################################## + +TOP=tlc2#change to the name of the TOP-Entity +DEVICE=xc3s4000-fg676-4#change to the device id found on the chip +VHDLSYNFILES=src/$(TOP).vhd#list all vhdl files in the project that have to be synthesized + +OPTMODE=Speed +OPTLEVEL=1 +EFFORT=high +UCF=src/$(TOP).ucf +SCRIPTFILE=$(TOP).scr +PROJECTFILE=$(TOP).prj +LOGFILE=$(TOP).log +TOPSIM=$(TOP)_tb +DOFILE=src/$(TOP).do +BITGEN=src/$(TOP).ut +ALLFILES=$(VHDLSYNFILES) src/$(TOPSIM).vhd +SHELL=/bin/bash + +all: help + +help: + @echo + @echo " make help : prints this help menu " + @echo " make use-vsim : simulate with Modelsim in batch mode, use >>do it<< to reload" + @echo " make use-vsim-gui : simulate with Modelsim and GUI" + @echo " make use-xst : synthesize with xst " + @echo " make implement : final step" + @echo " make ml : prints loaded modules. Use source bin/load_modules if modules are not loaded " + @echo " make files : prints info about the used files " + @echo " make vsim-help : prints appropriate steps for simulation" + @echo " make warnings-xst : prints warnings and info from the XST log file" + @echo " make warnings-implement : prints warnings and info from the PAR log file" + @echo " make clear : clears all XST output files" + @echo + +use-xst: $(VHDLSYNFILES) + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + @for i in $(VHDLSYNFILES); do bin/xstvhdl $$i >> $(PROJECTFILE); done + @echo run -ifn $(PROJECTFILE) -ifmt vhdl -ofn $(TOP).ngc -ofmt NGC -p $(DEVICE) -opt_mode $(OPTMODE) -opt_level $(OPTLEVEL) -top $(TOP) -rtlview yes > $(SCRIPTFILE) + @xst -ifn $(SCRIPTFILE) -ofn $(LOGFILE) + +implement: $(TOP).ngc + @mv -f src/*.ucf $(UCF)TMP + @mv -f $(UCF)TMP $(UCF) + @mv -f src/*.ut $(BITGEN)TMP + @mv -f $(BITGEN)TMP $(BITGEN) + bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) + +ml: + @/home/4all/packages/modules-2.0/sun5/bin/modulecmd tcsh list + +use-vsim: it $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run -all > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) + vsim -c work.$(TOPSIM) -do $(DOFILE) + +use-vsim-gui: $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run 1000 ns > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) +# vsim -gui work.$(TOPSIM) -do $(DOFILE) & + vsim -gui work.$(TOPSIM) -do it & + +clear: + @rm -f $(TOP).ngr $(TOP).msd $(TOP).msk $(TOP).rbt $(TOP).twr $(TOP).xpi $(TOP)_pad.csv $(TOP)_pad.txt $(TOP).bld + @rm -f $(TOP).ngc $(TOP).ncd $(TOP).ngd $(TOP).rba $(TOP).rbd $(TOP).rbb netlist.lst $(TOP).mrp $(TOP).ll $(TOP).bit + @rm -f $(TOP).lso $(TOP).ngm $(TOP).ngr $(TOP).pad $(TOP).par $(TOP).pcf transcript vsim.wlf $(TOP).log $(TOP).bgn *.twr *.xml *.map *.unroutes + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + +files: + @echo + @echo $(TOP)".ngc : netlist output from XST" + @echo $(TOP)".ngr : netlist output from XST for RTL and Technology viewers" + @echo $(TOP)".scr : script file for XST, generated by Makefile" + @echo $(TOP)".prj : contains the vhdl source files, generated by Makefile." + @echo $(TOP)".log : log file, output from XST" + @echo $(TOP)".ucf : user constraints file with pins description, write yourself" + @echo $(TOP)".ut : config. script for BITGEN, write yourself" + @echo "it : do-script for Modelsim in batchmode, write yourself" + @echo $(TOP)".do : do-script for Modelsim in GUI-mode, write yourself" + @echo $(TOP)".par : PAR report file, generated by make implement" + @echo + +vsim-help: + @echo + @echo " mkdir modelsim : create main directoriy for simulation" + @echo " vlib modelsim/work : create work library for simulation" + @echo " vmap : prints all logical mapped librarys" + @echo " vmap -del work : delete actual mapping for work library" + @echo " vmap work modelsim/work : map logical library work to modelsim/work" + @echo " vcom -93 -check_synthesis -work work : compile source vhdl files" + @echo " vcom -93 -work work : compile top level testbench" + @echo " do it : use in batch mode to recompile the testbench and the top entity and to restart the simulation" + @echo + +warnings-xst: + @grep -n -i warning *.log + @grep -n -i info *.log + +warnings-implement: + @grep -n -i warning *.par *.twr + @grep -n -i info *.par *.twr Index: tags/vers/xst/work/hdpdeps.ref =================================================================== --- tags/vers/xst/work/hdpdeps.ref (nonexistent) +++ tags/vers/xst/work/hdpdeps.ref (revision 3) @@ -0,0 +1,33 @@ +V3 16 +FL /export/jack/dimo/vhdl/tlc/src/tlc.vhd 2008/05/13.14:36:57 J.40 +FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd 2008/06/17.17:42:45 J.40 +EN work/tlc2 1213717396 FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/tlc2/behavioral 1213717397 \ + FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd EN work/tlc2 1213717396 +FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd 2008/05/09.12:27:02 J.40 +EN work/FSM_COUNTER 1210328828 \ + FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/FSM_COUNTER/BEHAVIORAL 1210328829 \ + FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd \ + EN work/FSM_COUNTER 1210328828 +FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd 2008/05/09.13:20:51 J.40 +EN work/FSM_DETECTOR 1210332468 \ + FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/FSM_DETECTOR/BEHAVIORAL 1210332469 \ + FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd \ + EN work/FSM_DETECTOR 1210332468 +FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd 2008/05/08.11:45:00 J.40 +EN work/GENERIC_DELAY 1210239907 \ + FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/GENERIC_DELAY/BEHAVIORAL 1210239908 \ + FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd \ + EN work/GENERIC_DELAY 1210239907 +FL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd 2008/05/07.11:24:01 J.40 +PH work/ARRAY_TYPES 1210154389 \ + FL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd \ + PB ieee/std_logic_1164 1106404628 +FL /home/students/dimo/vhdl/Book/tlc/src/tlc.vhd 2008/05/09.17:02:45 J.40 Index: tags/vers/xst/work/hdllib.ref =================================================================== --- tags/vers/xst/work/hdllib.ref (nonexistent) +++ tags/vers/xst/work/hdllib.ref (revision 3) @@ -0,0 +1,14 @@ +PH array_types NULL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd sub00/vhpl01 1210154389 +EN fsm_detector NULL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd sub00/vhpl08 1210332468 +AR generic_ram behavioral /home/students/dimo/vhdl/Book/generic_ram/src/generic_ram.vhd sub00/vhpl03 1210156112 +EN tlc NULL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd sub00/vhpl10 1210751748 +AR tlc2 behavioral /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd sub00/vhpl13 1213717397 +AR generic_delay behavioral /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd sub00/vhpl05 1210239908 +AR fsm_counter behavioral /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd sub00/vhpl07 1210328829 +AR fsm_detector behavioral /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd sub00/vhpl09 1210332469 +PH array_data_types NULL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd sub00/vhpl00 1210152194 +EN fsm_counter NULL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd sub00/vhpl06 1210328828 +EN generic_ram NULL /home/students/dimo/vhdl/Book/generic_ram/src/generic_ram.vhd sub00/vhpl02 1210156111 +EN generic_delay NULL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd sub00/vhpl04 1210239907 +AR tlc behavioral /export/jack/dimo/vhdl/tlc/src/tlc.vhd sub00/vhpl11 1210682241 +EN tlc2 NULL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd sub00/vhpl12 1213717396 Index: tags/vers/xst/work/sub00/vhpl00.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl00.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl00.vho (revision 3) @@ -0,0 +1 @@ +HqHH!uFQGieeeieeeBiieeestd_logic_1164allBi:array_data_typesqBi6.:* qXBivQ2'vQ2'v'YA#)mc*6|.': vector_array*A#)::vector_array $1:'|62'P% qFQ=/home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhdBiarray_data_typesworkarray_data_typesworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl01.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl01.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl01.vho (revision 3) @@ -0,0 +1 @@ +Hu0H!uBFQGieeeieeeBiieeestd_logic_1164allBi: array_typesqBi6.:* qXBivQ2'vQ2'v'YA#)mc*6|.': vector_array*A#)::vector_array $1:'|62'P% qFQ=/home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhdBi array_typeswork array_typesworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl10.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl10.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl10.vho (revision 3) @@ -0,0 +1,11 @@ +:HXH*Gieeeieeeީieeestd_logic_1164allީieee numeric_stdallީ:tlcYީ 6J9]qIY +:N!au1Ai Y+qީv:@'S#)*.@'S +"'2:@.:one_sec_factor:q!6A.q@BiS +">FQN!@Bi:stb_period_factorN!q!J9ABiq@-US +"R Ya@U:green_period_factoraq! ]AUq@iyS +"emau1@iy:orange_period_factoru1q! +qIAiyq@}S +"y@}:red_period_factorq! A}q@S +"qA@:red_orange_period_factorAq! YAqv:clkqp +)q:rstqp +)q:j_leftqp)q:j_rightiqp)q@9'Q2Q! @9v[9:ledqp qP% Y(/export/jack/dimo/vhdl/tlc2/src/tlc2.vhdީtlcworktlcworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl02.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl02.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl02.vho (revision 3) @@ -0,0 +1,4 @@ +-HXH!OGieeeieeeieeestd_logic_1164allieee numeric_stdall: generic_ramY'2>FQ]ma) +*6BiJ9YqI Y+qv*@*: addr_size*q!'A#)q@ 6: data_size6q! 2A.qvBi:clkBiqp +>:q:wr_enaJ9qp FQ:qS]2R a@N!vYU]UqT-Yq'Q2N!eiy@av[aqI:data_inqIqp +maiyq@yu1}S]'y@}:addrqpyqS]2q@'Q2YA@qv[q:data_outqp)AqP% Y=/home/students/dimo/vhdl/Book/generic_ram/src/generic_ram.vhd generic_ramwork generic_ramworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl11.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl11.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl11.vho (revision 3) @@ -0,0 +1,55 @@ +H:H) Ϲ: +behavioral "J9qYA#)'*.26R YemaqAQ! +!]1a rFQ:U]iyqIY)i9 ީ $aI ))YIy   - +stb_orange_on: -stb_orange_off: -green0: -green1: -orange0: -orange1: -red0: -red1: - red_orange0: - red_orange1: ,J9 J9 +qYA#)'*.26.>FQ|J9Bi :stateFQ vJ9U:pr_stateU pR N! : nxt_state] pYN! viy: +pr_state_modeiy pea[ :nxt_state_modeqI pmaa[ @y'Q4u1}@yv[y:led_int p +y:one_secY pqa[ :go) pAa[ :mode pa[ : green_period pa[ : +orange_period pa[ : +red_periodi pa[ :red_orange_period9 pQa[ : +stb_period p!a[ :rst_int paC :set_intީ paC A)S +[Yo%aeY \S +CS1qmao'eqv U +FSFS T= rAryIA<$Yqa"! :mode_s_p$ E"!) ,)-cyAe(S +[8S +C8S04OC@Qo/9ZI:temp3I qLF B!>9 q@QMJ:Y:temp4Y qMUQM q:flagaa qN]ya[ q \mS +CmSeIi1QyS +[I@xRt)I@S|&I@qT6iI@AUYF I@V)UI[oWI[oXI[oYI[QoZiQI[!o[9!IS +[@])@ҩ^&@y_֑6i@I`aF @a1UCobCocCodC YoeqQC)of +A!r +ҩyI Y)MS +q[ S +]yC S(i[]y(r $,<h(ES +qC89S +]y[89S0i4Q=lC]y=Sw)]k@GoC)kS[SOKWyYopOkS d)_Ic1@[ar[a)gr<c1nr@ GWyn<mkg=Sw&qJ@zuv&S[Yq~AYovqS d&@)x)&r<rrzA<t=Sw6iБ@i{6iБS[!9Q Yo|9БS d6i@~6i̩r<yri y<zБ̩=SwF ZY@1IF YS[YQoQYS dF @F qr<Ara1A<Yq=SwUJ:6!@U6!S["Y!o!6!S dU*i.Q@&&U29r<.Q: r )": <6!29=r89Y9i !@qYFQS]'Aq@YS]2'*@#)'Q3#).2@*v\*:v:62>|Bi: : +vector_array > vBiqJ9wN!FQBi : vector_arrayJ9 vN!Y:int_ramY pUR iy +*a2]e +qaiyR eYi >[ySq>DySqIu1SqFRDY>UmboYvUqFTFT T= r}A<Y>U)o*vU Tand ryA<maaQma> :ram9 EQi % =/home/students/dimo/vhdl/Book/generic_ram/src/generic_ram.vhd! generic_ram +behavioralwork generic_ram +behavioralwork generic_ramworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl12.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl12.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl12.vho (revision 3) @@ -0,0 +1,4 @@ +/HBhHW۔Gieeeieeeieeestd_logic_1164allieee numeric_stdall:tlc2Y '2>J9Uamay*6BiN!YeqI}q Y+qv*@*:freq*q!'A#)q@-6:max_period_factor6q!2A.q@Bi:idle_period_factorBiq!>A:q@-N!:green_period_factorN!q! J9AFQq@Y:orange_period_factorYq! +UAR q@e:red_period_factoreq! aA]q@qI:red_orange_period_factorqIq! maAiyqv}:clk}qp +yu1q:rstqp +u1q:j_leftqpu1q:j_rightqqpu1q@A'Q2Y)@Av[A:ledqpqP% Y(/export/jack/dimo/vhdl/tlc2/src/tlc2.vhdtlc2worktlc2workstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl04.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl04.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl04.vho (revision 3) @@ -0,0 +1,7 @@ +H#(H"ˣiyGieeeieeeeieeestd_logic_1164alleieee numeric_stdalle: +generic_delayYe'2:BiR Y*6>FQU] Y+qev*@*:states*q!'A#)qv6:clk6qp +2.q:rst>qp +:.q:dFQqp Bi.q@N!J9'U:selUqp R N!q:q]qp +Y.qP% YiyA/home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhde +generic_delaywork +generic_delayworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl13.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl13.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl13.vho (revision 3) @@ -0,0 +1,14 @@ +H@HWەq: +behavioralR qYA#)'*.26:>Yamau1Ai !B! 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A) y\yS yCySީYS [ +%Ima +u1o'mar<qvU FSFS T= ra1q<$ +YryqA<#Ya!!y :mode_s_p$ E!!) ,).cyAma(S [8S C8S04OC@Qo09@2:temp0B:flagQCiiy[ y\ S yC S9!.S [&@G&S A[yJ[iyrةܑa<Iy"S ACS i[SI1PCiSw2A@SAS d q@UYr< q)r)<QAYr)<L"r<a*r*<F&".r *2<E.:QoZ6iiaAB!y :time_pF EAB!>9 UY! @QMY:tempYIaUQMI y\eIS yCeIS]yaa9S [i@qemUi[xoftAiS tU@iUCYojqAS dU)@AlAU[omAr<r|Y<hr<Qri1qxQ<di9reIQ!<c9Ia`Iy : one_sec_p E` q y\yS yCySҩ֑S [1ozIYao|Yr<ra1<yry<xav Yy :main_s_p +A Ev Yq  g! )]19A$iGj Y)S [GS ti>4Q*$o a4Q,o(a0ir<,89r$89<4Q0iG2@ oY.voraYq~ozaqr<~ArnvA<Yq2o)ar<rkA<!s000[o!CQoi!q!r9QS CS tiJ:a6oaaYБo̩ayr<БIrI<ay.o1ar<r I< )s001[o )CYoq )Y )rAYS C=S tiU*i:oa*iA"oa&r<".Qr.Q<*i&=.6!o29a: r<6!Ar.QA<=: ]1s010[IEMoI]1CUaoQy]1A]1rYIAMUaS CS tia|q>loha|q#)topaxr<tYrelY<|qx.)oAar<)raY<9s100[o9Cio9#)9rQiS CS timby2oay'Ʃoaʑr<Ʃar a<yʑ.1oIar<1r!a<As110[oACqoA'ArYqq o)a$is000[ o$i[o$i*$ir  Y,9o(QaGs001[4 0!7o4 G[?o;G2GrC,97?AOaoKyajs010[W1SI[oW1j[bo_j6jrfOa[b#)ronas100[zYvq~AozY[o):rr~A'oa s110[io [9oQ > r!i9V1oas010[đyođ[Ioar1yIa)Yi :main_c_p E  %q(/export/jack/dimo/vhdl/tlc2/src/tlc2.vhdtlc2 +behavioralworktlc2 +behavioralworktlc2workstd_logic_1164ieeestandardstd \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl05.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl05.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl05.vho (revision 3) @@ -0,0 +1,11 @@ +8HH"ˤ: +behavioralY r}q)! #)'9!'Q3'YA@qv\q':temp'#)A. +q.A*'SY:DVA: +6\>A:Bi>#) 2[N!SY2DN!SFQJ9 #)R ]U'R Ye@U@iyeU!iyUUa:iea>#)iySiyu1@qIv}Uy T-} >#)qImaa4avqUYFTFT T=q v)UA Tand) rN!r2Bi<@>#)Bj>#)R +Qi9oQYa 2:BjR + :delay E ! %eA/home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd +generic_delay +behavioralwork +generic_delay +behavioralwork +generic_delayworkstandardstdstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl06.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl06.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl06.vho (revision 3) @@ -0,0 +1 @@ +H@H$&R GieeeieeeN!ieeestd_logic_1164allN!ieee numeric_stdallN!: fsm_counterYN!#)*Bi'.FQ Y+qN!v':clk'qp#)Aq:rst.qp*Aq@6'Q32:>@6vZ6FQ:outputFQqp Bi>qP% YR =/home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhdN! fsm_counterwork fsm_counterworkstd_logic_1164ieeestandardstd \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl07.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl07.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl07.vho (revision 3) @@ -0,0 +1,8 @@ +H#(H$&: +behavioralJ9qYA#)'*.26R YYrFQ:U]q) -state0: -state1: -state2: -state3: -state4: -state5: -state6: -state7: -state8: -state9: ,J9 J9 +qYA#)'*.26.>FQ|J9Bi :stateFQ vJ9U:pr_stateU pR N! : nxt_state] pYN! S*C)maoiyR ) #*\yS#*CySYqIu1AYo}R AvUFSFS T= vqUY Tandq ryrema<)Aaaa#** :seq E ) +yYD9s.]yAR qioYy@!@!S  {[! ީY uQY E9o BjyyriީYIo!aYY@@S  {[ +Y u1Y Eo"BjYqYrqI +A)o#AYD9@(@(S 48,{[(0,9o0IBj]y2]yrY6iUVYi1o1eIYA@ t@tS x{[t|xqY umY Eqo2|BjAaaArYi1qaR :comb E) %N"=/home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd fsm_counter +behavioralwork fsm_counter +behavioralwork fsm_counterworkstd_logic_1164ieeestandardstd numeric_stdieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl08.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl08.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl08.vho (revision 3) @@ -0,0 +1 @@ +HH$54J9GieeeieeeFQieeestd_logic_1164allFQieee numeric_stdallFQ: fsm_detectorYFQ#)*2:'.6> Y+qFQv':d'qp#)Aq:clk.qp*Aq:rst6qp2Aq:output>qp :AqP% YJ9?/home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhdFQ fsm_detectorwork fsm_detectorworkstd_logic_1164ieee \ No newline at end of file Index: tags/vers/xst/work/sub00/vhpl09.vho =================================================================== --- tags/vers/xst/work/sub00/vhpl09.vho (nonexistent) +++ tags/vers/xst/work/sub00/vhpl09.vho (revision 3) @@ -0,0 +1,5 @@ +^HpH$55o1: +behavioralkI 2qYA:Biu1qcyr.#)>FQqI}Yga_ kI-zero#) -first#) -second#) -ok#) ,2 2qYA.'.|2* :state. v2>:pr_state> p:6 : nxt_stateFQ pBi6 Su12CUoR : *\aSu1*CaSY]Biiyoe:vqIUu1FSFSma T=qI v}Uy Tand} raiyrN!U<J9aqJ9*2 :seqY Eq )_ ,[:ASu1#*CqoBioBir<iri< !Q:  r!i9)Su1#*CaYo"Biao#ީBiyr<IrI<"ay[o%1:qrI)Su1#*CAA o&BiAqo' +BiYr<q)r )<&AY,[$o)!:,Y,r()$)Su1#*CH!A8o*4BiH!@Qo+

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