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https://opencores.org/ocsvn/tsv/tsv/trunk
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/tsv/trunk/test/T001.TSV
0,0 → 1,8
module mkExample (Empty); |
//Reg#(Bit#(8)) r <- mkReg(?); // don't-care is used for the |
//Reg#(Bit#(8)) r1<- mkReg(8'h33); |
Reg#(Bit#(8)) r2<- mkReg(~0); |
rule every( True ); // reset value of the Reg |
$display("value is %h", r); // the value of r is displayed |
endrule |
endmodule |