Subversion Repositories utosnet

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.v

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.ngc

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.gise

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.xise

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.sym

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.veo

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.xco

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.asy

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.vho

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.ise

utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/ipcore_dir/dataRegister.vhd (revision 3) @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRegister.vhd when simulating +-- the core, dataRegister. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY dataRegister IS + port ( + clka: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(5 downto 0); + dina: IN std_logic_VECTOR(31 downto 0); + douta: OUT std_logic_VECTOR(31 downto 0); + clkb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(5 downto 0); + dinb: IN std_logic_VECTOR(31 downto 0); + doutb: OUT std_logic_VECTOR(31 downto 0)); +END dataRegister; + +ARCHITECTURE dataRegister_a OF dataRegister IS +-- synthesis translate_off +component wrapped_dataRegister + port ( + clka: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(5 downto 0); + dina: IN std_logic_VECTOR(31 downto 0); + douta: OUT std_logic_VECTOR(31 downto 0); + clkb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(5 downto 0); + dinb: IN std_logic_VECTOR(31 downto 0); + doutb: OUT std_logic_VECTOR(31 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRegister use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 2, + c_rstram_b => 0, + c_rstram_a => 0, + c_has_injecterr => 0, + c_rst_type => "SYNC", + c_prim_type => 1, + c_read_width_b => 32, + c_initb_val => "0", + c_family => "spartan3", + c_read_width_a => 32, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_has_mem_output_regs_a => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_write_depth_b => 64, + c_write_depth_a => 64, + c_has_rstb => 0, + c_has_rsta => 0, + c_has_mux_output_regs_b => 0, + c_inita_val => "0", + c_has_mux_output_regs_a => 0, + c_addra_width => 6, + c_addrb_width => 6, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 32, + c_write_width_a => 32, + c_read_depth_b => 64, + c_read_depth_a => 64, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_rst_priority_b => "CE", + c_rst_priority_a => "CE", + c_use_default_data => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_dataRegister + port map ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb); +-- synthesis translate_on + +END dataRegister_a; + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/top.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/top.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/top.vhd (revision 3) @@ -0,0 +1,111 @@ +---------------------------------------------------------------------------------- +-- Company: University of Southern Denmark +-- Engineer: Simon Falsig +-- +-- Create Date: 19/03/2010 +-- Design Name: uTosNet_spi Example +-- Module Name: top - Behavioral +-- Project Name: uTosNet +-- Target Devices: SDU XC3S50AN Board +-- Tool versions: Xilinx ISE 11.4 +-- Description: This is a simple example showing the use of the uTosNet_spi +-- module. +-- +-- Revision: +-- Revision 0.10 - Initial release +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity top is +Port ( CLK_50M_I : in STD_LOGIC; + LEDS_O : out STD_LOGIC_VECTOR(2 downto 0); + SPI_MISO_O : out STD_LOGIC; + SPI_MOSI_I : in STD_LOGIC; + SPI_EN_I : in STD_LOGIC; + SPI_CLK_I : in STD_LOGIC); +end top; + +architecture Behavioral of top is + + component uTosNet_spi is + Port ( clk_50M : in STD_LOGIC; + spi_miso : out STD_LOGIC; + spi_mosi : in STD_LOGIC; + spi_clk : in STD_LOGIC; + spi_en : in STD_LOGIC; + dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0); + dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0); + dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0); + dataReg_clk : in STD_LOGIC; + dataReg_writeEnable : in STD_LOGIC); + end component; + + type STATES is (IDLE, SETUP, CLK, DONE); + + signal state : STATES := IDLE; + signal nextState : STATES := IDLE; + + signal dataReg_addr : STD_LOGIC_VECTOR(5 downto 0); + signal dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0); + signal dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0); + signal dataReg_clk : STD_LOGIC; + signal dataReg_we : STD_LOGIC; +begin + + uTosNet_spiInst : uTosNet_spi + Port map ( clk_50M => CLK_50M_I, + spi_miso => SPI_MISO_O, + spi_mosi => SPI_MOSI_I, + spi_en => SPI_EN_I, + spi_clk => SPI_CLK_I, + dataReg_addr => dataReg_addr, + dataReg_dataIn => dataReg_dataIn, + dataReg_dataOut => dataReg_dataOut, + dataReg_clk => dataReg_clk, + dataReg_writeEnable => dataReg_we); + + process(CLK_50M_I) + begin + if(CLK_50M_I = '1' and CLK_50M_I'event) then + state <= nextState; + + case state is + when IDLE => + when SETUP => + dataReg_addr <= "000000"; + dataReg_clk <= '0'; + dataReg_we <= '0'; + when CLK => + dataReg_clk <= '1'; + when DONE => + LEDS_O <= dataReg_dataOut(2 downto 0); + end case; + end if; + end process; + + process(state) + begin + case state is + when IDLE => + nextState <= SETUP; + when SETUP => + nextState <= CLK; + when CLK => + nextState <= DONE; + when DONE => + nextState <= IDLE; + end case; + end process; + + +end Behavioral; + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.xise =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.xise (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.xise (revision 3) @@ -0,0 +1,70 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi_xc3s50an.ucf =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi_xc3s50an.ucf (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi_xc3s50an.ucf (revision 3) @@ -0,0 +1,16 @@ +NET "CLK_50M_I" LOC = P124; +NET "CLK_50M_I" IOSTANDARD = LVTTL; +NET "LEDS_O[0]" LOC = P10; +NET "LEDS_O[0]" IOSTANDARD = LVTTL; +NET "LEDS_O[1]" LOC = P12; +NET "LEDS_O[1]" IOSTANDARD = LVTTL; +NET "LEDS_O[2]" LOC = P13; +NET "LEDS_O[2]" IOSTANDARD = LVTTL; +NET "SPI_MISO_O" LOC = P16; +NET "SPI_MISO_O" IOSTANDARD = LVTTL; +NET "SPI_MOSI_I" LOC = P15; +NET "SPI_MOSI_I" IOSTANDARD = LVTTL; +NET "SPI_CLK_I" LOC = P18; +NET "SPI_CLK_I" IOSTANDARD = LVTTL; +NET "SPI_EN_I" LOC = P19; +NET "SPI_EN_I" IOSTANDARD = LVTTL; Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_spi/uTosNet_spi.vhd (revision 3) @@ -0,0 +1,174 @@ +---------------------------------------------------------------------------------- +-- Company: University of Southern Denmark +-- Engineer: Simon Falsig +-- +-- Create Date: 19/3/2010 +-- Design Name: uTosNet +-- Module Name: uTosNet_spi - Behavioral +-- Project Name: uTosNet +-- Target Devices: SDU XC3S50AN Board +-- Tool versions: Xilinx ISE 11.4 +-- Description: PseudoTosNet is designed to provide an interface similar to +-- the full-blown TosNet core, but usable on the SDU XC3S50AN +-- Board. It features a SPI module which is made for use in +-- conjunction with a Digi Connect ME 9210 with the Generic +-- TosNet Masternode application. By using this combination, it +-- is possible to access the blockram from any Ethernet-enabled +-- device. +-- +-- Revision: +-- Revision 0.10 - Initial release +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity uTosNet_spi is +Port ( clk_50M : in STD_LOGIC; + spi_miso : out STD_LOGIC; + spi_mosi : in STD_LOGIC; + spi_clk : in STD_LOGIC; + spi_en : in STD_LOGIC; + dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0); + dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0); + dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0); + dataReg_clk : in STD_LOGIC; + dataReg_writeEnable : in STD_LOGIC); +end uTosNet_spi; + +architecture Behavioral of uTosNet_spi is + + component dataRegister + Port ( clka : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR(0 downto 0); + addra : in STD_LOGIC_VECTOR(5 downto 0); + dina : in STD_LOGIC_VECTOR(31 downto 0); + douta : out STD_LOGIC_VECTOR(31 downto 0); + clkb : in STD_LOGIC; + web : in STD_LOGIC_VECTOR(0 downto 0); + addrb : in STD_LOGIC_VECTOR(5 downto 0); + dinb : in STD_LOGIC_VECTOR(31 downto 0); + doutb : out STD_LOGIC_VECTOR(31 downto 0)); + end component; + + signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0); + signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0); + signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0); + signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0); + signal int_dataReg_clk : STD_LOGIC; + + signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0); + + signal readData : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + signal writeAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal readAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal doWrite : STD_LOGIC := '0'; + signal doRead : STD_LOGIC := '0'; + + signal int_spi_mosi : STD_LOGIC; + signal int_spi_clk : STD_LOGIC; + signal int_spi_en : STD_LOGIC; + signal last_spi_clk : STD_LOGIC; + + signal dataInBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + signal dataOutBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1'); + + signal bitCounter : STD_LOGIC_VECTOR(6 downto 0) := (others => '0'); + +begin + + dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:) + + dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister + Port map ( clka => dataReg_clk, --PortA is used for the user application + wea => dataReg_writeEnable_V, -- + addra => dataReg_addr, -- + dina => dataReg_dataIn, -- + douta => dataReg_dataOut, -- + clkb => int_dataReg_clk, --PortB is used for the SPI interface + web => int_dataReg_we, -- + addrb => int_dataReg_addr, -- + dinb => int_dataReg_dataIn, -- + doutb => int_dataReg_dataOut); -- + + --Synchronize inputs + process(clk_50M) + begin + if(clk_50M = '0' and clk_50M'event) then + int_spi_mosi <= spi_mosi; + int_spi_clk <= spi_clk; + int_spi_en <= spi_en; + end if; + end process; + + --SPI Process + process(clk_50M) + begin + if(clk_50M = '1' and clk_50M'event) then + last_spi_clk <= int_spi_clk; --Save current value to use for manual edge triggering + + if(int_spi_en = '1') then --SPI is not enabled (spi_en is active low) + bitCounter <= (others => '0'); --Reset the bitcounter + + if((doWrite = '1') and (int_dataReg_we = "0")) then --If a write was requested in the previously received command, + int_dataReg_addr <= writeAddress; -- then prepare it, + int_dataReg_dataIn <= dataInBuffer; -- the data to write are those left in the input buffer, + int_dataReg_we <= "1"; -- + int_dataReg_clk <= '0'; -- + elsif((doWrite = '1') and (int_dataReg_clk = '0')) then -- + int_dataReg_clk <= '1'; -- and perform it by pulling the dataReg clock high + doWrite <= '0'; --Write is done + else --If there aren't any writes to perform, + int_dataReg_clk <= '0'; -- just clear the various signals + int_dataReg_we <= "0"; -- + doRead <= '0'; -- + doWrite <= '0'; -- + end if; + else --SPI is enabled + if(int_spi_clk = '0' and last_spi_clk = '1') then --Falling edge on spi_clk + dataInBuffer <= dataInBuffer(30 downto 0) & int_spi_mosi; --Read next received bit into the input buffer, + bitCounter <= bitCounter + 1; -- and increment the bitcounter + elsif(int_spi_clk = '1' and last_spi_clk = '0') then --Rising edge on spi_clk + spi_miso <= dataOutBuffer(31); --Write out the next bit from the output buffer, + dataOutBuffer <= dataOutBuffer(30 downto 0) & '0'; -- and left-shift the buffer + end if; + + case bitCounter is --Parse the command + when "0000101" => --Bit 27 (the 5th read bit), + doRead <= dataInBuffer(0); -- contains the 'doRead' flag + when "0010000" => --Bits 16-25 (available when 16 bits have been read), + readAddress <= dataInBuffer(5 downto 0); -- contain the address to read from + when "0010001" => --Bit 15 (the 17th read bit), + int_dataReg_addr <= readAddress; -- doesn't contain anything useful, but we can easily use the timeslot for reading from the dataregister + int_dataReg_we <= "0"; -- + int_dataReg_clk <= '0'; -- + when "0010010" => --Bit 14 (the 18th read bit), + int_dataReg_clk <= '1'; -- still nothing, now performing the read by pulling the dataregister clock high + when "0010011" => --Bit 13 (the 19th read bit), + int_dataReg_clk <= '0'; -- the read is finished, + readData <= int_dataReg_dataOut; -- and the read value is stored + when "0010101" => --Bit 11 (the 21st read bit), + doWrite <= dataInBuffer(0); -- contains the 'doWrite' flag + when "0011111" => --Bit 1 (the 31st read bit), + if(doRead = '1') then -- we're not using this bit for anything right now, but we need to put the previously read data value into the output buffer now + dataOutBuffer <= readData; -- + else --If a read was not requested, + dataOutBuffer <= (others => '0'); -- the output buffer is just filled with zeros instead + end if; + when "0100000" => --Bits 9-0 (available when 32 bits have been read), + writeAddress <= dataInBuffer(5 downto 0); -- contain the address to write to + when others => --Other bit positions are ignored + end case; + end if; + + end if; + end process; + +end Behavioral; Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.v =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.v (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.v (revision 3) @@ -0,0 +1,148 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file dataRegister.v when simulating +// the core, dataRegister. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module dataRegister( + clka, + wea, + addra, + dina, + douta, + clkb, + web, + addrb, + dinb, + doutb); + + +input clka; +input [0 : 0] wea; +input [5 : 0] addra; +input [31 : 0] dina; +output [31 : 0] douta; +input clkb; +input [0 : 0] web; +input [5 : 0] addrb; +input [31 : 0] dinb; +output [31 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V3_3 #( + .C_ADDRA_WIDTH(6), + .C_ADDRB_WIDTH(6), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(2), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(64), + .C_READ_DEPTH_B(64), + .C_READ_WIDTH_A(32), + .C_READ_WIDTH_B(32), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(1), + .C_USE_ECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(64), + .C_WRITE_DEPTH_B(64), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(32), + .C_WRITE_WIDTH_B(32), + .C_XDEVICEFAMILY("spartan3a")) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .CLKB(clkb), + .WEB(web), + .ADDRB(addrb), + .DINB(dinb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .RSTB(), + .ENB(), + .REGCEB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of dataRegister is "black_box" + +endmodule + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ncf =================================================================== Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.gise =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.gise (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.gise (revision 3) @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ngc =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ngc (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ngc (revision 3) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$20;41<,[o}e~g`n;"2*776&=$:;-*6;123456789>;7=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<>5>.137?42=AGZ^X7OKDSC?56<768>0=94FNQWW>DBCZK6:?7>11192>LHW]]0|il2?:1<24>7=AGZ^X7yjb=294;753:81EC^ZT;FJE956294:>6==:HLSQQ112906?OIX\^1hd`n<2394;743:81EC^ZT;fjjg:493:5=>5<2;MVPUSS2MEJ0>?50?30?64=G\^[YY4KOC>05?699<18>7AZTQWW>air|h68=7>114906?IR\Y__6iaztc>05?69m29x9=oatpe201+3981?6D@_UU8GMUG;;3:5=<5;:HLSQQ11197>LHW]]0\IL2<:1<24>2=AGZ^X7YJB=194;753=0DYY^ZT;FLTD:4294:>6:5OTVSQQ11395>LHW]]0jhi|n<483:44<>3CE\XZ5aefqf93=87;<7;4@UURVP?tcimnyinm35;2=<>GCL[K7<374AEFQE977601JHI\N<03==>GCL[K7=?0m;@FGVD:6;3:556OKDSC?568?3HNO^L2>>99B@ATF4;437LJKR@>0:==FLMXJ0907;@FGVD:2611JHI\N<7<;?DBCZH6<255NDEPB8=8?3HNO^L26>99B@ATE49427LJKRC>24;?>89B@ATE4885n6OKDS@?56<7601JHI\M<01=<>GCL[H7=364AEFQF94902KOH_L33?:8EABUJ5>546OKDS@?1;>GCL[H753=4AMN0?GS502H^_RGAFN31?FNBKBUGENKASD]W]UC33JF@M95LLJ@:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_IIm4D@VB[ROC\AUJo6JNT@]TMAROWK<0HDO30?58@LG;994<7IGN<03=3>BNI5;92:5KI@>27;169GMD:6?7=0HDO319<4?AOF4835:6JFA=3=3>BNI58;2:5KI@>15;1?08;EKB8759?2NBM1<;>69GMD:5=7=0HDO327<4?AOF4;=5;6JFA=0;:2=CAH695384DHC?6;14=7IGN<9<5?AOF404=7IGM<1<4?AOE48:5;6JFB=32:2=CAK6:>394DH@?56803MCI0<:17:FJF9726>1OEO2>6?58@LD;9>4<7IGM<0:=3>BNJ5;22;5KIC>2:2=CAK69<394DH@?64803MCI0?<17:FJF9446>1OEO2=4?58@LD;:<4<7IGM<34=3>BNJ58<2:5KIC>1<;1409;EKA87803MCI0>>19:FJF956294<7IGM<23=2>BNJ595:6JFB=6=2>BNJ5?5:6JFB=4=2>BNJ5=5:6JFB=:=2>BNJ535;6JFP@>3:2=CAYK7=394DHRB878>3MC[M1=50?58@LVF4:4<7IG_B=2=3>BNXK6:2:5KIQ@?6;?4?>69GMUD;;7<0HBO30?58@JG;994<7IAN<03=3>BHI5;92:5KO@>27;169GKD:6?7=0HBO319<4?AIF4835:6J@A=3=3>BHI58;2:5KO@>15;1?08;EMB8759?2NDM1<;>69GKD:5=7=0HBO327<4?AIF4;=5;6J@A=0;:2=CGH695384DNC?6;14=7IAN<9<5?AIF404=7IAM<1<4?AIE48:5;6J@B=32:2=CGK6:>394DN@?56803MEI0<:17:FLF9726>1OCO2>6?58@JD;9>4<7IAM<0:=3>BHJ5;22;5KOC>2:2=CGK69<394DN@?64803MEI0?<17:FLF9446>1OCO2=4?58@JD;:<4<7IAM<34=3>BHJ58<2:5KOC>1<;1409;EMA87803MEI0>>19:FLF956294<7IAM<23=2>BHJ595:6J@B=6=2>BHJ5?5:6J@B=4=2>BHJ5=5:6J@B=:=2>BHJ535;6J@P@>3:2=CGYK7=394DNRB878>3ME[M1=50?58@JVF4:4<7IA_B=2=3>BHXK6:2:5KOQ@?6;?4?>69GKUD;;790ICO<;DLA5>A43NDO46GAIUR\45>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<;6GAIU]342=NF@^T<<94IOKW[5403@DBXR><7:KMMQY7<>1BBDZP0458MKOSW9<<7D@FT^243>OIA]U;4:5FNHV\4<11BBDZP1458MKOSW8<<7D@FT^343>OIA]U:4:5FNHV\5<1C69JJLRX9M=0ECG[_0G4?LHN\V;M;6GAIU]142=NF@^T><94IOKW[7403@DBXR<<7:KMMQY5<>1BBDZP2458MKOSW;<<7D@FT^043>OIA]U94:5FNHV\6<11BBDZP3458MKOSW:<<7D@FT^143>OIA]U84:5FNHV\7<1O8;HLJPZ5E?2CEEYQOIA]UI:6B@AEGG3>JHO@IJ@n5BakmqR`ttafdh7@gaosTfvvohf;1E=>5A1168J467<2D:<<:4N0210>H68:>0B<>;4:L24020668J46?<2D:<4=4N037?K768=1E=459M54333G;::95A1057?K760=1E=<7<;O310>H6:9>0B<<>4:L26722568J442<2D:>;:4N0040>H6:1>0B<<63:L271=I9::?7C?<159M56433G;8?95A1267?K74==1E=>8;;O3031=I9:2?7C?<929M512;86@>4068J425<2D:8>:4N0670>H6<<>0B<:94:L2022386@>4818J4333G;><95A1430?K71;2D:;>5A1918J4?53G887CH5=:1E>;=4N350?K4?;2D95>5A3118J6743G99?6@<329M7157<;O637>H39:1E8?=4N510?K23;2D?9>5A4718J1143G>3?6@;929M155H2?:1E95=4N4;1?K043G<;?6@9129M275?90B;9<;O4;7>H11;1E;>5A7118J2743G=9?6@8329M315?87C993:L437=I0:1E4<=4N900?K>4;2D38>5A8418J=043G2<;O;27>H>::1E5>=4N860?K?2;2D2:>5A9618J<>43G32j6@M_CWPTLHXX[E[_:5AEUULVN45YCB;8RLCPW]S[I;5XE@>3:3=PMH6:2;5XE@>1:==PMH686=09;VGB86813^OI0=09;VGA84813^OI0?07;VGA86<76?1\IO2<>c9TVLRBWOCY_Ym4WSKWAZKHLLUJo6Y]IUG\IJBBWK;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@<0T^ZCIC58\VRXOGN<7U][_WA@f>^XKFXNSD@IO79[`gYNlo1SheQ_rhoUawungg;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaa159\gb)ci}kYijg|tdp-jbi?3hno~l&?)99b`atf 8#37ljkr`*1-==flmxj$>'7;`fgvd.3!11jhi|n(4+;?dbczh6;255ndepb848?3hno~l2=>99b`atf4:437ljkr`>7:d=flmxj084?>99b`atf4<437ljkrc*3-==flmxi$<'7;`fgvg.5!11jhi|m(2+;?dbczk"?%55ndepa,0/?3hno~o2?>99b`ate48437ljkrc>1:==flmxi0>07;`fgvg:36h1jhi|m<483:==flmxi080=c:`ooZkbeVmnbRx<_2.#\ljnfq*HC_K/Gdlfvdrhz);:">:4cmib0>ekcki0hlznRdejwqcu:>1omyo]efkpp`t+jeaTahcPgdl\r6Y4$GEEI!@@ND1a6>bf|hXnkd}{es.ahnYjmdUlicQy3^1/fYoizUyijmjb<2/gZnf{Vxnknkn=1.`[hcjW}s{i0<#c^pppwgjWk7; nQ}supbiZg:8%iT~~zPtxrf9V_IK%iTdl}Piohfgqcuz4:'oR~}il]w}uc:9%iTecg{b^tbh86+kVxnmiQxievk[g;4:%iT~hok_vkgpmYf5:8'oRjfs``oaZqfzgUid{Qlomn>4)eXagcSkgce^lbi`;igVidiRhfld]okdbbl%iT{g{e^ol``Ye5^XBXHQIISQW(fYpz`~nS`ake^c>SWOSMVLB^^Z#c^ov|ZvnxlfbbhQ|t`efw86+kVbjRcjm^mvpussW{olRl20-a\hjgcW`dbxRhfld?3(fYoizUfi`Q`uurvpZtbozUj1="l_vpjp`Ycmy~cSo394-a\swosmVnn|yfPa<47(fYoizUyyl20-a\lduXzz~j1="l_hljpdYqie7; nQgar]nq}Yh}}z~xR|jgr]a95*dWakxS`{w_nwwtprXzlmxSl3?,b]b`atfW~coxe39,b]b`ateW~coxe39,b]gacgrd}Uomyo20-a\qvcXmji65)eX`hyTicl20-a\lduXmgk6&7:fjjd.6!11oeco'11+;?aoii!;:%55kioc+57/?3mcem%?<)99gmkg/9=#37igaa)36-==cagk#=;'7;ekme-70!11oeco'19+;?aoii!;2%:5kioc+6,>&8:fjjd.59 20hd`n(30*<>bnfh"9?$64dhlb,72.02nbbl&=5(:8`lhf ;<"46jfn`*13,>1oeco'6(58`lhf >#<7igaa):*3>bnfh"2%:5kioc?4;>18:fjjd:69720hd`n<00=<>bnfh6:?364dhlb842902nbbl2>5?:8`lhf48<546jfn`>23;>99gmkg;::437igaa=07:==cagk7>807;ekme941611oeco326<;?aoii583255kioc?6<803mcem1<18:fjjd:487k0hd`n<2394;>?17:fjjd:46>1oeco34?58`lhf4<4<7igaa=4=3>bnfh6<2:5kioc?<;1)99gmkd/99#37igab)32-==cagh#=?'7;ekmf-74!11oecl'15+;?aoij!;>%55kio`+53/?3mcen%?8)99gmkd/91#37igab)3:-2=cagh#>$64dhla,76.02nbbo&=1(:8`lhe ;8"46jfnc*17,>bnfk"9;$64dhla,7>.02nbbo&=9(58`lhe :#37igab)13-==cagh#?<'8;ekmf-2.?2nbbo&:)69gmkd/> =0hd`m(6+4?aoij!2";6jfnc*:-2=cagh7<364dhla846902nbbo2>1?:8`lhe488546jfnc>27;>bnfk6:;364dhla84>902nbbo2>9?58`lhe48437igab=03:==cagh7><07;ekmf945611oecl322<;?aoij58?255kio`?608?3mcen1<9>99gmkd;:>437igab=0;:==cagh7>408;ekmf94902nbbo2<0?c8`lhe4:;1<364dhla8679?2nbbo2<>69gmkd;<7=0hd`m<4<4?aoij5<5;6jfnc>4:2=cagh74394dhla8<8?3me~xl&?)99gkprf 8#27iazt`*24,?)89gkprf 88"56j`uuc+56/>3me~xl&>4(;8`jssi!;>%45kotvb,40.12ndyyo'16+:?air|h":4$74dnwwe-7>!11ocxzn(3+:?air|h"9<$74dnwwe-46!01ocxzn(30*=>bh}}k#>>'6;emvpd.5< 30hb{{a)06-<=cg|~j$?8&9:flqqg/:>#27iazt`*1<,?)99gkprf =#37iazt`*6-==cg|~j$;'7;emvpd.0!11ocxzn(9+;?air|h"2%55kotvb858>3me~xl2>0?;8`jssi5;:245kotvb844912ndyyo312<:?air|h6:8374dnwwe972601ocxzn<04==>bh}}k7=:06;emvpd:60730hb{{a=3::==cg|~j0<06;emvpd:58730hb{{a=02:<=cg|~j0?<19:flqqg;::427iazt`>10;?89gkprf4;<556j`uuc?628>3me~xl2=8?;8`jssi582255kotvb878>3me~xl2<0?`8`jssi59:6=06;emvpd:49720hb{{a=1=<>bh}}k78364dnwwe93902ndyyo36?:8`jssi5=546j`uuc?<;>bh}}h#=='6;emvpg.69 30hb{{b)31-<=cg|~i$<=&9:flqqd/9=#27iaztc*21,?3me~xo&=1(;8`jssj!89%45kotva,75.12ndyyl'25+:?air|k"99$74dnwwf-41!01ocxzm(35*=>bh}}h#>5'6;emvpg.51 20hb{{b)1*=>bh}}h#?='6;emvpg.49 20hb{{b)6*<>bh}}h#9$64dnwwf-0.02ndyyl'7(:8`jssj!2"46j`uu`+=,>19:flqqd;99427iaztc>25;?89gkpre489556j`uu`?518>3me~xo2>5?;8`jssj5;=245kotva841912ndyyl319<:?air|k6:5364dnwwf97912ndyyl321<:?air|k69=374dnwwf945601ocxzm<31==>bh}}h7>906;emvpg:5=730hb{{b=05:<=cg|~i0?919:flqqd;:1427iaztc>1=;>05?6912ndyyl330<;?air|k68255kotva818?3me~xo2:>99gkpre4?437iaztc>4:==cg|~i0507;emvpg:>611nhdh=nff0?`hf;2oeni5fnkg`padn|lxyh6gajdawwgosm{x37cilbtko`f=ulhno~hml(1+`?wbflmxnon&>)b9q`dbczlih$?'l;sfb`atbkj"8%n5}d`fgv`ed =#h7jndepfgf.2!j1yhljkrda`858b3{njhi|jcb>6>5813{oloho9;sgdg`d33{ym95}su`4?vdn|lxy:6yja)2*<>qbi5:1<384wdc?4;0<lh#<$64wd`?4?69>2}nn1>1}ABs7g54>33;3``<5;?=mwc?j6;38j4c02<1/=h:51ed8yV5b2::m6>4>33;3``<5;?=m7^?=9;120?6=9:82U4m39:87>5120:4ac=::<3<6j=0783>4<6sZ>;6>>i:28277?7ll09?;9i;wV2g2<7280:644>ke;0022`<,8n:6<{#9j81==5m21494??72:02cg9Y7dc!7d<399?6`>c283?>o4:<0;6)?l4;112>h6k:0;76g>ed83>!7d<3;m86`>c283?>o6mm0;6)?l4;3e0>h6k:0:76g>eb83>!7d<3;m86`>c281?>o6mk0;6)?l4;3e0>h6k:0876g>e`83>!7d<3;m86`>c287?>o6m00;6)?l4;3e0>h6k:0>76g>fc83>!7d<38;=6`>c283?>o6nh0;6)?l4;035>h6k:0:76g>f883>!7d<38;=6`>c281?>o6n10;6)?l4;035>h6k:0876g>f683>!7d<38;=6`>c287?>o6n?0;6)?l4;035>h6k:0>76a=a783>!7d<38h96`>c283?>i5i<0;6)?l4;0`1>h6k:0:76a=a283>!7d<38h96`>c281?>i5i;0;6)?l4;0`1>h6k:0876a=a083>!7d<38h96`>c287?>i5i90;6)?l4;0`1>h6k:0>76a=9g83>!7d<38h96`>c285?>i51l0;6)?l4;0`1>h6k:0<76a=9e83>!7d<38h96`>c28;?>i51j0;6)?l4;0`1>h6k:0276a=9c83>!7d<38h96`>c28b?>i51h0;6)?l4;0`1>h6k:0i76a=9983>!7d<38h96`>c28`?>i51>0;6)?l4;0`1>h6k:0o76a=9783>!7d<38h96`>c28f?>i51<0;6)?l4;0`1>h6k:0m76a=9583>!7d<38h96`>c2824>=h:091<7*>c581g0=i9j91=<54o3;1>5<#9j>1>n;4n0a0>44<3f82=7>5$0a7>7e23g;h?7?<;:m1=5<72-;h875h50;&2g1<5k<1e=n=51498k7gd290/=n:52b78j4e428<07b7c?l3;34?>i5ih0;6)?l4;0`1>h6k:0:465`2`;94?"6k=09o85a1b195<=4>c:9l6!7d<39;:6`>c283?>i5m?0;6)?l4;132>h6k:0:76a=e583>!7d<39;:6`>c281?>i5m:0;6)?l4;132>h6k:0876a=e383>!7d<39;:6`>c287?>i5m80;6)?l4;132>h6k:0>76a=e183>!7d<39;:6`>c285?>i5lo0;6)?l4;132>h6k:0<76a=dd83>!7d<39;:6`>c28;?>i5lm0;6)?l4;132>h6k:0276a=db83>!7d<39;:6`>c28b?>i5lk0;6)?l4;132>h6k:0i76a=d883>!7d<39;:6`>c28`?>i5l10;6)?l4;132>h6k:0o76a=d683>!7d<39;:6`>c28f?>i5l?0;6)?l4;132>h6k:0m76a=d483>!7d<39;:6`>c2824>=h:m>1<7*>c58043=i9j91=<54o3f0>5<#9j>1?=84n0a0>44<3f8o>7>5$0a7>6613g;h?7?<;:m1`4<72-;h87=?6:l2g6<6<21d>i>50;&2g1<48?1e=n=51498k7cc290/=n:53148j4e428<07bi5mk0;6)?l4;132>h6k:0:465`2dc94?"6k=08<;5a1b195<=>9;o3`7?7e32e9i84?:%3`0?57>2d:o>4>c:9l6ag=83.:o94<079m5f5=9m10c?mi:18'5f2=;9<0b>o58<0;66g=2583>!7d<38??6`>c283?>o5::0;6)?l4;077>h6k:0:76g=2083>!7d<38??6`>c281?>o5:90;6)?l4;077>h6k:0876g=1g83>!7d<38??6`>c287?>o59l0;6)?l4;077>h6k:0>76g=1e83>!7d<38??6`>c285?>o59j0;6)?l4;077>h6k:0<76g=1c83>!7d<38??6`>c28;?>o59h0;6)?l4;077>h6k:0276g=1883>!7d<38??6`>c28b?>o5910;6)?l4;077>h6k:0i76g=1783>!7d<38??6`>c28`?>o59<0;6)?l4;077>h6k:0o76g=1583>!7d<38??6`>c28f?>o59:0;6)?l4;077>h6k:0m76g=1383>!7d<38??6`>c2824>=n:8;1<7*>c58106=i9j91=<54i333>5<#9j>1>9=4n0a0>44<3`8;j7>5$0a7>7243g;h?7?<;:k14`<72-;h87<;3:l2g6<6<21b>=j50;&2g1<5<:1e=n=51498m74f290/=n:52518j4e428<07d<=9;29 4e32;>87c?l3;34?>o5:10;6)?l4;077>h6k:0:465f23594?"6k=098>5a1b195<=?4?:%3`0?43;2d:o>4>c:9j641=83.:o94=429m5f5=9m10e?>l:18'5f2=:=90b!7d<38386`>c283?>o5>=0;6)?l4;0;0>h6k:0:76g=6383>!7d<38386`>c281?>o5>80;6)?l4;0;0>h6k:0876g=6183>!7d<38386`>c287?>o5=o0;6)?l4;0;0>h6k:0>76g=5d83>!7d<38386`>c285?>o5=m0;6)?l4;0;0>h6k:0<76g=5b83>!7d<38386`>c28;?>o5=k0;6)?l4;0;0>h6k:0276g=5`83>!7d<38386`>c28b?>o5=00;6)?l4;0;0>h6k:0i76g=5683>!7d<38386`>c28`?>o5=?0;6)?l4;0;0>h6k:0o76g=5483>!7d<38386`>c28f?>o5==0;6)?l4;0;0>h6k:0m76g=5283>!7d<38386`>c2824>=n:<81<7*>c581<1=i9j91=<54i372>5<#9j>1>5:4n0a0>44<3`8><7>5$0a7>7>33g;h?7?<;:k10c<72-;h87<74:l2g6<6<21b>9k50;&2g1<50=1e=n=51498m70e290/=n:52968j4e428<07d<9a;29 4e32;2?7c?l3;34?>o5>00;6)?l4;0;0>h6k:0:465f27:94?"6k=09495a1b195<=4?:%3`0?4?<2d:o>4>c:9j60>=83.:o94=859m5f5=9m10e?:k:18'5f2=:1>0bd183>4<729qC=nh4$0a`>4b73f;h=7>5;|`ga?6=93:1cg9'5fe=ll1dhi4?::a7<<72h:1?77={I3`b>\4i3;9w<756;5952<603o1j7o5b;3:>`g6;%1a>7603-9m6?>7;%3aa?7d82c8=>4?::m05d<72-;h87=>c:l2g6<732e8=44?:%3`0?56k2d:o>4>;:m05=<72-;h87=>c:l2g6<532e8=:4?:%3`0?56k2d:o>4<;:m053<72-;h87=>c:l2g6<332e8=84?:%3`0?56k2d:o>4:;:k055<722c8=<4?::k05a<722c8=h4?::k067<72-;h87==3:l2g6<732c8>84?:%3`0?55>2d:o>4?;:k2a`<72-;h87?i4:l2g6<732c:ii4?:%3`0?7a<2d:o>4>;:k2af<72-;h87?i4:l2g6<532c:io4?:%3`0?7a<2d:o>4<;:k2ad<72-;h87?i4:l2g6<332c:i44?:%3`0?7a<2d:o>4:;:k2bg<72-;h874>;:k2b<<72-;h874<;:k2b2<72-;h874:;:k05c<722c8>=4?::m064<722e9m;4?:%3`0?4d=2d:o>4?;:m1e0<72-;h874?:%3`0?4d=2d:o>4=;:m1e7<72-;h874;;:m1e5<72-;h8749;:m1=`<72-;h8747;:m1=f<72-;h8732e95o4?:%3`0?4d=2d:o>4n;:m1=d<72-;h874l;:m1=2<72-;h874j;:m1=0<72-;h874>0:9l6<5=83.:o94=c49m5f5=9810c?7=:18'5f2=:j?0b93:1(!7d<38h96`>c2820>=h:1l1<7*>c581g0=i9j91=854o3c`>5<#9j>1>n;4n0a0>40<3f8jn7>5$0a7>7e23g;h?7?8;:m1ed<72-;h87l750;&2g1<5k<1e=n=51898k7g?290/=n:52b78j4e428k07b7c?l3;3a?>i5i=0;6)?l4;0`1>h6k:0:o65`28;94?"6k=09o85a1b195a=2d:o>4?;:m1a3<72-;h87=?6:l2g6<632e9i94?:%3`0?57>2d:o>4=;:m1a6<72-;h87=?6:l2g6<432e9i?4?:%3`0?57>2d:o>4;;:m1a4<72-;h87=?6:l2g6<232e9i=4?:%3`0?57>2d:o>49;:m1`c<72-;h87=?6:l2g6<032e9hh4?:%3`0?57>2d:o>47;:m1`a<72-;h87=?6:l2g6<>32e9hn4?:%3`0?57>2d:o>4n;:m1`g<72-;h87=?6:l2g62d:o>4l;:m1`=<72-;h87=?6:l2g62d:o>4j;:m1`3<72-;h87=?6:l2g62d:o>4>0:9l6a2=83.:o94<079m5f5=9810c?j<:18'5f2=;9<0b!7d<39;:6`>c2820>=h:m:1<7*>c58043=i9j91=854o3gg>5<#9j>1?=84n0a0>40<3f8no7>5$0a7>6613g;h?7?8;:m1ag<72-;h87=?6:l2g6<6021d>ho50;&2g1<48?1e=n=51898k7c>290/=n:53148j4e428k07bi5m<0;6)?l4;132>h6k:0:o65`2ec94?"6k=08<;5a1b195a=>9;o3`7?7a32c9<94?::k140<722c9>94?:%3`0?43;2d:o>4?;:k166<72-;h87<;3:l2g6<632c9><4?:%3`0?43;2d:o>4=;:k165<72-;h87<;3:l2g6<432c9=k4?:%3`0?43;2d:o>4;;:k15`<72-;h87<;3:l2g6<232c9=i4?:%3`0?43;2d:o>49;:k15f<72-;h87<;3:l2g6<032c9=o4?:%3`0?43;2d:o>47;:k15d<72-;h87<;3:l2g6<>32c9=44?:%3`0?43;2d:o>4n;:k15=<72-;h87<;3:l2g64l;:k150<72-;h87<;3:l2g64j;:k156<72-;h87<;3:l2g64>0:9j647=83.:o94=429m5f5=9810e???:18'5f2=:=90b!7d<38??6`>c2820>=n:9n1<7*>c58106=i9j91=854i30b>5<#9j>1>9=4n0a0>40<3`8957>5$0a7>7243g;h?7?8;:k16=<72-;h87<;3:l2g6<6021b>?950;&2g1<5<:1e=n=51898m741290/=n:52518j4e428k07d<=5;29 4e32;>87c?l3;3a?>o5:;0;6)?l4;077>h6k:0:o65f20594?"6k=098>5a1b195a=4?;:k121<72-;h87<74:l2g6<632c9:?4?:%3`0?4?<2d:o>4=;:k124<72-;h87<74:l2g6<432c9:=4?:%3`0?4?<2d:o>4;;:k11c<72-;h87<74:l2g6<232c99h4?:%3`0?4?<2d:o>49;:k11a<72-;h87<74:l2g6<032c99n4?:%3`0?4?<2d:o>47;:k11g<72-;h87<74:l2g6<>32c99l4?:%3`0?4?<2d:o>4n;:k11<<72-;h87<74:l2g64l;:k113<72-;h87<74:l2g64j;:k111<72-;h87<74:l2g64?:%3`0?4?<2d:o>4>0:9j604=83.:o94=859m5f5=9810e?;>:18'5f2=:1>0b!7d<38386`>c2820>=n:=o1<7*>c581<1=i9j91=854i34a>5<#9j>1>5:4n0a0>40<3`8=m7>5$0a7>7>33g;h?7?8;:k12<<72-;h87<74:l2g6<6021b>;650;&2g1<50=1e=n=51898m700290/=n:52968j4e428k07d<96;29 4e32;2?7c?l3;3a?>o5>:0;6)?l4;0;0>h6k:0:o65f24:94?"6k=09495a1b195a=o6=4+1b696=25}#9ji1hh5G1d28L4ea3fno6=44}c3f6?6=93:1cb82`5=O9l:0DN6ko1Q?l4l{586>=<>28;1=?4>3;37>f2682?!7503;0(ih52:&f4?4<,l;1>6*j2;08 `5=:2.n87<4$0ff>4bd3-;h47?4$d596>"b0380(h752:&fe?4<,lh1>6*jc;08 `b=:2.ni7<4$dd96>"a8380(k?52:&e6?4<,o91>6*i4;08 c3=:2.m:7<4$g596>"a0380(k752:&ee?4<,oh1>6*ic;08 cb=:2.mi7<4$gd96>"689097)??1;08 4652;1/===52:&241<53-;;97<4$025>7=#99=1>6*>0981?!771380(<>n:39'55d=:2.:"699097)?>1;08 4752;1/=<=52:&251<53-;:97<4$035>7=#98=1>6*>1981?!761380("6:9097)?=1;08 4452;1/=?=52:&261<53-;997<4$005>7=#9j<1?55+e481?!c12;1/=ij51ea8 4e>281b?n4?::k0`?6=3`ni6=44iea94?=n9jk1<75f1b`94?=n9o0;6)?l4;3f?k7d;3:07d?k:18'5f2=9l1e=n=51:9j5f<72-;h87?j;o3`7?4<3`;i6=4+1b695`=i9j91?65f2983>!7d<3;n7c?l3;68?l40290/=n:51d9m5f5==21b>;4?:%3`0?7b3g;h?784;h06>5<#9j>1=h5a1b193>=n:=0;6)?l4;3f?k7d;3207d<<:18'5f2=9l1e=n=59:9j67<72-;h87?j;o3`7?g<3`8:6=4+1b695`=i9j91n65f2183>!7d<3;n7c?l3;a8?l7f290/=n:51d9m5f5=l21b>h4?:%3`0?4c3g;h?7>4;h0`>5<#9j>1>i5a1b195>=n:k0;6)?l4;0g?k7d;3807d!7d<38o7c?l3;48?l53290/=n:52e9m5f5=?21b?>4?:%3`0?4c3g;h?764;h11>5<#9j>1>i5a1b19=>=n;80;6)?l4;0g?k7d;3k07d=?:18'5f2=:m1e=n=5b:9j6c<72-;h87!7d<3?i7c?l3;28?l3f290/=n:55c9m5f5=921b954?:%3`0?3e3g;h?7<4;h74>5<#9j>19o5a1b197>=n=?0;6)?l4;7a?k7d;3>07d;::18'5f2==k1e=n=55:9j11<72-;h87;m;o3`7?0<3`?86=4+1b691g=i9j91;65f5383>!7d<3?i7c?l3;:8?l36290/=n:55c9m5f5=121b9=4?:%3`0?3e3g;h?7o4;h6e>5<#9j>19o5a1b19f>=nj6=4+1b691g=i9j91j65f4883>!7d<3?i7c?l3;33?>o303:1(43<3`<86=4+1b691g=i9j91=;54i7094?"6k=0>n6`>c2823>=n>80;6)?l4;7a?k7d;3;376g90;29 4e324>b:9j1a<72-;h87;m;o3`7?7d32c>57>5$0a7>0d5<#9j>19o5a1b195`=c586f>h6k:0:j65f7e83>!7d<3=h7c?l3;28?l1e290/=n:57b9m5f5=921b;44?:%3`0?1d3g;h?7<4;h5;>5<#9j>1;n5a1b197>=n?>0;6)?l4;5`?k7d;3>07d99:18'5f2=?j1e=n=55:9j30<72-;h879l;o3`7?0<3`=?6=4+1b693f=i9j91;65f7283>!7d<3=h7c?l3;:8?l15290/=n:57b9m5f5=121b;<4?:%3`0?1d3g;h?7o4;h53>5<#9j>1;n5a1b19f>=n>l0;6)?l4;5`?k7d;3i07d8k:18'5f2=?j1e=n=5d:9j2f<72-;h879l;o3`7?c<3`!7d<3=h7c?l3;33?>o113:1(43<3`2?6=4+1b693f=i9j91=;54i9194?"6k=0c2823>=n0;0;6)?l4;5`?k7d;3;376g71;29 4e32>i0b7290/=n:57b9m5f5=9h10e:h50;&2g1<0k2d:o>4>b:9j3`<72-;h879l;o3`7?7d32c5$0a7>2e5<#9j>1;n5a1b195`=1<7*>c584g>h6k:0:j65f8883>!7d<3237c?l3;28?l>0290/=n:5899m5f5=921b4;4?:%3`0?>?3g;h?7<4;h:6>5<#9j>1455a1b197>=n0l0;6)?l4;:g?k7d;3:07d6l:18'5f2=0m1e=n=51:9j=n9m>1<7*>c582`0=i9j91=65f1e194?"6k=0:h85a1b196>=n9m81<7*>c582`0=i9j91?65f1e`94?"6k=0:hl5a1b194>=n9m31<7*>c582`d=i9j91=65f1e:94?"6k=0:hl5a1b196>=n9m=1<7*>c582`d=i9j91?65`a983>!7d<3k<7c?l3;28?jg1290/=n:5a69m5f5=921dm94?:%3`0?g03g;h?7<4;nc0>5<#9j>1m:5a1b197>=hi;0;6)?l4;c4?k7d;3>07bo>:18'5f2=i>1e=n=55:9le5<72-;h87o8;o3`7?0<3f3m6=4+1b69e2=i9j91;65`9d83>!7d<3k<7c?l3;:8?j?c290/=n:5a69m5f5=121d5n4?:%3`0?g03g;h?7o4;n;a>5<#9j>1m:5a1b19f>=h100;6)?l4;c4?k7d;3i07b77:18'5f2=i>1e=n=5d:9l=2<72-;h87o8;o3`7?c<3f3=6=4+1b69e2=i9j91j65`9483>!7d<3k<7c?l3;33?>i><3:1(1e=n=51398k<4=83.:o94n7:l2g6<6;21d5<4?:%3`0?g03g;h?7?;;:m:4?6=,8i?6l94n0a0>43<3fkm6=4+1b69e2=i9j91=;54o`g94?"6k=0j;6`>c2823>=him0;6)?l4;c4?k7d;3;376anc;29 4e32h=0b4>b:9le<<72-;h87o8;o3`7?7d32ej97>5$0a7>d15<#9j>1m:5a1b195`=c58b3>h6k:0:j65`c883>!7d<3i37c?l3;28?je0290/=n:5c99m5f5=921do84?:%3`0?e?3g;h?7<4;na7>5<#9j>1o55a1b197>=hk:0;6)?l4;a;?k7d;3>07bm=:18'5f2=k11e=n=55:9lg4<72-;h87m7;o3`7?0<3fi;6=4+1b69g==i9j91;65`bg83>!7d<3i37c?l3;:8?jdb290/=n:5c99m5f5=121dni4?:%3`0?e?3g;h?7o4;n``>5<#9j>1o55a1b19f>=hjh0;6)?l4;a;?k7d;3i07bl6:18'5f2=k11e=n=5d:9lf=<72-;h87m7;o3`7?c<3fh<6=4+1b69g==i9j91j65`b783>!7d<3i37c?l3;33?>ie=3:1(43<3fn;6=4+1b69g==i9j91=;54obd94?"6k=0h46`>c2823>=hkl0;6)?l4;a;?k7d;3;376ald;29 4e32j20b4>b:9lgd<72-;h87m7;o3`7?7d32eh:7>5$0a7>f>5<#9j>1o55a1b195`=c58`<>h6k:0:j65`d483>!7d<3n?7c?l3;28?jb4290/=n:5d59m5f5=921dh?4?:%3`0?b33g;h?7<4;nf2>5<#9j>1h95a1b197>=hlh0;6)?l4;f:?k7d;3:07bj7:18'5f2=l01e=n=51:9l`2<72-;h87j6;o3`7?4<3fn=6=4+1b69`<=i9j91?65rs23a>5<5;rT95:?2a4c`9>5fb=9jh01n850;0xZ7g134;hh7o7;|q1g1<72;qU>l;4=0ag>d07>52z\1e6=:9jn1m95rs3a2>5<5sW8j>63>ce8b7>{t:j:1<77}Y:h:01vP=9g9>5fb=i91v?lk:181[4>m27:oi46f:p6ge=838pR?7k;<3``??b3ty9no4?:3y]6;6km02n6s|2c594?4|V;3370?ld;;:?xu5j?0;6?uQ285894ec2020q~>2wx>o=50;0xZ7?334;hh77:;|q1f7<72;qU>4=4=0ag><252z\1=7=:9jn15>5rs3`3>5<5sW82=63>ce8:6>{t:hl1<77}Y:1l01vP=ab9>5fb=io1v?ml:181[4fj27:oi4ne:p6fd=838pR?on;<3``?gc3ty9ol4?:3y]6d?<58io6lm4}r0`=?6=:rT9m5521bf9eg=z{;i36=4={_0b3>;6km0jm6s|2b594?4|V;k?70?ld;c:?xu5k:0;6?uQ28;894ec2h?0q~h84=0ag>f152z\1a1=:9jn1o85rs221>5<5sW8n?63>ce8`0>{t;9;1<77}Y:l;01vP=e19>5fb=k81v?hj:181[4cn27:oi4l0:p6cb=838pR?jj;<3``?da3ty9jn4?:3y]6ab<58io6ok4}r0ef?6=:rT9hn521bf9fa=z{;lj6=4={_0gf>;6km0io6s|2g:94?4|V;n270?ld;`b?xu5n>0;6?uQ2e:894ec2k30q~16=nj5b99~w7`22909wSk:50;0xZ7b234;hh7l9;|q1b6<72;qU>i:4=0ag>g37>52z\1`6=:9jn1n95rs3d2>5<5sW8o>63>ce8a7>{t:o:1<77}Y:m:01vP=ee9>5fb=l91v>>k:181[4bk27:oi4lf:p75e=838pR?km;<3``?eb3ty8;6km0hn6s|31:94?4|V;o>70?ld;ab?xu48=0;6?uQ2ec894ec2j<0q~0}Y;;?01ce82`==:9jn1=i94}r3e1?6=:rT:ih521bf95g=z{8l86=4={_3f`>;6km0946s|1g094?4|V8oh70?ld;04?xu6n80;6?uQ1d`894ec2;<0q~?i0;296~X6mh16=nj5249~w4ca2909wS?j9:?2ga<5<2wx>=<50;0xZ4`e34;hh76152z\2b<=:9jn1?;5rs0df>5<5sW;m463>ce801>{t9on1<7fb83>7}Y9o<01vP=259>5fb==j1v?:=:181[45;27:oi4:a:p616=838pR?<>;<3``?3?3ty9?k4?:3y]676<58io6894}r00a?6=:rT9=k521bf913=z{;9o6=4={_02a>;6km0>96s|22a94?4|V;;o70?ld;77?xu5;k0;6?uQ20a894ec2<90q~<2909wS<>a:?2ga<292wx>>650;0xZ77>34;hh7;?;|q172<72;qU><64=0ag>1`52z\153=:9jn18i5rs317>5<5sW8:963>ce87g>{t::91<7i7p}=3383>7}Y:8901vP=139>5fb=<01v?=?:181[46927:oi4;8:p67`=838pR???;<3``?203ty9>h4?:3y]65`<58io6984}r01`?6=:rT9;6km0?86s|25`94?4|V;8j70?ld;40?xu59950;0xZ74134;hh7;i;|q103<72;qU>?;4=0ag>0c52z\167=:9jn19i5rs362>5<5sW8:;63>ce86=>{t::<1<7n7p}=2c83>7}Y:9h01vP=649>5fb=?m1v?6<:181[41<27:oi48b:p6=7=838pR?8=;<3``?1>3ty94=4?:3y]637<58io6:64}r04b?6=:rT9:=521bf932=z{;=n6=4={_06b>;6km0<:6s|26f94?4|V;?n70?ld;56?xu5?j0;6?uQ24f894ec2>>0q~<8b;296~X5=j16=nj5729~w71f2909wS<:b:?2ga<0:2wx>:750;0xZ73f34;hh79>;|q13=<72;qU>874=0ag>2652z\112=:9jn1:h5rs356>5<5sW8>:63>ce85`>{t:>>1<77}Y:<>01vP=529>5fb=>h1v?9>:181[42:27:oi499:p626=838pR?;>;<3``?0?3ty9:k4?:3y]606<58io6;94}r05a?6=:rT98k521bf923=z{;;6km0=96s|29a94?4|V;016=nj5839~w7>>2909wS<98:?2ga5650;0xZ70034;hh76?;|q1<2<72;qU>;84=0ag>2`52z\126=:9jn1;h5rs3:1>5<5sW8>463>ce84e>{t:>=1<77}Y:=i01e382g4=:9jn1ho521bf9`f=zuz8;87>52z\141=:;009<95+1bg953e52z\067=:;008>?5+1bg95<352z\2a`=:;00:ih5+1bg95d652z\2aa=:;00:ii5+1bg95d?7>52z\2af=:;00:in5+1bg95g552z\2ag=:;00:io5+1bg957c52z\2ad=:;00:il5+1bg956?52z\2a<=:;00:i45+1bg951252z\161=:;009>95+1bg951`7>52z\166=:;009>>5+1bg950g52z\164=:;009><5+1bg953352z\165=:;009>=5+1bg953>52z\15c=:;009=k5+1bg953?52z\15`=:;009=h5+1bg953g52z\15a=:;009=i5+1bg953d52z\15f=:;009=n5+1bg953b52z\15g=:;009=o5+1bg953c52z\15d=:;009=l5+1bg953`52z\15<=:;009=45+1bg952652z\15==:;009=55+1bg952752z\153=:;009=;5+1bg952452z\150=:;009=85+1bg952552z\151=:;009=95+1bg95227>52z\156=:;009=>5+1bg952352z\157=:;009=?5+1bg952052z\154=:;009=<5+1bg952152z\155=:;009==5+1bg952>52z\14c=:;00952z\14`=:;00952z\14a=:;00952z\16d=:;009>l5+1bg952e52z\16<=:;009>45+1bg952b52z\16==:;009>55+1bg952c52z\162=:;009>:5+1bg952`52z\163=:;009>;5+1bg95=652z\160=:;009>85+1bg95=752z\167=:;009>?5+1bg95=452z\152=:;009=:5+1bg95=552z\14f=:;00952z\14g=:;00952z\1e3=:;009m;5+1bg95=052z\1e0=:;009m85+1bg95=17>52z\1e6=:;009m>5+1bg95=>52z\1e7=:;009m?5+1bg95=?52z\1e4=:;009m<5+1bg95=g52z\1e5=:;009m=5+1bg95=d52z\1=c=:;0095k5+1bg95=e52z\1=`=:;0095h5+1bg95=b52z\1=a=:;0095i5+1bg95=c52z\1=f=:;0095n5+1bg95=`52z\1=g=:;0095o5+1bg95<652z\1=d=:;0095l5+1bg95<752z\1===:;009555+1bg95<452z\1=2=:;0095:5+1bg95<552z\1=3=:;0095;5+1bg95<252z\1=0=:;009585+1bg95<052z\1=1=:;009595+1bg95<17>52z\1=6=:;0095>5+1bg95<>52z\1=7=:;0095?5+1bg9552z\1=4=:;0095<5+1bg9552z\1=5=:;0095=5+1bg9552z\152z\1ef=:;009mn5+1bg9552z\1eg=:;009mo5+1bg9552z\1ed=:;009ml5+1bg95<`52z\1e<=:;009m45+1bg95d752z\1e==:;009m55+1bg95d452z\1e2=:;009m:5+1bg95d552z\1e1=:;009m95+1bg95d252z\1=<=:;009545+1bg95d352z\1<`=:;0094h5+1bg95d052z\152z\140=:;009<85+1bg95d>52z\060=:;008>85+1bg95dg7>52z\2bg=:;00:jo5+1bg95dd52z\2bd=:;00:jl5+1bg95de52z\2b<=:;00:j45+1bg95db52z\2b==:;00:j55+1bg95dc52z\2b2=:;00:j:5+1bg95d`52z\2b3=:;00:j;5+1bg95g652z\120=:;009:85+1bg95g752z\121=:;009:95+1bg95g452z\127=:;009:?5+1bg95g252z\124=:;009:<5+1bg95g352z\125=:;009:=5+1bg95g052z\11c=:;0099k5+1bg95g152z\11`=:;0099h5+1bg95g>52z\11a=:;0099i5+1bg95g?52z\11f=:;0099n5+1bg95gg52z\11g=:;0099o5+1bg95gd52z\11d=:;0099l5+1bg95ge52z\11<=:;009945+1bg95gb52z\112=:;0099:5+1bg957`52z\113=:;0099;5+1bg956652z\110=:;009985+1bg956752z\111=:;009995+1bg95647>52z\116=:;0099>5+1bg956552z\117=:;0099?5+1bg956252z\114=:;0099<5+1bg956352z\115=:;0099=5+1bg956052z\10c=:;0098k5+1bg956152z\10`=:;0098h5+1bg956>52z\12g=:;009:o5+1bg956g52z\12d=:;009:l5+1bg956d52z\12<=:;009:45+1bg956e52z\12==:;009:55+1bg956b52z\122=:;009::5+1bg956c52z\123=:;009:;5+1bg956`52z\126=:;009:>5+1bg95167>52z\11==:;009955+1bg951752z\10a=:;0098i5+1bg951452z\10f=:;0098n5+1bg951552z\1a2=:;009i:5+1bg951352z\1a3=:;009i;5+1bg951052z\1a1=:;009i95+1bg95117>52z\1a6=:;009i>5+1bg951>52z\1a7=:;009i?5+1bg951?52z\1a4=:;009i<5+1bg951g52z\1a5=:;009i=5+1bg951d52z\1`c=:;009hk5+1bg951e52z\1``=:;009hh5+1bg951b52z\1`a=:;009hi5+1bg951c52z\1`f=:;009hn5+1bg950652z\1`g=:;009ho5+1bg950752z\1`<=:;009h45+1bg950452z\1`==:;009h55+1bg950552z\1`2=:;009h:5+1bg950252z\1`3=:;009h;5+1bg950352z\1`0=:;009h85+1bg950052z\1`1=:;009h95+1bg95017>52z\1`6=:;009h>5+1bg950>52z\1`7=:;009h?5+1bg950?52z\1`4=:;009h<5+1bg950d52z\1`5=:;009h=5+1bg950e52z\1aa=:;009ii5+1bg950b52z\1af=:;009in5+1bg950c52z\1ag=:;009io5+1bg950`52z\1ad=:;009il5+1bg953652z\1a<=:;009i45+1bg953752z\1a==:;009i55+1bg953452z\1a0=:;009i85+1bg953552z\1`d=:;009hl5+1bg953252z\1gc=:;009ok5+1bg953052z\1g`=:;009oh5+1bg95317>52zJ2gc=zf;386=4={I3`b>{i:0>1<7>3:1>vF>cg9~j7?02909wE?lf:m6<>=838pD5<5sA;hj6sa28a94?4|@8im7p`=9e83>7}O9jl0qc<6e;296~N6ko1vb?7i:181M7dn2we>l>50;0xL4ea3td9m<4?:3yK5f`7>52zJ2gc=zf;k86=4={I3`b>{i:h>1<73:1>vF>cg9~j7g02909wE?lf:m6d>=838pD5<5sA;hj6sa2`a94?4|@8im7p`=ae83>7}O9jl0qco>50;0xL4ea3td9n<4?:3yK5f`7>52zJ2gc=zf;h86=4={I3`b>{i:k>1<73:1>vF>cg9~j7d02909wE?lf:m6g>=838pD5<5sA;hj6sa2ca94?4|@8im7p`=be83>7}O9jl0qcn>50;0xL4ea3td9o<4?:3yK5f`7>52zJ2gc=zf;i86=4={I3`b>{i:j>1<73:1>vF>cg9~j7e02909wE?lf:m6f>=838pD5<5sA;hj6sa2ba94?4|@8im7p`=ce83>7}O9jl0qci>50;0xL4ea3td9h<4?:3yK5f`7>52zJ2gc=zf;n86=4={I3`b>{i:m>1<73:1>vF>cg9~j7b02909wE?lf:m6a>=838pD5<5sA;hj6sa2ea94?4|@8im7p`=de83>7}O9jl0qch>50;0xL4ea3td9i<4?:3yK5f`7>52zJ2gc=zf;o86=4={I3`b>{i:l>1<73:1>vF>cg9~j7c02909wE?lf:m6`>=838pD5<5sA;hj6sa2da94?4|@8im7p`=ee83>7}O9jl0qck>50;0xL4ea3td9j<4?:3yK5f`7>52zJ2gc=zf;l86=4={I3`b>{i:o>1<73:1>vF>cg9~j7`02909wE?lf:m6c>=838pD5<5sA;hj6sa2ga94?4|@8im7p`=fe83>7}O9jl0qc50;0xL4ea3td8<<4?:3yK5f`7>52zJ2gc=zf::86=4={I3`b>{i;9>1<73:1>vF>cg9~j6602909wE?lf:m75>=838pD5<5sA;hj6sa31a94?4|@8im7p`<0e83>7}O9jl0qc=?e;296~N6ko1vb>>i:181M7dn2we?<>50;0xL4ea3td8=<4?:3yK5f`7>52zJ2gc=zf:;86=4={I3`b>{i;8>1<73:1>vF>cg9~j6702909wE?lf:m74>=838pD5<5sA;hj6sa30a94?4|@8im7p`<1e83>7}O9jl0qc=>e;296~N6ko1vb>?i:181M7dn2we??>50;0xL4ea3td:jk4?:0yK5f`51zJ2gc=zutwKLNu + + BLOCK + 2009-11-2T14:49:15 + + + + + + + + + + + + dataRegister + + + + + + + + + + + + + + + + + + + + + + + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xise =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xise (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xise (revision 3) @@ -0,0 +1,329 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xco =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xco (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.xco (revision 3) @@ -0,0 +1,89 @@ +############################################################## +# +# Xilinx Core Generator version 11.3 +# Date: Mon Nov 02 14:50:24 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s50an +SET devicefamily = spartan3a +SET flowvendor = Foundation_ISE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dataRegister +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=true +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=32 +CSET read_width_b=32 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=64 +CSET write_width_a=32 +CSET write_width_b=32 +# END Parameters +GENERATE +# CRC: af90b416 Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.veo =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.veo (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.veo (revision 3) @@ -0,0 +1,52 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dataRegister YourInstanceName ( + .clka(clka), + .wea(wea), // Bus [0 : 0] + .addra(addra), // Bus [5 : 0] + .dina(dina), // Bus [31 : 0] + .douta(douta), // Bus [31 : 0] + .clkb(clkb), + .web(web), // Bus [0 : 0] + .addrb(addrb), // Bus [5 : 0] + .dinb(dinb), // Bus [31 : 0] + .doutb(doutb)); // Bus [31 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dataRegister.v when simulating +// the core, dataRegister. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.asy =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.asy (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.asy (revision 3) @@ -0,0 +1,45 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 dataRegister +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[5:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[31:0] +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName addrb[5:0] +PINATTR Polarity IN +LINE Wide 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName dinb[31:0] +PINATTR Polarity IN +LINE Wide 0 560 32 560 +PIN 0 560 LEFT 36 +PINATTR PinName web[0:0] +PINATTR Polarity IN +LINE Normal 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName clkb +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[31:0] +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName doutb[31:0] +PINATTR Polarity OUT + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vho =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vho (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vho (revision 3) @@ -0,0 +1,74 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component dataRegister + port ( + clka: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(5 downto 0); + dina: IN std_logic_VECTOR(31 downto 0); + douta: OUT std_logic_VECTOR(31 downto 0); + clkb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(5 downto 0); + dinb: IN std_logic_VECTOR(31 downto 0); + doutb: OUT std_logic_VECTOR(31 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of dataRegister: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dataRegister + port map ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file dataRegister.vhd when simulating +-- the core, dataRegister. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_xmdf.tcl =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_xmdf.tcl (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_xmdf.tcl (revision 3) @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide dataRegister_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::dataRegister_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::dataRegister_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name dataRegister +} +# ::dataRegister_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::dataRegister_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dataRegister_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module dataRegister +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_flist.txt =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_flist.txt (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister_flist.txt (revision 3) @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs\ +blk_mem_gen_ds512.pdf +dataRegister.asy +dataRegister.gise +dataRegister.ise +dataRegister.ngc +dataRegister.sym +dataRegister.v +dataRegister.veo +dataRegister.vhd +dataRegister.vho +dataRegister.xco +dataRegister.xise +dataRegister_flist.txt +dataRegister_readme.txt +dataRegister_xdb\tmp\ +dataRegister_xmdf.tcl Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ise =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ise (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ise (revision 3)

utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/ipcore_dir/dataRegister.vhd (revision 3) @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRegister.vhd when simulating +-- the core, dataRegister. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY dataRegister IS + port ( + clka: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(5 downto 0); + dina: IN std_logic_VECTOR(31 downto 0); + douta: OUT std_logic_VECTOR(31 downto 0); + clkb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(5 downto 0); + dinb: IN std_logic_VECTOR(31 downto 0); + doutb: OUT std_logic_VECTOR(31 downto 0)); +END dataRegister; + +ARCHITECTURE dataRegister_a OF dataRegister IS +-- synthesis translate_off +component wrapped_dataRegister + port ( + clka: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(5 downto 0); + dina: IN std_logic_VECTOR(31 downto 0); + douta: OUT std_logic_VECTOR(31 downto 0); + clkb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(5 downto 0); + dinb: IN std_logic_VECTOR(31 downto 0); + doutb: OUT std_logic_VECTOR(31 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRegister use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 2, + c_rstram_b => 0, + c_rstram_a => 0, + c_has_injecterr => 0, + c_rst_type => "SYNC", + c_prim_type => 1, + c_read_width_b => 32, + c_initb_val => "0", + c_family => "spartan3", + c_read_width_a => 32, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_has_mem_output_regs_a => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_write_depth_b => 64, + c_write_depth_a => 64, + c_has_rstb => 0, + c_has_rsta => 0, + c_has_mux_output_regs_b => 0, + c_inita_val => "0", + c_has_mux_output_regs_a => 0, + c_addra_width => 6, + c_addrb_width => 6, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 32, + c_write_width_a => 32, + c_read_depth_b => 64, + c_read_depth_a => 64, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_rst_priority_b => "CE", + c_rst_priority_a => "CE", + c_use_default_data => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_dataRegister + port map ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb); +-- synthesis translate_on + +END dataRegister_a; + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/top.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/top.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/top.vhd (revision 3) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: University of Southern Denmark +-- Engineer: Simon Falsig +-- +-- Create Date: 19/03/2010 +-- Design Name: uTosNet_uart Example +-- Module Name: top - Behavioral +-- Project Name: uTosNet +-- Target Devices: SDU XC3S50AN Board +-- Tool versions: Xilinx ISE 11.4 +-- Description: This is a simple example showing the use of the uTosNet_uart +-- module. +-- +-- Revision: +-- Revision 0.10 - Initial release +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity top is +Port ( CLK_50M_I : in STD_LOGIC; + LEDS_O : out STD_LOGIC_VECTOR(2 downto 0); + SERIAL_O : out STD_LOGIC; + SERIAL_I : in STD_LOGIC); +end top; + +architecture Behavioral of top is + + component uTosNet_uart is + Port ( clk_50M : in STD_LOGIC; + serial_out : out STD_LOGIC; + serial_in : in STD_LOGIC; + dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0); + dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0); + dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0); + dataReg_clk : in STD_LOGIC; + dataReg_writeEnable : in STD_LOGIC); + end component; + + type STATES is (IDLE, SETUP_1, CLK_1, DONE_1); + + signal state : STATES := IDLE; + signal nextState : STATES := IDLE; + + signal dataReg_addr : STD_LOGIC_VECTOR(5 downto 0); + signal dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + signal dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + signal dataReg_clk : STD_LOGIC; + signal dataReg_we : STD_LOGIC; + +begin + + uTosNet_uartInst : uTosNet_uart + Port map ( clk_50M => CLK_50M_I, + serial_out => SERIAL_O, + serial_in => SERIAL_I, + dataReg_addr => dataReg_addr, + dataReg_dataIn => "00000000000000000000000000000000", + dataReg_dataOut => dataReg_dataOut, + dataReg_clk => dataReg_clk, + dataReg_writeEnable => dataReg_we); + + process(CLK_50M_I) + begin + if(CLK_50M_I = '1' and CLK_50M_I'event) then + state <= nextState; + + case state is + when IDLE => + when SETUP_1 => + dataReg_addr <= "000000"; + dataReg_clk <= '0'; + dataReg_we <= '0'; + when CLK_1 => + dataReg_clk <= '1'; + when DONE_1 => + LEDS_O <= dataReg_dataOut(2 downto 0); + end case; + end if; + end process; + + process(state) + begin + case state is + when IDLE => + nextState <= SETUP_1; + when SETUP_1 => + nextState <= CLK_1; + when CLK_1 => + nextState <= DONE_1; + when DONE_1 => + nextState <= IDLE; + end case; + end process; + + +end Behavioral; + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.xise =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.xise (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.xise (revision 3) @@ -0,0 +1,95 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s400an.ucf =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s400an.ucf (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s400an.ucf (revision 3) @@ -0,0 +1,10 @@ +NET "CLK_50M_I" LOC = A8; +NET "CLK_50M_I" IOSTANDARD = LVTTL; +NET "LEDS_O[0]" LOC = Y5; +NET "LEDS_O[0]" IOSTANDARD = LVTTL; +NET "LEDS_O[1]" LOC = Y4; +NET "LEDS_O[1]" IOSTANDARD = LVTTL; +NET "SERIAL_I" LOC = E19; +NET "SERIAL_I" IOSTANDARD = LVTTL; +NET "SERIAL_O" LOC = E20; +NET "SERIAL_O" IOSTANDARD = LVTTL; Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s50an.ucf =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s50an.ucf (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart_xc3s50an.ucf (revision 3) @@ -0,0 +1,42 @@ +NET "CLK_50M_I" LOC = P124; +NET "CLK_50M_I" IOSTANDARD = LVTTL; +NET "LEDS_O[0]" LOC = P10; +NET "LEDS_O[0]" IOSTANDARD = LVTTL; +NET "LEDS_O[1]" LOC = P12; +NET "LEDS_O[1]" IOSTANDARD = LVTTL; +NET "LEDS_O[2]" LOC = P13; +NET "LEDS_O[2]" IOSTANDARD = LVTTL; +NET "SERIAL_I" LOC = P125; +NET "SERIAL_I" IOSTANDARD = LVTTL; +NET "SERIAL_O" LOC = P127; +NET "SERIAL_O" IOSTANDARD = LVTTL; +#NET "GFX_BLU_O[0]" LOC = P3; +#NET "GFX_BLU_O[0]" IOSTANDARD = LVTTL; +#NET "GFX_BLU_O[1]" LOC = P6; +#NET "GFX_BLU_O[1]" IOSTANDARD = LVTTL; +#NET "GFX_BLU_O[2]" LOC = P5; +#NET "GFX_BLU_O[2]" IOSTANDARD = LVTTL; +#NET "GFX_GRN_O[0]" LOC = P4; +#NET "GFX_GRN_O[0]" IOSTANDARD = LVTTL; +#NET "GFX_GRN_O[1]" LOC = P131; +#NET "GFX_GRN_O[1]" IOSTANDARD = LVTTL; +#NET "GFX_GRN_O[2]" LOC = P8; +#NET "GFX_GRN_O[2]" IOSTANDARD = LVTTL; +#NET "GFX_HS_O" LOC = P126; +#NET "GFX_HS_O" IOSTANDARD = LVTTL; +#NET "GFX_RED_O[0]" LOC = P129; +#NET "GFX_RED_O[0]" IOSTANDARD = LVTTL; +#NET "GFX_RED_O[1]" LOC = P132; +#NET "GFX_RED_O[1]" IOSTANDARD = LVTTL; +#NET "GFX_RED_O[2]" LOC = P7; +#NET "GFX_RED_O[2]" IOSTANDARD = LVTTL; +#NET "GFX_VS_O" LOC = P130; +#NET "GFX_VS_O" IOSTANDARD = LVTTL; +#NET "CLK_50M_I" TNM_NET = CLK_50M_I; +#TIMESPEC TS_CLK_50M_I = PERIOD "CLK_50M_I" 20 ns HIGH 50%; +#NET "dataReg_clk" TNM_NET = dataReg_clk; +#TIMESPEC TS_dataReg_clk = PERIOD "dataReg_clk" TS_CLK_50M_I * 2 HIGH 50%; +#NET "gfxInst/clkdiv1" TNM_NET = gfxInst/clkdiv1; +#TIMESPEC TS_gfxInst_clkdiv1 = PERIOD "gfxInst/clkdiv1" TS_CLK_50M_I * 2 HIGH 50%; +#NET "pseudoTosNet_uartInst/int_dataReg_clk" TNM_NET = pseudoTosNet_uartInst/int_dataReg_clk; +#TIMESPEC TS_pseudoTosNet_uartInst_int_dataReg_clk = PERIOD "pseudoTosNet_uartInst/int_dataReg_clk" TS_CLK_50M_I * 2 HIGH 50%; Index: utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.vhd =================================================================== --- utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.vhd (nonexistent) +++ utosnet/trunk/gateware/uTosNet_example/uTosNet_uart/uTosNet_uart.vhd (revision 3) @@ -0,0 +1,497 @@ +---------------------------------------------------------------------------------- +-- Company: University of Southern Denmark +-- Engineer: Simon Falsig +-- +-- Create Date: 19/03/2010 +-- Design Name: uTosNet +-- Module Name: uTosNet_usb - Behavioral +-- Project Name: uTosNet +-- Target Devices: SDU XC3S50AN Board +-- Tool versions: Xilinx ISE 11.4 +-- Description: This module implements a very simple ASCII based protocol over +-- a uart. Data can be read and written from and to one port of a +-- dual-port blockRAM, where the other blockRAM port is available +-- to the user application. Communication takes place at the fol- +-- lowing settings: +-- Baudrate: 115200 kbps +-- Parity: none +-- Bits: 8 data bits, 1 stop bit +-- Flowcontrol: none +-- The protocol format can be seen in the documentation files. +-- +-- Focus has mostly been on a simple implementation, as the +-- module is to be used during courses at the university. +-- +-- Dependencies: The module uses the uart implementation from Ken Chapmans +-- PicoBlaze. More specifically the following files: +-- uart_rx.vhd +-- kcuart_rx.vhd +-- bbfifo_16x8.vhd +-- uart_tx.vhd +-- kcuart_tx.vhd +-- These files can be downloaded from Xilinx: +-- https://secure.xilinx.com/webreg/register.do?group=picoblaze +-- +-- It should not be hard to implement the module using another +-- uart implementation though. +-- +-- Revision: +-- Revision 0.10 - Initial release +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity uTosNet_uart is +Port ( clk_50M : in STD_LOGIC; + serial_out : out STD_LOGIC; + serial_in : in STD_LOGIC; + dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0); + dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0); + dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0); + dataReg_clk : in STD_LOGIC; + dataReg_writeEnable : in STD_LOGIC); +end uTosNet_uart; + +architecture Behavioral of uTosNet_uart is + + component dataRegister + Port ( clka : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR(0 downto 0); + addra : in STD_LOGIC_VECTOR(5 downto 0); + dina : in STD_LOGIC_VECTOR(31 downto 0); + douta : out STD_LOGIC_VECTOR(31 downto 0); + clkb : in STD_LOGIC; + web : in STD_LOGIC_VECTOR(0 downto 0); + addrb : in STD_LOGIC_VECTOR(5 downto 0); + dinb : in STD_LOGIC_VECTOR(31 downto 0); + doutb : out STD_LOGIC_VECTOR(31 downto 0)); + end component; + + component uart_rx + Port ( serial_in : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR(7 downto 0); + read_buffer : in STD_LOGIC; + reset_buffer : in STD_LOGIC; + en_16_x_baud : in STD_LOGIC; + buffer_data_present : out STD_LOGIC; + buffer_full : out STD_LOGIC; + buffer_half_full : out STD_LOGIC; + clk : in STD_LOGIC); + end component; + + component uart_tx + Port ( serial_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + write_buffer : in STD_LOGIC; + reset_buffer : in STD_LOGIC; + en_16_x_baud : in STD_LOGIC; + buffer_full : out STD_LOGIC; + buffer_half_full : out STD_LOGIC; + clk : in STD_LOGIC); + end component; + + signal baudCount : integer range 0 to 36 :=0; + signal en_16_x_baud : STD_LOGIC; + signal readFromUart : STD_LOGIC; + signal rxData : STD_LOGIC_VECTOR(7 downto 0); + signal rxDataPresent : STD_LOGIC; + signal rxFull : STD_LOGIC; + signal rxHalfFull : STD_LOGIC; + + signal txData : STD_LOGIC_VECTOR(7 downto 0); + signal writeToUart : STD_LOGIC; + signal txFull : STD_LOGIC; + signal txHalfFull : STD_LOGIC; + + constant UARTDIV : STD_LOGIC_VECTOR(5 downto 0) := "011010"; + + type STATES is (IDLE, COMMAND_IN, WAIT1, REG_IN, WAIT2, INDEX_IN, WAIT3, SPACE_IN, WAIT4, DATA_IN, WAIT_DATA_IN, DATA_OUT, PERFORM_READ_SETUP, PERFORM_READ_CLK, PERFORM_READ_DONE, PERFORM_WRITE_SETUP, PERFORM_WRITE_CLK, PERFORM_WRITE_DONE); + + signal state : STATES := IDLE; + signal nextState : STATES := IDLE; + + type COMMANDS is (CMD_NONE, CMD_READ, CMD_WRITE, CMD_COMMIT_READ, CMD_COMMIT_WRITE); + + signal currentCommand : COMMANDS := CMD_NONE; + + signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0); + signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0); + signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0); + signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0); + signal int_dataReg_clk : STD_LOGIC; + + signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0); + + signal inputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + signal outputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1'); + + signal readCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); + signal writeCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); + + signal currentReg : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); + signal currentIndex : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); + + signal commitRead : STD_LOGIC := '0'; + signal commitWrite : STD_LOGIC := '0'; + +begin + + dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:) + + dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister + Port map ( clka => dataReg_clk, --PortA is used for the user application + wea => dataReg_writeEnable_V, -- + addra => dataReg_addr, -- + dina => dataReg_dataIn, -- + douta => dataReg_dataOut, -- + clkb => int_dataReg_clk, --PortB is used for the SPI interface + web => int_dataReg_we, -- + addrb => int_dataReg_addr, -- + dinb => int_dataReg_dataIn, -- + doutb => int_dataReg_dataOut); -- + + rx_inst: uart_rx + Port map ( serial_in => serial_in, + data_out => rxData, + read_buffer => readFromUart, + reset_buffer => '0', + en_16_x_baud => en_16_x_baud, + buffer_data_present => rxDataPresent, + buffer_full => rxFull, + buffer_half_full => rxHalfFull, + clk => clk_50M ); + + tx_inst : uart_tx + Port map ( serial_out => serial_out, + data_in => txData, + write_buffer => writeToUart, + reset_buffer => '0', + en_16_x_baud => en_16_x_baud, + buffer_full => txFull, + buffer_half_full => txHalfFull, + clk => clk_50M); + + baudTimer_inst: process(clk_50M) + begin + if(clk_50M'event and clk_50M='1')then + if(baudCount = UARTDIV)then + baudCount <= 0; + en_16_x_baud <= '1'; + else + baudCount <= baudCount + 1; + en_16_x_baud <= '0'; + end if; + end if; + end process baudTimer_inst; + + + process(clk_50M) + begin + if(clk_50M = '1' and clk_50M'event) then + state <= nextState; + + readFromUart <= '0'; + writeToUart <= '0'; + + case state is + when IDLE => + currentCommand <= CMD_NONE; + readCounter <= (others => '0'); + writeCounter <= (others => '0'); + commitRead <= '0'; + commitWrite <= '0'; + when COMMAND_IN => + commitRead <= '0'; + commitWrite <= '0'; + if(rxDataPresent = '1') then + case rxData is + when "01110010" => --'r' + currentCommand <= CMD_READ; + when "01110111" => --'w' + currentCommand <= CMD_WRITE; + when "01110100" => --'t' + commitRead <= '1'; + currentCommand <= CMD_NONE; + when "01100011" => --'c' + commitWrite <= '1'; + currentCommand <= CMD_NONE; + when others => + currentCommand <= CMD_NONE; + end case; + readFromUart <= '1'; + end if; + when WAIT1 => + when REG_IN => + if(rxDataPresent = '1') then + case rxData is + when "00110000" => + currentReg <= "000"; + when "00110001" => + currentReg <= "001"; + when "00110010" => + currentReg <= "010"; + when "00110011" => + currentReg <= "011"; + when "00110100" => + currentReg <= "100"; + when "00110101" => + currentReg <= "101"; + when "00110110" => + currentReg <= "110"; + when "00110111" => + currentReg <= "111"; + when others => + currentCommand <= CMD_NONE; + end case; + readFromUart <= '1'; + end if; + when WAIT2 => + when INDEX_IN => + if(rxDataPresent = '1') then + case rxData is + when "00110000" => + currentIndex <= "000"; + when "00110001" => + currentIndex <= "001"; + when "00110010" => + currentIndex <= "010"; + when "00110011" => + currentIndex <= "011"; + when "00110100" => + currentIndex <= "100"; + when "00110101" => + currentIndex <= "101"; + when "00110110" => + currentIndex <= "110"; + when "00110111" => + currentIndex <= "111"; + when others => + currentCommand <= CMD_NONE; + end case; + readFromUart <= '1'; + end if; + when WAIT3 => + when SPACE_IN => + if(rxDataPresent = '1') then + if(not(rxData = "00100000")) then + currentCommand <= CMD_NONE; + end if; + readFromUart <= '1'; + end if; + when WAIT4 => + when DATA_IN => + if(rxDataPresent = '1') then + case rxData is + when "00110000" => --'0' + inputBuffer <= inputBuffer(27 downto 0) & "0000"; + when "00110001" => --'1' + inputBuffer <= inputBuffer(27 downto 0) & "0001"; + when "00110010" => --'2' + inputBuffer <= inputBuffer(27 downto 0) & "0010"; + when "00110011" => --'3' + inputBuffer <= inputBuffer(27 downto 0) & "0011"; + when "00110100" => --'4' + inputBuffer <= inputBuffer(27 downto 0) & "0100"; + when "00110101" => --'5' + inputBuffer <= inputBuffer(27 downto 0) & "0101"; + when "00110110" => --'6' + inputBuffer <= inputBuffer(27 downto 0) & "0110"; + when "00110111" => --'7' + inputBuffer <= inputBuffer(27 downto 0) & "0111"; + when "00111000" => --'8' + inputBuffer <= inputBuffer(27 downto 0) & "1000"; + when "00111001" => --'9' + inputBuffer <= inputBuffer(27 downto 0) & "1001"; + when "01100001" => --'a' + inputBuffer <= inputBuffer(27 downto 0) & "1010"; + when "01100010" => --'b' + inputBuffer <= inputBuffer(27 downto 0) & "1011"; + when "01100011" => --'c' + inputBuffer <= inputBuffer(27 downto 0) & "1100"; + when "01100100" => --'d' + inputBuffer <= inputBuffer(27 downto 0) & "1101"; + when "01100101" => --'e' + inputBuffer <= inputBuffer(27 downto 0) & "1110"; + when "01100110" => --'f' + inputBuffer <= inputBuffer(27 downto 0) & "1111"; + when others => + currentCommand <= CMD_NONE; + end case; + readFromUart <= '1'; + readCounter <= readCounter + 1; + end if; + when WAIT_DATA_IN => + when DATA_OUT => + writeToUart <= '1'; + if(writeCounter = 8) then + txData <= "00100000"; --Transmit a space to make thinks look nicer...:) + else + case outputBuffer(31 downto 28) is + when "0000" => --'0' + txData <= "00110000"; + when "0001" => --'1' + txData <= "00110001"; + when "0010" => --'2' + txData <= "00110010"; + when "0011" => --'3' + txData <= "00110011"; + when "0100" => --'4' + txData <= "00110100"; + when "0101" => --'5' + txData <= "00110101"; + when "0110" => --'6' + txData <= "00110110"; + when "0111" => --'7' + txData <= "00110111"; + when "1000" => --'8' + txData <= "00111000"; + when "1001" => --'9' + txData <= "00111001"; + when "1010" => --'a' + txData <= "01100001"; + when "1011" => --'b' + txData <= "01100010"; + when "1100" => --'c' + txData <= "01100011"; + when "1101" => --'d' + txData <= "01100100"; + when "1110" => --'e' + txData <= "01100101"; + when "1111" => --'f' + txData <= "01100110"; + when others => + end case; + end if; + outputBuffer <= outputBuffer(27 downto 0) & "0000"; + writeCounter <= writeCounter + 1; + when PERFORM_READ_SETUP => + int_dataReg_addr <= currentReg & currentIndex; + int_dataReg_we <= "0"; + int_dataReg_clk <= '0'; + when PERFORM_READ_CLK => + int_dataReg_clk <= '1'; + when PERFORM_READ_DONE => + outputBuffer <= int_dataReg_dataOut; + int_dataReg_clk <= '0'; + when PERFORM_WRITE_SETUP => + int_dataReg_addr <= currentReg & currentIndex; + int_dataReg_dataIn <= inputBuffer; + int_dataReg_we <= "1"; + int_dataReg_clk <= '0'; + when PERFORM_WRITE_CLK => + int_dataReg_clk <= '1'; + when PERFORM_WRITE_DONE => + int_dataReg_we <= "0"; + int_dataReg_clk <= '0'; + end case; + end if; + end process; + + process(state, rxDataPresent, currentCommand, readCounter, writeCounter) + begin + if((currentCommand = CMD_NONE) and not ((state = COMMAND_IN) or (state = IDLE))) then + nextState <= IDLE; + else + case state is + when IDLE => + nextState <= COMMAND_IN; + when COMMAND_IN => + if(rxDataPresent = '1') then + nextState <= WAIT1; + else + nextState <= COMMAND_IN; + end if; + when WAIT1 => + if(rxDataPresent = '0') then + nextState <= REG_IN; + else + nextState <= WAIT1; + end if; + when REG_IN => + if(rxDataPresent = '1') then + nextState <= WAIT2; + else + nextState <= REG_IN; + end if; + when WAIT2 => + if(rxDataPresent = '0') then + nextState <= INDEX_IN; + else + nextState <= WAIT2; + end if; + when INDEX_IN => + if(rxDataPresent = '1') then + nextState <= WAIT3; + else + nextState <= INDEX_IN; + end if; + when WAIT3 => + if(rxDataPresent = '0') then + if(currentCommand = CMD_READ) then + nextState <= PERFORM_READ_SETUP; + else + nextState <= SPACE_IN; + end if; + else + nextState <= WAIT3; + end if; + when SPACE_IN => + if(rxDataPresent = '1') then + nextState <= WAIT4; + else + nextState <= SPACE_IN; + end if; + when WAIT4 => + if(rxDataPresent = '0') then + nextState <= DATA_IN; + else + nextState <= WAIT4; + end if; + when DATA_IN => + if(rxDataPresent = '1') then + nextState <= WAIT_DATA_IN; + else + nextState <= DATA_IN; + end if; + when WAIT_DATA_IN => + if(rxDataPresent = '0') then + if(readCounter = 8) then + nextState <= PERFORM_WRITE_SETUP; + else + nextState <= DATA_IN; + end if; + else + nextState <= WAIT_DATA_IN; + end if; + when DATA_OUT => + if(writeCounter = 8) then + nextState <= IDLE; + else + nextState <= DATA_OUT; + end if; + when PERFORM_READ_SETUP => + nextState <= PERFORM_READ_CLK; + when PERFORM_READ_CLK => + nextState <= PERFORM_READ_DONE; + when PERFORM_READ_DONE => + nextState <= DATA_OUT; + when PERFORM_WRITE_SETUP => + nextState <= PERFORM_WRITE_CLK; + when PERFORM_WRITE_CLK => + nextState <= PERFORM_WRITE_DONE; + when PERFORM_WRITE_DONE => + nextState <= IDLE; + end case; + end if; + end process; + +end Behavioral; +