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/versatile_mem_ctrl/trunk/rtl/verilog/sdr_16_defines.v
0,0 → 1,89
`timescale 1ns/1ns
 
 
//
// Specify either type of memory
// or
// BA_SIZE, ROW_SIZE, COL_SIZE and SDRAM_DATA_WIDTH
//
// either in this file or as command line option; +define+MT48LC16M16
//
 
// number of adr lines to use
// 2^2 = 4 32 bit word burst
`define BURST_SIZE 2
 
`define MT48LC16M16
`ifdef MT48LC16M16
// using 1 of MT48LC16M16
// SDRAM data width is 16
`define SDRAM_DATA_WIDTH 16
`define COL_SIZE 9
`define ROW_SIZE 13
`define BA_SIZE 2
 
`define SDRAM16
`define BA tx_fifo_dat_o[28:27]
`define ROW tx_fifo_dat_o[26:14]
`define COL {4'b0000,tx_fifo_dat_o[14:10],burst_adr}
`define WORD_SIZE 1
`define WB_ADR_HI 24
`define WB_ADR_LO 2
`endif // `ifdef MT48LC16M16
 
//`define DEVICE MT48LC4M16
`ifdef MT48LC4M16
// using 1 of MT48LC4M16
// SDRAM data width is 16
`define SDRAM_DATA_WIDTH 16
`define COL_SIZE 8
`define ROW_SIZE 12
`define BA_SIZE 2
 
`define SDRAM16
`define COL {5'b0000,wb_adr_i[8:1]}
`define ROW wb_adr_i[20:9]
`define BA wb_adr_i[22:21]
`define WORD_SIZE 1
`define END_OF_BURST burst_counter[0]
`define WB_ADR_HI 22
`define WB_ADR_LO 1
`endif // `ifdef MT48LC4M16
 
 
// FIFO
`define DLY_INIT 4095
`define AREF_INIT 390
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
`define WB 1'b1
`define CL 2
`define BT 1'b0
`define BL 3'b000
 
// Adr to SDRAM {ba[1:0],a[12:0]}
`define A_LMR {2'b00,3'b000,`WB,2'b00,3'd`CL,`BT,`BL}
`define A_PRE {2'b00,13'b0010000000000}
`define A_ACT {ba,row}
`define A_READ {ba,col}
`define A_WRITE {ba,col}
`define A_DEFAULT {2'b00,13'b0000000000000}
 
// command
`define CMD {ras, cas, we}
`define CMD_NOP 3'b111
`define CMD_AREF 3'b001
`define CMD_LMR 3'b000
`define CMD_PRE 3'b010
`define CMD_ACT 3'b011
`define CMD_READ 3'b101
`define CMD_WRITE 3'b100
`define CMD_BT 3'b110
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v
1,3 → 1,5
`define SDR_16
 
`define PORT0
`define PORT1
//`define PORT2
/versatile_mem_ctrl/trunk/rtl/verilog/inc_adr.v
0,0 → 1,72
module inc_adr
(
input [3:0] adr_i,
input [2:0] cti_i,
input [1:0] bte_i,
input [7:0] fifo_empty,
input init,
input inc,
output reg [3:0] adr_o,
output reg done,
input clk,
input rst
);
 
reg init_i;
reg [1:0] bte;
reg [3:0] cnt;
 
// delay init one clock cycle to be able to read from mem
always @ (posedge clk or posedge rst)
if (rst)
init_i <= 1'b0;
else
init_i <= init;
// bte
always @ (posedge clk or posedge rst)
if (rst)
bte <= 2'b00;
else
if (init_i)
bte <= bte_i;
 
// adr_o
always @ (posedge clk or posedge rst)
if (rst)
adr_o <= 4'd0;
else
if (init_i)
adr_o <= adr_i;
else
if (inc)
case (bte)
2'b01: adr_o <= {adr_o[3:2], adr_o[1:0] + 2'd1};
2'b10: adr_o <= {adr_o[3], adr_o[2:0] + 3'd1};
default: adr_o <= adr_o + 4'd1;
endcase // case (bte)
// done
always @ (posedge clk or posedge rst)
if (rst)
{done,cnt} <= {1'b0,4'd0};
else
if (init_i)
begin
done <= ({bte_i,cti_i} == {2'b00,3'b000});
case (bte_i)
2'b01: cnt <= 4'd12;
2'b10: cnt <= 4'd8;
2'b11: cnt <= 4'd0;
default: cnt <= adr_i;
endcase
end
else
if (inc)
{done,cnt} <= cnt + 4'd1;
 
endmodule // inc_adr
 
/versatile_mem_ctrl/trunk/rtl/verilog/ctrl_counter_defines.v
17,6 → 17,9
// clear
`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v
1,4 → 1,7
`include "wb_sdram_ctrl_defines.v"
`include "versatile_mem_ctrl_defines.v"
`ifdef SDR_16
`include "sdr_16_defines.v"
`endif
 
module wb_sdram_ctrl_top
(
98,6 → 101,19
input wbs7_cyc_i,
input wbs7_stb_i,
output wbs7_ack_o,
`endif // `ifdef PORT7
`ifdef SDR_16
output reg [1:0] ba_pad_o,
output reg [12:0] a_pad_o,
output reg cs_n_pad_o,
output reg ras_pad_o,
output reg cas_pad_o,
output reg we_pad_o,
output reg [15:0] dq_pad_o,
output reg [1:0] dqm_pad_o,
input [15:0] dq_pad_i,
output reg dq_pad_oe,
output cke,
`endif
input wb_clk,
input wb_rst,
105,19 → 121,30
input sdram_clk
);
 
wire tx_fifo_a_dat_i;
wire tx_fifo_we;
wire [2:0] tx_fifo_a_sel_i;
wire [7:0] tx_fifo_full;
wire [35:0] tx_fifo_dat_i, tx_fifo_dat_o, tx_fifo_dat_wb;
wire tx_fifo_we, tx_fifo_re, tx_fifo_wb;
wire [2:0] tx_fifo_a_sel_i, tx_fifo_b_sel_i;
reg [2:0] tx_fifo_b_sel_i_cur;
wire [7:0] tx_fifo_full, tx_fifo_empty;
wire [3:0] burst_adr;
wire adr_init, adr_inc;
wire done;
wire [14:0] a;
wire cs_n;
 
wire ref_req, ref_ack;
// counters to keep track of fifo fill
 
`ifdef PORT0
wire wbs0_flag;
cyc_mask_counter cnt0
ctrl_counter cnt0
(
.clear((&wbs0_cti_i | !|wbs0_cti_i) & (!wbs0_flag | !wbs0_we_i)),
.cke(((tx_fifo_a_sel_i==3'd0)&tx_fifo_a_we) | wbs0_ack_o),
.clear((&wbs0_cti_i | !(|wbs0_cti_i)) & (!wbs0_flag | !wbs0_we_i)),
.cke(((tx_fifo_a_sel_i==3'd0)&tx_fifo_we) | wbs0_ack_o),
.zq(wbs0_flag),
.clk(wb_clk),
.rst(wb_rst)
126,10 → 153,10
 
`ifdef PORT1
wire wbs1_flag;
cyc_mask_counter cnt1
ctrl_counter cnt1
(
.clear((&wbs1_cti_i | !|wbs1_cti_i) & (!wbs1_flag | !wbs1_we_i)),
.cke(((tx_fifo_a_sel_i==3'd1)&tx_fifo_a_we) | wbs1_ack_o),
.clear((&wbs1_cti_i | !(|wbs1_cti_i)) & (!wbs1_flag | !wbs1_we_i)),
.cke(((tx_fifo_a_sel_i==3'd1)&tx_fifo_we) | wbs1_ack_o),
.zq(wbs1_flag),
.clk(wb_clk),
.rst(wb_rst)
138,10 → 165,10
 
`ifdef PORT2
wire wbs2_flag;
cyc_mask_counter cnt2
ctrl_counter cnt2
(
.clear((&wbs2_cti_i | !|wbs2_cti_i) & (!wbs2_flag | !wbs2_we_i)),
.cke(((tx_fifo_a_sel_i==3'd2)&tx_fifo_a_we) | wbs2_ack_o),
.clear((&wbs2_cti_i | !(|wbs2_cti_i)) & (!wbs2_flag | !wbs2_we_i)),
.cke(((tx_fifo_a_sel_i==3'd2)&tx_fifo_we) | wbs2_ack_o),
.zq(wbs2_flag),
.clk(wb_clk),
.rst(wb_rst)
150,10 → 177,10
 
`ifdef PORT3
wire wbs3_flag;
cyc_mask_counter cnt3
ctrl_counter cnt3
(
.clear((&wbs3_cti_i | !|wbs3_cti_i) & (!wbs3_flag | !wbs3_we_i)),
.cke(((tx_fifo_a_sel_i==3'd3)&tx_fifo_a_we) | wbs3_ack_o),
.clear((&wbs3_cti_i | !(|wbs3_cti_i)) & (!wbs3_flag | !wbs3_we_i)),
.cke(((tx_fifo_a_sel_i==3'd3)&tx_fifo_we) | wbs3_ack_o),
.zq(wbs0_flag),
.clk(wb_clk),
.rst(wb_rst)
162,10 → 189,10
 
`ifdef PORT4
wire wbs4_flag;
cyc_mask_counter cnt4
ctrl_counter cnt4
(
.clear((&wbs4_cti_i | !|wbs4_cti_i) & (!wbs4_flag | !wbs4_we_i)),
.cke(((tx_fifo_a_sel_i==3'd4)&tx_fifo_a_we) | wbs4_ack_o),
.clear((&wbs4_cti_i | !(|wbs4_cti_i)) & (!wbs4_flag | !wbs4_we_i)),
.cke(((tx_fifo_a_sel_i==3'd4)&tx_fifo_we) | wbs4_ack_o),
.zq(wbs4_flag),
.clk(wb_clk),
.rst(wb_rst)
174,10 → 201,10
 
`ifdef PORT5
wire wbs5_flag;
cyc_mask_counter cnt5
ctrl_counter cnt5
(
.clear((&wbs5_cti_i | !|wbs5_cti_i) & (!wbs5_flag | !wbs5_we_i)),
.cke(((tx_fifo_a_sel_i==3'd5)&tx_fifo_a_we) | wbs5_ack_o),
.clear((&wbs5_cti_i | !(|wbs5_cti_i)) & (!wbs5_flag | !wbs5_we_i)),
.cke(((tx_fifo_a_sel_i==3'd5)&tx_fifo_we) | wbs5_ack_o),
.zq(wbs5_flag),
.clk(wb_clk),
.rst(wb_rst)
186,10 → 213,10
 
`ifdef PORT6
wire wbs6_flag;
cyc_mask_counter cnt6
ctrl_counter cnt6
(
.clear((&wbs6_cti_i | !|wbs6_cti_i) & (!wbs6_flag | !wbs6_we_i)),
.cke(((tx_fifo_a_sel_i==3'd6)&tx_fifo_a_we) | wbs6_ack_o),
.clear((&wbs6_cti_i | !(|wbs6_cti_i)) & (!wbs6_flag | !wbs6_we_i)),
.cke(((tx_fifo_a_sel_i==3'd6)&tx_fifo_we) | wbs6_ack_o),
.zq(wbs6_flag),
.clk(wb_clk),
.rst(wb_rst)
198,10 → 225,10
 
`ifdef PORT7
wire wbs7_flag;
cyc_mask_counter cnt7
ctrl_counter cnt7
(
.clear((&wbs7_cti_i | !|wbs7_cti_i) & (!wbs7_flag | !wbs7_we_i)),
.cke(((tx_fifo_a_sel_i==3'd7)&tx_fifo_a_we) | wbs7_ack_o),
.clear((&wbs7_cti_i | !(|wbs7_cti_i)) & (!wbs7_flag | !wbs7_we_i)),
.cke(((tx_fifo_a_sel_i==3'd7)&tx_fifo_we) | wbs7_ack_o),
.zq(wbs7_flag),
.clk(wb_clk),
.rst(wb_rst)
298,25 → 325,137
`endif
{wbs0_adr_i,wbs0_we_i,wbs0_bte_i,wbs0_cti_i};
 
fifo tx_fifo
(
// A side
.a_dat_i(tx_fifo_dat_i),
.a_we_i(tx_fifo_we),
.a_fifo_sel_i(tx_fifo_a_sel_i),
.a_fifo_full_o(tx_fifo_full),
.a_clk(wb_clk),
// B side
.b_dat_o(),
.b_dat_i(),
.b_we_i(),
.b_re_i(),
.b_fifo_sel_i(),
.b_fifo_empty_o(),
.b_clk(sdram_clk),
// misc
.rst(wb_rst)
);
fifo tx_fifo
(
// A side
.a_dat_i(tx_fifo_dat_i),
.a_we_i(tx_fifo_we),
.a_fifo_sel_i(tx_fifo_a_sel_i),
.a_fifo_full_o(tx_fifo_full),
.a_clk(wb_clk),
// B side
.b_dat_o(tx_fifo_dat_o),
.b_re_i(tx_fifo_re),
.b_fifo_sel_i(tx_fifo_b_sel_i),
.b_fifo_empty_o(tx_fifo_empty),
.b_clk(sdram_clk),
// misc
.rst(wb_rst)
);
assign tx_fifo_b_sel_i
=
(adr_init & !tx_fifo_empty[4]) ? 3'd4 :
(adr_init & !tx_fifo_empty[5]) ? 3'd5 :
(adr_init & !tx_fifo_empty[6]) ? 3'd6 :
(adr_init & !tx_fifo_empty[7]) ? 3'd7 :
(adr_init & !tx_fifo_empty[0]) ? 3'd0 :
(adr_init & !tx_fifo_empty[1]) ? 3'd1 :
(adr_init & !tx_fifo_empty[2]) ? 3'd2 :
(adr_init & !tx_fifo_empty[3]) ? 3'd3 :
tx_fifo_b_sel_i_cur;
 
always @ (posedge sdram_clk or posedge wb_rst)
if (wb_rst)
tx_fifo_b_sel_i_cur <= 3'd0;
else if (adr_init)
tx_fifo_b_sel_i_cur <= tx_fifo_b_sel_i;
inc_adr inc_adr0
(
.adr_i(tx_fifo_dat_o[9:6]),
.bte_i(tx_fifo_dat_o[4:3]),
.cti_i(tx_fifo_dat_o[2:0]),
.fifo_empty(tx_fifo_empty),
.init(adr_init),
.inc(adr_inc),
.adr_o(burst_adr),
.done(done),
.clk(sdram_clk),
.rst(wb_rst)
);
 
`ifdef SDR_16
reg dq_oe, dq_flag;
wire [2:0] cmd;
 
ref_counter ref_counter0
(
.zq(ref_req),
.clk(sdram_clk),
.rst(wb_rst)
);
// SDR SDRAM 16 FSM
sdr_16 sdr_16_0
(
.adr_inc(adr_inc),
.adr_init(adr_init),
.fifo_re(tx_fifo_re),
.ba(`BA),
.row(`ROW),
.col(`COL),
.we(tx_fifo_dat_o[5]),
.done(done),
.fifo_empty(tx_fifo_empty),
.fifo_sel(tx_fifo_b_sel_i_cur),
// refresh
.ref_req(ref_req),
.ref_ack(ref_ack),
// sdram
.a(a),
.cmd(cmd),
.cs_n(cs_n),
.sdram_clk(sdram_clk),
.wb_rst(wb_rst)
);
 
always @ (posedge sdram_clk or posedge wb_rst)
if (wb_rst)
{dq_pad_o,dqm_pad_o,dq_oe,dq_flag} <= {16'h0000,2'b00,1'b0,1'b0};
else
if (cmd == `CMD_WRITE)
{dq_pad_o,dqm_pad_o,dq_oe,dq_flag} <= {tx_fifo_dat_o[35:20],!tx_fifo_dat_o[3:2],1'b1,1'b1};
else if (dq_flag)
{dq_pad_o,dqm_pad_o,dq_oe,dq_flag} <= {tx_fifo_dat_o[19: 4],!tx_fifo_dat_o[1:0],1'b1,1'b0};
else
{dq_oe,dq_flag} <= {1'b0,1'b0};
 
always @ (posedge sdram_clk or posedge wb_rst)
if (wb_rst)
{ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o} <= {2'b00,13'h0,1'b1,`CMD_NOP};
else
{ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o} <= {a,cs_n,cmd};
assign cke = 1'b1;
`endif // `ifdef SDR_16
// ack
`ifdef PORT0
assign wbs0_ack_o = !wbs0_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd0);
`endif
`ifdef PORT1
assign wbs1_ack_o = !wbs1_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd1);
`endif
`ifdef PORT2
assign wbs2_ack_o = !wbs2_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd2);
`endif
`ifdef PORT3
assign wbs3_ack_o = !wbs3_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd3);
`endif
`ifdef PORT4
assign wbs4_ack_o = !wbs4_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd4);
`endif
`ifdef PORT5
assign wbs5_ack_o = !wbs5_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd5);
`endif
`ifdef PORT6
assign wbs6_ack_o = !wbs6_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd6);
`endif
`ifdef PORT7
assign wbs7_ack_o = !wbs7_flag & tx_fifo_we & (tx_fifo_a_sel_i == 3'd7);
`endif
endmodule // wb_sdram_ctrl_top
/versatile_mem_ctrl/trunk/rtl/verilog/fifo.v
1,4 → 1,5
`include "wb_sdram_ctrl_defines.v"
`include "versatile_mem_ctrl_defines.v"
 
module fifo
(
// A side
9,8 → 10,6
input a_clk,
// B side
output [35:0] b_dat_o,
input [35:0] b_dat_i,
input b_we_i,
input b_re_i,
input [2:0] b_fifo_sel_i,
output [7:0] b_fifo_empty_o,
96,7 → 95,7
assign rptr0 = 5'h0;
assign radr0 = 5'h0;
assign a_fifo_full_o[0] = 1'b0;
assign b_fifo_empty_o[0] = 1'b0;
assign b_fifo_empty_o[0] = 1'b1;
`endif // !`ifdef PORT0
// WB#1
140,7 → 139,7
assign rptr1 = 5'h0;
assign radr1 = 5'h0;
assign a_fifo_full_o[1] = 1'b0;
assign b_fifo_empty_o[1] = 1'b0;
assign b_fifo_empty_o[1] = 1'b1;
`endif // !`ifdef PORT1
// WB#2
184,7 → 183,7
assign rptr2 = 5'h0;
assign radr2 = 5'h0;
assign a_fifo_full_o[2] = 1'b0;
assign b_fifo_empty_o[2] = 1'b0;
assign b_fifo_empty_o[2] = 1'b1;
`endif // !`ifdef PORT2
// WB#3
228,7 → 227,7
assign rptr3 = 5'h0;
assign radr3 = 5'h0;
assign a_fifo_full_o[3] = 1'b0;
assign b_fifo_empty_o[3] = 1'b0;
assign b_fifo_empty_o[3] = 1'b1;
`endif // !`ifdef PORT3
// WB#4
272,7 → 271,7
assign rptr4 = 5'h0;
assign radr4 = 5'h0;
assign a_fifo_full_o[4] = 1'b0;
assign b_fifo_empty_o[4] = 1'b0;
assign b_fifo_empty_o[4] = 1'b1;
`endif // !`ifdef PORT4
// WB#5
316,7 → 315,7
assign rptr5 = 5'h0;
assign radr5 = 5'h0;
assign a_fifo_full_o[5] = 1'b0;
assign b_fifo_empty_o[5] = 1'b0;
assign b_fifo_empty_o[5] = 1'b1;
`endif // !`ifdef PORT5
// WB#6
360,7 → 359,7
assign rptr6 = 5'h0;
assign radr6 = 5'h0;
assign a_fifo_full_o[6] = 1'b0;
assign b_fifo_empty_o[6] = 1'b0;
assign b_fifo_empty_o[6] = 1'b1;
`endif // !`ifdef PORT6
// WB#7
404,25 → 403,25
assign rptr7 = 5'h0;
assign radr7 = 5'h0;
assign a_fifo_full_o[7] = 1'b0;
assign b_fifo_empty_o[7] = 1'b0;
assign b_fifo_empty_o[7] = 1'b1;
`endif // !`ifdef PORT7
assign dpram_a_a = (a_fifo_sel_i==2'd0) ? {a_fifo_sel_i,wadr0} :
(a_fifo_sel_i==2'd1) ? {a_fifo_sel_i,wadr1} :
(a_fifo_sel_i==2'd2) ? {a_fifo_sel_i,wadr2} :
(a_fifo_sel_i==2'd3) ? {a_fifo_sel_i,wadr3} :
(a_fifo_sel_i==2'd4) ? {a_fifo_sel_i,wadr4} :
(a_fifo_sel_i==2'd5) ? {a_fifo_sel_i,wadr5} :
(a_fifo_sel_i==2'd6) ? {a_fifo_sel_i,wadr6} :
assign dpram_a_a = (a_fifo_sel_i==3'd0) ? {a_fifo_sel_i,wadr0} :
(a_fifo_sel_i==3'd1) ? {a_fifo_sel_i,wadr1} :
(a_fifo_sel_i==3'd2) ? {a_fifo_sel_i,wadr2} :
(a_fifo_sel_i==3'd3) ? {a_fifo_sel_i,wadr3} :
(a_fifo_sel_i==3'd4) ? {a_fifo_sel_i,wadr4} :
(a_fifo_sel_i==3'd5) ? {a_fifo_sel_i,wadr5} :
(a_fifo_sel_i==3'd6) ? {a_fifo_sel_i,wadr6} :
{a_fifo_sel_i,wadr7} ;
 
assign dpram_a_b = (b_fifo_sel_i==2'd0) ? {b_fifo_sel_i,radr0} :
(b_fifo_sel_i==2'd1) ? {b_fifo_sel_i,radr1} :
(b_fifo_sel_i==2'd2) ? {b_fifo_sel_i,radr2} :
(b_fifo_sel_i==2'd3) ? {b_fifo_sel_i,radr3} :
(b_fifo_sel_i==2'd4) ? {b_fifo_sel_i,radr4} :
(b_fifo_sel_i==2'd5) ? {b_fifo_sel_i,radr5} :
(b_fifo_sel_i==2'd6) ? {b_fifo_sel_i,radr6} :
assign dpram_a_b = (b_fifo_sel_i==3'd0) ? {b_fifo_sel_i,radr0} :
(b_fifo_sel_i==3'd1) ? {b_fifo_sel_i,radr1} :
(b_fifo_sel_i==3'd2) ? {b_fifo_sel_i,radr2} :
(b_fifo_sel_i==3'd3) ? {b_fifo_sel_i,radr3} :
(b_fifo_sel_i==3'd4) ? {b_fifo_sel_i,radr4} :
(b_fifo_sel_i==3'd5) ? {b_fifo_sel_i,radr5} :
(b_fifo_sel_i==3'd6) ? {b_fifo_sel_i,radr6} :
{b_fifo_sel_i,radr7} ;
441,8 → 440,8
.clk_a(a_clk),
.q_b(b_dat_o),
.adr_b(dpram_a_b),
.d_b(b_dat_i),
.we_b(b_we_i),
.d_b(36'h0),
.we_b(1'b0),
.clk_b(b_clk)
);
 
/versatile_mem_ctrl/trunk/rtl/verilog/fifo_adr_counter_defines.v
17,6 → 17,8
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_16.fzm
0,0 → 1,13362
## File last modified by Fizzim: 10:46:28 on 2009-06-24
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## END STATE OBJECT
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def_type
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1
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1
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<stub>
false
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<textObj>
Initialization of SDRAM
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<y>
78
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<page>
2
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<color>
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<type>
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## END STATE TRANSITION OBJECT
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trans37
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trans38
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def_type
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1
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LOCAL
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2
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GLOBAL_VAR
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## END STATE TRANSITION OBJECT
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trans40
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## END STATE TRANSITION OBJECT
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output
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GLOBAL_VAR
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trans42
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## END STATE TRANSITION OBJECT
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trans43
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GLOBAL_VAR
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## END STATE TRANSITION OBJECT
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trans57
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0
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## END STATE TRANSITION OBJECT
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trans60
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0
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## END STATE TRANSITION OBJECT
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GLOBAL_VAR
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GLOBAL_VAR
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/versatile_mem_ctrl/trunk/rtl/verilog/ref_counter_defines.v
0,0 → 1,41
// module name
`define CNT_MODULE_NAME ref_counter
 
// counter type = [BINARY, GRAY, LFSR]
//`define CNT_TYPE_BINARY
//`define CNT_TYPE_GRAY
`define CNT_TYPE_LFSR
 
// q as output
//`define CNT_Q
// for gray type counter optional binary output
//`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 10
 
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
 
// wrap around creates shorter cycle than maximum length
`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'h3ffff
 
// clock enable
//`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
`define CNT_ZQ
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
17,7 → 17,16
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > ctrl_counter.v
 
sdr_16:
perl fizzim.pl -encoding onehot < sdr_16.fzm > tmp1.v
vppreproc --simple tmp1.v > sdr_16.v
 
ref_counter:
cp ref_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > ref_counter.v
 
versatile_mem_ctrl:
vppreproc --simple versatile_mem_ctrl_top.v ctrl_counter.v fifo.v | cat copyright.v - > versatile_mem_ctrl_ip.v
vppreproc --simple versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v fifo_adr_counter.v ctrl_counter.v fifo.v inc_adr.v ref_counter.v sdr_16.v versatile_mem_ctrl_top.v | cat copyright.v - > versatile_mem_ctrl_ip.v
 
all: ctrl_counter dual_port_ram fifo_adr_counter fifo versatile_mem_ctrl
all: ctrl_counter dual_port_ram fifo_adr_counter ref_counter sdr_16 versatile_mem_ctrl

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