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/tags/start/bench/verilog/wb_mast_model.v
0,0 → 1,683
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Master Model ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $
//
// $Date: 2001-10-19 11:04:23 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input clk, rst;
output [31:0] adr;
input [31:0] din;
output [31:0] dout;
output cyc, stb;
output [3:0] sel;
output we;
input ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg [31:0] adr;
reg [31:0] dout;
reg cyc, stb;
reg [3:0] sel;
reg we;
 
reg [31:0] mem[mem_size:0];
integer cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
cyc = 0;
stb = 0;
sel = 4'hx;
we = 1'hx;
cnt = 0;
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
 
task mem_fill;
 
integer n;
begin
cnt = 0;
cnt = 0;
for(n=0;n<mem_size;n=n+1)
begin
mem[n] = $random;
end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input [31:0] a;
input [3:0] s;
input [31:0] d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input [31:0] a;
input [3:0] s;
input delay;
input [31:0] d1;
input [31:0] d2;
input [31:0] d3;
input [31:0] d4;
 
integer delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
adr = $random;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
adr = $random;
for(n=0;n<count;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
if(n!=0) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
//adr = 32'hxxxx_xxxx;
adr = $random;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + count;
end
endtask
 
 
task wb_rmw;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
cnt = cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
// if(n!=0)
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cnt = cnt + wcount;
stb=0;
repeat(delay) @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
cnt = cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
 
cyc = 0;
stb = 0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input [31:0] a;
input [3:0] s;
output [31:0] d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err) @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input [31:0] a;
input [3:0] s;
input delay;
output [31:0] d1;
output [31:0] d2;
output [31:0] d3;
output [31:0] d4;
 
integer delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
adr = $random;
sel = s;
repeat(delay) @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err) @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = $random;
end
endtask
 
 
 
task wb_rd_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hxxxx_xxxx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hffff_ffff;
//adr = 32'hxxxx_xxxx;
adr = $random;
 
cnt = cnt + count;
end
endtask
 
endmodule
/tags/start/bench/verilog/wb_slv_model.v
0,0 → 1,157
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Slave Model ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_slv_model.v,v 1.1.1.1 2001-10-19 11:04:25 rudi Exp $
//
// $Date: 2001-10-19 11:04:25 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:11:29 rudi
// Initial Release
//
//
//
 
`include "wb_model_defines.v"
 
module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input clk, rst;
input [31:0] adr, din;
output [31:0] dout;
input cyc, stb;
input [3:0] sel;
input we;
output ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 13;
parameter sz = (1<<mem_size)-1;
 
reg [31:0] mem[sz:0];
wire mem_re, mem_we;
wire [31:0] tmp;
reg [31:0] dout, tmp2;
 
reg err, rty;
reg [31:0] del_ack;
reg [5:0] delay;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
begin
delay = 0;
err = 0;
rty = 0;
#2;
$display("\nINFO: WISHBONE MEMORY MODEL INSTANTIATED (%m)");
$display(" Memory Size %0d address lines %0d words\n",
mem_size, sz+1);
end
 
assign mem_re = cyc & stb & !we;
assign mem_we = cyc & stb & we;
 
assign tmp = mem[adr[mem_size+1:2]];
 
always @(sel or tmp or mem_re or ack)
if(mem_re & ack)
begin
dout[31:24] <= #1 sel[3] ? tmp[31:24] : 8'hxx;
dout[23:16] <= #1 sel[2] ? tmp[23:16] : 8'hxx;
dout[15:08] <= #1 sel[1] ? tmp[15:08] : 8'hxx;
dout[07:00] <= #1 sel[0] ? tmp[07:00] : 8'hxx;
end
else dout <= #1 32'hzzzz_zzzz;
 
 
always @(sel or tmp or din)
begin
tmp2[31:24] = !sel[3] ? tmp[31:24] : din[31:24];
tmp2[23:16] = !sel[2] ? tmp[23:16] : din[23:16];
tmp2[15:08] = !sel[1] ? tmp[15:08] : din[15:08];
tmp2[07:00] = !sel[0] ? tmp[07:00] : din[07:00];
end
 
always @(posedge clk)
if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;
 
always @(posedge clk)
del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};
 
assign #1 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);
 
task fill_mem;
input mode;
 
integer n, mode;
 
begin
 
for(n=0;n<(sz+1);n=n+1)
begin
case(mode)
0: mem[n] = { ~n[15:0], n[15:0] };
1: mem[n] = $random;
endcase
end
 
end
endtask
 
endmodule
/tags/start/bench/verilog/test_bench_top.v
0,0 → 1,1054
/////////////////////////////////////////////////////////////////////
//// ////
//// Top Level Test Bench ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.1.1.1 2001-10-19 11:04:25 rudi Exp $
//
// $Date: 2001-10-19 11:04:25 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
//
 
 
`include "wb_conmax_defines.v"
 
module test;
 
reg clk;
reg rst;
 
// IO Prototypes
wire [31:0] m0_data_i;
wire [31:0] m0_data_o;
wire [31:0] m0_addr_i;
wire [3:0] m0_sel_i;
wire m0_we_i;
wire m0_cyc_i;
wire m0_stb_i;
wire m0_ack_o;
wire m0_err_o;
wire m0_rty_o;
wire [31:0] m1_data_i;
wire [31:0] m1_data_o;
wire [31:0] m1_addr_i;
wire [3:0] m1_sel_i;
wire m1_we_i;
wire m1_cyc_i;
wire m1_stb_i;
wire m1_ack_o;
wire m1_err_o;
wire m1_rty_o;
wire [31:0] m2_data_i;
wire [31:0] m2_data_o;
wire [31:0] m2_addr_i;
wire [3:0] m2_sel_i;
wire m2_we_i;
wire m2_cyc_i;
wire m2_stb_i;
wire m2_ack_o;
wire m2_err_o;
wire m2_rty_o;
wire [31:0] m3_data_i;
wire [31:0] m3_data_o;
wire [31:0] m3_addr_i;
wire [3:0] m3_sel_i;
wire m3_we_i;
wire m3_cyc_i;
wire m3_stb_i;
wire m3_ack_o;
wire m3_err_o;
wire m3_rty_o;
wire [31:0] m4_data_i;
wire [31:0] m4_data_o;
wire [31:0] m4_addr_i;
wire [3:0] m4_sel_i;
wire m4_we_i;
wire m4_cyc_i;
wire m4_stb_i;
wire m4_ack_o;
wire m4_err_o;
wire m4_rty_o;
wire [31:0] m5_data_i;
wire [31:0] m5_data_o;
wire [31:0] m5_addr_i;
wire [3:0] m5_sel_i;
wire m5_we_i;
wire m5_cyc_i;
wire m5_stb_i;
wire m5_ack_o;
wire m5_err_o;
wire m5_rty_o;
wire [31:0] m6_data_i;
wire [31:0] m6_data_o;
wire [31:0] m6_addr_i;
wire [3:0] m6_sel_i;
wire m6_we_i;
wire m6_cyc_i;
wire m6_stb_i;
wire m6_ack_o;
wire m6_err_o;
wire m6_rty_o;
wire [31:0] m7_data_i;
wire [31:0] m7_data_o;
wire [31:0] m7_addr_i;
wire [3:0] m7_sel_i;
wire m7_we_i;
wire m7_cyc_i;
wire m7_stb_i;
wire m7_ack_o;
wire m7_err_o;
wire m7_rty_o;
wire [31:0] s0_data_i;
wire [31:0] s0_data_o;
wire [31:0] s0_addr_o;
wire [3:0] s0_sel_o;
wire s0_we_o;
wire s0_cyc_o;
wire s0_stb_o;
wire s0_ack_i;
wire s0_err_i;
wire s0_rty_i;
wire [31:0] s1_data_i;
wire [31:0] s1_data_o;
wire [31:0] s1_addr_o;
wire [3:0] s1_sel_o;
wire s1_we_o;
wire s1_cyc_o;
wire s1_stb_o;
wire s1_ack_i;
wire s1_err_i;
wire s1_rty_i;
wire [31:0] s2_data_i;
wire [31:0] s2_data_o;
wire [31:0] s2_addr_o;
wire [3:0] s2_sel_o;
wire s2_we_o;
wire s2_cyc_o;
wire s2_stb_o;
wire s2_ack_i;
wire s2_err_i;
wire s2_rty_i;
wire [31:0] s3_data_i;
wire [31:0] s3_data_o;
wire [31:0] s3_addr_o;
wire [3:0] s3_sel_o;
wire s3_we_o;
wire s3_cyc_o;
wire s3_stb_o;
wire s3_ack_i;
wire s3_err_i;
wire s3_rty_i;
wire [31:0] s4_data_i;
wire [31:0] s4_data_o;
wire [31:0] s4_addr_o;
wire [3:0] s4_sel_o;
wire s4_we_o;
wire s4_cyc_o;
wire s4_stb_o;
wire s4_ack_i;
wire s4_err_i;
wire s4_rty_i;
wire [31:0] s5_data_i;
wire [31:0] s5_data_o;
wire [31:0] s5_addr_o;
wire [3:0] s5_sel_o;
wire s5_we_o;
wire s5_cyc_o;
wire s5_stb_o;
wire s5_ack_i;
wire s5_err_i;
wire s5_rty_i;
wire [31:0] s6_data_i;
wire [31:0] s6_data_o;
wire [31:0] s6_addr_o;
wire [3:0] s6_sel_o;
wire s6_we_o;
wire s6_cyc_o;
wire s6_stb_o;
wire s6_ack_i;
wire s6_err_i;
wire s6_rty_i;
wire [31:0] s7_data_i;
wire [31:0] s7_data_o;
wire [31:0] s7_addr_o;
wire [3:0] s7_sel_o;
wire s7_we_o;
wire s7_cyc_o;
wire s7_stb_o;
wire s7_ack_i;
wire s7_err_i;
wire s7_rty_i;
wire [31:0] s8_data_i;
wire [31:0] s8_data_o;
wire [31:0] s8_addr_o;
wire [3:0] s8_sel_o;
wire s8_we_o;
wire s8_cyc_o;
wire s8_stb_o;
wire s8_ack_i;
wire s8_err_i;
wire s8_rty_i;
wire [31:0] s9_data_i;
wire [31:0] s9_data_o;
wire [31:0] s9_addr_o;
wire [3:0] s9_sel_o;
wire s9_we_o;
wire s9_cyc_o;
wire s9_stb_o;
wire s9_ack_i;
wire s9_err_i;
wire s9_rty_i;
wire [31:0] s10_data_i;
wire [31:0] s10_data_o;
wire [31:0] s10_addr_o;
wire [3:0] s10_sel_o;
wire s10_we_o;
wire s10_cyc_o;
wire s10_stb_o;
wire s10_ack_i;
wire s10_err_i;
wire s10_rty_i;
wire [31:0] s11_data_i;
wire [31:0] s11_data_o;
wire [31:0] s11_addr_o;
wire [3:0] s11_sel_o;
wire s11_we_o;
wire s11_cyc_o;
wire s11_stb_o;
wire s11_ack_i;
wire s11_err_i;
wire s11_rty_i;
wire [31:0] s12_data_i;
wire [31:0] s12_data_o;
wire [31:0] s12_addr_o;
wire [3:0] s12_sel_o;
wire s12_we_o;
wire s12_cyc_o;
wire s12_stb_o;
wire s12_ack_i;
wire s12_err_i;
wire s12_rty_i;
wire [31:0] s13_data_i;
wire [31:0] s13_data_o;
wire [31:0] s13_addr_o;
wire [3:0] s13_sel_o;
wire s13_we_o;
wire s13_cyc_o;
wire s13_stb_o;
wire s13_ack_i;
wire s13_err_i;
wire s13_rty_i;
wire [31:0] s14_data_i;
wire [31:0] s14_data_o;
wire [31:0] s14_addr_o;
wire [3:0] s14_sel_o;
wire s14_we_o;
wire s14_cyc_o;
wire s14_stb_o;
wire s14_ack_i;
wire s14_err_i;
wire s14_rty_i;
wire [31:0] s15_data_i;
wire [31:0] s15_data_o;
wire [31:0] s15_addr_o;
wire [3:0] s15_sel_o;
wire s15_we_o;
wire s15_cyc_o;
wire s15_stb_o;
wire s15_ack_i;
wire s15_err_i;
wire s15_rty_i;
 
 
// Test Bench Variables
reg [31:0] wd_cnt;
integer error_cnt;
integer verbose;
 
// Misc Variables
 
/////////////////////////////////////////////////////////////////////
//
// Defines
//
 
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
 
initial
begin
$timeformat (-9, 1, " ns", 10);
 
$display("\n\n");
$display("*****************************************************");
$display("* WISHBONE Connection Matrix Simulation started ... *");
$display("*****************************************************");
$display("\n");
 
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",test,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
wd_cnt = 0;
error_cnt = 0;
clk = 1;
rst = 1;
verbose = 1;
 
repeat(5) @(posedge clk);
s0.delay = 1;
s1.delay = 1;
s2.delay = 1;
s3.delay = 1;
s4.delay = 1;
s5.delay = 1;
s6.delay = 1;
s7.delay = 1;
s8.delay = 1;
s9.delay = 1;
s10.delay = 1;
s11.delay = 1;
s12.delay = 1;
s13.delay = 1;
s14.delay = 1;
s15.delay = 1;
#1;
rst = 0;
repeat(5) @(posedge clk);
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(1) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Regression Run ... :");
$display(" :....................................................:");
verbose = 0;
 
test_dp1;
test_rf;
test_arb1;
test_arb2;
test_dp2;
 
end
else
if(1) // Debug Tests
begin
$display(" ......................................................");
$display(" : :");
$display(" : Test Debug Testing ... :");
$display(" :....................................................:");
 
test_dp2;
 
end
 
repeat(100) @(posedge clk);
$finish;
end // End of Initial
 
/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//
 
always #5 clk = ~clk;
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(posedge clk)
if(m0_ack_o | m1_ack_o | m2_ack_o | m3_ack_o |
m4_ack_o | m5_ack_o | m6_ack_o | m7_ack_o)
wd_cnt = 0;
else
wd_cnt = wd_cnt +1;
 
always @(wd_cnt)
if(wd_cnt > 5000)
begin
$display("\n*******************************************");
$display("*** ERROR: Watchdog Counter Expired ... ***");
$display("*******************************************\n");
$finish;
end
 
/////////////////////////////////////////////////////////////////////
//
// IO Monitors
//
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE Inter Connect
//
 
wb_conmax_top #(32,
32,
4'hf,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2,
2'd2
) conmax(
.clk_i( clk ),
.rst_i( rst ),
.m0_data_i( m0_data_i ),
.m0_data_o( m0_data_o ),
.m0_addr_i( m0_addr_i ),
.m0_sel_i( m0_sel_i ),
.m0_we_i( m0_we_i ),
.m0_cyc_i( m0_cyc_i ),
.m0_stb_i( m0_stb_i ),
.m0_ack_o( m0_ack_o ),
.m0_err_o( m0_err_o ),
.m0_rty_o( m0_rty_o ),
.m1_data_i( m1_data_i ),
.m1_data_o( m1_data_o ),
.m1_addr_i( m1_addr_i ),
.m1_sel_i( m1_sel_i ),
.m1_we_i( m1_we_i ),
.m1_cyc_i( m1_cyc_i ),
.m1_stb_i( m1_stb_i ),
.m1_ack_o( m1_ack_o ),
.m1_err_o( m1_err_o ),
.m1_rty_o( m1_rty_o ),
.m2_data_i( m2_data_i ),
.m2_data_o( m2_data_o ),
.m2_addr_i( m2_addr_i ),
.m2_sel_i( m2_sel_i ),
.m2_we_i( m2_we_i ),
.m2_cyc_i( m2_cyc_i ),
.m2_stb_i( m2_stb_i ),
.m2_ack_o( m2_ack_o ),
.m2_err_o( m2_err_o ),
.m2_rty_o( m2_rty_o ),
.m3_data_i( m3_data_i ),
.m3_data_o( m3_data_o ),
.m3_addr_i( m3_addr_i ),
.m3_sel_i( m3_sel_i ),
.m3_we_i( m3_we_i ),
.m3_cyc_i( m3_cyc_i ),
.m3_stb_i( m3_stb_i ),
.m3_ack_o( m3_ack_o ),
.m3_err_o( m3_err_o ),
.m3_rty_o( m3_rty_o ),
.m4_data_i( m4_data_i ),
.m4_data_o( m4_data_o ),
.m4_addr_i( m4_addr_i ),
.m4_sel_i( m4_sel_i ),
.m4_we_i( m4_we_i ),
.m4_cyc_i( m4_cyc_i ),
.m4_stb_i( m4_stb_i ),
.m4_ack_o( m4_ack_o ),
.m4_err_o( m4_err_o ),
.m4_rty_o( m4_rty_o ),
.m5_data_i( m5_data_i ),
.m5_data_o( m5_data_o ),
.m5_addr_i( m5_addr_i ),
.m5_sel_i( m5_sel_i ),
.m5_we_i( m5_we_i ),
.m5_cyc_i( m5_cyc_i ),
.m5_stb_i( m5_stb_i ),
.m5_ack_o( m5_ack_o ),
.m5_err_o( m5_err_o ),
.m5_rty_o( m5_rty_o ),
.m6_data_i( m6_data_i ),
.m6_data_o( m6_data_o ),
.m6_addr_i( m6_addr_i ),
.m6_sel_i( m6_sel_i ),
.m6_we_i( m6_we_i ),
.m6_cyc_i( m6_cyc_i ),
.m6_stb_i( m6_stb_i ),
.m6_ack_o( m6_ack_o ),
.m6_err_o( m6_err_o ),
.m6_rty_o( m6_rty_o ),
.m7_data_i( m7_data_i ),
.m7_data_o( m7_data_o ),
.m7_addr_i( m7_addr_i ),
.m7_sel_i( m7_sel_i ),
.m7_we_i( m7_we_i ),
.m7_cyc_i( m7_cyc_i ),
.m7_stb_i( m7_stb_i ),
.m7_ack_o( m7_ack_o ),
.m7_err_o( m7_err_o ),
.m7_rty_o( m7_rty_o ),
.s0_data_i( s0_data_i ),
.s0_data_o( s0_data_o ),
.s0_addr_o( s0_addr_o ),
.s0_sel_o( s0_sel_o ),
.s0_we_o( s0_we_o ),
.s0_cyc_o( s0_cyc_o ),
.s0_stb_o( s0_stb_o ),
.s0_ack_i( s0_ack_i ),
.s0_err_i( s0_err_i ),
.s0_rty_i( s0_rty_i ),
.s1_data_i( s1_data_i ),
.s1_data_o( s1_data_o ),
.s1_addr_o( s1_addr_o ),
.s1_sel_o( s1_sel_o ),
.s1_we_o( s1_we_o ),
.s1_cyc_o( s1_cyc_o ),
.s1_stb_o( s1_stb_o ),
.s1_ack_i( s1_ack_i ),
.s1_err_i( s1_err_i ),
.s1_rty_i( s1_rty_i ),
.s2_data_i( s2_data_i ),
.s2_data_o( s2_data_o ),
.s2_addr_o( s2_addr_o ),
.s2_sel_o( s2_sel_o ),
.s2_we_o( s2_we_o ),
.s2_cyc_o( s2_cyc_o ),
.s2_stb_o( s2_stb_o ),
.s2_ack_i( s2_ack_i ),
.s2_err_i( s2_err_i ),
.s2_rty_i( s2_rty_i ),
.s3_data_i( s3_data_i ),
.s3_data_o( s3_data_o ),
.s3_addr_o( s3_addr_o ),
.s3_sel_o( s3_sel_o ),
.s3_we_o( s3_we_o ),
.s3_cyc_o( s3_cyc_o ),
.s3_stb_o( s3_stb_o ),
.s3_ack_i( s3_ack_i ),
.s3_err_i( s3_err_i ),
.s3_rty_i( s3_rty_i ),
.s4_data_i( s4_data_i ),
.s4_data_o( s4_data_o ),
.s4_addr_o( s4_addr_o ),
.s4_sel_o( s4_sel_o ),
.s4_we_o( s4_we_o ),
.s4_cyc_o( s4_cyc_o ),
.s4_stb_o( s4_stb_o ),
.s4_ack_i( s4_ack_i ),
.s4_err_i( s4_err_i ),
.s4_rty_i( s4_rty_i ),
.s5_data_i( s5_data_i ),
.s5_data_o( s5_data_o ),
.s5_addr_o( s5_addr_o ),
.s5_sel_o( s5_sel_o ),
.s5_we_o( s5_we_o ),
.s5_cyc_o( s5_cyc_o ),
.s5_stb_o( s5_stb_o ),
.s5_ack_i( s5_ack_i ),
.s5_err_i( s5_err_i ),
.s5_rty_i( s5_rty_i ),
.s6_data_i( s6_data_i ),
.s6_data_o( s6_data_o ),
.s6_addr_o( s6_addr_o ),
.s6_sel_o( s6_sel_o ),
.s6_we_o( s6_we_o ),
.s6_cyc_o( s6_cyc_o ),
.s6_stb_o( s6_stb_o ),
.s6_ack_i( s6_ack_i ),
.s6_err_i( s6_err_i ),
.s6_rty_i( s6_rty_i ),
.s7_data_i( s7_data_i ),
.s7_data_o( s7_data_o ),
.s7_addr_o( s7_addr_o ),
.s7_sel_o( s7_sel_o ),
.s7_we_o( s7_we_o ),
.s7_cyc_o( s7_cyc_o ),
.s7_stb_o( s7_stb_o ),
.s7_ack_i( s7_ack_i ),
.s7_err_i( s7_err_i ),
.s7_rty_i( s7_rty_i ),
.s8_data_i( s8_data_i ),
.s8_data_o( s8_data_o ),
.s8_addr_o( s8_addr_o ),
.s8_sel_o( s8_sel_o ),
.s8_we_o( s8_we_o ),
.s8_cyc_o( s8_cyc_o ),
.s8_stb_o( s8_stb_o ),
.s8_ack_i( s8_ack_i ),
.s8_err_i( s8_err_i ),
.s8_rty_i( s8_rty_i ),
.s9_data_i( s9_data_i ),
.s9_data_o( s9_data_o ),
.s9_addr_o( s9_addr_o ),
.s9_sel_o( s9_sel_o ),
.s9_we_o( s9_we_o ),
.s9_cyc_o( s9_cyc_o ),
.s9_stb_o( s9_stb_o ),
.s9_ack_i( s9_ack_i ),
.s9_err_i( s9_err_i ),
.s9_rty_i( s9_rty_i ),
.s10_data_i( s10_data_i ),
.s10_data_o( s10_data_o ),
.s10_addr_o( s10_addr_o ),
.s10_sel_o( s10_sel_o ),
.s10_we_o( s10_we_o ),
.s10_cyc_o( s10_cyc_o ),
.s10_stb_o( s10_stb_o ),
.s10_ack_i( s10_ack_i ),
.s10_err_i( s10_err_i ),
.s10_rty_i( s10_rty_i ),
.s11_data_i( s11_data_i ),
.s11_data_o( s11_data_o ),
.s11_addr_o( s11_addr_o ),
.s11_sel_o( s11_sel_o ),
.s11_we_o( s11_we_o ),
.s11_cyc_o( s11_cyc_o ),
.s11_stb_o( s11_stb_o ),
.s11_ack_i( s11_ack_i ),
.s11_err_i( s11_err_i ),
.s11_rty_i( s11_rty_i ),
.s12_data_i( s12_data_i ),
.s12_data_o( s12_data_o ),
.s12_addr_o( s12_addr_o ),
.s12_sel_o( s12_sel_o ),
.s12_we_o( s12_we_o ),
.s12_cyc_o( s12_cyc_o ),
.s12_stb_o( s12_stb_o ),
.s12_ack_i( s12_ack_i ),
.s12_err_i( s12_err_i ),
.s12_rty_i( s12_rty_i ),
.s13_data_i( s13_data_i ),
.s13_data_o( s13_data_o ),
.s13_addr_o( s13_addr_o ),
.s13_sel_o( s13_sel_o ),
.s13_we_o( s13_we_o ),
.s13_cyc_o( s13_cyc_o ),
.s13_stb_o( s13_stb_o ),
.s13_ack_i( s13_ack_i ),
.s13_err_i( s13_err_i ),
.s13_rty_i( s13_rty_i ),
.s14_data_i( s14_data_i ),
.s14_data_o( s14_data_o ),
.s14_addr_o( s14_addr_o ),
.s14_sel_o( s14_sel_o ),
.s14_we_o( s14_we_o ),
.s14_cyc_o( s14_cyc_o ),
.s14_stb_o( s14_stb_o ),
.s14_ack_i( s14_ack_i ),
.s14_err_i( s14_err_i ),
.s14_rty_i( s14_rty_i ),
.s15_data_i( s15_data_i ),
.s15_data_o( s15_data_o ),
.s15_addr_o( s15_addr_o ),
.s15_sel_o( s15_sel_o ),
.s15_we_o( s15_we_o ),
.s15_cyc_o( s15_cyc_o ),
.s15_stb_o( s15_stb_o ),
.s15_ack_i( s15_ack_i ),
.s15_err_i( s15_err_i ),
.s15_rty_i( s15_rty_i )
);
 
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE Master Models
//
 
wb_mast m0( .clk( clk ),
.rst( ~rst ),
.adr( m0_addr_i ),
.din( m0_data_o ),
.dout( m0_data_i ),
.cyc( m0_cyc_i ),
.stb( m0_stb_i ),
.sel( m0_sel_i ),
.we( m0_we_i ),
.ack( m0_ack_o ),
.err( m0_err_o ),
.rty( m0_rty_o )
);
 
wb_mast m1( .clk( clk ),
.rst( ~rst ),
.adr( m1_addr_i ),
.din( m1_data_o ),
.dout( m1_data_i ),
.cyc( m1_cyc_i ),
.stb( m1_stb_i ),
.sel( m1_sel_i ),
.we( m1_we_i ),
.ack( m1_ack_o ),
.err( m1_err_o ),
.rty( m1_rty_o )
);
 
wb_mast m2( .clk( clk ),
.rst( ~rst ),
.adr( m2_addr_i ),
.din( m2_data_o ),
.dout( m2_data_i ),
.cyc( m2_cyc_i ),
.stb( m2_stb_i ),
.sel( m2_sel_i ),
.we( m2_we_i ),
.ack( m2_ack_o ),
.err( m2_err_o ),
.rty( m2_rty_o )
);
 
wb_mast m3( .clk( clk ),
.rst( ~rst ),
.adr( m3_addr_i ),
.din( m3_data_o ),
.dout( m3_data_i ),
.cyc( m3_cyc_i ),
.stb( m3_stb_i ),
.sel( m3_sel_i ),
.we( m3_we_i ),
.ack( m3_ack_o ),
.err( m3_err_o ),
.rty( m3_rty_o )
);
 
wb_mast m4( .clk( clk ),
.rst( ~rst ),
.adr( m4_addr_i ),
.din( m4_data_o ),
.dout( m4_data_i ),
.cyc( m4_cyc_i ),
.stb( m4_stb_i ),
.sel( m4_sel_i ),
.we( m4_we_i ),
.ack( m4_ack_o ),
.err( m4_err_o ),
.rty( m4_rty_o )
);
 
wb_mast m5( .clk( clk ),
.rst( ~rst ),
.adr( m5_addr_i ),
.din( m5_data_o ),
.dout( m5_data_i ),
.cyc( m5_cyc_i ),
.stb( m5_stb_i ),
.sel( m5_sel_i ),
.we( m5_we_i ),
.ack( m5_ack_o ),
.err( m5_err_o ),
.rty( m5_rty_o )
);
 
wb_mast m6( .clk( clk ),
.rst( ~rst ),
.adr( m6_addr_i ),
.din( m6_data_o ),
.dout( m6_data_i ),
.cyc( m6_cyc_i ),
.stb( m6_stb_i ),
.sel( m6_sel_i ),
.we( m6_we_i ),
.ack( m6_ack_o ),
.err( m6_err_o ),
.rty( m6_rty_o )
);
 
wb_mast m7( .clk( clk ),
.rst( ~rst ),
.adr( m7_addr_i ),
.din( m7_data_o ),
.dout( m7_data_i ),
.cyc( m7_cyc_i ),
.stb( m7_stb_i ),
.sel( m7_sel_i ),
.we( m7_we_i ),
.ack( m7_ack_o ),
.err( m7_err_o ),
.rty( m7_rty_o )
);
 
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE Slave Models
//
 
wb_slv s0( .clk( clk ),
.rst( ~rst ),
.adr( s0_addr_o ),
.din( s0_data_o ),
.dout( s0_data_i ),
.cyc( s0_cyc_o ),
.stb( s0_stb_o ),
.sel( s0_sel_o ),
.we( s0_we_o ),
.ack( s0_ack_i ),
.err( s0_err_i ),
.rty( s0_rty_i )
);
 
wb_slv s1( .clk( clk ),
.rst( ~rst ),
.adr( s1_addr_o ),
.din( s1_data_o ),
.dout( s1_data_i ),
.cyc( s1_cyc_o ),
.stb( s1_stb_o ),
.sel( s1_sel_o ),
.we( s1_we_o ),
.ack( s1_ack_i ),
.err( s1_err_i ),
.rty( s1_rty_i )
);
 
wb_slv s2( .clk( clk ),
.rst( ~rst ),
.adr( s2_addr_o ),
.din( s2_data_o ),
.dout( s2_data_i ),
.cyc( s2_cyc_o ),
.stb( s2_stb_o ),
.sel( s2_sel_o ),
.we( s2_we_o ),
.ack( s2_ack_i ),
.err( s2_err_i ),
.rty( s2_rty_i )
);
 
wb_slv s3( .clk( clk ),
.rst( ~rst ),
.adr( s3_addr_o ),
.din( s3_data_o ),
.dout( s3_data_i ),
.cyc( s3_cyc_o ),
.stb( s3_stb_o ),
.sel( s3_sel_o ),
.we( s3_we_o ),
.ack( s3_ack_i ),
.err( s3_err_i ),
.rty( s3_rty_i )
);
 
wb_slv s4( .clk( clk ),
.rst( ~rst ),
.adr( s4_addr_o ),
.din( s4_data_o ),
.dout( s4_data_i ),
.cyc( s4_cyc_o ),
.stb( s4_stb_o ),
.sel( s4_sel_o ),
.we( s4_we_o ),
.ack( s4_ack_i ),
.err( s4_err_i ),
.rty( s4_rty_i )
);
 
wb_slv s5( .clk( clk ),
.rst( ~rst ),
.adr( s5_addr_o ),
.din( s5_data_o ),
.dout( s5_data_i ),
.cyc( s5_cyc_o ),
.stb( s5_stb_o ),
.sel( s5_sel_o ),
.we( s5_we_o ),
.ack( s5_ack_i ),
.err( s5_err_i ),
.rty( s5_rty_i )
);
 
wb_slv s6( .clk( clk ),
.rst( ~rst ),
.adr( s6_addr_o ),
.din( s6_data_o ),
.dout( s6_data_i ),
.cyc( s6_cyc_o ),
.stb( s6_stb_o ),
.sel( s6_sel_o ),
.we( s6_we_o ),
.ack( s6_ack_i ),
.err( s6_err_i ),
.rty( s6_rty_i )
);
 
wb_slv s7( .clk( clk ),
.rst( ~rst ),
.adr( s7_addr_o ),
.din( s7_data_o ),
.dout( s7_data_i ),
.cyc( s7_cyc_o ),
.stb( s7_stb_o ),
.sel( s7_sel_o ),
.we( s7_we_o ),
.ack( s7_ack_i ),
.err( s7_err_i ),
.rty( s7_rty_i )
);
 
wb_slv s8( .clk( clk ),
.rst( ~rst ),
.adr( s8_addr_o ),
.din( s8_data_o ),
.dout( s8_data_i ),
.cyc( s8_cyc_o ),
.stb( s8_stb_o ),
.sel( s8_sel_o ),
.we( s8_we_o ),
.ack( s8_ack_i ),
.err( s8_err_i ),
.rty( s8_rty_i )
);
 
wb_slv s9( .clk( clk ),
.rst( ~rst ),
.adr( s9_addr_o ),
.din( s9_data_o ),
.dout( s9_data_i ),
.cyc( s9_cyc_o ),
.stb( s9_stb_o ),
.sel( s9_sel_o ),
.we( s9_we_o ),
.ack( s9_ack_i ),
.err( s9_err_i ),
.rty( s9_rty_i )
);
 
wb_slv s10( .clk( clk ),
.rst( ~rst ),
.adr( s10_addr_o ),
.din( s10_data_o ),
.dout( s10_data_i ),
.cyc( s10_cyc_o ),
.stb( s10_stb_o ),
.sel( s10_sel_o ),
.we( s10_we_o ),
.ack( s10_ack_i ),
.err( s10_err_i ),
.rty( s10_rty_i )
);
 
wb_slv s11( .clk( clk ),
.rst( ~rst ),
.adr( s11_addr_o ),
.din( s11_data_o ),
.dout( s11_data_i ),
.cyc( s11_cyc_o ),
.stb( s11_stb_o ),
.sel( s11_sel_o ),
.we( s11_we_o ),
.ack( s11_ack_i ),
.err( s11_err_i ),
.rty( s11_rty_i )
);
 
wb_slv s12( .clk( clk ),
.rst( ~rst ),
.adr( s12_addr_o ),
.din( s12_data_o ),
.dout( s12_data_i ),
.cyc( s12_cyc_o ),
.stb( s12_stb_o ),
.sel( s12_sel_o ),
.we( s12_we_o ),
.ack( s12_ack_i ),
.err( s12_err_i ),
.rty( s12_rty_i )
);
 
wb_slv s13( .clk( clk ),
.rst( ~rst ),
.adr( s13_addr_o ),
.din( s13_data_o ),
.dout( s13_data_i ),
.cyc( s13_cyc_o ),
.stb( s13_stb_o ),
.sel( s13_sel_o ),
.we( s13_we_o ),
.ack( s13_ack_i ),
.err( s13_err_i ),
.rty( s13_rty_i )
);
 
wb_slv s14( .clk( clk ),
.rst( ~rst ),
.adr( s14_addr_o ),
.din( s14_data_o ),
.dout( s14_data_i ),
.cyc( s14_cyc_o ),
.stb( s14_stb_o ),
.sel( s14_sel_o ),
.we( s14_we_o ),
.ack( s14_ack_i ),
.err( s14_err_i ),
.rty( s14_rty_i )
);
 
wb_slv s15( .clk( clk ),
.rst( ~rst ),
.adr( s15_addr_o ),
.din( s15_data_o ),
.dout( s15_data_i ),
.cyc( s15_cyc_o ),
.stb( s15_stb_o ),
.sel( s15_sel_o ),
.we( s15_we_o ),
.ack( s15_ack_i ),
.err( s15_err_i ),
.rty( s15_rty_i )
);
 
`include "tests.v"
 
endmodule
 
/tags/start/bench/verilog/tests.v
0,0 → 1,847
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Matrix Test Cases ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: tests.v,v 1.1.1.1 2001-10-19 11:04:27 rudi Exp $
//
// $Date: 2001-10-19 11:04:27 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
//
 
 
task show_errors;
 
begin
 
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +--------------------+");
 
end
endtask
 
 
task init_all_mem;
 
begin
s0.fill_mem(1);
s1.fill_mem(1);
s2.fill_mem(1);
s3.fill_mem(1);
s4.fill_mem(1);
s5.fill_mem(1);
s6.fill_mem(1);
s7.fill_mem(1);
s8.fill_mem(1);
s9.fill_mem(1);
s10.fill_mem(1);
s11.fill_mem(1);
s12.fill_mem(1);
s13.fill_mem(1);
s14.fill_mem(1);
s15.fill_mem(1);
 
m0.mem_fill;
m1.mem_fill;
m2.mem_fill;
m3.mem_fill;
m4.mem_fill;
m5.mem_fill;
m6.mem_fill;
m7.mem_fill;
 
end
endtask
 
 
task verify;
input master;
input slave;
input count;
 
integer master, slave, count;
begin
verify_sub(master,slave,count,0,0);
end
endtask
 
 
task verify_sub;
input master;
input slave;
input count;
input mo;
input so;
 
integer master, slave, count;
integer mo, so;
integer o;
integer n;
reg [31:0] mdata, sdata;
 
begin
 
//$display("V2: %0d %0d %0d %0d %0d",master, slave, count, mo,so);
 
for(n=0;n<count;n=n+1)
begin
case(master)
0: mdata = m0.mem[n+mo];
1: mdata = m1.mem[n+mo];
2: mdata = m2.mem[n+mo];
3: mdata = m3.mem[n+mo];
4: mdata = m4.mem[n+mo];
5: mdata = m5.mem[n+mo];
6: mdata = m6.mem[n+mo];
7: mdata = m7.mem[n+mo];
default:
begin
$display("ERROR: Illegal Master %0d", master);
$finish;
end
endcase
 
o = 0;
case(master)
0: o = 16'h000;
1: o = 16'h040;
2: o = 16'h080;
3: o = 16'h0c0;
4: o = 16'h100;
5: o = 16'h140;
6: o = 16'h180;
7: o = 16'h1c0;
endcase
 
case(slave)
0: sdata = s0.mem[n+o+so];
1: sdata = s1.mem[n+o+so];
2: sdata = s2.mem[n+o+so];
3: sdata = s3.mem[n+o+so];
4: sdata = s4.mem[n+o+so];
5: sdata = s5.mem[n+o+so];
6: sdata = s6.mem[n+o+so];
7: sdata = s7.mem[n+o+so];
8: sdata = s8.mem[n+o+so];
9: sdata = s9.mem[n+o+so];
10: sdata = s10.mem[n+o+so];
11: sdata = s11.mem[n+o+so];
12: sdata = s12.mem[n+o+so];
13: sdata = s13.mem[n+o+so];
14: sdata = s14.mem[n+o+so];
15: sdata = s15.mem[n+o+so];
default:
begin
$display("ERROR: Illegal Slave %0d", slave);
$finish;
end
endcase
 
//$display("INFO: Master[%0d]: %h - Slave[%0d]: %h (%0t)",
// master, mdata, slave, sdata, $time);
 
if(mdata !== sdata)
begin
$display("ERROR: Master[%0d][%0d]: %h - Slave[%0d]: %h (%0t)",
master, n, mdata, slave, sdata, $time);
error_cnt = error_cnt + 1;
end
end
end
 
endtask
 
 
task test_arb1;
 
integer n, del;
reg [31:0] data;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Arb. 1 Test ... ***");
$display("*****************************************************\n");
 
del = 4;
for(del = 0;del < 5; del=del+1 )
begin
$display("Delay: %0d", del);
init_all_mem;
m1.wb_wr1( 32'hff00_0000, 4'hf, 32'h0000_a5ff);
 
fork
begin
m0.wb_rd_mult( 32'h0000_0000 + (0 << 28), 4'hf, del, 4);
m0.wb_rd1( 32'hff00_0000, 4'hf, data);
if(data !== 32'h0000_a5ff)
begin
$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
error_cnt = error_cnt + 1;
end
m0.wb_wr_mult( 32'h0000_0010 + (0 << 28), 4'hf, del, 4);
m0.wb_rd_mult( 32'h0000_0020 + (0 << 28), 4'hf, del, 4);
m0.wb_wr_mult( 32'h0000_0030 + (0 << 28), 4'hf, del, 4);
end
 
begin
m1.wb_wr_mult( 32'h0000_0100 + (0 << 28), 4'hf, del, 4);
m1.wb_rd_mult( 32'h0000_0110 + (0 << 28), 4'hf, del, 4);
m1.wb_rd1( 32'hff00_0000, 4'hf, data);
if(data !== 32'h0000_a5ff)
begin
$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
error_cnt = error_cnt + 1;
end
m1.wb_wr_mult( 32'h0000_0120 + (0 << 28), 4'hf, del, 4);
m1.wb_rd_mult( 32'h0000_0130 + (0 << 28), 4'hf, del, 4);
end
 
begin
m2.wb_rd_mult( 32'h0000_0200 + (0 << 28), 4'hf, del, 4);
m2.wb_wr_mult( 32'h0000_0210 + (0 << 28), 4'hf, del, 4);
m2.wb_rd_mult( 32'h0000_0220 + (0 << 28), 4'hf, del, 4);
m2.wb_rd1( 32'hff00_0000, 4'hf, data);
if(data !== 32'h0000_a5ff)
begin
$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
error_cnt = error_cnt + 1;
end
m2.wb_wr_mult( 32'h0000_0230 + (0 << 28), 4'hf, del, 4);
end
 
begin
m3.wb_wr_mult( 32'h0000_0300 + (0 << 28), 4'hf, del, 4);
m3.wb_rd_mult( 32'h0000_0310 + (0 << 28), 4'hf, del, 4);
m3.wb_wr_mult( 32'h0000_0320 + (0 << 28), 4'hf, del, 4);
m3.wb_rd_mult( 32'h0000_0330 + (0 << 28), 4'hf, del, 4);
m3.wb_rd1( 32'hff00_0000, 4'hf, data);
if(data !== 32'h0000_a5ff)
begin
$display("ERROR: RF read mismatch: Exp. a5ff, Got %h", data);
error_cnt = error_cnt + 1;
end
end
 
begin
m4.wb_rd_mult( 32'h0000_0400 + (1 << 28), 4'hf, del, 4);
m4.wb_wr_mult( 32'h0000_0410 + (1 << 28), 4'hf, del, 4);
m4.wb_rd_mult( 32'h0000_0420 + (1 << 28), 4'hf, del, 4);
m4.wb_wr_mult( 32'h0000_0430 + (1 << 28), 4'hf, del, 4);
end
 
begin
m5.wb_rd_mult( 32'h0000_0500 + (1 << 28), 4'hf, del, 4);
m5.wb_wr_mult( 32'h0000_0510 + (1 << 28), 4'hf, del, 4);
m5.wb_rd_mult( 32'h0000_0520 + (1 << 28), 4'hf, del, 4);
m5.wb_wr_mult( 32'h0000_0530 + (1 << 28), 4'hf, del, 4);
end
 
begin
m6.wb_wr_mult( 32'h0000_0600 + (15 << 28), 4'hf, del, 4);
m6.wb_rd_mult( 32'h0000_0610 + (15 << 28), 4'hf, del, 4);
m6.wb_wr_mult( 32'h0000_0620 + (15 << 28), 4'hf, del, 4);
m6.wb_rd_mult( 32'h0000_0630 + (15 << 28), 4'hf, del, 4);
end
 
begin
m7.wb_wr_mult( 32'h0000_0700 + (15 << 28), 4'hf, del, 4);
m7.wb_rd_mult( 32'h0000_0710 + (15 << 28), 4'hf, del, 4);
m7.wb_wr_mult( 32'h0000_0720 + (15 << 28), 4'hf, del, 4);
m7.wb_rd_mult( 32'h0000_0730 + (15 << 28), 4'hf, del, 4);
end
join
 
verify(0,0,16);
verify(1,0,16);
verify(2,0,16);
verify(3,0,16);
verify(4,1,16);
verify(5,1,16);
verify(6,15,16);
verify(7,15,16);
end
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
task test_arb2;
 
integer m, del, siz;
integer n, a, b;
time t[0:7];
reg [1:0] p[0:7];
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Arb. 2 Test ... ***");
$display("*****************************************************\n");
 
 
siz = 4;
del = 0;
m=0;
for(m=0;m<32;m=m+1)
for(del=0;del<7;del=del+1)
for(siz=1;siz<5;siz=siz+1)
begin
 
init_all_mem;
$display("Mode: %0d del: %0d, siz: %0d", m, del, siz);
 
case(m)
0:
begin
p[7] = 2'd3; // M 7
p[6] = 2'd1; // M 6
p[5] = 2'd2; // M 5
p[4] = 2'd3; // M 4
p[3] = 2'd0; // M 3
p[2] = 2'd1; // M 2
p[1] = 2'd0; // M 1
p[0] = 2'd2; // M 0
end
 
4:
begin
p[7] = 2'd0; // M 7
p[6] = 2'd1; // M 6
p[5] = 2'd2; // M 5
p[4] = 2'd3; // M 4
p[3] = 2'd3; // M 3
p[2] = 2'd2; // M 2
p[1] = 2'd1; // M 1
p[0] = 2'd0; // M 0
end
 
8:
begin
p[7] = 2'd3; // M 7
p[6] = 2'd2; // M 6
p[5] = 2'd1; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd0; // M 3
p[2] = 2'd1; // M 2
p[1] = 2'd2; // M 1
p[0] = 2'd3; // M 0
end
 
12:
begin
p[7] = 2'd3; // M 7
p[6] = 2'd3; // M 6
p[5] = 2'd3; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd0; // M 3
p[2] = 2'd0; // M 2
p[1] = 2'd1; // M 1
p[0] = 2'd1; // M 0
end
 
16:
begin
p[7] = 2'd0; // M 7
p[6] = 2'd0; // M 6
p[5] = 2'd0; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd1; // M 3
p[2] = 2'd1; // M 2
p[1] = 2'd3; // M 1
p[0] = 2'd3; // M 0
end
 
20:
begin
p[7] = 2'd3; // M 7
p[6] = 2'd0; // M 6
p[5] = 2'd2; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd1; // M 3
p[2] = 2'd0; // M 2
p[1] = 2'd0; // M 1
p[0] = 2'd0; // M 0
end
 
24:
begin
p[7] = 2'd0; // M 7
p[6] = 2'd0; // M 6
p[5] = 2'd1; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd0; // M 3
p[2] = 2'd2; // M 2
p[1] = 2'd0; // M 1
p[0] = 2'd3; // M 0
end
 
28:
begin
p[7] = 2'd0; // M 7
p[6] = 2'd0; // M 6
p[5] = 2'd1; // M 5
p[4] = 2'd0; // M 4
p[3] = 2'd0; // M 3
p[2] = 2'd0; // M 2
p[1] = 2'd0; // M 1
p[0] = 2'd3; // M 0
end
 
default:
begin
p[7] = p[7] + 1;// M 7
p[6] = p[6] + 1;// M 6
p[5] = p[5] + 1;// M 5
p[4] = p[4] + 1;// M 4
p[3] = p[3] + 1;// M 3
p[2] = p[2] + 1;// M 2
p[1] = p[1] + 1;// M 1
p[0] = p[0] + 1;// M 0
end
endcase
 
m1.wb_wr1( 32'hff00_0000, 4'hf, {16'h0000, p[7], p[6], p[5],
p[4], p[3], p[2], p[1], p[0]} );
 
@(posedge clk);
fork
begin
repeat(del) @(posedge clk);
m0.wb_wr_mult( 32'h0000_0000 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m0.wb_rd_mult( 32'h0000_0000 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m0.wb_wr_mult( 32'h0000_0000 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m0.wb_rd_mult( 32'h0000_0000 + (siz * 12), 4'hf, del, siz);
t[0] = $time;
end
 
begin
repeat(del) @(posedge clk);
m1.wb_rd_mult( 32'h0000_0100 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m1.wb_wr_mult( 32'h0000_0100 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m1.wb_rd_mult( 32'h0000_0100 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m1.wb_wr_mult( 32'h0000_0100 + (siz * 12), 4'hf, del, siz);
t[1] = $time;
end
 
begin
repeat(del) @(posedge clk);
m2.wb_wr_mult( 32'h0000_0200 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m2.wb_rd_mult( 32'h0000_0200 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m2.wb_wr_mult( 32'h0000_0200 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m2.wb_rd_mult( 32'h0000_0200 + (siz * 12), 4'hf, del, siz);
t[2] = $time;
end
 
begin
repeat(del) @(posedge clk);
m3.wb_rd_mult( 32'h0000_0300 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m3.wb_wr_mult( 32'h0000_0300 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m3.wb_rd_mult( 32'h0000_0300 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m3.wb_wr_mult( 32'h0000_0300 + (siz * 12), 4'hf, del, siz);
t[3] = $time;
end
 
begin
repeat(del) @(posedge clk);
m4.wb_wr_mult( 32'h0000_0400 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m4.wb_rd_mult( 32'h0000_0400 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m4.wb_wr_mult( 32'h0000_0400 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m4.wb_rd_mult( 32'h0000_0400 + (siz * 12), 4'hf, del, siz);
t[4] = $time;
end
 
begin
repeat(del) @(posedge clk);
m5.wb_rd_mult( 32'h0000_0500 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m5.wb_wr_mult( 32'h0000_0500 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m5.wb_rd_mult( 32'h0000_0500 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m5.wb_wr_mult( 32'h0000_0500 + (siz * 12), 4'hf, del, siz);
t[5] = $time;
end
 
begin
repeat(del) @(posedge clk);
m6.wb_wr_mult( 32'h0000_0600 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m6.wb_rd_mult( 32'h0000_0600 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m6.wb_wr_mult( 32'h0000_0600 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m6.wb_rd_mult( 32'h0000_0600 + (siz * 12), 4'hf, del, siz);
t[6] = $time;
end
 
begin
repeat(del) @(posedge clk);
m7.wb_wr_mult( 32'h0000_0700 , 4'hf, del, siz);
repeat(del) @(posedge clk);
m7.wb_rd_mult( 32'h0000_0700 + (siz * 4), 4'hf, del, siz);
repeat(del) @(posedge clk);
m7.wb_wr_mult( 32'h0000_0700 + (siz * 8), 4'hf, del, siz);
repeat(del) @(posedge clk);
m7.wb_rd_mult( 32'h0000_0700 + (siz * 12), 4'hf, del, siz);
t[7] = $time;
end
 
join
 
verify(0,0,siz*4);
verify(1,0,siz*4);
verify(2,0,siz*4);
verify(3,0,siz*4);
verify(4,0,siz*4);
verify(5,0,siz*4);
verify(6,0,siz*4);
verify(7,0,siz*4);
 
for(a=0;a<8;a=a+1)
for(b=0;b<8;b=b+1)
if((t[a] < t[b]) & (p[a] <= p[b]) & (p[a] != p[b]) )
begin
$display("ERROR: Master %0d compleated before Master %0d", a, b);
$display(" M[%0d] pri: %0d (t: %0t)", a, p[a], t[a]);
$display(" M[%0d] pri: %0d (t: %0t)", b, p[b], t[b]);
error_cnt = error_cnt + 1;
end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task test_dp1;
 
integer n;
reg [3:0] s0, s1, s2, s3, s4, s5, s6, s7;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Datapath 1 Test ... ***");
$display("*****************************************************\n");
 
s0 = 0;
s1 = 1;
s2 = 2;
s3 = 3;
s4 = 4;
s5 = 5;
s6 = 6;
s7 = 7;
 
for(n=0;n<16;n=n+1)
begin
init_all_mem;
$display("Mode: %0d", n);
 
fork
 
begin
m0.wb_wr_mult( 32'h0000_0000 + (s0 << 28), 4'hf, 0, 4);
m0.wb_rd_mult( 32'h0000_0010 + (s0 << 28), 4'hf, 0, 4);
m0.wb_wr_mult( 32'h0000_0020 + (s0 << 28), 4'hf, 0, 4);
m0.wb_rd_mult( 32'h0000_0030 + (s0 << 28), 4'hf, 0, 4);
end
 
begin
m1.wb_wr_mult( 32'h0000_0100 + (s1 << 28), 4'hf, 0, 4);
m1.wb_rd_mult( 32'h0000_0110 + (s1 << 28), 4'hf, 0, 4);
m1.wb_wr_mult( 32'h0000_0120 + (s1 << 28), 4'hf, 0, 4);
m1.wb_rd_mult( 32'h0000_0130 + (s1 << 28), 4'hf, 0, 4);
end
 
begin
m2.wb_wr_mult( 32'h0000_0200 + (s2 << 28), 4'hf, 0, 4);
m2.wb_rd_mult( 32'h0000_0210 + (s2 << 28), 4'hf, 0, 4);
m2.wb_wr_mult( 32'h0000_0220 + (s2 << 28), 4'hf, 0, 4);
m2.wb_rd_mult( 32'h0000_0230 + (s2 << 28), 4'hf, 0, 4);
end
 
begin
m3.wb_wr_mult( 32'h0000_0300 + (s3 << 28), 4'hf, 0, 4);
m3.wb_rd_mult( 32'h0000_0310 + (s3 << 28), 4'hf, 0, 4);
m3.wb_wr_mult( 32'h0000_0320 + (s3 << 28), 4'hf, 0, 4);
m3.wb_rd_mult( 32'h0000_0330 + (s3 << 28), 4'hf, 0, 4);
end
 
begin
m4.wb_wr_mult( 32'h0000_0400 + (s4 << 28), 4'hf, 0, 4);
m4.wb_rd_mult( 32'h0000_0410 + (s4 << 28), 4'hf, 0, 4);
m4.wb_wr_mult( 32'h0000_0420 + (s4 << 28), 4'hf, 0, 4);
m4.wb_rd_mult( 32'h0000_0430 + (s4 << 28), 4'hf, 0, 4);
end
 
begin
m5.wb_wr_mult( 32'h0000_0500 + (s5 << 28), 4'hf, 0, 4);
m5.wb_rd_mult( 32'h0000_0510 + (s5 << 28), 4'hf, 0, 4);
m5.wb_wr_mult( 32'h0000_0520 + (s5 << 28), 4'hf, 0, 4);
m5.wb_rd_mult( 32'h0000_0530 + (s5 << 28), 4'hf, 0, 4);
end
 
begin
m6.wb_wr_mult( 32'h0000_0600 + (s6 << 28), 4'hf, 0, 4);
m6.wb_rd_mult( 32'h0000_0610 + (s6 << 28), 4'hf, 0, 4);
m6.wb_wr_mult( 32'h0000_0620 + (s6 << 28), 4'hf, 0, 4);
m6.wb_rd_mult( 32'h0000_0630 + (s6 << 28), 4'hf, 0, 4);
end
 
begin
m7.wb_wr_mult( 32'h0000_0700 + (s7 << 28), 4'hf, 0, 4);
m7.wb_rd_mult( 32'h0000_0710 + (s7 << 28), 4'hf, 0, 4);
m7.wb_wr_mult( 32'h0000_0720 + (s7 << 28), 4'hf, 0, 4);
m7.wb_rd_mult( 32'h0000_0730 + (s7 << 28), 4'hf, 0, 4);
end
 
join
 
verify(0,s0,16);
verify(1,s1,16);
verify(2,s2,16);
verify(3,s3,16);
verify(4,s4,16);
verify(5,s5,16);
verify(6,s6,16);
verify(7,s7,16);
 
@(posedge clk);
 
s0 = s0 + 1;
s1 = s1 + 1;
s2 = s2 + 1;
s3 = s3 + 1;
s4 = s4 + 1;
s5 = s5 + 1;
s6 = s6 + 1;
s7 = s7 + 1;
 
@(posedge clk);
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
task test_dp2;
 
integer del;
integer x0, x1, x2, x3, x4, x5, x6, x7;
reg [3:0] m;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Datapath 2 Test ... ***");
$display("*****************************************************\n");
 
del=0;
for(del=0;del<5;del=del+1)
begin
init_all_mem;
$display("Delay: %0d", del);
 
fork
 
begin
for(x0=0;x0<16;x0=x0+1)
m0.wb_rd_mult( 32'h0000_0000 + ((0+x0) << 28) + (x0<<4), 4'hf, del, 4);
end
 
begin
for(x1=0;x1<16;x1=x1+1)
m1.wb_rd_mult( 32'h0000_0100 + ((1+x1) << 28) + (x1<<4), 4'hf, del, 4);
end
 
begin
for(x2=0;x2<16;x2=x2+1)
m2.wb_rd_mult( 32'h0000_0200 + ((2+x2) << 28) + (x2<<4), 4'hf, del, 4);
 
end
 
begin
for(x3=0;x3<16;x3=x3+1)
m3.wb_rd_mult( 32'h0000_0300 + ((3+x3) << 28) + (x3<<4), 4'hf, del, 4);
end
 
begin
for(x4=0;x4<16;x4=x4+1)
m4.wb_rd_mult( 32'h0000_0400 + ((4+x4) << 28) + (x4<<4), 4'hf, del, 4);
end
 
begin
for(x5=0;x5<16;x5=x5+1)
m5.wb_rd_mult( 32'h0000_0500 + ((5+x5) << 28) + (x5<<4), 4'hf, del, 4);
end
 
begin
for(x6=0;x6<16;x6=x6+1)
m6.wb_rd_mult( 32'h0000_0600 + ((6+x6) << 28) + (x6<<4), 4'hf, del, 4);
end
 
begin
for(x7=0;x7<16;x7=x7+1)
m7.wb_rd_mult( 32'h0000_0700 + ((7+x7) << 28) + (x7<<4), 4'hf, del, 4);
end
join
 
for(x1=0;x1<8;x1=x1+1)
for(x0=0;x0<16;x0=x0+1)
begin
m = x0+x1;
verify_sub(x1,m,4,(x0*4),(x0*4));
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
task test_rf;
 
integer n, m;
reg [31:0] wdata[0:15];
reg [31:0] rdata[0:15];
reg [15:0] rtmp, wtmp;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Register File Test ... ***");
$display("*****************************************************\n");
 
for(m=0;m<5;m=m+1)
begin
$display("Mode: %0d", m);
 
for(n=0;n<16;n=n+1)
wdata[n] = $random;
 
for(n=0;n<16;n=n+1)
case(m)
0: m0.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
1: m3.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
2: m5.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
3: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
4: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
endcase
 
for(n=0;n<16;n=n+1)
case(m)
0: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
1: m3.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
2: m6.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
3: m0.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
4: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
endcase
 
for(n=0;n<16;n=n+1)
begin
rtmp = rdata[n];
wtmp = wdata[n];
if(rtmp !== wtmp)
begin
$display("ERROR: RF[%0d] Mismatch. Expected: %h, Got: %h (%0t)",
n, wtmp, rtmp, $time);
end
end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
 
end
endtask
 
/tags/start/bench/verilog/wb_model_defines.v
0,0 → 1,54
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Model Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_model_defines.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $
//
// $Date: 2001-10-19 11:04:23 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
//
 
`timescale 1ns / 10ps
/tags/start/mast1.pl
0,0 → 1,53
#!/bin/perl
 
 
for($n=16;$n<16;$n++) {
 
printf(" // Slave %0d Interface\n", $n );
printf(" s%0d_data_i, s%0d_data_o, s%0d_addr_o, s%0d_sel_o, s%0d_we_o, s%0d_cyc_o,\n", $n, $n, $n, $n, $n, $n );
printf(" s%0d_stb_o, s%0d_ack_i, s%0d_err_i, s%0d_rty_i,\n\n", $n, $n, $n, $n );
 
}
 
for($n=0;$n<8;$n++) {
 
printf("// Master %0d Interface\n", $n);
printf("input [dw-1:0] m%0d_data_i;\n", $n);
printf("output [dw-1:0] m%0d_data_o;\n", $n);
printf("input [aw-1:0] m%0d_addr_i;\n", $n);
printf("input [sw-1:0] m%0d_sel_i;\n", $n);
printf("input m%0d_we_i;\n", $n);
printf("input m%0d_cyc_i;\n", $n);
printf("input m%0d_stb_i;\n", $n);
printf("output m%0d_ack_o;\n", $n);
printf("output m%0d_err_o;\n", $n);
printf("output m%0d_rty_o;\n\n", $n);
 
}
 
for($n=0;$n<16;$n++) {
 
printf("// Slave %0d Interface\n", $n);
printf("input [dw-1:0] s%0d_data_i;\n", $n);
printf("output [dw-1:0] s%0d_data_o;\n", $n);
printf("output [aw-1:0] s%0d_addr_o;\n", $n);
printf("output [sw-1:0] s%0d_sel_o;\n", $n);
printf("output s%0d_we_o;\n", $n);
printf("output s%0d_cyc_o;\n", $n);
printf("output s%0d_stb_o;\n", $n);
printf("input s%0d_ack_i;\n", $n);
printf("input s%0d_err_i;\n", $n);
printf("input s%0d_rty_i;\n\n", $n);
 
 
}
 
 
for($n=8;$n<8;$n++) {
 
printf(" // Master %0d Interface\n", $n );
printf(" m%0d_data_i, m%0d_data_o, m%0d_addr_i, m%0d_sel_i, m%0d_we_i, m%0d_cyc_i,\n", $n, $n, $n, $n, $n, $n );
printf(" m%0d_stb_i, m%0d_ack_o, m%0d_err_o, m%0d_rty_o,\n\n", $n, $n, $n, $n );
 
}
 
tags/start/mast1.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/start/slv1.pl =================================================================== --- tags/start/slv1.pl (nonexistent) +++ tags/start/slv1.pl (revision 3) @@ -0,0 +1,180 @@ + +for($n=0;$n<8;$n++) { + +printf("wb_ic_master_if m%0d(\n",$n); +printf(" .clk_i( clk_i ),\n",$n); +printf(" .rst_i( rst_i ),\n",$n); +printf(" .wb_data_i( m%0d_data_i ),\n",$n); +printf(" .wb_data_o( m%0d_data_o ),\n",$n); +printf(" .wb_addr_i( m%0d_addr_i ),\n",$n); +printf(" .wb_sel_i( m%0d_sel_i ),\n",$n); +printf(" .wb_we_i( m%0d_we_i ),\n",$n); +printf(" .wb_cyc_i( m%0d_cyc_i ),\n",$n); +printf(" .wb_stb_i( m%0d_stb_i ),\n",$n); +printf(" .wb_ack_o( m%0d_ack_o ),\n",$n); +printf(" .wb_err_o( m%0d_err_o ),\n",$n); +printf(" .wb_rty_o( m%0d_rty_o ),\n",$n); +printf(" .s0_data_i( m%0ds0_data_i ),\n",$n); +printf(" .s0_data_o( m%0ds0_data_o ),\n",$n); +printf(" .s0_addr_o( m%0ds0_addr ),\n",$n); +printf(" .s0_sel_o( m%0ds0_sel ),\n",$n); +printf(" .s0_we_o( m%0ds0_we ),\n",$n); +printf(" .s0_cyc_o( m%0ds0_cyc ),\n",$n); +printf(" .s0_stb_o( m%0ds0_stb ),\n",$n); +printf(" .s0_ack_i( m%0ds0_ack ),\n",$n); +printf(" .s0_err_i( m%0ds0_err ),\n",$n); +printf(" .s0_rty_i( m%0ds0_rty ),\n",$n); +printf(" .s1_data_i( m%0ds1_data_i ),\n",$n); +printf(" .s1_data_o( m%0ds1_data_o ),\n",$n); +printf(" .s1_addr_o( m%0ds1_addr ),\n",$n); +printf(" .s1_sel_o( m%0ds1_sel ),\n",$n); +printf(" .s1_we_o( m%0ds1_we ),\n",$n); +printf(" .s1_cyc_o( m%0ds1_cyc ),\n",$n); +printf(" .s1_stb_o( m%0ds1_stb ),\n",$n); +printf(" .s1_ack_i( m%0ds1_ack ),\n",$n); +printf(" .s1_err_i( m%0ds1_err ),\n",$n); +printf(" .s1_rty_i( m%0ds1_rty ),\n",$n); +printf(" .s2_data_i( m%0ds2_data_i ),\n",$n); +printf(" .s2_data_o( m%0ds2_data_o ),\n",$n); +printf(" .s2_addr_o( m%0ds2_addr ),\n",$n); +printf(" .s2_sel_o( m%0ds2_sel ),\n",$n); +printf(" .s2_we_o( m%0ds2_we ),\n",$n); +printf(" .s2_cyc_o( m%0ds2_cyc ),\n",$n); +printf(" .s2_stb_o( m%0ds2_stb ),\n",$n); +printf(" .s2_ack_i( m%0ds2_ack ),\n",$n); +printf(" .s2_err_i( m%0ds2_err ),\n",$n); +printf(" .s2_rty_i( m%0ds2_rty ),\n",$n); +printf(" .s3_data_i( m%0ds3_data_i ),\n",$n); +printf(" .s3_data_o( m%0ds3_data_o ),\n",$n); +printf(" .s3_addr_o( m%0ds3_addr ),\n",$n); +printf(" .s3_sel_o( m%0ds3_sel ),\n",$n); +printf(" .s3_we_o( m%0ds3_we ),\n",$n); +printf(" .s3_cyc_o( m%0ds3_cyc ),\n",$n); +printf(" .s3_stb_o( m%0ds3_stb ),\n",$n); +printf(" .s3_ack_i( m%0ds3_ack ),\n",$n); +printf(" .s3_err_i( m%0ds3_err ),\n",$n); +printf(" .s3_rty_i( m%0ds3_rty ),\n",$n); +printf(" .s4_data_i( m%0ds4_data_i ),\n",$n); +printf(" .s4_data_o( m%0ds4_data_o ),\n",$n); +printf(" .s4_addr_o( m%0ds4_addr ),\n",$n); +printf(" .s4_sel_o( m%0ds4_sel ),\n",$n); +printf(" .s4_we_o( m%0ds4_we ),\n",$n); +printf(" .s4_cyc_o( m%0ds4_cyc ),\n",$n); +printf(" .s4_stb_o( m%0ds4_stb ),\n",$n); +printf(" .s4_ack_i( m%0ds4_ack ),\n",$n); +printf(" .s4_err_i( m%0ds4_err ),\n",$n); +printf(" .s4_rty_i( m%0ds4_rty ),\n",$n); +printf(" .s5_data_i( m%0ds5_data_i ),\n",$n); +printf(" .s5_data_o( m%0ds5_data_o ),\n",$n); +printf(" .s5_addr_o( m%0ds5_addr ),\n",$n); +printf(" .s5_sel_o( m%0ds5_sel ),\n",$n); +printf(" .s5_we_o( m%0ds5_we ),\n",$n); +printf(" .s5_cyc_o( m%0ds5_cyc ),\n",$n); +printf(" .s5_stb_o( m%0ds5_stb ),\n",$n); +printf(" .s5_ack_i( m%0ds5_ack ),\n",$n); +printf(" .s5_err_i( m%0ds5_err ),\n",$n); +printf(" .s5_rty_i( m%0ds5_rty ),\n",$n); +printf(" .s6_data_i( m%0ds6_data_i ),\n",$n); +printf(" .s6_data_o( m%0ds6_data_o ),\n",$n); +printf(" .s6_addr_o( m%0ds6_addr ),\n",$n); +printf(" .s6_sel_o( m%0ds6_sel ),\n",$n); +printf(" .s6_we_o( m%0ds6_we ),\n",$n); +printf(" .s6_cyc_o( m%0ds6_cyc ),\n",$n); +printf(" .s6_stb_o( m%0ds6_stb ),\n",$n); +printf(" .s6_ack_i( m%0ds6_ack ),\n",$n); +printf(" .s6_err_i( m%0ds6_err ),\n",$n); +printf(" .s6_rty_i( m%0ds6_rty ),\n",$n); +printf(" .s7_data_i( m%0ds7_data_i ),\n",$n); +printf(" .s7_data_o( m%0ds7_data_o ),\n",$n); +printf(" .s7_addr_o( m%0ds7_addr ),\n",$n); +printf(" .s7_sel_o( m%0ds7_sel ),\n",$n); +printf(" .s7_we_o( m%0ds7_we ),\n",$n); +printf(" .s7_cyc_o( m%0ds7_cyc ),\n",$n); +printf(" .s7_stb_o( m%0ds7_stb ),\n",$n); +printf(" .s7_ack_i( m%0ds7_ack ),\n",$n); +printf(" .s7_err_i( m%0ds7_err ),\n",$n); +printf(" .s7_rty_i( m%0ds7_rty ),\n",$n); +printf(" .s8_data_i( m%0ds8_data_i ),\n",$n); +printf(" .s8_data_o( m%0ds8_data_o ),\n",$n); +printf(" .s8_addr_o( m%0ds8_addr ),\n",$n); +printf(" .s8_sel_o( m%0ds8_sel ),\n",$n); +printf(" .s8_we_o( m%0ds8_we ),\n",$n); +printf(" .s8_cyc_o( m%0ds8_cyc ),\n",$n); +printf(" .s8_stb_o( m%0ds8_stb ),\n",$n); +printf(" .s8_ack_i( m%0ds8_ack ),\n",$n); +printf(" .s8_err_i( m%0ds8_err ),\n",$n); +printf(" .s8_rty_i( m%0ds8_rty ),\n",$n); +printf(" .s9_data_i( m%0ds9_data_i ),\n",$n); +printf(" .s9_data_o( m%0ds9_data_o ),\n",$n); +printf(" .s9_addr_o( m%0ds9_addr ),\n",$n); +printf(" .s9_sel_o( m%0ds9_sel ),\n",$n); +printf(" .s9_we_o( m%0ds9_we ),\n",$n); +printf(" .s9_cyc_o( m%0ds9_cyc ),\n",$n); +printf(" .s9_stb_o( m%0ds9_stb ),\n",$n); +printf(" .s9_ack_i( m%0ds9_ack ),\n",$n); +printf(" .s9_err_i( m%0ds9_err ),\n",$n); +printf(" .s9_rty_i( m%0ds9_rty ),\n",$n); +printf(" .s10_data_i( m%0ds10_data_i ),\n",$n); +printf(" .s10_data_o( m%0ds10_data_o ),\n",$n); +printf(" .s10_addr_o( m%0ds10_addr ),\n",$n); +printf(" .s10_sel_o( m%0ds10_sel ),\n",$n); +printf(" .s10_we_o( m%0ds10_we ),\n",$n); +printf(" .s10_cyc_o( m%0ds10_cyc ),\n",$n); +printf(" .s10_stb_o( m%0ds10_stb ),\n",$n); +printf(" .s10_ack_i( m%0ds10_ack ),\n",$n); +printf(" .s10_err_i( m%0ds10_err ),\n",$n); +printf(" .s10_rty_i( m%0ds10_rty ),\n",$n); +printf(" .s11_data_i( m%0ds11_data_i ),\n",$n); +printf(" .s11_data_o( m%0ds11_data_o ),\n",$n); +printf(" .s11_addr_o( m%0ds11_addr ),\n",$n); +printf(" .s11_sel_o( m%0ds11_sel ),\n",$n); +printf(" .s11_we_o( m%0ds11_we ),\n",$n); +printf(" .s11_cyc_o( m%0ds11_cyc ),\n",$n); +printf(" .s11_stb_o( m%0ds11_stb ),\n",$n); +printf(" .s11_ack_i( m%0ds11_ack ),\n",$n); +printf(" .s11_err_i( m%0ds11_err ),\n",$n); +printf(" .s11_rty_i( m%0ds11_rty ),\n",$n); +printf(" .s12_data_i( m%0ds12_data_i ),\n",$n); +printf(" .s12_data_o( m%0ds12_data_o ),\n",$n); +printf(" .s12_addr_o( m%0ds12_addr ),\n",$n); +printf(" .s12_sel_o( m%0ds12_sel ),\n",$n); +printf(" .s12_we_o( m%0ds12_we ),\n",$n); +printf(" .s12_cyc_o( m%0ds12_cyc ),\n",$n); +printf(" .s12_stb_o( m%0ds12_stb ),\n",$n); +printf(" .s12_ack_i( m%0ds12_ack ),\n",$n); +printf(" .s12_err_i( m%0ds12_err ),\n",$n); +printf(" .s12_rty_i( m%0ds12_rty ),\n",$n); +printf(" .s13_data_i( m%0ds13_data_i ),\n",$n); +printf(" .s13_data_o( m%0ds13_data_o ),\n",$n); +printf(" .s13_addr_o( m%0ds13_addr ),\n",$n); +printf(" .s13_sel_o( m%0ds13_sel ),\n",$n); +printf(" .s13_we_o( m%0ds13_we ),\n",$n); +printf(" .s13_cyc_o( m%0ds13_cyc ),\n",$n); +printf(" .s13_stb_o( m%0ds13_stb ),\n",$n); +printf(" .s13_ack_i( m%0ds13_ack ),\n",$n); +printf(" .s13_err_i( m%0ds13_err ),\n",$n); +printf(" .s13_rty_i( m%0ds13_rty ),\n",$n); +printf(" .s14_data_i( m%0ds14_data_i ),\n",$n); +printf(" .s14_data_o( m%0ds14_data_o ),\n",$n); +printf(" .s14_addr_o( m%0ds14_addr ),\n",$n); +printf(" .s14_sel_o( m%0ds14_sel ),\n",$n); +printf(" .s14_we_o( m%0ds14_we ),\n",$n); +printf(" .s14_cyc_o( m%0ds14_cyc ),\n",$n); +printf(" .s14_stb_o( m%0ds14_stb ),\n",$n); +printf(" .s14_ack_i( m%0ds14_ack ),\n",$n); +printf(" .s14_err_i( m%0ds14_err ),\n",$n); +printf(" .s14_rty_i( m%0ds14_rty ),\n",$n); +printf(" .s15_data_i( m%0ds15_data_i ),\n",$n); +printf(" .s15_data_o( m%0ds15_data_o ),\n",$n); +printf(" .s15_addr_o( m%0ds15_addr ),\n",$n); +printf(" .s15_sel_o( m%0ds15_sel ),\n",$n); +printf(" .s15_we_o( m%0ds15_we ),\n",$n); +printf(" .s15_cyc_o( m%0ds15_cyc ),\n",$n); +printf(" .s15_stb_o( m%0ds15_stb ),\n",$n); +printf(" .s15_ack_i( m%0ds15_ack ),\n",$n); +printf(" .s15_err_i( m%0ds15_err ),\n",$n); +printf(" .s15_rty_i( m%0ds15_rty )\n",$n); +printf(" );\n\n" ); + + + } Index: tags/start/slv2.pl =================================================================== --- tags/start/slv2.pl (nonexistent) +++ tags/start/slv2.pl (revision 3) @@ -0,0 +1,18 @@ + +for($n=0;$n<8;$n++) { +for($m=0;$m<16;$m++) { + +printf("wire [dw-1:0] m%0ds%0d_data_i;\n",$n,$m); +printf("wire [dw-1:0] m%0ds%0d_data_o;\n",$n,$m); +printf("wire [aw-1:0] m%0ds%0d_addr;\n",$n,$m); +printf("wire [sw-1:0] m%0ds%0d_sel;\n",$n,$m); +printf("wire m%0ds%0d_we;\n",$n,$m); +printf("wire m%0ds%0d_cyc;\n",$n,$m); +printf("wire m%0ds%0d_stb;\n",$n,$m); +printf("wire m%0ds%0d_ack;\n",$n,$m); +printf("wire m%0ds%0d_err;\n",$n,$m); +printf("wire m%0ds%0d_rty;\n",$n,$m); + +} + +} Index: tags/start/rtl/verilog/wb_conmax_pri_enc.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_pri_enc.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_pri_enc.v (revision 3) @@ -0,0 +1,179 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Priority Encoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_pri_enc.v,v 1.1.1.1 2001-10-19 11:01:41 rudi Exp $ +// +// $Date: 2001-10-19 11:01:41 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_pri_enc( + valid, + pri0, pri1, pri2, pri3, + pri4, pri5, pri6, pri7, + pri_out + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input [7:0] valid; +input [1:0] pri0, pri1, pri2, pri3; +input [1:0] pri4, pri5, pri6, pri7; +output [1:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out; +wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out; +wire [3:0] pri_out_tmp; +reg [1:0] pri_out0, pri_out1; +wire [1:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Priority Decoders +// + +wb_conmax_pri_dec #(pri_sel) pd0( + .valid( valid[0] ), + .pri_in( pri0 ), + .pri_out( pri0_out ) + ); + + +wb_conmax_pri_dec #(pri_sel) pd1( + .valid( valid[1] ), + .pri_in( pri1 ), + .pri_out( pri1_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd2( + .valid( valid[2] ), + .pri_in( pri2 ), + .pri_out( pri2_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd3( + .valid( valid[3] ), + .pri_in( pri3 ), + .pri_out( pri3_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd4( + .valid( valid[4] ), + .pri_in( pri4 ), + .pri_out( pri4_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd5( + .valid( valid[5] ), + .pri_in( pri5 ), + .pri_out( pri5_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd6( + .valid( valid[6] ), + .pri_in( pri6 ), + .pri_out( pri6_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd7( + .valid( valid[7] ), + .pri_in( pri7 ), + .pri_out( pri7_out ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Priority Encoding +// + +assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | + pri4_out | pri5_out | pri6_out | pri7_out; + +// 4 Priority Levels +always @(pri_out_tmp) + if(pri_out_tmp[3]) pri_out1 = 2'h3; + else + if(pri_out_tmp[2]) pri_out1 = 2'h2; + else + if(pri_out_tmp[1]) pri_out1 = 2'h1; + else pri_out1 = 2'h0; + +// 2 Priority Levels +always @(pri_out_tmp) + if(pri_out_tmp[1]) pri_out0 = 2'h1; + else pri_out0 = 2'h0; + +//////////////////////////////////////////////////////////////////// +// +// Final Priority Output +// + +// Select configured priority + +assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 ); + +endmodule + + Index: tags/start/rtl/verilog/wb_conmax_msel.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_msel.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_msel.v (revision 3) @@ -0,0 +1,239 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Master Select //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_msel.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $ +// +// $Date: 2001-10-19 11:01:38 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_msel( + clk_i, rst_i, + conf, req, sel, next + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; +input [15:0] conf; +input [7:0] req; +output [2:0] sel; +input next; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [1:0] pri0, pri1, pri2, pri3; +wire [1:0] pri4, pri5, pri6, pri7; +wire [1:0] pri_out_d; +reg [1:0] pri_out; + +wire [7:0] req_p0, req_p1, req_p2, req_p3; +wire [2:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; + +reg [2:0] sel1, sel2; +wire [2:0] sel; + +//////////////////////////////////////////////////////////////////// +// +// Priority Select logic +// + +assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0]; +assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0; + +assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2]; +assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0; + +assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4]; +assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0; + +assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6]; +assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0; + +assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8]; +assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0; + +assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10]; +assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0; + +assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12]; +assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0; + +assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14]; +assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0; + +// Priority Encoder +wb_conmax_pri_enc #(pri_sel) pri_enc( + .valid( req ), + .pri0( pri0 ), + .pri1( pri1 ), + .pri2( pri2 ), + .pri3( pri3 ), + .pri4( pri4 ), + .pri5( pri5 ), + .pri6( pri6 ), + .pri7( pri7 ), + .pri_out( pri_out_d ) + ); + +always @(posedge clk_i) + if(rst_i) pri_out <= #1 2'h0; + else + if(next) pri_out <= #1 pri_out_d; + +//////////////////////////////////////////////////////////////////// +// +// Arbiters +// + +assign req_p0[0] = req[0] & (pri0 == 2'd0); +assign req_p0[1] = req[1] & (pri1 == 2'd0); +assign req_p0[2] = req[2] & (pri2 == 2'd0); +assign req_p0[3] = req[3] & (pri3 == 2'd0); +assign req_p0[4] = req[4] & (pri4 == 2'd0); +assign req_p0[5] = req[5] & (pri5 == 2'd0); +assign req_p0[6] = req[6] & (pri6 == 2'd0); +assign req_p0[7] = req[7] & (pri7 == 2'd0); + +assign req_p1[0] = req[0] & (pri0 == 2'd1); +assign req_p1[1] = req[1] & (pri1 == 2'd1); +assign req_p1[2] = req[2] & (pri2 == 2'd1); +assign req_p1[3] = req[3] & (pri3 == 2'd1); +assign req_p1[4] = req[4] & (pri4 == 2'd1); +assign req_p1[5] = req[5] & (pri5 == 2'd1); +assign req_p1[6] = req[6] & (pri6 == 2'd1); +assign req_p1[7] = req[7] & (pri7 == 2'd1); + +assign req_p2[0] = req[0] & (pri0 == 2'd2); +assign req_p2[1] = req[1] & (pri1 == 2'd2); +assign req_p2[2] = req[2] & (pri2 == 2'd2); +assign req_p2[3] = req[3] & (pri3 == 2'd2); +assign req_p2[4] = req[4] & (pri4 == 2'd2); +assign req_p2[5] = req[5] & (pri5 == 2'd2); +assign req_p2[6] = req[6] & (pri6 == 2'd2); +assign req_p2[7] = req[7] & (pri7 == 2'd2); + +assign req_p3[0] = req[0] & (pri0 == 2'd3); +assign req_p3[1] = req[1] & (pri1 == 2'd3); +assign req_p3[2] = req[2] & (pri2 == 2'd3); +assign req_p3[3] = req[3] & (pri3 == 2'd3); +assign req_p3[4] = req[4] & (pri4 == 2'd3); +assign req_p3[5] = req[5] & (pri5 == 2'd3); +assign req_p3[6] = req[6] & (pri6 == 2'd3); +assign req_p3[7] = req[7] & (pri7 == 2'd3); + +wb_conmax_arb arb0( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p0 ), + .gnt( gnt_p0 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb1( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p1 ), + .gnt( gnt_p1 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb2( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p2 ), + .gnt( gnt_p2 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb3( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p3 ), + .gnt( gnt_p3 ), + .next( 1'b0 ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Final Master Select +// + +always @(pri_out or gnt_p0 or gnt_p1) + if(pri_out[0]) sel1 = gnt_p1; + else sel1 = gnt_p0; + + +always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3) + case(pri_out) + 2'd0: sel2 = gnt_p0; + 2'd1: sel2 = gnt_p1; + 2'd2: sel2 = gnt_p2; + 2'd3: sel2 = gnt_p3; + endcase + + +assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 ); + +endmodule + Index: tags/start/rtl/verilog/wb_conmax_top.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_top.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_top.v (revision 3) @@ -0,0 +1,4799 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_ic/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_top.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $ +// +// $Date: 2001-10-19 11:01:38 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_top( + clk_i, rst_i, + + // Master 0 Interface + m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, + + // Master 1 Interface + m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, + + // Master 2 Interface + m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, + + // Master 3 Interface + m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, + + // Master 4 Interface + m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, + + // Master 5 Interface + m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, + + // Master 6 Interface + m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, + + // Master 7 Interface + m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, + + // Slave 0 Interface + s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, + + // Slave 1 Interface + s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, + + // Slave 2 Interface + s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, + + // Slave 3 Interface + s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, + + // Slave 4 Interface + s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, + + // Slave 5 Interface + s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, + + // Slave 6 Interface + s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, + + // Slave 7 Interface + s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, + + // Slave 8 Interface + s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o, + s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i, + + // Slave 9 Interface + s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o, + s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i, + + // Slave 10 Interface + s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o, + s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i, + + // Slave 11 Interface + s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o, + s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i, + + // Slave 12 Interface + s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o, + s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i, + + // Slave 13 Interface + s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o, + s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i, + + // Slave 14 Interface + s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o, + s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i, + + // Slave 15 Interface + s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o, + s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter [3:0] rf_addr = 4'hf; +parameter [1:0] pri_sel0 = 2'd2; +parameter [1:0] pri_sel1 = 2'd2; +parameter [1:0] pri_sel2 = 2'd2; +parameter [1:0] pri_sel3 = 2'd2; +parameter [1:0] pri_sel4 = 2'd2; +parameter [1:0] pri_sel5 = 2'd2; +parameter [1:0] pri_sel6 = 2'd2; +parameter [1:0] pri_sel7 = 2'd2; +parameter [1:0] pri_sel8 = 2'd2; +parameter [1:0] pri_sel9 = 2'd2; +parameter [1:0] pri_sel10 = 2'd2; +parameter [1:0] pri_sel11 = 2'd2; +parameter [1:0] pri_sel12 = 2'd2; +parameter [1:0] pri_sel13 = 2'd2; +parameter [1:0] pri_sel14 = 2'd2; +parameter [1:0] pri_sel15 = 2'd2; + +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Master 0 Interface +input [dw-1:0] m0_data_i; +output [dw-1:0] m0_data_o; +input [aw-1:0] m0_addr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_data_i; +output [dw-1:0] m1_data_o; +input [aw-1:0] m1_addr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_data_i; +output [dw-1:0] m2_data_o; +input [aw-1:0] m2_addr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_data_i; +output [dw-1:0] m3_data_o; +input [aw-1:0] m3_addr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_data_i; +output [dw-1:0] m4_data_o; +input [aw-1:0] m4_addr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_data_i; +output [dw-1:0] m5_data_o; +input [aw-1:0] m5_addr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_data_i; +output [dw-1:0] m6_data_o; +input [aw-1:0] m6_addr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_data_i; +output [dw-1:0] m7_data_o; +input [aw-1:0] m7_addr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_data_i; +output [dw-1:0] s0_data_o; +output [aw-1:0] s0_addr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_data_i; +output [dw-1:0] s1_data_o; +output [aw-1:0] s1_addr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_data_i; +output [dw-1:0] s2_data_o; +output [aw-1:0] s2_addr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_data_i; +output [dw-1:0] s3_data_o; +output [aw-1:0] s3_addr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_data_i; +output [dw-1:0] s4_data_o; +output [aw-1:0] s4_addr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_data_i; +output [dw-1:0] s5_data_o; +output [aw-1:0] s5_addr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_data_i; +output [dw-1:0] s6_data_o; +output [aw-1:0] s6_addr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_data_i; +output [dw-1:0] s7_data_o; +output [aw-1:0] s7_addr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + +// Slave 8 Interface +input [dw-1:0] s8_data_i; +output [dw-1:0] s8_data_o; +output [aw-1:0] s8_addr_o; +output [sw-1:0] s8_sel_o; +output s8_we_o; +output s8_cyc_o; +output s8_stb_o; +input s8_ack_i; +input s8_err_i; +input s8_rty_i; + +// Slave 9 Interface +input [dw-1:0] s9_data_i; +output [dw-1:0] s9_data_o; +output [aw-1:0] s9_addr_o; +output [sw-1:0] s9_sel_o; +output s9_we_o; +output s9_cyc_o; +output s9_stb_o; +input s9_ack_i; +input s9_err_i; +input s9_rty_i; + +// Slave 10 Interface +input [dw-1:0] s10_data_i; +output [dw-1:0] s10_data_o; +output [aw-1:0] s10_addr_o; +output [sw-1:0] s10_sel_o; +output s10_we_o; +output s10_cyc_o; +output s10_stb_o; +input s10_ack_i; +input s10_err_i; +input s10_rty_i; + +// Slave 11 Interface +input [dw-1:0] s11_data_i; +output [dw-1:0] s11_data_o; +output [aw-1:0] s11_addr_o; +output [sw-1:0] s11_sel_o; +output s11_we_o; +output s11_cyc_o; +output s11_stb_o; +input s11_ack_i; +input s11_err_i; +input s11_rty_i; + +// Slave 12 Interface +input [dw-1:0] s12_data_i; +output [dw-1:0] s12_data_o; +output [aw-1:0] s12_addr_o; +output [sw-1:0] s12_sel_o; +output s12_we_o; +output s12_cyc_o; +output s12_stb_o; +input s12_ack_i; +input s12_err_i; +input s12_rty_i; + +// Slave 13 Interface +input [dw-1:0] s13_data_i; +output [dw-1:0] s13_data_o; +output [aw-1:0] s13_addr_o; +output [sw-1:0] s13_sel_o; +output s13_we_o; +output s13_cyc_o; +output s13_stb_o; +input s13_ack_i; +input s13_err_i; +input s13_rty_i; + +// Slave 14 Interface +input [dw-1:0] s14_data_i; +output [dw-1:0] s14_data_o; +output [aw-1:0] s14_addr_o; +output [sw-1:0] s14_sel_o; +output s14_we_o; +output s14_cyc_o; +output s14_stb_o; +input s14_ack_i; +input s14_err_i; +input s14_rty_i; + +// Slave 15 Interface +input [dw-1:0] s15_data_i; +output [dw-1:0] s15_data_o; +output [aw-1:0] s15_addr_o; +output [sw-1:0] s15_sel_o; +output s15_we_o; +output s15_cyc_o; +output s15_stb_o; +input s15_ack_i; +input s15_err_i; +input s15_rty_i; + +//////////////////////////////////////////////////////////////////// +// +// Local wires +// + +wire [dw-1:0] i_s15_data_i; +wire [dw-1:0] i_s15_data_o; +wire [aw-1:0] i_s15_addr_o; +wire [sw-1:0] i_s15_sel_o; +wire i_s15_we_o; +wire i_s15_cyc_o; +wire i_s15_stb_o; +wire i_s15_ack_i; +wire i_s15_err_i; +wire i_s15_rty_i; + +wire [dw-1:0] m0s0_data_i; +wire [dw-1:0] m0s0_data_o; +wire [aw-1:0] m0s0_addr; +wire [sw-1:0] m0s0_sel; +wire m0s0_we; +wire m0s0_cyc; +wire m0s0_stb; +wire m0s0_ack; +wire m0s0_err; +wire m0s0_rty; +wire [dw-1:0] m0s1_data_i; +wire [dw-1:0] m0s1_data_o; +wire [aw-1:0] m0s1_addr; +wire [sw-1:0] m0s1_sel; +wire m0s1_we; +wire m0s1_cyc; +wire m0s1_stb; +wire m0s1_ack; +wire m0s1_err; +wire m0s1_rty; +wire [dw-1:0] m0s2_data_i; +wire [dw-1:0] m0s2_data_o; +wire [aw-1:0] m0s2_addr; +wire [sw-1:0] m0s2_sel; +wire m0s2_we; +wire m0s2_cyc; +wire m0s2_stb; +wire m0s2_ack; +wire m0s2_err; +wire m0s2_rty; +wire [dw-1:0] m0s3_data_i; +wire [dw-1:0] m0s3_data_o; +wire [aw-1:0] m0s3_addr; +wire [sw-1:0] m0s3_sel; +wire m0s3_we; +wire m0s3_cyc; +wire m0s3_stb; +wire m0s3_ack; +wire m0s3_err; +wire m0s3_rty; +wire [dw-1:0] m0s4_data_i; +wire [dw-1:0] m0s4_data_o; +wire [aw-1:0] m0s4_addr; +wire [sw-1:0] m0s4_sel; +wire m0s4_we; +wire m0s4_cyc; +wire m0s4_stb; +wire m0s4_ack; +wire m0s4_err; +wire m0s4_rty; +wire [dw-1:0] m0s5_data_i; +wire [dw-1:0] m0s5_data_o; +wire [aw-1:0] m0s5_addr; +wire [sw-1:0] m0s5_sel; +wire m0s5_we; +wire m0s5_cyc; +wire m0s5_stb; +wire m0s5_ack; +wire m0s5_err; +wire m0s5_rty; +wire [dw-1:0] m0s6_data_i; +wire [dw-1:0] m0s6_data_o; +wire [aw-1:0] m0s6_addr; +wire [sw-1:0] m0s6_sel; +wire m0s6_we; +wire m0s6_cyc; +wire m0s6_stb; +wire m0s6_ack; +wire m0s6_err; +wire m0s6_rty; +wire [dw-1:0] m0s7_data_i; +wire [dw-1:0] m0s7_data_o; +wire [aw-1:0] m0s7_addr; +wire [sw-1:0] m0s7_sel; +wire m0s7_we; +wire m0s7_cyc; +wire m0s7_stb; +wire m0s7_ack; +wire m0s7_err; +wire m0s7_rty; +wire [dw-1:0] m0s8_data_i; +wire [dw-1:0] m0s8_data_o; +wire [aw-1:0] m0s8_addr; +wire [sw-1:0] m0s8_sel; +wire m0s8_we; +wire m0s8_cyc; +wire m0s8_stb; +wire m0s8_ack; +wire m0s8_err; +wire m0s8_rty; +wire [dw-1:0] m0s9_data_i; +wire [dw-1:0] m0s9_data_o; +wire [aw-1:0] m0s9_addr; +wire [sw-1:0] m0s9_sel; +wire m0s9_we; +wire m0s9_cyc; +wire m0s9_stb; +wire m0s9_ack; +wire m0s9_err; +wire m0s9_rty; +wire [dw-1:0] m0s10_data_i; +wire [dw-1:0] m0s10_data_o; +wire [aw-1:0] m0s10_addr; +wire [sw-1:0] m0s10_sel; +wire m0s10_we; +wire m0s10_cyc; +wire m0s10_stb; +wire m0s10_ack; +wire m0s10_err; +wire m0s10_rty; +wire [dw-1:0] m0s11_data_i; +wire [dw-1:0] m0s11_data_o; +wire [aw-1:0] m0s11_addr; +wire [sw-1:0] m0s11_sel; +wire m0s11_we; +wire m0s11_cyc; +wire m0s11_stb; +wire m0s11_ack; +wire m0s11_err; +wire m0s11_rty; +wire [dw-1:0] m0s12_data_i; +wire [dw-1:0] m0s12_data_o; +wire [aw-1:0] m0s12_addr; +wire [sw-1:0] m0s12_sel; +wire m0s12_we; +wire m0s12_cyc; +wire m0s12_stb; +wire m0s12_ack; +wire m0s12_err; +wire m0s12_rty; +wire [dw-1:0] m0s13_data_i; +wire [dw-1:0] m0s13_data_o; +wire [aw-1:0] m0s13_addr; +wire [sw-1:0] m0s13_sel; +wire m0s13_we; +wire m0s13_cyc; +wire m0s13_stb; +wire m0s13_ack; +wire m0s13_err; +wire m0s13_rty; +wire [dw-1:0] m0s14_data_i; +wire [dw-1:0] m0s14_data_o; +wire [aw-1:0] m0s14_addr; +wire [sw-1:0] m0s14_sel; +wire m0s14_we; +wire m0s14_cyc; +wire m0s14_stb; +wire m0s14_ack; +wire m0s14_err; +wire m0s14_rty; +wire [dw-1:0] m0s15_data_i; +wire [dw-1:0] m0s15_data_o; +wire [aw-1:0] m0s15_addr; +wire [sw-1:0] m0s15_sel; +wire m0s15_we; +wire m0s15_cyc; +wire m0s15_stb; +wire m0s15_ack; +wire m0s15_err; +wire m0s15_rty; +wire [dw-1:0] m1s0_data_i; +wire [dw-1:0] m1s0_data_o; +wire [aw-1:0] m1s0_addr; +wire [sw-1:0] m1s0_sel; +wire m1s0_we; +wire m1s0_cyc; +wire m1s0_stb; +wire m1s0_ack; +wire m1s0_err; +wire m1s0_rty; +wire [dw-1:0] m1s1_data_i; +wire [dw-1:0] m1s1_data_o; +wire [aw-1:0] m1s1_addr; +wire [sw-1:0] m1s1_sel; +wire m1s1_we; +wire m1s1_cyc; +wire m1s1_stb; +wire m1s1_ack; +wire m1s1_err; +wire m1s1_rty; +wire [dw-1:0] m1s2_data_i; +wire [dw-1:0] m1s2_data_o; +wire [aw-1:0] m1s2_addr; +wire [sw-1:0] m1s2_sel; +wire m1s2_we; +wire m1s2_cyc; +wire m1s2_stb; +wire m1s2_ack; +wire m1s2_err; +wire m1s2_rty; +wire [dw-1:0] m1s3_data_i; +wire [dw-1:0] m1s3_data_o; +wire [aw-1:0] m1s3_addr; +wire [sw-1:0] m1s3_sel; +wire m1s3_we; +wire m1s3_cyc; +wire m1s3_stb; +wire m1s3_ack; +wire m1s3_err; +wire m1s3_rty; +wire [dw-1:0] m1s4_data_i; +wire [dw-1:0] m1s4_data_o; +wire [aw-1:0] m1s4_addr; +wire [sw-1:0] m1s4_sel; +wire m1s4_we; +wire m1s4_cyc; +wire m1s4_stb; +wire m1s4_ack; +wire m1s4_err; +wire m1s4_rty; +wire [dw-1:0] m1s5_data_i; +wire [dw-1:0] m1s5_data_o; +wire [aw-1:0] m1s5_addr; +wire [sw-1:0] m1s5_sel; +wire m1s5_we; +wire m1s5_cyc; +wire m1s5_stb; +wire m1s5_ack; +wire m1s5_err; +wire m1s5_rty; +wire [dw-1:0] m1s6_data_i; +wire [dw-1:0] m1s6_data_o; +wire [aw-1:0] m1s6_addr; +wire [sw-1:0] m1s6_sel; +wire m1s6_we; +wire m1s6_cyc; +wire m1s6_stb; +wire m1s6_ack; +wire m1s6_err; +wire m1s6_rty; +wire [dw-1:0] m1s7_data_i; +wire [dw-1:0] m1s7_data_o; +wire [aw-1:0] m1s7_addr; +wire [sw-1:0] m1s7_sel; +wire m1s7_we; +wire m1s7_cyc; +wire m1s7_stb; +wire m1s7_ack; +wire m1s7_err; +wire m1s7_rty; +wire [dw-1:0] m1s8_data_i; +wire [dw-1:0] m1s8_data_o; +wire [aw-1:0] m1s8_addr; +wire [sw-1:0] m1s8_sel; +wire m1s8_we; +wire m1s8_cyc; +wire m1s8_stb; +wire m1s8_ack; +wire m1s8_err; +wire m1s8_rty; +wire [dw-1:0] m1s9_data_i; +wire [dw-1:0] m1s9_data_o; +wire [aw-1:0] m1s9_addr; +wire [sw-1:0] m1s9_sel; +wire m1s9_we; +wire m1s9_cyc; +wire m1s9_stb; +wire m1s9_ack; +wire m1s9_err; +wire m1s9_rty; +wire [dw-1:0] m1s10_data_i; +wire [dw-1:0] m1s10_data_o; +wire [aw-1:0] m1s10_addr; +wire [sw-1:0] m1s10_sel; +wire m1s10_we; +wire m1s10_cyc; +wire m1s10_stb; +wire m1s10_ack; +wire m1s10_err; +wire m1s10_rty; +wire [dw-1:0] m1s11_data_i; +wire [dw-1:0] m1s11_data_o; +wire [aw-1:0] m1s11_addr; +wire [sw-1:0] m1s11_sel; +wire m1s11_we; +wire m1s11_cyc; +wire m1s11_stb; +wire m1s11_ack; +wire m1s11_err; +wire m1s11_rty; +wire [dw-1:0] m1s12_data_i; +wire [dw-1:0] m1s12_data_o; +wire [aw-1:0] m1s12_addr; +wire [sw-1:0] m1s12_sel; +wire m1s12_we; +wire m1s12_cyc; +wire m1s12_stb; +wire m1s12_ack; +wire m1s12_err; +wire m1s12_rty; +wire [dw-1:0] m1s13_data_i; +wire [dw-1:0] m1s13_data_o; +wire [aw-1:0] m1s13_addr; +wire [sw-1:0] m1s13_sel; +wire m1s13_we; +wire m1s13_cyc; +wire m1s13_stb; +wire m1s13_ack; +wire m1s13_err; +wire m1s13_rty; +wire [dw-1:0] m1s14_data_i; +wire [dw-1:0] m1s14_data_o; +wire [aw-1:0] m1s14_addr; +wire [sw-1:0] m1s14_sel; +wire m1s14_we; +wire m1s14_cyc; +wire m1s14_stb; +wire m1s14_ack; +wire m1s14_err; +wire m1s14_rty; +wire [dw-1:0] m1s15_data_i; +wire [dw-1:0] m1s15_data_o; +wire [aw-1:0] m1s15_addr; +wire [sw-1:0] m1s15_sel; +wire m1s15_we; +wire m1s15_cyc; +wire m1s15_stb; +wire m1s15_ack; +wire m1s15_err; +wire m1s15_rty; +wire [dw-1:0] m2s0_data_i; +wire [dw-1:0] m2s0_data_o; +wire [aw-1:0] m2s0_addr; +wire [sw-1:0] m2s0_sel; +wire m2s0_we; +wire m2s0_cyc; +wire m2s0_stb; +wire m2s0_ack; +wire m2s0_err; +wire m2s0_rty; +wire [dw-1:0] m2s1_data_i; +wire [dw-1:0] m2s1_data_o; +wire [aw-1:0] m2s1_addr; +wire [sw-1:0] m2s1_sel; +wire m2s1_we; +wire m2s1_cyc; +wire m2s1_stb; +wire m2s1_ack; +wire m2s1_err; +wire m2s1_rty; +wire [dw-1:0] m2s2_data_i; +wire [dw-1:0] m2s2_data_o; +wire [aw-1:0] m2s2_addr; +wire [sw-1:0] m2s2_sel; +wire m2s2_we; +wire m2s2_cyc; +wire m2s2_stb; +wire m2s2_ack; +wire m2s2_err; +wire m2s2_rty; +wire [dw-1:0] m2s3_data_i; +wire [dw-1:0] m2s3_data_o; +wire [aw-1:0] m2s3_addr; +wire [sw-1:0] m2s3_sel; +wire m2s3_we; +wire m2s3_cyc; +wire m2s3_stb; +wire m2s3_ack; +wire m2s3_err; +wire m2s3_rty; +wire [dw-1:0] m2s4_data_i; +wire [dw-1:0] m2s4_data_o; +wire [aw-1:0] m2s4_addr; +wire [sw-1:0] m2s4_sel; +wire m2s4_we; +wire m2s4_cyc; +wire m2s4_stb; +wire m2s4_ack; +wire m2s4_err; +wire m2s4_rty; +wire [dw-1:0] m2s5_data_i; +wire [dw-1:0] m2s5_data_o; +wire [aw-1:0] m2s5_addr; +wire [sw-1:0] m2s5_sel; +wire m2s5_we; +wire m2s5_cyc; +wire m2s5_stb; +wire m2s5_ack; +wire m2s5_err; +wire m2s5_rty; +wire [dw-1:0] m2s6_data_i; +wire [dw-1:0] m2s6_data_o; +wire [aw-1:0] m2s6_addr; +wire [sw-1:0] m2s6_sel; +wire m2s6_we; +wire m2s6_cyc; +wire m2s6_stb; +wire m2s6_ack; +wire m2s6_err; +wire m2s6_rty; +wire [dw-1:0] m2s7_data_i; +wire [dw-1:0] m2s7_data_o; +wire [aw-1:0] m2s7_addr; +wire [sw-1:0] m2s7_sel; +wire m2s7_we; +wire m2s7_cyc; +wire m2s7_stb; +wire m2s7_ack; +wire m2s7_err; +wire m2s7_rty; +wire [dw-1:0] m2s8_data_i; +wire [dw-1:0] m2s8_data_o; +wire [aw-1:0] m2s8_addr; +wire [sw-1:0] m2s8_sel; +wire m2s8_we; +wire m2s8_cyc; +wire m2s8_stb; +wire m2s8_ack; +wire m2s8_err; +wire m2s8_rty; +wire [dw-1:0] m2s9_data_i; +wire [dw-1:0] m2s9_data_o; +wire [aw-1:0] m2s9_addr; +wire [sw-1:0] m2s9_sel; +wire m2s9_we; +wire m2s9_cyc; +wire m2s9_stb; +wire m2s9_ack; +wire m2s9_err; +wire m2s9_rty; +wire [dw-1:0] m2s10_data_i; +wire [dw-1:0] m2s10_data_o; +wire [aw-1:0] m2s10_addr; +wire [sw-1:0] m2s10_sel; +wire m2s10_we; +wire m2s10_cyc; +wire m2s10_stb; +wire m2s10_ack; +wire m2s10_err; +wire m2s10_rty; +wire [dw-1:0] m2s11_data_i; +wire [dw-1:0] m2s11_data_o; +wire [aw-1:0] m2s11_addr; +wire [sw-1:0] m2s11_sel; +wire m2s11_we; +wire m2s11_cyc; +wire m2s11_stb; +wire m2s11_ack; +wire m2s11_err; +wire m2s11_rty; +wire [dw-1:0] m2s12_data_i; +wire [dw-1:0] m2s12_data_o; +wire [aw-1:0] m2s12_addr; +wire [sw-1:0] m2s12_sel; +wire m2s12_we; +wire m2s12_cyc; +wire m2s12_stb; +wire m2s12_ack; +wire m2s12_err; +wire m2s12_rty; +wire [dw-1:0] m2s13_data_i; +wire [dw-1:0] m2s13_data_o; +wire [aw-1:0] m2s13_addr; +wire [sw-1:0] m2s13_sel; +wire m2s13_we; +wire m2s13_cyc; +wire m2s13_stb; +wire m2s13_ack; +wire m2s13_err; +wire m2s13_rty; +wire [dw-1:0] m2s14_data_i; +wire [dw-1:0] m2s14_data_o; +wire [aw-1:0] m2s14_addr; +wire [sw-1:0] m2s14_sel; +wire m2s14_we; +wire m2s14_cyc; +wire m2s14_stb; +wire m2s14_ack; +wire m2s14_err; +wire m2s14_rty; +wire [dw-1:0] m2s15_data_i; +wire [dw-1:0] m2s15_data_o; +wire [aw-1:0] m2s15_addr; +wire [sw-1:0] m2s15_sel; +wire m2s15_we; +wire m2s15_cyc; +wire m2s15_stb; +wire m2s15_ack; +wire m2s15_err; +wire m2s15_rty; +wire [dw-1:0] m3s0_data_i; +wire [dw-1:0] m3s0_data_o; +wire [aw-1:0] m3s0_addr; +wire [sw-1:0] m3s0_sel; +wire m3s0_we; +wire m3s0_cyc; +wire m3s0_stb; +wire m3s0_ack; +wire m3s0_err; +wire m3s0_rty; +wire [dw-1:0] m3s1_data_i; +wire [dw-1:0] m3s1_data_o; +wire [aw-1:0] m3s1_addr; +wire [sw-1:0] m3s1_sel; +wire m3s1_we; +wire m3s1_cyc; +wire m3s1_stb; +wire m3s1_ack; +wire m3s1_err; +wire m3s1_rty; +wire [dw-1:0] m3s2_data_i; +wire [dw-1:0] m3s2_data_o; +wire [aw-1:0] m3s2_addr; +wire [sw-1:0] m3s2_sel; +wire m3s2_we; +wire m3s2_cyc; +wire m3s2_stb; +wire m3s2_ack; +wire m3s2_err; +wire m3s2_rty; +wire [dw-1:0] m3s3_data_i; +wire [dw-1:0] m3s3_data_o; +wire [aw-1:0] m3s3_addr; +wire [sw-1:0] m3s3_sel; +wire m3s3_we; +wire m3s3_cyc; +wire m3s3_stb; +wire m3s3_ack; +wire m3s3_err; +wire m3s3_rty; +wire [dw-1:0] m3s4_data_i; +wire [dw-1:0] m3s4_data_o; +wire [aw-1:0] m3s4_addr; +wire [sw-1:0] m3s4_sel; +wire m3s4_we; +wire m3s4_cyc; +wire m3s4_stb; +wire m3s4_ack; +wire m3s4_err; +wire m3s4_rty; +wire [dw-1:0] m3s5_data_i; +wire [dw-1:0] m3s5_data_o; +wire [aw-1:0] m3s5_addr; +wire [sw-1:0] m3s5_sel; +wire m3s5_we; +wire m3s5_cyc; +wire m3s5_stb; +wire m3s5_ack; +wire m3s5_err; +wire m3s5_rty; +wire [dw-1:0] m3s6_data_i; +wire [dw-1:0] m3s6_data_o; +wire [aw-1:0] m3s6_addr; +wire [sw-1:0] m3s6_sel; +wire m3s6_we; +wire m3s6_cyc; +wire m3s6_stb; +wire m3s6_ack; +wire m3s6_err; +wire m3s6_rty; +wire [dw-1:0] m3s7_data_i; +wire [dw-1:0] m3s7_data_o; +wire [aw-1:0] m3s7_addr; +wire [sw-1:0] m3s7_sel; +wire m3s7_we; +wire m3s7_cyc; +wire m3s7_stb; +wire m3s7_ack; +wire m3s7_err; +wire m3s7_rty; +wire [dw-1:0] m3s8_data_i; +wire [dw-1:0] m3s8_data_o; +wire [aw-1:0] m3s8_addr; +wire [sw-1:0] m3s8_sel; +wire m3s8_we; +wire m3s8_cyc; +wire m3s8_stb; +wire m3s8_ack; +wire m3s8_err; +wire m3s8_rty; +wire [dw-1:0] m3s9_data_i; +wire [dw-1:0] m3s9_data_o; +wire [aw-1:0] m3s9_addr; +wire [sw-1:0] m3s9_sel; +wire m3s9_we; +wire m3s9_cyc; +wire m3s9_stb; +wire m3s9_ack; +wire m3s9_err; +wire m3s9_rty; +wire [dw-1:0] m3s10_data_i; +wire [dw-1:0] m3s10_data_o; +wire [aw-1:0] m3s10_addr; +wire [sw-1:0] m3s10_sel; +wire m3s10_we; +wire m3s10_cyc; +wire m3s10_stb; +wire m3s10_ack; +wire m3s10_err; +wire m3s10_rty; +wire [dw-1:0] m3s11_data_i; +wire [dw-1:0] m3s11_data_o; +wire [aw-1:0] m3s11_addr; +wire [sw-1:0] m3s11_sel; +wire m3s11_we; +wire m3s11_cyc; +wire m3s11_stb; +wire m3s11_ack; +wire m3s11_err; +wire m3s11_rty; +wire [dw-1:0] m3s12_data_i; +wire [dw-1:0] m3s12_data_o; +wire [aw-1:0] m3s12_addr; +wire [sw-1:0] m3s12_sel; +wire m3s12_we; +wire m3s12_cyc; +wire m3s12_stb; +wire m3s12_ack; +wire m3s12_err; +wire m3s12_rty; +wire [dw-1:0] m3s13_data_i; +wire [dw-1:0] m3s13_data_o; +wire [aw-1:0] m3s13_addr; +wire [sw-1:0] m3s13_sel; +wire m3s13_we; +wire m3s13_cyc; +wire m3s13_stb; +wire m3s13_ack; +wire m3s13_err; +wire m3s13_rty; +wire [dw-1:0] m3s14_data_i; +wire [dw-1:0] m3s14_data_o; +wire [aw-1:0] m3s14_addr; +wire [sw-1:0] m3s14_sel; +wire m3s14_we; +wire m3s14_cyc; +wire m3s14_stb; +wire m3s14_ack; +wire m3s14_err; +wire m3s14_rty; +wire [dw-1:0] m3s15_data_i; +wire [dw-1:0] m3s15_data_o; +wire [aw-1:0] m3s15_addr; +wire [sw-1:0] m3s15_sel; +wire m3s15_we; +wire m3s15_cyc; +wire m3s15_stb; +wire m3s15_ack; +wire m3s15_err; +wire m3s15_rty; +wire [dw-1:0] m4s0_data_i; +wire [dw-1:0] m4s0_data_o; +wire [aw-1:0] m4s0_addr; +wire [sw-1:0] m4s0_sel; +wire m4s0_we; +wire m4s0_cyc; +wire m4s0_stb; +wire m4s0_ack; +wire m4s0_err; +wire m4s0_rty; +wire [dw-1:0] m4s1_data_i; +wire [dw-1:0] m4s1_data_o; +wire [aw-1:0] m4s1_addr; +wire [sw-1:0] m4s1_sel; +wire m4s1_we; +wire m4s1_cyc; +wire m4s1_stb; +wire m4s1_ack; +wire m4s1_err; +wire m4s1_rty; +wire [dw-1:0] m4s2_data_i; +wire [dw-1:0] m4s2_data_o; +wire [aw-1:0] m4s2_addr; +wire [sw-1:0] m4s2_sel; +wire m4s2_we; +wire m4s2_cyc; +wire m4s2_stb; +wire m4s2_ack; +wire m4s2_err; +wire m4s2_rty; +wire [dw-1:0] m4s3_data_i; +wire [dw-1:0] m4s3_data_o; +wire [aw-1:0] m4s3_addr; +wire [sw-1:0] m4s3_sel; +wire m4s3_we; +wire m4s3_cyc; +wire m4s3_stb; +wire m4s3_ack; +wire m4s3_err; +wire m4s3_rty; +wire [dw-1:0] m4s4_data_i; +wire [dw-1:0] m4s4_data_o; +wire [aw-1:0] m4s4_addr; +wire [sw-1:0] m4s4_sel; +wire m4s4_we; +wire m4s4_cyc; +wire m4s4_stb; +wire m4s4_ack; +wire m4s4_err; +wire m4s4_rty; +wire [dw-1:0] m4s5_data_i; +wire [dw-1:0] m4s5_data_o; +wire [aw-1:0] m4s5_addr; +wire [sw-1:0] m4s5_sel; +wire m4s5_we; +wire m4s5_cyc; +wire m4s5_stb; +wire m4s5_ack; +wire m4s5_err; +wire m4s5_rty; +wire [dw-1:0] m4s6_data_i; +wire [dw-1:0] m4s6_data_o; +wire [aw-1:0] m4s6_addr; +wire [sw-1:0] m4s6_sel; +wire m4s6_we; +wire m4s6_cyc; +wire m4s6_stb; +wire m4s6_ack; +wire m4s6_err; +wire m4s6_rty; +wire [dw-1:0] m4s7_data_i; +wire [dw-1:0] m4s7_data_o; +wire [aw-1:0] m4s7_addr; +wire [sw-1:0] m4s7_sel; +wire m4s7_we; +wire m4s7_cyc; +wire m4s7_stb; +wire m4s7_ack; +wire m4s7_err; +wire m4s7_rty; +wire [dw-1:0] m4s8_data_i; +wire [dw-1:0] m4s8_data_o; +wire [aw-1:0] m4s8_addr; +wire [sw-1:0] m4s8_sel; +wire m4s8_we; +wire m4s8_cyc; +wire m4s8_stb; +wire m4s8_ack; +wire m4s8_err; +wire m4s8_rty; +wire [dw-1:0] m4s9_data_i; +wire [dw-1:0] m4s9_data_o; +wire [aw-1:0] m4s9_addr; +wire [sw-1:0] m4s9_sel; +wire m4s9_we; +wire m4s9_cyc; +wire m4s9_stb; +wire m4s9_ack; +wire m4s9_err; +wire m4s9_rty; +wire [dw-1:0] m4s10_data_i; +wire [dw-1:0] m4s10_data_o; +wire [aw-1:0] m4s10_addr; +wire [sw-1:0] m4s10_sel; +wire m4s10_we; +wire m4s10_cyc; +wire m4s10_stb; +wire m4s10_ack; +wire m4s10_err; +wire m4s10_rty; +wire [dw-1:0] m4s11_data_i; +wire [dw-1:0] m4s11_data_o; +wire [aw-1:0] m4s11_addr; +wire [sw-1:0] m4s11_sel; +wire m4s11_we; +wire m4s11_cyc; +wire m4s11_stb; +wire m4s11_ack; +wire m4s11_err; +wire m4s11_rty; +wire [dw-1:0] m4s12_data_i; +wire [dw-1:0] m4s12_data_o; +wire [aw-1:0] m4s12_addr; +wire [sw-1:0] m4s12_sel; +wire m4s12_we; +wire m4s12_cyc; +wire m4s12_stb; +wire m4s12_ack; +wire m4s12_err; +wire m4s12_rty; +wire [dw-1:0] m4s13_data_i; +wire [dw-1:0] m4s13_data_o; +wire [aw-1:0] m4s13_addr; +wire [sw-1:0] m4s13_sel; +wire m4s13_we; +wire m4s13_cyc; +wire m4s13_stb; +wire m4s13_ack; +wire m4s13_err; +wire m4s13_rty; +wire [dw-1:0] m4s14_data_i; +wire [dw-1:0] m4s14_data_o; +wire [aw-1:0] m4s14_addr; +wire [sw-1:0] m4s14_sel; +wire m4s14_we; +wire m4s14_cyc; +wire m4s14_stb; +wire m4s14_ack; +wire m4s14_err; +wire m4s14_rty; +wire [dw-1:0] m4s15_data_i; +wire [dw-1:0] m4s15_data_o; +wire [aw-1:0] m4s15_addr; +wire [sw-1:0] m4s15_sel; +wire m4s15_we; +wire m4s15_cyc; +wire m4s15_stb; +wire m4s15_ack; +wire m4s15_err; +wire m4s15_rty; +wire [dw-1:0] m5s0_data_i; +wire [dw-1:0] m5s0_data_o; +wire [aw-1:0] m5s0_addr; +wire [sw-1:0] m5s0_sel; +wire m5s0_we; +wire m5s0_cyc; +wire m5s0_stb; +wire m5s0_ack; +wire m5s0_err; +wire m5s0_rty; +wire [dw-1:0] m5s1_data_i; +wire [dw-1:0] m5s1_data_o; +wire [aw-1:0] m5s1_addr; +wire [sw-1:0] m5s1_sel; +wire m5s1_we; +wire m5s1_cyc; +wire m5s1_stb; +wire m5s1_ack; +wire m5s1_err; +wire m5s1_rty; +wire [dw-1:0] m5s2_data_i; +wire [dw-1:0] m5s2_data_o; +wire [aw-1:0] m5s2_addr; +wire [sw-1:0] m5s2_sel; +wire m5s2_we; +wire m5s2_cyc; +wire m5s2_stb; +wire m5s2_ack; +wire m5s2_err; +wire m5s2_rty; +wire [dw-1:0] m5s3_data_i; +wire [dw-1:0] m5s3_data_o; +wire [aw-1:0] m5s3_addr; +wire [sw-1:0] m5s3_sel; +wire m5s3_we; +wire m5s3_cyc; +wire m5s3_stb; +wire m5s3_ack; +wire m5s3_err; +wire m5s3_rty; +wire [dw-1:0] m5s4_data_i; +wire [dw-1:0] m5s4_data_o; +wire [aw-1:0] m5s4_addr; +wire [sw-1:0] m5s4_sel; +wire m5s4_we; +wire m5s4_cyc; +wire m5s4_stb; +wire m5s4_ack; +wire m5s4_err; +wire m5s4_rty; +wire [dw-1:0] m5s5_data_i; +wire [dw-1:0] m5s5_data_o; +wire [aw-1:0] m5s5_addr; +wire [sw-1:0] m5s5_sel; +wire m5s5_we; +wire m5s5_cyc; +wire m5s5_stb; +wire m5s5_ack; +wire m5s5_err; +wire m5s5_rty; +wire [dw-1:0] m5s6_data_i; +wire [dw-1:0] m5s6_data_o; +wire [aw-1:0] m5s6_addr; +wire [sw-1:0] m5s6_sel; +wire m5s6_we; +wire m5s6_cyc; +wire m5s6_stb; +wire m5s6_ack; +wire m5s6_err; +wire m5s6_rty; +wire [dw-1:0] m5s7_data_i; +wire [dw-1:0] m5s7_data_o; +wire [aw-1:0] m5s7_addr; +wire [sw-1:0] m5s7_sel; +wire m5s7_we; +wire m5s7_cyc; +wire m5s7_stb; +wire m5s7_ack; +wire m5s7_err; +wire m5s7_rty; +wire [dw-1:0] m5s8_data_i; +wire [dw-1:0] m5s8_data_o; +wire [aw-1:0] m5s8_addr; +wire [sw-1:0] m5s8_sel; +wire m5s8_we; +wire m5s8_cyc; +wire m5s8_stb; +wire m5s8_ack; +wire m5s8_err; +wire m5s8_rty; +wire [dw-1:0] m5s9_data_i; +wire [dw-1:0] m5s9_data_o; +wire [aw-1:0] m5s9_addr; +wire [sw-1:0] m5s9_sel; +wire m5s9_we; +wire m5s9_cyc; +wire m5s9_stb; +wire m5s9_ack; +wire m5s9_err; +wire m5s9_rty; +wire [dw-1:0] m5s10_data_i; +wire [dw-1:0] m5s10_data_o; +wire [aw-1:0] m5s10_addr; +wire [sw-1:0] m5s10_sel; +wire m5s10_we; +wire m5s10_cyc; +wire m5s10_stb; +wire m5s10_ack; +wire m5s10_err; +wire m5s10_rty; +wire [dw-1:0] m5s11_data_i; +wire [dw-1:0] m5s11_data_o; +wire [aw-1:0] m5s11_addr; +wire [sw-1:0] m5s11_sel; +wire m5s11_we; +wire m5s11_cyc; +wire m5s11_stb; +wire m5s11_ack; +wire m5s11_err; +wire m5s11_rty; +wire [dw-1:0] m5s12_data_i; +wire [dw-1:0] m5s12_data_o; +wire [aw-1:0] m5s12_addr; +wire [sw-1:0] m5s12_sel; +wire m5s12_we; +wire m5s12_cyc; +wire m5s12_stb; +wire m5s12_ack; +wire m5s12_err; +wire m5s12_rty; +wire [dw-1:0] m5s13_data_i; +wire [dw-1:0] m5s13_data_o; +wire [aw-1:0] m5s13_addr; +wire [sw-1:0] m5s13_sel; +wire m5s13_we; +wire m5s13_cyc; +wire m5s13_stb; +wire m5s13_ack; +wire m5s13_err; +wire m5s13_rty; +wire [dw-1:0] m5s14_data_i; +wire [dw-1:0] m5s14_data_o; +wire [aw-1:0] m5s14_addr; +wire [sw-1:0] m5s14_sel; +wire m5s14_we; +wire m5s14_cyc; +wire m5s14_stb; +wire m5s14_ack; +wire m5s14_err; +wire m5s14_rty; +wire [dw-1:0] m5s15_data_i; +wire [dw-1:0] m5s15_data_o; +wire [aw-1:0] m5s15_addr; +wire [sw-1:0] m5s15_sel; +wire m5s15_we; +wire m5s15_cyc; +wire m5s15_stb; +wire m5s15_ack; +wire m5s15_err; +wire m5s15_rty; +wire [dw-1:0] m6s0_data_i; +wire [dw-1:0] m6s0_data_o; +wire [aw-1:0] m6s0_addr; +wire [sw-1:0] m6s0_sel; +wire m6s0_we; +wire m6s0_cyc; +wire m6s0_stb; +wire m6s0_ack; +wire m6s0_err; +wire m6s0_rty; +wire [dw-1:0] m6s1_data_i; +wire [dw-1:0] m6s1_data_o; +wire [aw-1:0] m6s1_addr; +wire [sw-1:0] m6s1_sel; +wire m6s1_we; +wire m6s1_cyc; +wire m6s1_stb; +wire m6s1_ack; +wire m6s1_err; +wire m6s1_rty; +wire [dw-1:0] m6s2_data_i; +wire [dw-1:0] m6s2_data_o; +wire [aw-1:0] m6s2_addr; +wire [sw-1:0] m6s2_sel; +wire m6s2_we; +wire m6s2_cyc; +wire m6s2_stb; +wire m6s2_ack; +wire m6s2_err; +wire m6s2_rty; +wire [dw-1:0] m6s3_data_i; +wire [dw-1:0] m6s3_data_o; +wire [aw-1:0] m6s3_addr; +wire [sw-1:0] m6s3_sel; +wire m6s3_we; +wire m6s3_cyc; +wire m6s3_stb; +wire m6s3_ack; +wire m6s3_err; +wire m6s3_rty; +wire [dw-1:0] m6s4_data_i; +wire [dw-1:0] m6s4_data_o; +wire [aw-1:0] m6s4_addr; +wire [sw-1:0] m6s4_sel; +wire m6s4_we; +wire m6s4_cyc; +wire m6s4_stb; +wire m6s4_ack; +wire m6s4_err; +wire m6s4_rty; +wire [dw-1:0] m6s5_data_i; +wire [dw-1:0] m6s5_data_o; +wire [aw-1:0] m6s5_addr; +wire [sw-1:0] m6s5_sel; +wire m6s5_we; +wire m6s5_cyc; +wire m6s5_stb; +wire m6s5_ack; +wire m6s5_err; +wire m6s5_rty; +wire [dw-1:0] m6s6_data_i; +wire [dw-1:0] m6s6_data_o; +wire [aw-1:0] m6s6_addr; +wire [sw-1:0] m6s6_sel; +wire m6s6_we; +wire m6s6_cyc; +wire m6s6_stb; +wire m6s6_ack; +wire m6s6_err; +wire m6s6_rty; +wire [dw-1:0] m6s7_data_i; +wire [dw-1:0] m6s7_data_o; +wire [aw-1:0] m6s7_addr; +wire [sw-1:0] m6s7_sel; +wire m6s7_we; +wire m6s7_cyc; +wire m6s7_stb; +wire m6s7_ack; +wire m6s7_err; +wire m6s7_rty; +wire [dw-1:0] m6s8_data_i; +wire [dw-1:0] m6s8_data_o; +wire [aw-1:0] m6s8_addr; +wire [sw-1:0] m6s8_sel; +wire m6s8_we; +wire m6s8_cyc; +wire m6s8_stb; +wire m6s8_ack; +wire m6s8_err; +wire m6s8_rty; +wire [dw-1:0] m6s9_data_i; +wire [dw-1:0] m6s9_data_o; +wire [aw-1:0] m6s9_addr; +wire [sw-1:0] m6s9_sel; +wire m6s9_we; +wire m6s9_cyc; +wire m6s9_stb; +wire m6s9_ack; +wire m6s9_err; +wire m6s9_rty; +wire [dw-1:0] m6s10_data_i; +wire [dw-1:0] m6s10_data_o; +wire [aw-1:0] m6s10_addr; +wire [sw-1:0] m6s10_sel; +wire m6s10_we; +wire m6s10_cyc; +wire m6s10_stb; +wire m6s10_ack; +wire m6s10_err; +wire m6s10_rty; +wire [dw-1:0] m6s11_data_i; +wire [dw-1:0] m6s11_data_o; +wire [aw-1:0] m6s11_addr; +wire [sw-1:0] m6s11_sel; +wire m6s11_we; +wire m6s11_cyc; +wire m6s11_stb; +wire m6s11_ack; +wire m6s11_err; +wire m6s11_rty; +wire [dw-1:0] m6s12_data_i; +wire [dw-1:0] m6s12_data_o; +wire [aw-1:0] m6s12_addr; +wire [sw-1:0] m6s12_sel; +wire m6s12_we; +wire m6s12_cyc; +wire m6s12_stb; +wire m6s12_ack; +wire m6s12_err; +wire m6s12_rty; +wire [dw-1:0] m6s13_data_i; +wire [dw-1:0] m6s13_data_o; +wire [aw-1:0] m6s13_addr; +wire [sw-1:0] m6s13_sel; +wire m6s13_we; +wire m6s13_cyc; +wire m6s13_stb; +wire m6s13_ack; +wire m6s13_err; +wire m6s13_rty; +wire [dw-1:0] m6s14_data_i; +wire [dw-1:0] m6s14_data_o; +wire [aw-1:0] m6s14_addr; +wire [sw-1:0] m6s14_sel; +wire m6s14_we; +wire m6s14_cyc; +wire m6s14_stb; +wire m6s14_ack; +wire m6s14_err; +wire m6s14_rty; +wire [dw-1:0] m6s15_data_i; +wire [dw-1:0] m6s15_data_o; +wire [aw-1:0] m6s15_addr; +wire [sw-1:0] m6s15_sel; +wire m6s15_we; +wire m6s15_cyc; +wire m6s15_stb; +wire m6s15_ack; +wire m6s15_err; +wire m6s15_rty; +wire [dw-1:0] m7s0_data_i; +wire [dw-1:0] m7s0_data_o; +wire [aw-1:0] m7s0_addr; +wire [sw-1:0] m7s0_sel; +wire m7s0_we; +wire m7s0_cyc; +wire m7s0_stb; +wire m7s0_ack; +wire m7s0_err; +wire m7s0_rty; +wire [dw-1:0] m7s1_data_i; +wire [dw-1:0] m7s1_data_o; +wire [aw-1:0] m7s1_addr; +wire [sw-1:0] m7s1_sel; +wire m7s1_we; +wire m7s1_cyc; +wire m7s1_stb; +wire m7s1_ack; +wire m7s1_err; +wire m7s1_rty; +wire [dw-1:0] m7s2_data_i; +wire [dw-1:0] m7s2_data_o; +wire [aw-1:0] m7s2_addr; +wire [sw-1:0] m7s2_sel; +wire m7s2_we; +wire m7s2_cyc; +wire m7s2_stb; +wire m7s2_ack; +wire m7s2_err; +wire m7s2_rty; +wire [dw-1:0] m7s3_data_i; +wire [dw-1:0] m7s3_data_o; +wire [aw-1:0] m7s3_addr; +wire [sw-1:0] m7s3_sel; +wire m7s3_we; +wire m7s3_cyc; +wire m7s3_stb; +wire m7s3_ack; +wire m7s3_err; +wire m7s3_rty; +wire [dw-1:0] m7s4_data_i; +wire [dw-1:0] m7s4_data_o; +wire [aw-1:0] m7s4_addr; +wire [sw-1:0] m7s4_sel; +wire m7s4_we; +wire m7s4_cyc; +wire m7s4_stb; +wire m7s4_ack; +wire m7s4_err; +wire m7s4_rty; +wire [dw-1:0] m7s5_data_i; +wire [dw-1:0] m7s5_data_o; +wire [aw-1:0] m7s5_addr; +wire [sw-1:0] m7s5_sel; +wire m7s5_we; +wire m7s5_cyc; +wire m7s5_stb; +wire m7s5_ack; +wire m7s5_err; +wire m7s5_rty; +wire [dw-1:0] m7s6_data_i; +wire [dw-1:0] m7s6_data_o; +wire [aw-1:0] m7s6_addr; +wire [sw-1:0] m7s6_sel; +wire m7s6_we; +wire m7s6_cyc; +wire m7s6_stb; +wire m7s6_ack; +wire m7s6_err; +wire m7s6_rty; +wire [dw-1:0] m7s7_data_i; +wire [dw-1:0] m7s7_data_o; +wire [aw-1:0] m7s7_addr; +wire [sw-1:0] m7s7_sel; +wire m7s7_we; +wire m7s7_cyc; +wire m7s7_stb; +wire m7s7_ack; +wire m7s7_err; +wire m7s7_rty; +wire [dw-1:0] m7s8_data_i; +wire [dw-1:0] m7s8_data_o; +wire [aw-1:0] m7s8_addr; +wire [sw-1:0] m7s8_sel; +wire m7s8_we; +wire m7s8_cyc; +wire m7s8_stb; +wire m7s8_ack; +wire m7s8_err; +wire m7s8_rty; +wire [dw-1:0] m7s9_data_i; +wire [dw-1:0] m7s9_data_o; +wire [aw-1:0] m7s9_addr; +wire [sw-1:0] m7s9_sel; +wire m7s9_we; +wire m7s9_cyc; +wire m7s9_stb; +wire m7s9_ack; +wire m7s9_err; +wire m7s9_rty; +wire [dw-1:0] m7s10_data_i; +wire [dw-1:0] m7s10_data_o; +wire [aw-1:0] m7s10_addr; +wire [sw-1:0] m7s10_sel; +wire m7s10_we; +wire m7s10_cyc; +wire m7s10_stb; +wire m7s10_ack; +wire m7s10_err; +wire m7s10_rty; +wire [dw-1:0] m7s11_data_i; +wire [dw-1:0] m7s11_data_o; +wire [aw-1:0] m7s11_addr; +wire [sw-1:0] m7s11_sel; +wire m7s11_we; +wire m7s11_cyc; +wire m7s11_stb; +wire m7s11_ack; +wire m7s11_err; +wire m7s11_rty; +wire [dw-1:0] m7s12_data_i; +wire [dw-1:0] m7s12_data_o; +wire [aw-1:0] m7s12_addr; +wire [sw-1:0] m7s12_sel; +wire m7s12_we; +wire m7s12_cyc; +wire m7s12_stb; +wire m7s12_ack; +wire m7s12_err; +wire m7s12_rty; +wire [dw-1:0] m7s13_data_i; +wire [dw-1:0] m7s13_data_o; +wire [aw-1:0] m7s13_addr; +wire [sw-1:0] m7s13_sel; +wire m7s13_we; +wire m7s13_cyc; +wire m7s13_stb; +wire m7s13_ack; +wire m7s13_err; +wire m7s13_rty; +wire [dw-1:0] m7s14_data_i; +wire [dw-1:0] m7s14_data_o; +wire [aw-1:0] m7s14_addr; +wire [sw-1:0] m7s14_sel; +wire m7s14_we; +wire m7s14_cyc; +wire m7s14_stb; +wire m7s14_ack; +wire m7s14_err; +wire m7s14_rty; +wire [dw-1:0] m7s15_data_i; +wire [dw-1:0] m7s15_data_o; +wire [aw-1:0] m7s15_addr; +wire [sw-1:0] m7s15_sel; +wire m7s15_we; +wire m7s15_cyc; +wire m7s15_stb; +wire m7s15_ack; +wire m7s15_err; +wire m7s15_rty; + +wire [15:0] conf0; +wire [15:0] conf1; +wire [15:0] conf2; +wire [15:0] conf3; +wire [15:0] conf4; +wire [15:0] conf5; +wire [15:0] conf6; +wire [15:0] conf7; +wire [15:0] conf8; +wire [15:0] conf9; +wire [15:0] conf10; +wire [15:0] conf11; +wire [15:0] conf12; +wire [15:0] conf13; +wire [15:0] conf14; +wire [15:0] conf15; + +//////////////////////////////////////////////////////////////////// +// +// Initial Configuration Check +// + +// synopsys translate_off +initial + begin + if(dw<16) + begin + $display("ERROR: Setting Data bus width to less than 16 bits, will"); + $display(" make it impossible to use the configurations registers."); + $finish; + end + end +// synopsys translate_on + +//////////////////////////////////////////////////////////////////// +// +// Master Interfaces +// + +wb_conmax_master_if #(aw,dw,sw) m0( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m0_data_i ), + .wb_data_o( m0_data_o ), + .wb_addr_i( m0_addr_i ), + .wb_sel_i( m0_sel_i ), + .wb_we_i( m0_we_i ), + .wb_cyc_i( m0_cyc_i ), + .wb_stb_i( m0_stb_i ), + .wb_ack_o( m0_ack_o ), + .wb_err_o( m0_err_o ), + .wb_rty_o( m0_rty_o ), + .s0_data_i( m0s0_data_i ), + .s0_data_o( m0s0_data_o ), + .s0_addr_o( m0s0_addr ), + .s0_sel_o( m0s0_sel ), + .s0_we_o( m0s0_we ), + .s0_cyc_o( m0s0_cyc ), + .s0_stb_o( m0s0_stb ), + .s0_ack_i( m0s0_ack ), + .s0_err_i( m0s0_err ), + .s0_rty_i( m0s0_rty ), + .s1_data_i( m0s1_data_i ), + .s1_data_o( m0s1_data_o ), + .s1_addr_o( m0s1_addr ), + .s1_sel_o( m0s1_sel ), + .s1_we_o( m0s1_we ), + .s1_cyc_o( m0s1_cyc ), + .s1_stb_o( m0s1_stb ), + .s1_ack_i( m0s1_ack ), + .s1_err_i( m0s1_err ), + .s1_rty_i( m0s1_rty ), + .s2_data_i( m0s2_data_i ), + .s2_data_o( m0s2_data_o ), + .s2_addr_o( m0s2_addr ), + .s2_sel_o( m0s2_sel ), + .s2_we_o( m0s2_we ), + .s2_cyc_o( m0s2_cyc ), + .s2_stb_o( m0s2_stb ), + .s2_ack_i( m0s2_ack ), + .s2_err_i( m0s2_err ), + .s2_rty_i( m0s2_rty ), + .s3_data_i( m0s3_data_i ), + .s3_data_o( m0s3_data_o ), + .s3_addr_o( m0s3_addr ), + .s3_sel_o( m0s3_sel ), + .s3_we_o( m0s3_we ), + .s3_cyc_o( m0s3_cyc ), + .s3_stb_o( m0s3_stb ), + .s3_ack_i( m0s3_ack ), + .s3_err_i( m0s3_err ), + .s3_rty_i( m0s3_rty ), + .s4_data_i( m0s4_data_i ), + .s4_data_o( m0s4_data_o ), + .s4_addr_o( m0s4_addr ), + .s4_sel_o( m0s4_sel ), + .s4_we_o( m0s4_we ), + .s4_cyc_o( m0s4_cyc ), + .s4_stb_o( m0s4_stb ), + .s4_ack_i( m0s4_ack ), + .s4_err_i( m0s4_err ), + .s4_rty_i( m0s4_rty ), + .s5_data_i( m0s5_data_i ), + .s5_data_o( m0s5_data_o ), + .s5_addr_o( m0s5_addr ), + .s5_sel_o( m0s5_sel ), + .s5_we_o( m0s5_we ), + .s5_cyc_o( m0s5_cyc ), + .s5_stb_o( m0s5_stb ), + .s5_ack_i( m0s5_ack ), + .s5_err_i( m0s5_err ), + .s5_rty_i( m0s5_rty ), + .s6_data_i( m0s6_data_i ), + .s6_data_o( m0s6_data_o ), + .s6_addr_o( m0s6_addr ), + .s6_sel_o( m0s6_sel ), + .s6_we_o( m0s6_we ), + .s6_cyc_o( m0s6_cyc ), + .s6_stb_o( m0s6_stb ), + .s6_ack_i( m0s6_ack ), + .s6_err_i( m0s6_err ), + .s6_rty_i( m0s6_rty ), + .s7_data_i( m0s7_data_i ), + .s7_data_o( m0s7_data_o ), + .s7_addr_o( m0s7_addr ), + .s7_sel_o( m0s7_sel ), + .s7_we_o( m0s7_we ), + .s7_cyc_o( m0s7_cyc ), + .s7_stb_o( m0s7_stb ), + .s7_ack_i( m0s7_ack ), + .s7_err_i( m0s7_err ), + .s7_rty_i( m0s7_rty ), + .s8_data_i( m0s8_data_i ), + .s8_data_o( m0s8_data_o ), + .s8_addr_o( m0s8_addr ), + .s8_sel_o( m0s8_sel ), + .s8_we_o( m0s8_we ), + .s8_cyc_o( m0s8_cyc ), + .s8_stb_o( m0s8_stb ), + .s8_ack_i( m0s8_ack ), + .s8_err_i( m0s8_err ), + .s8_rty_i( m0s8_rty ), + .s9_data_i( m0s9_data_i ), + .s9_data_o( m0s9_data_o ), + .s9_addr_o( m0s9_addr ), + .s9_sel_o( m0s9_sel ), + .s9_we_o( m0s9_we ), + .s9_cyc_o( m0s9_cyc ), + .s9_stb_o( m0s9_stb ), + .s9_ack_i( m0s9_ack ), + .s9_err_i( m0s9_err ), + .s9_rty_i( m0s9_rty ), + .s10_data_i( m0s10_data_i ), + .s10_data_o( m0s10_data_o ), + .s10_addr_o( m0s10_addr ), + .s10_sel_o( m0s10_sel ), + .s10_we_o( m0s10_we ), + .s10_cyc_o( m0s10_cyc ), + .s10_stb_o( m0s10_stb ), + .s10_ack_i( m0s10_ack ), + .s10_err_i( m0s10_err ), + .s10_rty_i( m0s10_rty ), + .s11_data_i( m0s11_data_i ), + .s11_data_o( m0s11_data_o ), + .s11_addr_o( m0s11_addr ), + .s11_sel_o( m0s11_sel ), + .s11_we_o( m0s11_we ), + .s11_cyc_o( m0s11_cyc ), + .s11_stb_o( m0s11_stb ), + .s11_ack_i( m0s11_ack ), + .s11_err_i( m0s11_err ), + .s11_rty_i( m0s11_rty ), + .s12_data_i( m0s12_data_i ), + .s12_data_o( m0s12_data_o ), + .s12_addr_o( m0s12_addr ), + .s12_sel_o( m0s12_sel ), + .s12_we_o( m0s12_we ), + .s12_cyc_o( m0s12_cyc ), + .s12_stb_o( m0s12_stb ), + .s12_ack_i( m0s12_ack ), + .s12_err_i( m0s12_err ), + .s12_rty_i( m0s12_rty ), + .s13_data_i( m0s13_data_i ), + .s13_data_o( m0s13_data_o ), + .s13_addr_o( m0s13_addr ), + .s13_sel_o( m0s13_sel ), + .s13_we_o( m0s13_we ), + .s13_cyc_o( m0s13_cyc ), + .s13_stb_o( m0s13_stb ), + .s13_ack_i( m0s13_ack ), + .s13_err_i( m0s13_err ), + .s13_rty_i( m0s13_rty ), + .s14_data_i( m0s14_data_i ), + .s14_data_o( m0s14_data_o ), + .s14_addr_o( m0s14_addr ), + .s14_sel_o( m0s14_sel ), + .s14_we_o( m0s14_we ), + .s14_cyc_o( m0s14_cyc ), + .s14_stb_o( m0s14_stb ), + .s14_ack_i( m0s14_ack ), + .s14_err_i( m0s14_err ), + .s14_rty_i( m0s14_rty ), + .s15_data_i( m0s15_data_i ), + .s15_data_o( m0s15_data_o ), + .s15_addr_o( m0s15_addr ), + .s15_sel_o( m0s15_sel ), + .s15_we_o( m0s15_we ), + .s15_cyc_o( m0s15_cyc ), + .s15_stb_o( m0s15_stb ), + .s15_ack_i( m0s15_ack ), + .s15_err_i( m0s15_err ), + .s15_rty_i( m0s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m1( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m1_data_i ), + .wb_data_o( m1_data_o ), + .wb_addr_i( m1_addr_i ), + .wb_sel_i( m1_sel_i ), + .wb_we_i( m1_we_i ), + .wb_cyc_i( m1_cyc_i ), + .wb_stb_i( m1_stb_i ), + .wb_ack_o( m1_ack_o ), + .wb_err_o( m1_err_o ), + .wb_rty_o( m1_rty_o ), + .s0_data_i( m1s0_data_i ), + .s0_data_o( m1s0_data_o ), + .s0_addr_o( m1s0_addr ), + .s0_sel_o( m1s0_sel ), + .s0_we_o( m1s0_we ), + .s0_cyc_o( m1s0_cyc ), + .s0_stb_o( m1s0_stb ), + .s0_ack_i( m1s0_ack ), + .s0_err_i( m1s0_err ), + .s0_rty_i( m1s0_rty ), + .s1_data_i( m1s1_data_i ), + .s1_data_o( m1s1_data_o ), + .s1_addr_o( m1s1_addr ), + .s1_sel_o( m1s1_sel ), + .s1_we_o( m1s1_we ), + .s1_cyc_o( m1s1_cyc ), + .s1_stb_o( m1s1_stb ), + .s1_ack_i( m1s1_ack ), + .s1_err_i( m1s1_err ), + .s1_rty_i( m1s1_rty ), + .s2_data_i( m1s2_data_i ), + .s2_data_o( m1s2_data_o ), + .s2_addr_o( m1s2_addr ), + .s2_sel_o( m1s2_sel ), + .s2_we_o( m1s2_we ), + .s2_cyc_o( m1s2_cyc ), + .s2_stb_o( m1s2_stb ), + .s2_ack_i( m1s2_ack ), + .s2_err_i( m1s2_err ), + .s2_rty_i( m1s2_rty ), + .s3_data_i( m1s3_data_i ), + .s3_data_o( m1s3_data_o ), + .s3_addr_o( m1s3_addr ), + .s3_sel_o( m1s3_sel ), + .s3_we_o( m1s3_we ), + .s3_cyc_o( m1s3_cyc ), + .s3_stb_o( m1s3_stb ), + .s3_ack_i( m1s3_ack ), + .s3_err_i( m1s3_err ), + .s3_rty_i( m1s3_rty ), + .s4_data_i( m1s4_data_i ), + .s4_data_o( m1s4_data_o ), + .s4_addr_o( m1s4_addr ), + .s4_sel_o( m1s4_sel ), + .s4_we_o( m1s4_we ), + .s4_cyc_o( m1s4_cyc ), + .s4_stb_o( m1s4_stb ), + .s4_ack_i( m1s4_ack ), + .s4_err_i( m1s4_err ), + .s4_rty_i( m1s4_rty ), + .s5_data_i( m1s5_data_i ), + .s5_data_o( m1s5_data_o ), + .s5_addr_o( m1s5_addr ), + .s5_sel_o( m1s5_sel ), + .s5_we_o( m1s5_we ), + .s5_cyc_o( m1s5_cyc ), + .s5_stb_o( m1s5_stb ), + .s5_ack_i( m1s5_ack ), + .s5_err_i( m1s5_err ), + .s5_rty_i( m1s5_rty ), + .s6_data_i( m1s6_data_i ), + .s6_data_o( m1s6_data_o ), + .s6_addr_o( m1s6_addr ), + .s6_sel_o( m1s6_sel ), + .s6_we_o( m1s6_we ), + .s6_cyc_o( m1s6_cyc ), + .s6_stb_o( m1s6_stb ), + .s6_ack_i( m1s6_ack ), + .s6_err_i( m1s6_err ), + .s6_rty_i( m1s6_rty ), + .s7_data_i( m1s7_data_i ), + .s7_data_o( m1s7_data_o ), + .s7_addr_o( m1s7_addr ), + .s7_sel_o( m1s7_sel ), + .s7_we_o( m1s7_we ), + .s7_cyc_o( m1s7_cyc ), + .s7_stb_o( m1s7_stb ), + .s7_ack_i( m1s7_ack ), + .s7_err_i( m1s7_err ), + .s7_rty_i( m1s7_rty ), + .s8_data_i( m1s8_data_i ), + .s8_data_o( m1s8_data_o ), + .s8_addr_o( m1s8_addr ), + .s8_sel_o( m1s8_sel ), + .s8_we_o( m1s8_we ), + .s8_cyc_o( m1s8_cyc ), + .s8_stb_o( m1s8_stb ), + .s8_ack_i( m1s8_ack ), + .s8_err_i( m1s8_err ), + .s8_rty_i( m1s8_rty ), + .s9_data_i( m1s9_data_i ), + .s9_data_o( m1s9_data_o ), + .s9_addr_o( m1s9_addr ), + .s9_sel_o( m1s9_sel ), + .s9_we_o( m1s9_we ), + .s9_cyc_o( m1s9_cyc ), + .s9_stb_o( m1s9_stb ), + .s9_ack_i( m1s9_ack ), + .s9_err_i( m1s9_err ), + .s9_rty_i( m1s9_rty ), + .s10_data_i( m1s10_data_i ), + .s10_data_o( m1s10_data_o ), + .s10_addr_o( m1s10_addr ), + .s10_sel_o( m1s10_sel ), + .s10_we_o( m1s10_we ), + .s10_cyc_o( m1s10_cyc ), + .s10_stb_o( m1s10_stb ), + .s10_ack_i( m1s10_ack ), + .s10_err_i( m1s10_err ), + .s10_rty_i( m1s10_rty ), + .s11_data_i( m1s11_data_i ), + .s11_data_o( m1s11_data_o ), + .s11_addr_o( m1s11_addr ), + .s11_sel_o( m1s11_sel ), + .s11_we_o( m1s11_we ), + .s11_cyc_o( m1s11_cyc ), + .s11_stb_o( m1s11_stb ), + .s11_ack_i( m1s11_ack ), + .s11_err_i( m1s11_err ), + .s11_rty_i( m1s11_rty ), + .s12_data_i( m1s12_data_i ), + .s12_data_o( m1s12_data_o ), + .s12_addr_o( m1s12_addr ), + .s12_sel_o( m1s12_sel ), + .s12_we_o( m1s12_we ), + .s12_cyc_o( m1s12_cyc ), + .s12_stb_o( m1s12_stb ), + .s12_ack_i( m1s12_ack ), + .s12_err_i( m1s12_err ), + .s12_rty_i( m1s12_rty ), + .s13_data_i( m1s13_data_i ), + .s13_data_o( m1s13_data_o ), + .s13_addr_o( m1s13_addr ), + .s13_sel_o( m1s13_sel ), + .s13_we_o( m1s13_we ), + .s13_cyc_o( m1s13_cyc ), + .s13_stb_o( m1s13_stb ), + .s13_ack_i( m1s13_ack ), + .s13_err_i( m1s13_err ), + .s13_rty_i( m1s13_rty ), + .s14_data_i( m1s14_data_i ), + .s14_data_o( m1s14_data_o ), + .s14_addr_o( m1s14_addr ), + .s14_sel_o( m1s14_sel ), + .s14_we_o( m1s14_we ), + .s14_cyc_o( m1s14_cyc ), + .s14_stb_o( m1s14_stb ), + .s14_ack_i( m1s14_ack ), + .s14_err_i( m1s14_err ), + .s14_rty_i( m1s14_rty ), + .s15_data_i( m1s15_data_i ), + .s15_data_o( m1s15_data_o ), + .s15_addr_o( m1s15_addr ), + .s15_sel_o( m1s15_sel ), + .s15_we_o( m1s15_we ), + .s15_cyc_o( m1s15_cyc ), + .s15_stb_o( m1s15_stb ), + .s15_ack_i( m1s15_ack ), + .s15_err_i( m1s15_err ), + .s15_rty_i( m1s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m2( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m2_data_i ), + .wb_data_o( m2_data_o ), + .wb_addr_i( m2_addr_i ), + .wb_sel_i( m2_sel_i ), + .wb_we_i( m2_we_i ), + .wb_cyc_i( m2_cyc_i ), + .wb_stb_i( m2_stb_i ), + .wb_ack_o( m2_ack_o ), + .wb_err_o( m2_err_o ), + .wb_rty_o( m2_rty_o ), + .s0_data_i( m2s0_data_i ), + .s0_data_o( m2s0_data_o ), + .s0_addr_o( m2s0_addr ), + .s0_sel_o( m2s0_sel ), + .s0_we_o( m2s0_we ), + .s0_cyc_o( m2s0_cyc ), + .s0_stb_o( m2s0_stb ), + .s0_ack_i( m2s0_ack ), + .s0_err_i( m2s0_err ), + .s0_rty_i( m2s0_rty ), + .s1_data_i( m2s1_data_i ), + .s1_data_o( m2s1_data_o ), + .s1_addr_o( m2s1_addr ), + .s1_sel_o( m2s1_sel ), + .s1_we_o( m2s1_we ), + .s1_cyc_o( m2s1_cyc ), + .s1_stb_o( m2s1_stb ), + .s1_ack_i( m2s1_ack ), + .s1_err_i( m2s1_err ), + .s1_rty_i( m2s1_rty ), + .s2_data_i( m2s2_data_i ), + .s2_data_o( m2s2_data_o ), + .s2_addr_o( m2s2_addr ), + .s2_sel_o( m2s2_sel ), + .s2_we_o( m2s2_we ), + .s2_cyc_o( m2s2_cyc ), + .s2_stb_o( m2s2_stb ), + .s2_ack_i( m2s2_ack ), + .s2_err_i( m2s2_err ), + .s2_rty_i( m2s2_rty ), + .s3_data_i( m2s3_data_i ), + .s3_data_o( m2s3_data_o ), + .s3_addr_o( m2s3_addr ), + .s3_sel_o( m2s3_sel ), + .s3_we_o( m2s3_we ), + .s3_cyc_o( m2s3_cyc ), + .s3_stb_o( m2s3_stb ), + .s3_ack_i( m2s3_ack ), + .s3_err_i( m2s3_err ), + .s3_rty_i( m2s3_rty ), + .s4_data_i( m2s4_data_i ), + .s4_data_o( m2s4_data_o ), + .s4_addr_o( m2s4_addr ), + .s4_sel_o( m2s4_sel ), + .s4_we_o( m2s4_we ), + .s4_cyc_o( m2s4_cyc ), + .s4_stb_o( m2s4_stb ), + .s4_ack_i( m2s4_ack ), + .s4_err_i( m2s4_err ), + .s4_rty_i( m2s4_rty ), + .s5_data_i( m2s5_data_i ), + .s5_data_o( m2s5_data_o ), + .s5_addr_o( m2s5_addr ), + .s5_sel_o( m2s5_sel ), + .s5_we_o( m2s5_we ), + .s5_cyc_o( m2s5_cyc ), + .s5_stb_o( m2s5_stb ), + .s5_ack_i( m2s5_ack ), + .s5_err_i( m2s5_err ), + .s5_rty_i( m2s5_rty ), + .s6_data_i( m2s6_data_i ), + .s6_data_o( m2s6_data_o ), + .s6_addr_o( m2s6_addr ), + .s6_sel_o( m2s6_sel ), + .s6_we_o( m2s6_we ), + .s6_cyc_o( m2s6_cyc ), + .s6_stb_o( m2s6_stb ), + .s6_ack_i( m2s6_ack ), + .s6_err_i( m2s6_err ), + .s6_rty_i( m2s6_rty ), + .s7_data_i( m2s7_data_i ), + .s7_data_o( m2s7_data_o ), + .s7_addr_o( m2s7_addr ), + .s7_sel_o( m2s7_sel ), + .s7_we_o( m2s7_we ), + .s7_cyc_o( m2s7_cyc ), + .s7_stb_o( m2s7_stb ), + .s7_ack_i( m2s7_ack ), + .s7_err_i( m2s7_err ), + .s7_rty_i( m2s7_rty ), + .s8_data_i( m2s8_data_i ), + .s8_data_o( m2s8_data_o ), + .s8_addr_o( m2s8_addr ), + .s8_sel_o( m2s8_sel ), + .s8_we_o( m2s8_we ), + .s8_cyc_o( m2s8_cyc ), + .s8_stb_o( m2s8_stb ), + .s8_ack_i( m2s8_ack ), + .s8_err_i( m2s8_err ), + .s8_rty_i( m2s8_rty ), + .s9_data_i( m2s9_data_i ), + .s9_data_o( m2s9_data_o ), + .s9_addr_o( m2s9_addr ), + .s9_sel_o( m2s9_sel ), + .s9_we_o( m2s9_we ), + .s9_cyc_o( m2s9_cyc ), + .s9_stb_o( m2s9_stb ), + .s9_ack_i( m2s9_ack ), + .s9_err_i( m2s9_err ), + .s9_rty_i( m2s9_rty ), + .s10_data_i( m2s10_data_i ), + .s10_data_o( m2s10_data_o ), + .s10_addr_o( m2s10_addr ), + .s10_sel_o( m2s10_sel ), + .s10_we_o( m2s10_we ), + .s10_cyc_o( m2s10_cyc ), + .s10_stb_o( m2s10_stb ), + .s10_ack_i( m2s10_ack ), + .s10_err_i( m2s10_err ), + .s10_rty_i( m2s10_rty ), + .s11_data_i( m2s11_data_i ), + .s11_data_o( m2s11_data_o ), + .s11_addr_o( m2s11_addr ), + .s11_sel_o( m2s11_sel ), + .s11_we_o( m2s11_we ), + .s11_cyc_o( m2s11_cyc ), + .s11_stb_o( m2s11_stb ), + .s11_ack_i( m2s11_ack ), + .s11_err_i( m2s11_err ), + .s11_rty_i( m2s11_rty ), + .s12_data_i( m2s12_data_i ), + .s12_data_o( m2s12_data_o ), + .s12_addr_o( m2s12_addr ), + .s12_sel_o( m2s12_sel ), + .s12_we_o( m2s12_we ), + .s12_cyc_o( m2s12_cyc ), + .s12_stb_o( m2s12_stb ), + .s12_ack_i( m2s12_ack ), + .s12_err_i( m2s12_err ), + .s12_rty_i( m2s12_rty ), + .s13_data_i( m2s13_data_i ), + .s13_data_o( m2s13_data_o ), + .s13_addr_o( m2s13_addr ), + .s13_sel_o( m2s13_sel ), + .s13_we_o( m2s13_we ), + .s13_cyc_o( m2s13_cyc ), + .s13_stb_o( m2s13_stb ), + .s13_ack_i( m2s13_ack ), + .s13_err_i( m2s13_err ), + .s13_rty_i( m2s13_rty ), + .s14_data_i( m2s14_data_i ), + .s14_data_o( m2s14_data_o ), + .s14_addr_o( m2s14_addr ), + .s14_sel_o( m2s14_sel ), + .s14_we_o( m2s14_we ), + .s14_cyc_o( m2s14_cyc ), + .s14_stb_o( m2s14_stb ), + .s14_ack_i( m2s14_ack ), + .s14_err_i( m2s14_err ), + .s14_rty_i( m2s14_rty ), + .s15_data_i( m2s15_data_i ), + .s15_data_o( m2s15_data_o ), + .s15_addr_o( m2s15_addr ), + .s15_sel_o( m2s15_sel ), + .s15_we_o( m2s15_we ), + .s15_cyc_o( m2s15_cyc ), + .s15_stb_o( m2s15_stb ), + .s15_ack_i( m2s15_ack ), + .s15_err_i( m2s15_err ), + .s15_rty_i( m2s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m3( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m3_data_i ), + .wb_data_o( m3_data_o ), + .wb_addr_i( m3_addr_i ), + .wb_sel_i( m3_sel_i ), + .wb_we_i( m3_we_i ), + .wb_cyc_i( m3_cyc_i ), + .wb_stb_i( m3_stb_i ), + .wb_ack_o( m3_ack_o ), + .wb_err_o( m3_err_o ), + .wb_rty_o( m3_rty_o ), + .s0_data_i( m3s0_data_i ), + .s0_data_o( m3s0_data_o ), + .s0_addr_o( m3s0_addr ), + .s0_sel_o( m3s0_sel ), + .s0_we_o( m3s0_we ), + .s0_cyc_o( m3s0_cyc ), + .s0_stb_o( m3s0_stb ), + .s0_ack_i( m3s0_ack ), + .s0_err_i( m3s0_err ), + .s0_rty_i( m3s0_rty ), + .s1_data_i( m3s1_data_i ), + .s1_data_o( m3s1_data_o ), + .s1_addr_o( m3s1_addr ), + .s1_sel_o( m3s1_sel ), + .s1_we_o( m3s1_we ), + .s1_cyc_o( m3s1_cyc ), + .s1_stb_o( m3s1_stb ), + .s1_ack_i( m3s1_ack ), + .s1_err_i( m3s1_err ), + .s1_rty_i( m3s1_rty ), + .s2_data_i( m3s2_data_i ), + .s2_data_o( m3s2_data_o ), + .s2_addr_o( m3s2_addr ), + .s2_sel_o( m3s2_sel ), + .s2_we_o( m3s2_we ), + .s2_cyc_o( m3s2_cyc ), + .s2_stb_o( m3s2_stb ), + .s2_ack_i( m3s2_ack ), + .s2_err_i( m3s2_err ), + .s2_rty_i( m3s2_rty ), + .s3_data_i( m3s3_data_i ), + .s3_data_o( m3s3_data_o ), + .s3_addr_o( m3s3_addr ), + .s3_sel_o( m3s3_sel ), + .s3_we_o( m3s3_we ), + .s3_cyc_o( m3s3_cyc ), + .s3_stb_o( m3s3_stb ), + .s3_ack_i( m3s3_ack ), + .s3_err_i( m3s3_err ), + .s3_rty_i( m3s3_rty ), + .s4_data_i( m3s4_data_i ), + .s4_data_o( m3s4_data_o ), + .s4_addr_o( m3s4_addr ), + .s4_sel_o( m3s4_sel ), + .s4_we_o( m3s4_we ), + .s4_cyc_o( m3s4_cyc ), + .s4_stb_o( m3s4_stb ), + .s4_ack_i( m3s4_ack ), + .s4_err_i( m3s4_err ), + .s4_rty_i( m3s4_rty ), + .s5_data_i( m3s5_data_i ), + .s5_data_o( m3s5_data_o ), + .s5_addr_o( m3s5_addr ), + .s5_sel_o( m3s5_sel ), + .s5_we_o( m3s5_we ), + .s5_cyc_o( m3s5_cyc ), + .s5_stb_o( m3s5_stb ), + .s5_ack_i( m3s5_ack ), + .s5_err_i( m3s5_err ), + .s5_rty_i( m3s5_rty ), + .s6_data_i( m3s6_data_i ), + .s6_data_o( m3s6_data_o ), + .s6_addr_o( m3s6_addr ), + .s6_sel_o( m3s6_sel ), + .s6_we_o( m3s6_we ), + .s6_cyc_o( m3s6_cyc ), + .s6_stb_o( m3s6_stb ), + .s6_ack_i( m3s6_ack ), + .s6_err_i( m3s6_err ), + .s6_rty_i( m3s6_rty ), + .s7_data_i( m3s7_data_i ), + .s7_data_o( m3s7_data_o ), + .s7_addr_o( m3s7_addr ), + .s7_sel_o( m3s7_sel ), + .s7_we_o( m3s7_we ), + .s7_cyc_o( m3s7_cyc ), + .s7_stb_o( m3s7_stb ), + .s7_ack_i( m3s7_ack ), + .s7_err_i( m3s7_err ), + .s7_rty_i( m3s7_rty ), + .s8_data_i( m3s8_data_i ), + .s8_data_o( m3s8_data_o ), + .s8_addr_o( m3s8_addr ), + .s8_sel_o( m3s8_sel ), + .s8_we_o( m3s8_we ), + .s8_cyc_o( m3s8_cyc ), + .s8_stb_o( m3s8_stb ), + .s8_ack_i( m3s8_ack ), + .s8_err_i( m3s8_err ), + .s8_rty_i( m3s8_rty ), + .s9_data_i( m3s9_data_i ), + .s9_data_o( m3s9_data_o ), + .s9_addr_o( m3s9_addr ), + .s9_sel_o( m3s9_sel ), + .s9_we_o( m3s9_we ), + .s9_cyc_o( m3s9_cyc ), + .s9_stb_o( m3s9_stb ), + .s9_ack_i( m3s9_ack ), + .s9_err_i( m3s9_err ), + .s9_rty_i( m3s9_rty ), + .s10_data_i( m3s10_data_i ), + .s10_data_o( m3s10_data_o ), + .s10_addr_o( m3s10_addr ), + .s10_sel_o( m3s10_sel ), + .s10_we_o( m3s10_we ), + .s10_cyc_o( m3s10_cyc ), + .s10_stb_o( m3s10_stb ), + .s10_ack_i( m3s10_ack ), + .s10_err_i( m3s10_err ), + .s10_rty_i( m3s10_rty ), + .s11_data_i( m3s11_data_i ), + .s11_data_o( m3s11_data_o ), + .s11_addr_o( m3s11_addr ), + .s11_sel_o( m3s11_sel ), + .s11_we_o( m3s11_we ), + .s11_cyc_o( m3s11_cyc ), + .s11_stb_o( m3s11_stb ), + .s11_ack_i( m3s11_ack ), + .s11_err_i( m3s11_err ), + .s11_rty_i( m3s11_rty ), + .s12_data_i( m3s12_data_i ), + .s12_data_o( m3s12_data_o ), + .s12_addr_o( m3s12_addr ), + .s12_sel_o( m3s12_sel ), + .s12_we_o( m3s12_we ), + .s12_cyc_o( m3s12_cyc ), + .s12_stb_o( m3s12_stb ), + .s12_ack_i( m3s12_ack ), + .s12_err_i( m3s12_err ), + .s12_rty_i( m3s12_rty ), + .s13_data_i( m3s13_data_i ), + .s13_data_o( m3s13_data_o ), + .s13_addr_o( m3s13_addr ), + .s13_sel_o( m3s13_sel ), + .s13_we_o( m3s13_we ), + .s13_cyc_o( m3s13_cyc ), + .s13_stb_o( m3s13_stb ), + .s13_ack_i( m3s13_ack ), + .s13_err_i( m3s13_err ), + .s13_rty_i( m3s13_rty ), + .s14_data_i( m3s14_data_i ), + .s14_data_o( m3s14_data_o ), + .s14_addr_o( m3s14_addr ), + .s14_sel_o( m3s14_sel ), + .s14_we_o( m3s14_we ), + .s14_cyc_o( m3s14_cyc ), + .s14_stb_o( m3s14_stb ), + .s14_ack_i( m3s14_ack ), + .s14_err_i( m3s14_err ), + .s14_rty_i( m3s14_rty ), + .s15_data_i( m3s15_data_i ), + .s15_data_o( m3s15_data_o ), + .s15_addr_o( m3s15_addr ), + .s15_sel_o( m3s15_sel ), + .s15_we_o( m3s15_we ), + .s15_cyc_o( m3s15_cyc ), + .s15_stb_o( m3s15_stb ), + .s15_ack_i( m3s15_ack ), + .s15_err_i( m3s15_err ), + .s15_rty_i( m3s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m4( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m4_data_i ), + .wb_data_o( m4_data_o ), + .wb_addr_i( m4_addr_i ), + .wb_sel_i( m4_sel_i ), + .wb_we_i( m4_we_i ), + .wb_cyc_i( m4_cyc_i ), + .wb_stb_i( m4_stb_i ), + .wb_ack_o( m4_ack_o ), + .wb_err_o( m4_err_o ), + .wb_rty_o( m4_rty_o ), + .s0_data_i( m4s0_data_i ), + .s0_data_o( m4s0_data_o ), + .s0_addr_o( m4s0_addr ), + .s0_sel_o( m4s0_sel ), + .s0_we_o( m4s0_we ), + .s0_cyc_o( m4s0_cyc ), + .s0_stb_o( m4s0_stb ), + .s0_ack_i( m4s0_ack ), + .s0_err_i( m4s0_err ), + .s0_rty_i( m4s0_rty ), + .s1_data_i( m4s1_data_i ), + .s1_data_o( m4s1_data_o ), + .s1_addr_o( m4s1_addr ), + .s1_sel_o( m4s1_sel ), + .s1_we_o( m4s1_we ), + .s1_cyc_o( m4s1_cyc ), + .s1_stb_o( m4s1_stb ), + .s1_ack_i( m4s1_ack ), + .s1_err_i( m4s1_err ), + .s1_rty_i( m4s1_rty ), + .s2_data_i( m4s2_data_i ), + .s2_data_o( m4s2_data_o ), + .s2_addr_o( m4s2_addr ), + .s2_sel_o( m4s2_sel ), + .s2_we_o( m4s2_we ), + .s2_cyc_o( m4s2_cyc ), + .s2_stb_o( m4s2_stb ), + .s2_ack_i( m4s2_ack ), + .s2_err_i( m4s2_err ), + .s2_rty_i( m4s2_rty ), + .s3_data_i( m4s3_data_i ), + .s3_data_o( m4s3_data_o ), + .s3_addr_o( m4s3_addr ), + .s3_sel_o( m4s3_sel ), + .s3_we_o( m4s3_we ), + .s3_cyc_o( m4s3_cyc ), + .s3_stb_o( m4s3_stb ), + .s3_ack_i( m4s3_ack ), + .s3_err_i( m4s3_err ), + .s3_rty_i( m4s3_rty ), + .s4_data_i( m4s4_data_i ), + .s4_data_o( m4s4_data_o ), + .s4_addr_o( m4s4_addr ), + .s4_sel_o( m4s4_sel ), + .s4_we_o( m4s4_we ), + .s4_cyc_o( m4s4_cyc ), + .s4_stb_o( m4s4_stb ), + .s4_ack_i( m4s4_ack ), + .s4_err_i( m4s4_err ), + .s4_rty_i( m4s4_rty ), + .s5_data_i( m4s5_data_i ), + .s5_data_o( m4s5_data_o ), + .s5_addr_o( m4s5_addr ), + .s5_sel_o( m4s5_sel ), + .s5_we_o( m4s5_we ), + .s5_cyc_o( m4s5_cyc ), + .s5_stb_o( m4s5_stb ), + .s5_ack_i( m4s5_ack ), + .s5_err_i( m4s5_err ), + .s5_rty_i( m4s5_rty ), + .s6_data_i( m4s6_data_i ), + .s6_data_o( m4s6_data_o ), + .s6_addr_o( m4s6_addr ), + .s6_sel_o( m4s6_sel ), + .s6_we_o( m4s6_we ), + .s6_cyc_o( m4s6_cyc ), + .s6_stb_o( m4s6_stb ), + .s6_ack_i( m4s6_ack ), + .s6_err_i( m4s6_err ), + .s6_rty_i( m4s6_rty ), + .s7_data_i( m4s7_data_i ), + .s7_data_o( m4s7_data_o ), + .s7_addr_o( m4s7_addr ), + .s7_sel_o( m4s7_sel ), + .s7_we_o( m4s7_we ), + .s7_cyc_o( m4s7_cyc ), + .s7_stb_o( m4s7_stb ), + .s7_ack_i( m4s7_ack ), + .s7_err_i( m4s7_err ), + .s7_rty_i( m4s7_rty ), + .s8_data_i( m4s8_data_i ), + .s8_data_o( m4s8_data_o ), + .s8_addr_o( m4s8_addr ), + .s8_sel_o( m4s8_sel ), + .s8_we_o( m4s8_we ), + .s8_cyc_o( m4s8_cyc ), + .s8_stb_o( m4s8_stb ), + .s8_ack_i( m4s8_ack ), + .s8_err_i( m4s8_err ), + .s8_rty_i( m4s8_rty ), + .s9_data_i( m4s9_data_i ), + .s9_data_o( m4s9_data_o ), + .s9_addr_o( m4s9_addr ), + .s9_sel_o( m4s9_sel ), + .s9_we_o( m4s9_we ), + .s9_cyc_o( m4s9_cyc ), + .s9_stb_o( m4s9_stb ), + .s9_ack_i( m4s9_ack ), + .s9_err_i( m4s9_err ), + .s9_rty_i( m4s9_rty ), + .s10_data_i( m4s10_data_i ), + .s10_data_o( m4s10_data_o ), + .s10_addr_o( m4s10_addr ), + .s10_sel_o( m4s10_sel ), + .s10_we_o( m4s10_we ), + .s10_cyc_o( m4s10_cyc ), + .s10_stb_o( m4s10_stb ), + .s10_ack_i( m4s10_ack ), + .s10_err_i( m4s10_err ), + .s10_rty_i( m4s10_rty ), + .s11_data_i( m4s11_data_i ), + .s11_data_o( m4s11_data_o ), + .s11_addr_o( m4s11_addr ), + .s11_sel_o( m4s11_sel ), + .s11_we_o( m4s11_we ), + .s11_cyc_o( m4s11_cyc ), + .s11_stb_o( m4s11_stb ), + .s11_ack_i( m4s11_ack ), + .s11_err_i( m4s11_err ), + .s11_rty_i( m4s11_rty ), + .s12_data_i( m4s12_data_i ), + .s12_data_o( m4s12_data_o ), + .s12_addr_o( m4s12_addr ), + .s12_sel_o( m4s12_sel ), + .s12_we_o( m4s12_we ), + .s12_cyc_o( m4s12_cyc ), + .s12_stb_o( m4s12_stb ), + .s12_ack_i( m4s12_ack ), + .s12_err_i( m4s12_err ), + .s12_rty_i( m4s12_rty ), + .s13_data_i( m4s13_data_i ), + .s13_data_o( m4s13_data_o ), + .s13_addr_o( m4s13_addr ), + .s13_sel_o( m4s13_sel ), + .s13_we_o( m4s13_we ), + .s13_cyc_o( m4s13_cyc ), + .s13_stb_o( m4s13_stb ), + .s13_ack_i( m4s13_ack ), + .s13_err_i( m4s13_err ), + .s13_rty_i( m4s13_rty ), + .s14_data_i( m4s14_data_i ), + .s14_data_o( m4s14_data_o ), + .s14_addr_o( m4s14_addr ), + .s14_sel_o( m4s14_sel ), + .s14_we_o( m4s14_we ), + .s14_cyc_o( m4s14_cyc ), + .s14_stb_o( m4s14_stb ), + .s14_ack_i( m4s14_ack ), + .s14_err_i( m4s14_err ), + .s14_rty_i( m4s14_rty ), + .s15_data_i( m4s15_data_i ), + .s15_data_o( m4s15_data_o ), + .s15_addr_o( m4s15_addr ), + .s15_sel_o( m4s15_sel ), + .s15_we_o( m4s15_we ), + .s15_cyc_o( m4s15_cyc ), + .s15_stb_o( m4s15_stb ), + .s15_ack_i( m4s15_ack ), + .s15_err_i( m4s15_err ), + .s15_rty_i( m4s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m5( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m5_data_i ), + .wb_data_o( m5_data_o ), + .wb_addr_i( m5_addr_i ), + .wb_sel_i( m5_sel_i ), + .wb_we_i( m5_we_i ), + .wb_cyc_i( m5_cyc_i ), + .wb_stb_i( m5_stb_i ), + .wb_ack_o( m5_ack_o ), + .wb_err_o( m5_err_o ), + .wb_rty_o( m5_rty_o ), + .s0_data_i( m5s0_data_i ), + .s0_data_o( m5s0_data_o ), + .s0_addr_o( m5s0_addr ), + .s0_sel_o( m5s0_sel ), + .s0_we_o( m5s0_we ), + .s0_cyc_o( m5s0_cyc ), + .s0_stb_o( m5s0_stb ), + .s0_ack_i( m5s0_ack ), + .s0_err_i( m5s0_err ), + .s0_rty_i( m5s0_rty ), + .s1_data_i( m5s1_data_i ), + .s1_data_o( m5s1_data_o ), + .s1_addr_o( m5s1_addr ), + .s1_sel_o( m5s1_sel ), + .s1_we_o( m5s1_we ), + .s1_cyc_o( m5s1_cyc ), + .s1_stb_o( m5s1_stb ), + .s1_ack_i( m5s1_ack ), + .s1_err_i( m5s1_err ), + .s1_rty_i( m5s1_rty ), + .s2_data_i( m5s2_data_i ), + .s2_data_o( m5s2_data_o ), + .s2_addr_o( m5s2_addr ), + .s2_sel_o( m5s2_sel ), + .s2_we_o( m5s2_we ), + .s2_cyc_o( m5s2_cyc ), + .s2_stb_o( m5s2_stb ), + .s2_ack_i( m5s2_ack ), + .s2_err_i( m5s2_err ), + .s2_rty_i( m5s2_rty ), + .s3_data_i( m5s3_data_i ), + .s3_data_o( m5s3_data_o ), + .s3_addr_o( m5s3_addr ), + .s3_sel_o( m5s3_sel ), + .s3_we_o( m5s3_we ), + .s3_cyc_o( m5s3_cyc ), + .s3_stb_o( m5s3_stb ), + .s3_ack_i( m5s3_ack ), + .s3_err_i( m5s3_err ), + .s3_rty_i( m5s3_rty ), + .s4_data_i( m5s4_data_i ), + .s4_data_o( m5s4_data_o ), + .s4_addr_o( m5s4_addr ), + .s4_sel_o( m5s4_sel ), + .s4_we_o( m5s4_we ), + .s4_cyc_o( m5s4_cyc ), + .s4_stb_o( m5s4_stb ), + .s4_ack_i( m5s4_ack ), + .s4_err_i( m5s4_err ), + .s4_rty_i( m5s4_rty ), + .s5_data_i( m5s5_data_i ), + .s5_data_o( m5s5_data_o ), + .s5_addr_o( m5s5_addr ), + .s5_sel_o( m5s5_sel ), + .s5_we_o( m5s5_we ), + .s5_cyc_o( m5s5_cyc ), + .s5_stb_o( m5s5_stb ), + .s5_ack_i( m5s5_ack ), + .s5_err_i( m5s5_err ), + .s5_rty_i( m5s5_rty ), + .s6_data_i( m5s6_data_i ), + .s6_data_o( m5s6_data_o ), + .s6_addr_o( m5s6_addr ), + .s6_sel_o( m5s6_sel ), + .s6_we_o( m5s6_we ), + .s6_cyc_o( m5s6_cyc ), + .s6_stb_o( m5s6_stb ), + .s6_ack_i( m5s6_ack ), + .s6_err_i( m5s6_err ), + .s6_rty_i( m5s6_rty ), + .s7_data_i( m5s7_data_i ), + .s7_data_o( m5s7_data_o ), + .s7_addr_o( m5s7_addr ), + .s7_sel_o( m5s7_sel ), + .s7_we_o( m5s7_we ), + .s7_cyc_o( m5s7_cyc ), + .s7_stb_o( m5s7_stb ), + .s7_ack_i( m5s7_ack ), + .s7_err_i( m5s7_err ), + .s7_rty_i( m5s7_rty ), + .s8_data_i( m5s8_data_i ), + .s8_data_o( m5s8_data_o ), + .s8_addr_o( m5s8_addr ), + .s8_sel_o( m5s8_sel ), + .s8_we_o( m5s8_we ), + .s8_cyc_o( m5s8_cyc ), + .s8_stb_o( m5s8_stb ), + .s8_ack_i( m5s8_ack ), + .s8_err_i( m5s8_err ), + .s8_rty_i( m5s8_rty ), + .s9_data_i( m5s9_data_i ), + .s9_data_o( m5s9_data_o ), + .s9_addr_o( m5s9_addr ), + .s9_sel_o( m5s9_sel ), + .s9_we_o( m5s9_we ), + .s9_cyc_o( m5s9_cyc ), + .s9_stb_o( m5s9_stb ), + .s9_ack_i( m5s9_ack ), + .s9_err_i( m5s9_err ), + .s9_rty_i( m5s9_rty ), + .s10_data_i( m5s10_data_i ), + .s10_data_o( m5s10_data_o ), + .s10_addr_o( m5s10_addr ), + .s10_sel_o( m5s10_sel ), + .s10_we_o( m5s10_we ), + .s10_cyc_o( m5s10_cyc ), + .s10_stb_o( m5s10_stb ), + .s10_ack_i( m5s10_ack ), + .s10_err_i( m5s10_err ), + .s10_rty_i( m5s10_rty ), + .s11_data_i( m5s11_data_i ), + .s11_data_o( m5s11_data_o ), + .s11_addr_o( m5s11_addr ), + .s11_sel_o( m5s11_sel ), + .s11_we_o( m5s11_we ), + .s11_cyc_o( m5s11_cyc ), + .s11_stb_o( m5s11_stb ), + .s11_ack_i( m5s11_ack ), + .s11_err_i( m5s11_err ), + .s11_rty_i( m5s11_rty ), + .s12_data_i( m5s12_data_i ), + .s12_data_o( m5s12_data_o ), + .s12_addr_o( m5s12_addr ), + .s12_sel_o( m5s12_sel ), + .s12_we_o( m5s12_we ), + .s12_cyc_o( m5s12_cyc ), + .s12_stb_o( m5s12_stb ), + .s12_ack_i( m5s12_ack ), + .s12_err_i( m5s12_err ), + .s12_rty_i( m5s12_rty ), + .s13_data_i( m5s13_data_i ), + .s13_data_o( m5s13_data_o ), + .s13_addr_o( m5s13_addr ), + .s13_sel_o( m5s13_sel ), + .s13_we_o( m5s13_we ), + .s13_cyc_o( m5s13_cyc ), + .s13_stb_o( m5s13_stb ), + .s13_ack_i( m5s13_ack ), + .s13_err_i( m5s13_err ), + .s13_rty_i( m5s13_rty ), + .s14_data_i( m5s14_data_i ), + .s14_data_o( m5s14_data_o ), + .s14_addr_o( m5s14_addr ), + .s14_sel_o( m5s14_sel ), + .s14_we_o( m5s14_we ), + .s14_cyc_o( m5s14_cyc ), + .s14_stb_o( m5s14_stb ), + .s14_ack_i( m5s14_ack ), + .s14_err_i( m5s14_err ), + .s14_rty_i( m5s14_rty ), + .s15_data_i( m5s15_data_i ), + .s15_data_o( m5s15_data_o ), + .s15_addr_o( m5s15_addr ), + .s15_sel_o( m5s15_sel ), + .s15_we_o( m5s15_we ), + .s15_cyc_o( m5s15_cyc ), + .s15_stb_o( m5s15_stb ), + .s15_ack_i( m5s15_ack ), + .s15_err_i( m5s15_err ), + .s15_rty_i( m5s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m6( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m6_data_i ), + .wb_data_o( m6_data_o ), + .wb_addr_i( m6_addr_i ), + .wb_sel_i( m6_sel_i ), + .wb_we_i( m6_we_i ), + .wb_cyc_i( m6_cyc_i ), + .wb_stb_i( m6_stb_i ), + .wb_ack_o( m6_ack_o ), + .wb_err_o( m6_err_o ), + .wb_rty_o( m6_rty_o ), + .s0_data_i( m6s0_data_i ), + .s0_data_o( m6s0_data_o ), + .s0_addr_o( m6s0_addr ), + .s0_sel_o( m6s0_sel ), + .s0_we_o( m6s0_we ), + .s0_cyc_o( m6s0_cyc ), + .s0_stb_o( m6s0_stb ), + .s0_ack_i( m6s0_ack ), + .s0_err_i( m6s0_err ), + .s0_rty_i( m6s0_rty ), + .s1_data_i( m6s1_data_i ), + .s1_data_o( m6s1_data_o ), + .s1_addr_o( m6s1_addr ), + .s1_sel_o( m6s1_sel ), + .s1_we_o( m6s1_we ), + .s1_cyc_o( m6s1_cyc ), + .s1_stb_o( m6s1_stb ), + .s1_ack_i( m6s1_ack ), + .s1_err_i( m6s1_err ), + .s1_rty_i( m6s1_rty ), + .s2_data_i( m6s2_data_i ), + .s2_data_o( m6s2_data_o ), + .s2_addr_o( m6s2_addr ), + .s2_sel_o( m6s2_sel ), + .s2_we_o( m6s2_we ), + .s2_cyc_o( m6s2_cyc ), + .s2_stb_o( m6s2_stb ), + .s2_ack_i( m6s2_ack ), + .s2_err_i( m6s2_err ), + .s2_rty_i( m6s2_rty ), + .s3_data_i( m6s3_data_i ), + .s3_data_o( m6s3_data_o ), + .s3_addr_o( m6s3_addr ), + .s3_sel_o( m6s3_sel ), + .s3_we_o( m6s3_we ), + .s3_cyc_o( m6s3_cyc ), + .s3_stb_o( m6s3_stb ), + .s3_ack_i( m6s3_ack ), + .s3_err_i( m6s3_err ), + .s3_rty_i( m6s3_rty ), + .s4_data_i( m6s4_data_i ), + .s4_data_o( m6s4_data_o ), + .s4_addr_o( m6s4_addr ), + .s4_sel_o( m6s4_sel ), + .s4_we_o( m6s4_we ), + .s4_cyc_o( m6s4_cyc ), + .s4_stb_o( m6s4_stb ), + .s4_ack_i( m6s4_ack ), + .s4_err_i( m6s4_err ), + .s4_rty_i( m6s4_rty ), + .s5_data_i( m6s5_data_i ), + .s5_data_o( m6s5_data_o ), + .s5_addr_o( m6s5_addr ), + .s5_sel_o( m6s5_sel ), + .s5_we_o( m6s5_we ), + .s5_cyc_o( m6s5_cyc ), + .s5_stb_o( m6s5_stb ), + .s5_ack_i( m6s5_ack ), + .s5_err_i( m6s5_err ), + .s5_rty_i( m6s5_rty ), + .s6_data_i( m6s6_data_i ), + .s6_data_o( m6s6_data_o ), + .s6_addr_o( m6s6_addr ), + .s6_sel_o( m6s6_sel ), + .s6_we_o( m6s6_we ), + .s6_cyc_o( m6s6_cyc ), + .s6_stb_o( m6s6_stb ), + .s6_ack_i( m6s6_ack ), + .s6_err_i( m6s6_err ), + .s6_rty_i( m6s6_rty ), + .s7_data_i( m6s7_data_i ), + .s7_data_o( m6s7_data_o ), + .s7_addr_o( m6s7_addr ), + .s7_sel_o( m6s7_sel ), + .s7_we_o( m6s7_we ), + .s7_cyc_o( m6s7_cyc ), + .s7_stb_o( m6s7_stb ), + .s7_ack_i( m6s7_ack ), + .s7_err_i( m6s7_err ), + .s7_rty_i( m6s7_rty ), + .s8_data_i( m6s8_data_i ), + .s8_data_o( m6s8_data_o ), + .s8_addr_o( m6s8_addr ), + .s8_sel_o( m6s8_sel ), + .s8_we_o( m6s8_we ), + .s8_cyc_o( m6s8_cyc ), + .s8_stb_o( m6s8_stb ), + .s8_ack_i( m6s8_ack ), + .s8_err_i( m6s8_err ), + .s8_rty_i( m6s8_rty ), + .s9_data_i( m6s9_data_i ), + .s9_data_o( m6s9_data_o ), + .s9_addr_o( m6s9_addr ), + .s9_sel_o( m6s9_sel ), + .s9_we_o( m6s9_we ), + .s9_cyc_o( m6s9_cyc ), + .s9_stb_o( m6s9_stb ), + .s9_ack_i( m6s9_ack ), + .s9_err_i( m6s9_err ), + .s9_rty_i( m6s9_rty ), + .s10_data_i( m6s10_data_i ), + .s10_data_o( m6s10_data_o ), + .s10_addr_o( m6s10_addr ), + .s10_sel_o( m6s10_sel ), + .s10_we_o( m6s10_we ), + .s10_cyc_o( m6s10_cyc ), + .s10_stb_o( m6s10_stb ), + .s10_ack_i( m6s10_ack ), + .s10_err_i( m6s10_err ), + .s10_rty_i( m6s10_rty ), + .s11_data_i( m6s11_data_i ), + .s11_data_o( m6s11_data_o ), + .s11_addr_o( m6s11_addr ), + .s11_sel_o( m6s11_sel ), + .s11_we_o( m6s11_we ), + .s11_cyc_o( m6s11_cyc ), + .s11_stb_o( m6s11_stb ), + .s11_ack_i( m6s11_ack ), + .s11_err_i( m6s11_err ), + .s11_rty_i( m6s11_rty ), + .s12_data_i( m6s12_data_i ), + .s12_data_o( m6s12_data_o ), + .s12_addr_o( m6s12_addr ), + .s12_sel_o( m6s12_sel ), + .s12_we_o( m6s12_we ), + .s12_cyc_o( m6s12_cyc ), + .s12_stb_o( m6s12_stb ), + .s12_ack_i( m6s12_ack ), + .s12_err_i( m6s12_err ), + .s12_rty_i( m6s12_rty ), + .s13_data_i( m6s13_data_i ), + .s13_data_o( m6s13_data_o ), + .s13_addr_o( m6s13_addr ), + .s13_sel_o( m6s13_sel ), + .s13_we_o( m6s13_we ), + .s13_cyc_o( m6s13_cyc ), + .s13_stb_o( m6s13_stb ), + .s13_ack_i( m6s13_ack ), + .s13_err_i( m6s13_err ), + .s13_rty_i( m6s13_rty ), + .s14_data_i( m6s14_data_i ), + .s14_data_o( m6s14_data_o ), + .s14_addr_o( m6s14_addr ), + .s14_sel_o( m6s14_sel ), + .s14_we_o( m6s14_we ), + .s14_cyc_o( m6s14_cyc ), + .s14_stb_o( m6s14_stb ), + .s14_ack_i( m6s14_ack ), + .s14_err_i( m6s14_err ), + .s14_rty_i( m6s14_rty ), + .s15_data_i( m6s15_data_i ), + .s15_data_o( m6s15_data_o ), + .s15_addr_o( m6s15_addr ), + .s15_sel_o( m6s15_sel ), + .s15_we_o( m6s15_we ), + .s15_cyc_o( m6s15_cyc ), + .s15_stb_o( m6s15_stb ), + .s15_ack_i( m6s15_ack ), + .s15_err_i( m6s15_err ), + .s15_rty_i( m6s15_rty ) + ); + +wb_conmax_master_if #(aw,dw,sw) m7( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m7_data_i ), + .wb_data_o( m7_data_o ), + .wb_addr_i( m7_addr_i ), + .wb_sel_i( m7_sel_i ), + .wb_we_i( m7_we_i ), + .wb_cyc_i( m7_cyc_i ), + .wb_stb_i( m7_stb_i ), + .wb_ack_o( m7_ack_o ), + .wb_err_o( m7_err_o ), + .wb_rty_o( m7_rty_o ), + .s0_data_i( m7s0_data_i ), + .s0_data_o( m7s0_data_o ), + .s0_addr_o( m7s0_addr ), + .s0_sel_o( m7s0_sel ), + .s0_we_o( m7s0_we ), + .s0_cyc_o( m7s0_cyc ), + .s0_stb_o( m7s0_stb ), + .s0_ack_i( m7s0_ack ), + .s0_err_i( m7s0_err ), + .s0_rty_i( m7s0_rty ), + .s1_data_i( m7s1_data_i ), + .s1_data_o( m7s1_data_o ), + .s1_addr_o( m7s1_addr ), + .s1_sel_o( m7s1_sel ), + .s1_we_o( m7s1_we ), + .s1_cyc_o( m7s1_cyc ), + .s1_stb_o( m7s1_stb ), + .s1_ack_i( m7s1_ack ), + .s1_err_i( m7s1_err ), + .s1_rty_i( m7s1_rty ), + .s2_data_i( m7s2_data_i ), + .s2_data_o( m7s2_data_o ), + .s2_addr_o( m7s2_addr ), + .s2_sel_o( m7s2_sel ), + .s2_we_o( m7s2_we ), + .s2_cyc_o( m7s2_cyc ), + .s2_stb_o( m7s2_stb ), + .s2_ack_i( m7s2_ack ), + .s2_err_i( m7s2_err ), + .s2_rty_i( m7s2_rty ), + .s3_data_i( m7s3_data_i ), + .s3_data_o( m7s3_data_o ), + .s3_addr_o( m7s3_addr ), + .s3_sel_o( m7s3_sel ), + .s3_we_o( m7s3_we ), + .s3_cyc_o( m7s3_cyc ), + .s3_stb_o( m7s3_stb ), + .s3_ack_i( m7s3_ack ), + .s3_err_i( m7s3_err ), + .s3_rty_i( m7s3_rty ), + .s4_data_i( m7s4_data_i ), + .s4_data_o( m7s4_data_o ), + .s4_addr_o( m7s4_addr ), + .s4_sel_o( m7s4_sel ), + .s4_we_o( m7s4_we ), + .s4_cyc_o( m7s4_cyc ), + .s4_stb_o( m7s4_stb ), + .s4_ack_i( m7s4_ack ), + .s4_err_i( m7s4_err ), + .s4_rty_i( m7s4_rty ), + .s5_data_i( m7s5_data_i ), + .s5_data_o( m7s5_data_o ), + .s5_addr_o( m7s5_addr ), + .s5_sel_o( m7s5_sel ), + .s5_we_o( m7s5_we ), + .s5_cyc_o( m7s5_cyc ), + .s5_stb_o( m7s5_stb ), + .s5_ack_i( m7s5_ack ), + .s5_err_i( m7s5_err ), + .s5_rty_i( m7s5_rty ), + .s6_data_i( m7s6_data_i ), + .s6_data_o( m7s6_data_o ), + .s6_addr_o( m7s6_addr ), + .s6_sel_o( m7s6_sel ), + .s6_we_o( m7s6_we ), + .s6_cyc_o( m7s6_cyc ), + .s6_stb_o( m7s6_stb ), + .s6_ack_i( m7s6_ack ), + .s6_err_i( m7s6_err ), + .s6_rty_i( m7s6_rty ), + .s7_data_i( m7s7_data_i ), + .s7_data_o( m7s7_data_o ), + .s7_addr_o( m7s7_addr ), + .s7_sel_o( m7s7_sel ), + .s7_we_o( m7s7_we ), + .s7_cyc_o( m7s7_cyc ), + .s7_stb_o( m7s7_stb ), + .s7_ack_i( m7s7_ack ), + .s7_err_i( m7s7_err ), + .s7_rty_i( m7s7_rty ), + .s8_data_i( m7s8_data_i ), + .s8_data_o( m7s8_data_o ), + .s8_addr_o( m7s8_addr ), + .s8_sel_o( m7s8_sel ), + .s8_we_o( m7s8_we ), + .s8_cyc_o( m7s8_cyc ), + .s8_stb_o( m7s8_stb ), + .s8_ack_i( m7s8_ack ), + .s8_err_i( m7s8_err ), + .s8_rty_i( m7s8_rty ), + .s9_data_i( m7s9_data_i ), + .s9_data_o( m7s9_data_o ), + .s9_addr_o( m7s9_addr ), + .s9_sel_o( m7s9_sel ), + .s9_we_o( m7s9_we ), + .s9_cyc_o( m7s9_cyc ), + .s9_stb_o( m7s9_stb ), + .s9_ack_i( m7s9_ack ), + .s9_err_i( m7s9_err ), + .s9_rty_i( m7s9_rty ), + .s10_data_i( m7s10_data_i ), + .s10_data_o( m7s10_data_o ), + .s10_addr_o( m7s10_addr ), + .s10_sel_o( m7s10_sel ), + .s10_we_o( m7s10_we ), + .s10_cyc_o( m7s10_cyc ), + .s10_stb_o( m7s10_stb ), + .s10_ack_i( m7s10_ack ), + .s10_err_i( m7s10_err ), + .s10_rty_i( m7s10_rty ), + .s11_data_i( m7s11_data_i ), + .s11_data_o( m7s11_data_o ), + .s11_addr_o( m7s11_addr ), + .s11_sel_o( m7s11_sel ), + .s11_we_o( m7s11_we ), + .s11_cyc_o( m7s11_cyc ), + .s11_stb_o( m7s11_stb ), + .s11_ack_i( m7s11_ack ), + .s11_err_i( m7s11_err ), + .s11_rty_i( m7s11_rty ), + .s12_data_i( m7s12_data_i ), + .s12_data_o( m7s12_data_o ), + .s12_addr_o( m7s12_addr ), + .s12_sel_o( m7s12_sel ), + .s12_we_o( m7s12_we ), + .s12_cyc_o( m7s12_cyc ), + .s12_stb_o( m7s12_stb ), + .s12_ack_i( m7s12_ack ), + .s12_err_i( m7s12_err ), + .s12_rty_i( m7s12_rty ), + .s13_data_i( m7s13_data_i ), + .s13_data_o( m7s13_data_o ), + .s13_addr_o( m7s13_addr ), + .s13_sel_o( m7s13_sel ), + .s13_we_o( m7s13_we ), + .s13_cyc_o( m7s13_cyc ), + .s13_stb_o( m7s13_stb ), + .s13_ack_i( m7s13_ack ), + .s13_err_i( m7s13_err ), + .s13_rty_i( m7s13_rty ), + .s14_data_i( m7s14_data_i ), + .s14_data_o( m7s14_data_o ), + .s14_addr_o( m7s14_addr ), + .s14_sel_o( m7s14_sel ), + .s14_we_o( m7s14_we ), + .s14_cyc_o( m7s14_cyc ), + .s14_stb_o( m7s14_stb ), + .s14_ack_i( m7s14_ack ), + .s14_err_i( m7s14_err ), + .s14_rty_i( m7s14_rty ), + .s15_data_i( m7s15_data_i ), + .s15_data_o( m7s15_data_o ), + .s15_addr_o( m7s15_addr ), + .s15_sel_o( m7s15_sel ), + .s15_we_o( m7s15_we ), + .s15_cyc_o( m7s15_cyc ), + .s15_stb_o( m7s15_stb ), + .s15_ack_i( m7s15_ack ), + .s15_err_i( m7s15_err ), + .s15_rty_i( m7s15_rty ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Slave Interfaces +// + +wb_conmax_slave_if #(pri_sel0,aw,dw,sw) s0( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf0 ), + .wb_data_i( s0_data_i ), + .wb_data_o( s0_data_o ), + .wb_addr_o( s0_addr_o ), + .wb_sel_o( s0_sel_o ), + .wb_we_o( s0_we_o ), + .wb_cyc_o( s0_cyc_o ), + .wb_stb_o( s0_stb_o ), + .wb_ack_i( s0_ack_i ), + .wb_err_i( s0_err_i ), + .wb_rty_i( s0_rty_i ), + .m0_data_i( m0s0_data_o ), + .m0_data_o( m0s0_data_i ), + .m0_addr_i( m0s0_addr ), + .m0_sel_i( m0s0_sel ), + .m0_we_i( m0s0_we ), + .m0_cyc_i( m0s0_cyc ), + .m0_stb_i( m0s0_stb ), + .m0_ack_o( m0s0_ack ), + .m0_err_o( m0s0_err ), + .m0_rty_o( m0s0_rty ), + .m1_data_i( m1s0_data_o ), + .m1_data_o( m1s0_data_i ), + .m1_addr_i( m1s0_addr ), + .m1_sel_i( m1s0_sel ), + .m1_we_i( m1s0_we ), + .m1_cyc_i( m1s0_cyc ), + .m1_stb_i( m1s0_stb ), + .m1_ack_o( m1s0_ack ), + .m1_err_o( m1s0_err ), + .m1_rty_o( m1s0_rty ), + .m2_data_i( m2s0_data_o ), + .m2_data_o( m2s0_data_i ), + .m2_addr_i( m2s0_addr ), + .m2_sel_i( m2s0_sel ), + .m2_we_i( m2s0_we ), + .m2_cyc_i( m2s0_cyc ), + .m2_stb_i( m2s0_stb ), + .m2_ack_o( m2s0_ack ), + .m2_err_o( m2s0_err ), + .m2_rty_o( m2s0_rty ), + .m3_data_i( m3s0_data_o ), + .m3_data_o( m3s0_data_i ), + .m3_addr_i( m3s0_addr ), + .m3_sel_i( m3s0_sel ), + .m3_we_i( m3s0_we ), + .m3_cyc_i( m3s0_cyc ), + .m3_stb_i( m3s0_stb ), + .m3_ack_o( m3s0_ack ), + .m3_err_o( m3s0_err ), + .m3_rty_o( m3s0_rty ), + .m4_data_i( m4s0_data_o ), + .m4_data_o( m4s0_data_i ), + .m4_addr_i( m4s0_addr ), + .m4_sel_i( m4s0_sel ), + .m4_we_i( m4s0_we ), + .m4_cyc_i( m4s0_cyc ), + .m4_stb_i( m4s0_stb ), + .m4_ack_o( m4s0_ack ), + .m4_err_o( m4s0_err ), + .m4_rty_o( m4s0_rty ), + .m5_data_i( m5s0_data_o ), + .m5_data_o( m5s0_data_i ), + .m5_addr_i( m5s0_addr ), + .m5_sel_i( m5s0_sel ), + .m5_we_i( m5s0_we ), + .m5_cyc_i( m5s0_cyc ), + .m5_stb_i( m5s0_stb ), + .m5_ack_o( m5s0_ack ), + .m5_err_o( m5s0_err ), + .m5_rty_o( m5s0_rty ), + .m6_data_i( m6s0_data_o ), + .m6_data_o( m6s0_data_i ), + .m6_addr_i( m6s0_addr ), + .m6_sel_i( m6s0_sel ), + .m6_we_i( m6s0_we ), + .m6_cyc_i( m6s0_cyc ), + .m6_stb_i( m6s0_stb ), + .m6_ack_o( m6s0_ack ), + .m6_err_o( m6s0_err ), + .m6_rty_o( m6s0_rty ), + .m7_data_i( m7s0_data_o ), + .m7_data_o( m7s0_data_i ), + .m7_addr_i( m7s0_addr ), + .m7_sel_i( m7s0_sel ), + .m7_we_i( m7s0_we ), + .m7_cyc_i( m7s0_cyc ), + .m7_stb_i( m7s0_stb ), + .m7_ack_o( m7s0_ack ), + .m7_err_o( m7s0_err ), + .m7_rty_o( m7s0_rty ) + ); + +wb_conmax_slave_if #(pri_sel1,aw,dw,sw) s1( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf1 ), + .wb_data_i( s1_data_i ), + .wb_data_o( s1_data_o ), + .wb_addr_o( s1_addr_o ), + .wb_sel_o( s1_sel_o ), + .wb_we_o( s1_we_o ), + .wb_cyc_o( s1_cyc_o ), + .wb_stb_o( s1_stb_o ), + .wb_ack_i( s1_ack_i ), + .wb_err_i( s1_err_i ), + .wb_rty_i( s1_rty_i ), + .m0_data_i( m0s1_data_o ), + .m0_data_o( m0s1_data_i ), + .m0_addr_i( m0s1_addr ), + .m0_sel_i( m0s1_sel ), + .m0_we_i( m0s1_we ), + .m0_cyc_i( m0s1_cyc ), + .m0_stb_i( m0s1_stb ), + .m0_ack_o( m0s1_ack ), + .m0_err_o( m0s1_err ), + .m0_rty_o( m0s1_rty ), + .m1_data_i( m1s1_data_o ), + .m1_data_o( m1s1_data_i ), + .m1_addr_i( m1s1_addr ), + .m1_sel_i( m1s1_sel ), + .m1_we_i( m1s1_we ), + .m1_cyc_i( m1s1_cyc ), + .m1_stb_i( m1s1_stb ), + .m1_ack_o( m1s1_ack ), + .m1_err_o( m1s1_err ), + .m1_rty_o( m1s1_rty ), + .m2_data_i( m2s1_data_o ), + .m2_data_o( m2s1_data_i ), + .m2_addr_i( m2s1_addr ), + .m2_sel_i( m2s1_sel ), + .m2_we_i( m2s1_we ), + .m2_cyc_i( m2s1_cyc ), + .m2_stb_i( m2s1_stb ), + .m2_ack_o( m2s1_ack ), + .m2_err_o( m2s1_err ), + .m2_rty_o( m2s1_rty ), + .m3_data_i( m3s1_data_o ), + .m3_data_o( m3s1_data_i ), + .m3_addr_i( m3s1_addr ), + .m3_sel_i( m3s1_sel ), + .m3_we_i( m3s1_we ), + .m3_cyc_i( m3s1_cyc ), + .m3_stb_i( m3s1_stb ), + .m3_ack_o( m3s1_ack ), + .m3_err_o( m3s1_err ), + .m3_rty_o( m3s1_rty ), + .m4_data_i( m4s1_data_o ), + .m4_data_o( m4s1_data_i ), + .m4_addr_i( m4s1_addr ), + .m4_sel_i( m4s1_sel ), + .m4_we_i( m4s1_we ), + .m4_cyc_i( m4s1_cyc ), + .m4_stb_i( m4s1_stb ), + .m4_ack_o( m4s1_ack ), + .m4_err_o( m4s1_err ), + .m4_rty_o( m4s1_rty ), + .m5_data_i( m5s1_data_o ), + .m5_data_o( m5s1_data_i ), + .m5_addr_i( m5s1_addr ), + .m5_sel_i( m5s1_sel ), + .m5_we_i( m5s1_we ), + .m5_cyc_i( m5s1_cyc ), + .m5_stb_i( m5s1_stb ), + .m5_ack_o( m5s1_ack ), + .m5_err_o( m5s1_err ), + .m5_rty_o( m5s1_rty ), + .m6_data_i( m6s1_data_o ), + .m6_data_o( m6s1_data_i ), + .m6_addr_i( m6s1_addr ), + .m6_sel_i( m6s1_sel ), + .m6_we_i( m6s1_we ), + .m6_cyc_i( m6s1_cyc ), + .m6_stb_i( m6s1_stb ), + .m6_ack_o( m6s1_ack ), + .m6_err_o( m6s1_err ), + .m6_rty_o( m6s1_rty ), + .m7_data_i( m7s1_data_o ), + .m7_data_o( m7s1_data_i ), + .m7_addr_i( m7s1_addr ), + .m7_sel_i( m7s1_sel ), + .m7_we_i( m7s1_we ), + .m7_cyc_i( m7s1_cyc ), + .m7_stb_i( m7s1_stb ), + .m7_ack_o( m7s1_ack ), + .m7_err_o( m7s1_err ), + .m7_rty_o( m7s1_rty ) + ); + +wb_conmax_slave_if #(pri_sel2,aw,dw,sw) s2( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf2 ), + .wb_data_i( s2_data_i ), + .wb_data_o( s2_data_o ), + .wb_addr_o( s2_addr_o ), + .wb_sel_o( s2_sel_o ), + .wb_we_o( s2_we_o ), + .wb_cyc_o( s2_cyc_o ), + .wb_stb_o( s2_stb_o ), + .wb_ack_i( s2_ack_i ), + .wb_err_i( s2_err_i ), + .wb_rty_i( s2_rty_i ), + .m0_data_i( m0s2_data_o ), + .m0_data_o( m0s2_data_i ), + .m0_addr_i( m0s2_addr ), + .m0_sel_i( m0s2_sel ), + .m0_we_i( m0s2_we ), + .m0_cyc_i( m0s2_cyc ), + .m0_stb_i( m0s2_stb ), + .m0_ack_o( m0s2_ack ), + .m0_err_o( m0s2_err ), + .m0_rty_o( m0s2_rty ), + .m1_data_i( m1s2_data_o ), + .m1_data_o( m1s2_data_i ), + .m1_addr_i( m1s2_addr ), + .m1_sel_i( m1s2_sel ), + .m1_we_i( m1s2_we ), + .m1_cyc_i( m1s2_cyc ), + .m1_stb_i( m1s2_stb ), + .m1_ack_o( m1s2_ack ), + .m1_err_o( m1s2_err ), + .m1_rty_o( m1s2_rty ), + .m2_data_i( m2s2_data_o ), + .m2_data_o( m2s2_data_i ), + .m2_addr_i( m2s2_addr ), + .m2_sel_i( m2s2_sel ), + .m2_we_i( m2s2_we ), + .m2_cyc_i( m2s2_cyc ), + .m2_stb_i( m2s2_stb ), + .m2_ack_o( m2s2_ack ), + .m2_err_o( m2s2_err ), + .m2_rty_o( m2s2_rty ), + .m3_data_i( m3s2_data_o ), + .m3_data_o( m3s2_data_i ), + .m3_addr_i( m3s2_addr ), + .m3_sel_i( m3s2_sel ), + .m3_we_i( m3s2_we ), + .m3_cyc_i( m3s2_cyc ), + .m3_stb_i( m3s2_stb ), + .m3_ack_o( m3s2_ack ), + .m3_err_o( m3s2_err ), + .m3_rty_o( m3s2_rty ), + .m4_data_i( m4s2_data_o ), + .m4_data_o( m4s2_data_i ), + .m4_addr_i( m4s2_addr ), + .m4_sel_i( m4s2_sel ), + .m4_we_i( m4s2_we ), + .m4_cyc_i( m4s2_cyc ), + .m4_stb_i( m4s2_stb ), + .m4_ack_o( m4s2_ack ), + .m4_err_o( m4s2_err ), + .m4_rty_o( m4s2_rty ), + .m5_data_i( m5s2_data_o ), + .m5_data_o( m5s2_data_i ), + .m5_addr_i( m5s2_addr ), + .m5_sel_i( m5s2_sel ), + .m5_we_i( m5s2_we ), + .m5_cyc_i( m5s2_cyc ), + .m5_stb_i( m5s2_stb ), + .m5_ack_o( m5s2_ack ), + .m5_err_o( m5s2_err ), + .m5_rty_o( m5s2_rty ), + .m6_data_i( m6s2_data_o ), + .m6_data_o( m6s2_data_i ), + .m6_addr_i( m6s2_addr ), + .m6_sel_i( m6s2_sel ), + .m6_we_i( m6s2_we ), + .m6_cyc_i( m6s2_cyc ), + .m6_stb_i( m6s2_stb ), + .m6_ack_o( m6s2_ack ), + .m6_err_o( m6s2_err ), + .m6_rty_o( m6s2_rty ), + .m7_data_i( m7s2_data_o ), + .m7_data_o( m7s2_data_i ), + .m7_addr_i( m7s2_addr ), + .m7_sel_i( m7s2_sel ), + .m7_we_i( m7s2_we ), + .m7_cyc_i( m7s2_cyc ), + .m7_stb_i( m7s2_stb ), + .m7_ack_o( m7s2_ack ), + .m7_err_o( m7s2_err ), + .m7_rty_o( m7s2_rty ) + ); + +wb_conmax_slave_if #(pri_sel3,aw,dw,sw) s3( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf3 ), + .wb_data_i( s3_data_i ), + .wb_data_o( s3_data_o ), + .wb_addr_o( s3_addr_o ), + .wb_sel_o( s3_sel_o ), + .wb_we_o( s3_we_o ), + .wb_cyc_o( s3_cyc_o ), + .wb_stb_o( s3_stb_o ), + .wb_ack_i( s3_ack_i ), + .wb_err_i( s3_err_i ), + .wb_rty_i( s3_rty_i ), + .m0_data_i( m0s3_data_o ), + .m0_data_o( m0s3_data_i ), + .m0_addr_i( m0s3_addr ), + .m0_sel_i( m0s3_sel ), + .m0_we_i( m0s3_we ), + .m0_cyc_i( m0s3_cyc ), + .m0_stb_i( m0s3_stb ), + .m0_ack_o( m0s3_ack ), + .m0_err_o( m0s3_err ), + .m0_rty_o( m0s3_rty ), + .m1_data_i( m1s3_data_o ), + .m1_data_o( m1s3_data_i ), + .m1_addr_i( m1s3_addr ), + .m1_sel_i( m1s3_sel ), + .m1_we_i( m1s3_we ), + .m1_cyc_i( m1s3_cyc ), + .m1_stb_i( m1s3_stb ), + .m1_ack_o( m1s3_ack ), + .m1_err_o( m1s3_err ), + .m1_rty_o( m1s3_rty ), + .m2_data_i( m2s3_data_o ), + .m2_data_o( m2s3_data_i ), + .m2_addr_i( m2s3_addr ), + .m2_sel_i( m2s3_sel ), + .m2_we_i( m2s3_we ), + .m2_cyc_i( m2s3_cyc ), + .m2_stb_i( m2s3_stb ), + .m2_ack_o( m2s3_ack ), + .m2_err_o( m2s3_err ), + .m2_rty_o( m2s3_rty ), + .m3_data_i( m3s3_data_o ), + .m3_data_o( m3s3_data_i ), + .m3_addr_i( m3s3_addr ), + .m3_sel_i( m3s3_sel ), + .m3_we_i( m3s3_we ), + .m3_cyc_i( m3s3_cyc ), + .m3_stb_i( m3s3_stb ), + .m3_ack_o( m3s3_ack ), + .m3_err_o( m3s3_err ), + .m3_rty_o( m3s3_rty ), + .m4_data_i( m4s3_data_o ), + .m4_data_o( m4s3_data_i ), + .m4_addr_i( m4s3_addr ), + .m4_sel_i( m4s3_sel ), + .m4_we_i( m4s3_we ), + .m4_cyc_i( m4s3_cyc ), + .m4_stb_i( m4s3_stb ), + .m4_ack_o( m4s3_ack ), + .m4_err_o( m4s3_err ), + .m4_rty_o( m4s3_rty ), + .m5_data_i( m5s3_data_o ), + .m5_data_o( m5s3_data_i ), + .m5_addr_i( m5s3_addr ), + .m5_sel_i( m5s3_sel ), + .m5_we_i( m5s3_we ), + .m5_cyc_i( m5s3_cyc ), + .m5_stb_i( m5s3_stb ), + .m5_ack_o( m5s3_ack ), + .m5_err_o( m5s3_err ), + .m5_rty_o( m5s3_rty ), + .m6_data_i( m6s3_data_o ), + .m6_data_o( m6s3_data_i ), + .m6_addr_i( m6s3_addr ), + .m6_sel_i( m6s3_sel ), + .m6_we_i( m6s3_we ), + .m6_cyc_i( m6s3_cyc ), + .m6_stb_i( m6s3_stb ), + .m6_ack_o( m6s3_ack ), + .m6_err_o( m6s3_err ), + .m6_rty_o( m6s3_rty ), + .m7_data_i( m7s3_data_o ), + .m7_data_o( m7s3_data_i ), + .m7_addr_i( m7s3_addr ), + .m7_sel_i( m7s3_sel ), + .m7_we_i( m7s3_we ), + .m7_cyc_i( m7s3_cyc ), + .m7_stb_i( m7s3_stb ), + .m7_ack_o( m7s3_ack ), + .m7_err_o( m7s3_err ), + .m7_rty_o( m7s3_rty ) + ); + +wb_conmax_slave_if #(pri_sel4,aw,dw,sw) s4( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf4 ), + .wb_data_i( s4_data_i ), + .wb_data_o( s4_data_o ), + .wb_addr_o( s4_addr_o ), + .wb_sel_o( s4_sel_o ), + .wb_we_o( s4_we_o ), + .wb_cyc_o( s4_cyc_o ), + .wb_stb_o( s4_stb_o ), + .wb_ack_i( s4_ack_i ), + .wb_err_i( s4_err_i ), + .wb_rty_i( s4_rty_i ), + .m0_data_i( m0s4_data_o ), + .m0_data_o( m0s4_data_i ), + .m0_addr_i( m0s4_addr ), + .m0_sel_i( m0s4_sel ), + .m0_we_i( m0s4_we ), + .m0_cyc_i( m0s4_cyc ), + .m0_stb_i( m0s4_stb ), + .m0_ack_o( m0s4_ack ), + .m0_err_o( m0s4_err ), + .m0_rty_o( m0s4_rty ), + .m1_data_i( m1s4_data_o ), + .m1_data_o( m1s4_data_i ), + .m1_addr_i( m1s4_addr ), + .m1_sel_i( m1s4_sel ), + .m1_we_i( m1s4_we ), + .m1_cyc_i( m1s4_cyc ), + .m1_stb_i( m1s4_stb ), + .m1_ack_o( m1s4_ack ), + .m1_err_o( m1s4_err ), + .m1_rty_o( m1s4_rty ), + .m2_data_i( m2s4_data_o ), + .m2_data_o( m2s4_data_i ), + .m2_addr_i( m2s4_addr ), + .m2_sel_i( m2s4_sel ), + .m2_we_i( m2s4_we ), + .m2_cyc_i( m2s4_cyc ), + .m2_stb_i( m2s4_stb ), + .m2_ack_o( m2s4_ack ), + .m2_err_o( m2s4_err ), + .m2_rty_o( m2s4_rty ), + .m3_data_i( m3s4_data_o ), + .m3_data_o( m3s4_data_i ), + .m3_addr_i( m3s4_addr ), + .m3_sel_i( m3s4_sel ), + .m3_we_i( m3s4_we ), + .m3_cyc_i( m3s4_cyc ), + .m3_stb_i( m3s4_stb ), + .m3_ack_o( m3s4_ack ), + .m3_err_o( m3s4_err ), + .m3_rty_o( m3s4_rty ), + .m4_data_i( m4s4_data_o ), + .m4_data_o( m4s4_data_i ), + .m4_addr_i( m4s4_addr ), + .m4_sel_i( m4s4_sel ), + .m4_we_i( m4s4_we ), + .m4_cyc_i( m4s4_cyc ), + .m4_stb_i( m4s4_stb ), + .m4_ack_o( m4s4_ack ), + .m4_err_o( m4s4_err ), + .m4_rty_o( m4s4_rty ), + .m5_data_i( m5s4_data_o ), + .m5_data_o( m5s4_data_i ), + .m5_addr_i( m5s4_addr ), + .m5_sel_i( m5s4_sel ), + .m5_we_i( m5s4_we ), + .m5_cyc_i( m5s4_cyc ), + .m5_stb_i( m5s4_stb ), + .m5_ack_o( m5s4_ack ), + .m5_err_o( m5s4_err ), + .m5_rty_o( m5s4_rty ), + .m6_data_i( m6s4_data_o ), + .m6_data_o( m6s4_data_i ), + .m6_addr_i( m6s4_addr ), + .m6_sel_i( m6s4_sel ), + .m6_we_i( m6s4_we ), + .m6_cyc_i( m6s4_cyc ), + .m6_stb_i( m6s4_stb ), + .m6_ack_o( m6s4_ack ), + .m6_err_o( m6s4_err ), + .m6_rty_o( m6s4_rty ), + .m7_data_i( m7s4_data_o ), + .m7_data_o( m7s4_data_i ), + .m7_addr_i( m7s4_addr ), + .m7_sel_i( m7s4_sel ), + .m7_we_i( m7s4_we ), + .m7_cyc_i( m7s4_cyc ), + .m7_stb_i( m7s4_stb ), + .m7_ack_o( m7s4_ack ), + .m7_err_o( m7s4_err ), + .m7_rty_o( m7s4_rty ) + ); + +wb_conmax_slave_if #(pri_sel5,aw,dw,sw) s5( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf5 ), + .wb_data_i( s5_data_i ), + .wb_data_o( s5_data_o ), + .wb_addr_o( s5_addr_o ), + .wb_sel_o( s5_sel_o ), + .wb_we_o( s5_we_o ), + .wb_cyc_o( s5_cyc_o ), + .wb_stb_o( s5_stb_o ), + .wb_ack_i( s5_ack_i ), + .wb_err_i( s5_err_i ), + .wb_rty_i( s5_rty_i ), + .m0_data_i( m0s5_data_o ), + .m0_data_o( m0s5_data_i ), + .m0_addr_i( m0s5_addr ), + .m0_sel_i( m0s5_sel ), + .m0_we_i( m0s5_we ), + .m0_cyc_i( m0s5_cyc ), + .m0_stb_i( m0s5_stb ), + .m0_ack_o( m0s5_ack ), + .m0_err_o( m0s5_err ), + .m0_rty_o( m0s5_rty ), + .m1_data_i( m1s5_data_o ), + .m1_data_o( m1s5_data_i ), + .m1_addr_i( m1s5_addr ), + .m1_sel_i( m1s5_sel ), + .m1_we_i( m1s5_we ), + .m1_cyc_i( m1s5_cyc ), + .m1_stb_i( m1s5_stb ), + .m1_ack_o( m1s5_ack ), + .m1_err_o( m1s5_err ), + .m1_rty_o( m1s5_rty ), + .m2_data_i( m2s5_data_o ), + .m2_data_o( m2s5_data_i ), + .m2_addr_i( m2s5_addr ), + .m2_sel_i( m2s5_sel ), + .m2_we_i( m2s5_we ), + .m2_cyc_i( m2s5_cyc ), + .m2_stb_i( m2s5_stb ), + .m2_ack_o( m2s5_ack ), + .m2_err_o( m2s5_err ), + .m2_rty_o( m2s5_rty ), + .m3_data_i( m3s5_data_o ), + .m3_data_o( m3s5_data_i ), + .m3_addr_i( m3s5_addr ), + .m3_sel_i( m3s5_sel ), + .m3_we_i( m3s5_we ), + .m3_cyc_i( m3s5_cyc ), + .m3_stb_i( m3s5_stb ), + .m3_ack_o( m3s5_ack ), + .m3_err_o( m3s5_err ), + .m3_rty_o( m3s5_rty ), + .m4_data_i( m4s5_data_o ), + .m4_data_o( m4s5_data_i ), + .m4_addr_i( m4s5_addr ), + .m4_sel_i( m4s5_sel ), + .m4_we_i( m4s5_we ), + .m4_cyc_i( m4s5_cyc ), + .m4_stb_i( m4s5_stb ), + .m4_ack_o( m4s5_ack ), + .m4_err_o( m4s5_err ), + .m4_rty_o( m4s5_rty ), + .m5_data_i( m5s5_data_o ), + .m5_data_o( m5s5_data_i ), + .m5_addr_i( m5s5_addr ), + .m5_sel_i( m5s5_sel ), + .m5_we_i( m5s5_we ), + .m5_cyc_i( m5s5_cyc ), + .m5_stb_i( m5s5_stb ), + .m5_ack_o( m5s5_ack ), + .m5_err_o( m5s5_err ), + .m5_rty_o( m5s5_rty ), + .m6_data_i( m6s5_data_o ), + .m6_data_o( m6s5_data_i ), + .m6_addr_i( m6s5_addr ), + .m6_sel_i( m6s5_sel ), + .m6_we_i( m6s5_we ), + .m6_cyc_i( m6s5_cyc ), + .m6_stb_i( m6s5_stb ), + .m6_ack_o( m6s5_ack ), + .m6_err_o( m6s5_err ), + .m6_rty_o( m6s5_rty ), + .m7_data_i( m7s5_data_o ), + .m7_data_o( m7s5_data_i ), + .m7_addr_i( m7s5_addr ), + .m7_sel_i( m7s5_sel ), + .m7_we_i( m7s5_we ), + .m7_cyc_i( m7s5_cyc ), + .m7_stb_i( m7s5_stb ), + .m7_ack_o( m7s5_ack ), + .m7_err_o( m7s5_err ), + .m7_rty_o( m7s5_rty ) + ); + +wb_conmax_slave_if #(pri_sel6,aw,dw,sw) s6( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf6 ), + .wb_data_i( s6_data_i ), + .wb_data_o( s6_data_o ), + .wb_addr_o( s6_addr_o ), + .wb_sel_o( s6_sel_o ), + .wb_we_o( s6_we_o ), + .wb_cyc_o( s6_cyc_o ), + .wb_stb_o( s6_stb_o ), + .wb_ack_i( s6_ack_i ), + .wb_err_i( s6_err_i ), + .wb_rty_i( s6_rty_i ), + .m0_data_i( m0s6_data_o ), + .m0_data_o( m0s6_data_i ), + .m0_addr_i( m0s6_addr ), + .m0_sel_i( m0s6_sel ), + .m0_we_i( m0s6_we ), + .m0_cyc_i( m0s6_cyc ), + .m0_stb_i( m0s6_stb ), + .m0_ack_o( m0s6_ack ), + .m0_err_o( m0s6_err ), + .m0_rty_o( m0s6_rty ), + .m1_data_i( m1s6_data_o ), + .m1_data_o( m1s6_data_i ), + .m1_addr_i( m1s6_addr ), + .m1_sel_i( m1s6_sel ), + .m1_we_i( m1s6_we ), + .m1_cyc_i( m1s6_cyc ), + .m1_stb_i( m1s6_stb ), + .m1_ack_o( m1s6_ack ), + .m1_err_o( m1s6_err ), + .m1_rty_o( m1s6_rty ), + .m2_data_i( m2s6_data_o ), + .m2_data_o( m2s6_data_i ), + .m2_addr_i( m2s6_addr ), + .m2_sel_i( m2s6_sel ), + .m2_we_i( m2s6_we ), + .m2_cyc_i( m2s6_cyc ), + .m2_stb_i( m2s6_stb ), + .m2_ack_o( m2s6_ack ), + .m2_err_o( m2s6_err ), + .m2_rty_o( m2s6_rty ), + .m3_data_i( m3s6_data_o ), + .m3_data_o( m3s6_data_i ), + .m3_addr_i( m3s6_addr ), + .m3_sel_i( m3s6_sel ), + .m3_we_i( m3s6_we ), + .m3_cyc_i( m3s6_cyc ), + .m3_stb_i( m3s6_stb ), + .m3_ack_o( m3s6_ack ), + .m3_err_o( m3s6_err ), + .m3_rty_o( m3s6_rty ), + .m4_data_i( m4s6_data_o ), + .m4_data_o( m4s6_data_i ), + .m4_addr_i( m4s6_addr ), + .m4_sel_i( m4s6_sel ), + .m4_we_i( m4s6_we ), + .m4_cyc_i( m4s6_cyc ), + .m4_stb_i( m4s6_stb ), + .m4_ack_o( m4s6_ack ), + .m4_err_o( m4s6_err ), + .m4_rty_o( m4s6_rty ), + .m5_data_i( m5s6_data_o ), + .m5_data_o( m5s6_data_i ), + .m5_addr_i( m5s6_addr ), + .m5_sel_i( m5s6_sel ), + .m5_we_i( m5s6_we ), + .m5_cyc_i( m5s6_cyc ), + .m5_stb_i( m5s6_stb ), + .m5_ack_o( m5s6_ack ), + .m5_err_o( m5s6_err ), + .m5_rty_o( m5s6_rty ), + .m6_data_i( m6s6_data_o ), + .m6_data_o( m6s6_data_i ), + .m6_addr_i( m6s6_addr ), + .m6_sel_i( m6s6_sel ), + .m6_we_i( m6s6_we ), + .m6_cyc_i( m6s6_cyc ), + .m6_stb_i( m6s6_stb ), + .m6_ack_o( m6s6_ack ), + .m6_err_o( m6s6_err ), + .m6_rty_o( m6s6_rty ), + .m7_data_i( m7s6_data_o ), + .m7_data_o( m7s6_data_i ), + .m7_addr_i( m7s6_addr ), + .m7_sel_i( m7s6_sel ), + .m7_we_i( m7s6_we ), + .m7_cyc_i( m7s6_cyc ), + .m7_stb_i( m7s6_stb ), + .m7_ack_o( m7s6_ack ), + .m7_err_o( m7s6_err ), + .m7_rty_o( m7s6_rty ) + ); + +wb_conmax_slave_if #(pri_sel7,aw,dw,sw) s7( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf7 ), + .wb_data_i( s7_data_i ), + .wb_data_o( s7_data_o ), + .wb_addr_o( s7_addr_o ), + .wb_sel_o( s7_sel_o ), + .wb_we_o( s7_we_o ), + .wb_cyc_o( s7_cyc_o ), + .wb_stb_o( s7_stb_o ), + .wb_ack_i( s7_ack_i ), + .wb_err_i( s7_err_i ), + .wb_rty_i( s7_rty_i ), + .m0_data_i( m0s7_data_o ), + .m0_data_o( m0s7_data_i ), + .m0_addr_i( m0s7_addr ), + .m0_sel_i( m0s7_sel ), + .m0_we_i( m0s7_we ), + .m0_cyc_i( m0s7_cyc ), + .m0_stb_i( m0s7_stb ), + .m0_ack_o( m0s7_ack ), + .m0_err_o( m0s7_err ), + .m0_rty_o( m0s7_rty ), + .m1_data_i( m1s7_data_o ), + .m1_data_o( m1s7_data_i ), + .m1_addr_i( m1s7_addr ), + .m1_sel_i( m1s7_sel ), + .m1_we_i( m1s7_we ), + .m1_cyc_i( m1s7_cyc ), + .m1_stb_i( m1s7_stb ), + .m1_ack_o( m1s7_ack ), + .m1_err_o( m1s7_err ), + .m1_rty_o( m1s7_rty ), + .m2_data_i( m2s7_data_o ), + .m2_data_o( m2s7_data_i ), + .m2_addr_i( m2s7_addr ), + .m2_sel_i( m2s7_sel ), + .m2_we_i( m2s7_we ), + .m2_cyc_i( m2s7_cyc ), + .m2_stb_i( m2s7_stb ), + .m2_ack_o( m2s7_ack ), + .m2_err_o( m2s7_err ), + .m2_rty_o( m2s7_rty ), + .m3_data_i( m3s7_data_o ), + .m3_data_o( m3s7_data_i ), + .m3_addr_i( m3s7_addr ), + .m3_sel_i( m3s7_sel ), + .m3_we_i( m3s7_we ), + .m3_cyc_i( m3s7_cyc ), + .m3_stb_i( m3s7_stb ), + .m3_ack_o( m3s7_ack ), + .m3_err_o( m3s7_err ), + .m3_rty_o( m3s7_rty ), + .m4_data_i( m4s7_data_o ), + .m4_data_o( m4s7_data_i ), + .m4_addr_i( m4s7_addr ), + .m4_sel_i( m4s7_sel ), + .m4_we_i( m4s7_we ), + .m4_cyc_i( m4s7_cyc ), + .m4_stb_i( m4s7_stb ), + .m4_ack_o( m4s7_ack ), + .m4_err_o( m4s7_err ), + .m4_rty_o( m4s7_rty ), + .m5_data_i( m5s7_data_o ), + .m5_data_o( m5s7_data_i ), + .m5_addr_i( m5s7_addr ), + .m5_sel_i( m5s7_sel ), + .m5_we_i( m5s7_we ), + .m5_cyc_i( m5s7_cyc ), + .m5_stb_i( m5s7_stb ), + .m5_ack_o( m5s7_ack ), + .m5_err_o( m5s7_err ), + .m5_rty_o( m5s7_rty ), + .m6_data_i( m6s7_data_o ), + .m6_data_o( m6s7_data_i ), + .m6_addr_i( m6s7_addr ), + .m6_sel_i( m6s7_sel ), + .m6_we_i( m6s7_we ), + .m6_cyc_i( m6s7_cyc ), + .m6_stb_i( m6s7_stb ), + .m6_ack_o( m6s7_ack ), + .m6_err_o( m6s7_err ), + .m6_rty_o( m6s7_rty ), + .m7_data_i( m7s7_data_o ), + .m7_data_o( m7s7_data_i ), + .m7_addr_i( m7s7_addr ), + .m7_sel_i( m7s7_sel ), + .m7_we_i( m7s7_we ), + .m7_cyc_i( m7s7_cyc ), + .m7_stb_i( m7s7_stb ), + .m7_ack_o( m7s7_ack ), + .m7_err_o( m7s7_err ), + .m7_rty_o( m7s7_rty ) + ); + +wb_conmax_slave_if #(pri_sel8,aw,dw,sw) s8( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf8 ), + .wb_data_i( s8_data_i ), + .wb_data_o( s8_data_o ), + .wb_addr_o( s8_addr_o ), + .wb_sel_o( s8_sel_o ), + .wb_we_o( s8_we_o ), + .wb_cyc_o( s8_cyc_o ), + .wb_stb_o( s8_stb_o ), + .wb_ack_i( s8_ack_i ), + .wb_err_i( s8_err_i ), + .wb_rty_i( s8_rty_i ), + .m0_data_i( m0s8_data_o ), + .m0_data_o( m0s8_data_i ), + .m0_addr_i( m0s8_addr ), + .m0_sel_i( m0s8_sel ), + .m0_we_i( m0s8_we ), + .m0_cyc_i( m0s8_cyc ), + .m0_stb_i( m0s8_stb ), + .m0_ack_o( m0s8_ack ), + .m0_err_o( m0s8_err ), + .m0_rty_o( m0s8_rty ), + .m1_data_i( m1s8_data_o ), + .m1_data_o( m1s8_data_i ), + .m1_addr_i( m1s8_addr ), + .m1_sel_i( m1s8_sel ), + .m1_we_i( m1s8_we ), + .m1_cyc_i( m1s8_cyc ), + .m1_stb_i( m1s8_stb ), + .m1_ack_o( m1s8_ack ), + .m1_err_o( m1s8_err ), + .m1_rty_o( m1s8_rty ), + .m2_data_i( m2s8_data_o ), + .m2_data_o( m2s8_data_i ), + .m2_addr_i( m2s8_addr ), + .m2_sel_i( m2s8_sel ), + .m2_we_i( m2s8_we ), + .m2_cyc_i( m2s8_cyc ), + .m2_stb_i( m2s8_stb ), + .m2_ack_o( m2s8_ack ), + .m2_err_o( m2s8_err ), + .m2_rty_o( m2s8_rty ), + .m3_data_i( m3s8_data_o ), + .m3_data_o( m3s8_data_i ), + .m3_addr_i( m3s8_addr ), + .m3_sel_i( m3s8_sel ), + .m3_we_i( m3s8_we ), + .m3_cyc_i( m3s8_cyc ), + .m3_stb_i( m3s8_stb ), + .m3_ack_o( m3s8_ack ), + .m3_err_o( m3s8_err ), + .m3_rty_o( m3s8_rty ), + .m4_data_i( m4s8_data_o ), + .m4_data_o( m4s8_data_i ), + .m4_addr_i( m4s8_addr ), + .m4_sel_i( m4s8_sel ), + .m4_we_i( m4s8_we ), + .m4_cyc_i( m4s8_cyc ), + .m4_stb_i( m4s8_stb ), + .m4_ack_o( m4s8_ack ), + .m4_err_o( m4s8_err ), + .m4_rty_o( m4s8_rty ), + .m5_data_i( m5s8_data_o ), + .m5_data_o( m5s8_data_i ), + .m5_addr_i( m5s8_addr ), + .m5_sel_i( m5s8_sel ), + .m5_we_i( m5s8_we ), + .m5_cyc_i( m5s8_cyc ), + .m5_stb_i( m5s8_stb ), + .m5_ack_o( m5s8_ack ), + .m5_err_o( m5s8_err ), + .m5_rty_o( m5s8_rty ), + .m6_data_i( m6s8_data_o ), + .m6_data_o( m6s8_data_i ), + .m6_addr_i( m6s8_addr ), + .m6_sel_i( m6s8_sel ), + .m6_we_i( m6s8_we ), + .m6_cyc_i( m6s8_cyc ), + .m6_stb_i( m6s8_stb ), + .m6_ack_o( m6s8_ack ), + .m6_err_o( m6s8_err ), + .m6_rty_o( m6s8_rty ), + .m7_data_i( m7s8_data_o ), + .m7_data_o( m7s8_data_i ), + .m7_addr_i( m7s8_addr ), + .m7_sel_i( m7s8_sel ), + .m7_we_i( m7s8_we ), + .m7_cyc_i( m7s8_cyc ), + .m7_stb_i( m7s8_stb ), + .m7_ack_o( m7s8_ack ), + .m7_err_o( m7s8_err ), + .m7_rty_o( m7s8_rty ) + ); + +wb_conmax_slave_if #(pri_sel9,aw,dw,sw) s9( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf9 ), + .wb_data_i( s9_data_i ), + .wb_data_o( s9_data_o ), + .wb_addr_o( s9_addr_o ), + .wb_sel_o( s9_sel_o ), + .wb_we_o( s9_we_o ), + .wb_cyc_o( s9_cyc_o ), + .wb_stb_o( s9_stb_o ), + .wb_ack_i( s9_ack_i ), + .wb_err_i( s9_err_i ), + .wb_rty_i( s9_rty_i ), + .m0_data_i( m0s9_data_o ), + .m0_data_o( m0s9_data_i ), + .m0_addr_i( m0s9_addr ), + .m0_sel_i( m0s9_sel ), + .m0_we_i( m0s9_we ), + .m0_cyc_i( m0s9_cyc ), + .m0_stb_i( m0s9_stb ), + .m0_ack_o( m0s9_ack ), + .m0_err_o( m0s9_err ), + .m0_rty_o( m0s9_rty ), + .m1_data_i( m1s9_data_o ), + .m1_data_o( m1s9_data_i ), + .m1_addr_i( m1s9_addr ), + .m1_sel_i( m1s9_sel ), + .m1_we_i( m1s9_we ), + .m1_cyc_i( m1s9_cyc ), + .m1_stb_i( m1s9_stb ), + .m1_ack_o( m1s9_ack ), + .m1_err_o( m1s9_err ), + .m1_rty_o( m1s9_rty ), + .m2_data_i( m2s9_data_o ), + .m2_data_o( m2s9_data_i ), + .m2_addr_i( m2s9_addr ), + .m2_sel_i( m2s9_sel ), + .m2_we_i( m2s9_we ), + .m2_cyc_i( m2s9_cyc ), + .m2_stb_i( m2s9_stb ), + .m2_ack_o( m2s9_ack ), + .m2_err_o( m2s9_err ), + .m2_rty_o( m2s9_rty ), + .m3_data_i( m3s9_data_o ), + .m3_data_o( m3s9_data_i ), + .m3_addr_i( m3s9_addr ), + .m3_sel_i( m3s9_sel ), + .m3_we_i( m3s9_we ), + .m3_cyc_i( m3s9_cyc ), + .m3_stb_i( m3s9_stb ), + .m3_ack_o( m3s9_ack ), + .m3_err_o( m3s9_err ), + .m3_rty_o( m3s9_rty ), + .m4_data_i( m4s9_data_o ), + .m4_data_o( m4s9_data_i ), + .m4_addr_i( m4s9_addr ), + .m4_sel_i( m4s9_sel ), + .m4_we_i( m4s9_we ), + .m4_cyc_i( m4s9_cyc ), + .m4_stb_i( m4s9_stb ), + .m4_ack_o( m4s9_ack ), + .m4_err_o( m4s9_err ), + .m4_rty_o( m4s9_rty ), + .m5_data_i( m5s9_data_o ), + .m5_data_o( m5s9_data_i ), + .m5_addr_i( m5s9_addr ), + .m5_sel_i( m5s9_sel ), + .m5_we_i( m5s9_we ), + .m5_cyc_i( m5s9_cyc ), + .m5_stb_i( m5s9_stb ), + .m5_ack_o( m5s9_ack ), + .m5_err_o( m5s9_err ), + .m5_rty_o( m5s9_rty ), + .m6_data_i( m6s9_data_o ), + .m6_data_o( m6s9_data_i ), + .m6_addr_i( m6s9_addr ), + .m6_sel_i( m6s9_sel ), + .m6_we_i( m6s9_we ), + .m6_cyc_i( m6s9_cyc ), + .m6_stb_i( m6s9_stb ), + .m6_ack_o( m6s9_ack ), + .m6_err_o( m6s9_err ), + .m6_rty_o( m6s9_rty ), + .m7_data_i( m7s9_data_o ), + .m7_data_o( m7s9_data_i ), + .m7_addr_i( m7s9_addr ), + .m7_sel_i( m7s9_sel ), + .m7_we_i( m7s9_we ), + .m7_cyc_i( m7s9_cyc ), + .m7_stb_i( m7s9_stb ), + .m7_ack_o( m7s9_ack ), + .m7_err_o( m7s9_err ), + .m7_rty_o( m7s9_rty ) + ); + +wb_conmax_slave_if #(pri_sel10,aw,dw,sw) s10( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf10 ), + .wb_data_i( s10_data_i ), + .wb_data_o( s10_data_o ), + .wb_addr_o( s10_addr_o ), + .wb_sel_o( s10_sel_o ), + .wb_we_o( s10_we_o ), + .wb_cyc_o( s10_cyc_o ), + .wb_stb_o( s10_stb_o ), + .wb_ack_i( s10_ack_i ), + .wb_err_i( s10_err_i ), + .wb_rty_i( s10_rty_i ), + .m0_data_i( m0s10_data_o ), + .m0_data_o( m0s10_data_i ), + .m0_addr_i( m0s10_addr ), + .m0_sel_i( m0s10_sel ), + .m0_we_i( m0s10_we ), + .m0_cyc_i( m0s10_cyc ), + .m0_stb_i( m0s10_stb ), + .m0_ack_o( m0s10_ack ), + .m0_err_o( m0s10_err ), + .m0_rty_o( m0s10_rty ), + .m1_data_i( m1s10_data_o ), + .m1_data_o( m1s10_data_i ), + .m1_addr_i( m1s10_addr ), + .m1_sel_i( m1s10_sel ), + .m1_we_i( m1s10_we ), + .m1_cyc_i( m1s10_cyc ), + .m1_stb_i( m1s10_stb ), + .m1_ack_o( m1s10_ack ), + .m1_err_o( m1s10_err ), + .m1_rty_o( m1s10_rty ), + .m2_data_i( m2s10_data_o ), + .m2_data_o( m2s10_data_i ), + .m2_addr_i( m2s10_addr ), + .m2_sel_i( m2s10_sel ), + .m2_we_i( m2s10_we ), + .m2_cyc_i( m2s10_cyc ), + .m2_stb_i( m2s10_stb ), + .m2_ack_o( m2s10_ack ), + .m2_err_o( m2s10_err ), + .m2_rty_o( m2s10_rty ), + .m3_data_i( m3s10_data_o ), + .m3_data_o( m3s10_data_i ), + .m3_addr_i( m3s10_addr ), + .m3_sel_i( m3s10_sel ), + .m3_we_i( m3s10_we ), + .m3_cyc_i( m3s10_cyc ), + .m3_stb_i( m3s10_stb ), + .m3_ack_o( m3s10_ack ), + .m3_err_o( m3s10_err ), + .m3_rty_o( m3s10_rty ), + .m4_data_i( m4s10_data_o ), + .m4_data_o( m4s10_data_i ), + .m4_addr_i( m4s10_addr ), + .m4_sel_i( m4s10_sel ), + .m4_we_i( m4s10_we ), + .m4_cyc_i( m4s10_cyc ), + .m4_stb_i( m4s10_stb ), + .m4_ack_o( m4s10_ack ), + .m4_err_o( m4s10_err ), + .m4_rty_o( m4s10_rty ), + .m5_data_i( m5s10_data_o ), + .m5_data_o( m5s10_data_i ), + .m5_addr_i( m5s10_addr ), + .m5_sel_i( m5s10_sel ), + .m5_we_i( m5s10_we ), + .m5_cyc_i( m5s10_cyc ), + .m5_stb_i( m5s10_stb ), + .m5_ack_o( m5s10_ack ), + .m5_err_o( m5s10_err ), + .m5_rty_o( m5s10_rty ), + .m6_data_i( m6s10_data_o ), + .m6_data_o( m6s10_data_i ), + .m6_addr_i( m6s10_addr ), + .m6_sel_i( m6s10_sel ), + .m6_we_i( m6s10_we ), + .m6_cyc_i( m6s10_cyc ), + .m6_stb_i( m6s10_stb ), + .m6_ack_o( m6s10_ack ), + .m6_err_o( m6s10_err ), + .m6_rty_o( m6s10_rty ), + .m7_data_i( m7s10_data_o ), + .m7_data_o( m7s10_data_i ), + .m7_addr_i( m7s10_addr ), + .m7_sel_i( m7s10_sel ), + .m7_we_i( m7s10_we ), + .m7_cyc_i( m7s10_cyc ), + .m7_stb_i( m7s10_stb ), + .m7_ack_o( m7s10_ack ), + .m7_err_o( m7s10_err ), + .m7_rty_o( m7s10_rty ) + ); + +wb_conmax_slave_if #(pri_sel11,aw,dw,sw) s11( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf11 ), + .wb_data_i( s11_data_i ), + .wb_data_o( s11_data_o ), + .wb_addr_o( s11_addr_o ), + .wb_sel_o( s11_sel_o ), + .wb_we_o( s11_we_o ), + .wb_cyc_o( s11_cyc_o ), + .wb_stb_o( s11_stb_o ), + .wb_ack_i( s11_ack_i ), + .wb_err_i( s11_err_i ), + .wb_rty_i( s11_rty_i ), + .m0_data_i( m0s11_data_o ), + .m0_data_o( m0s11_data_i ), + .m0_addr_i( m0s11_addr ), + .m0_sel_i( m0s11_sel ), + .m0_we_i( m0s11_we ), + .m0_cyc_i( m0s11_cyc ), + .m0_stb_i( m0s11_stb ), + .m0_ack_o( m0s11_ack ), + .m0_err_o( m0s11_err ), + .m0_rty_o( m0s11_rty ), + .m1_data_i( m1s11_data_o ), + .m1_data_o( m1s11_data_i ), + .m1_addr_i( m1s11_addr ), + .m1_sel_i( m1s11_sel ), + .m1_we_i( m1s11_we ), + .m1_cyc_i( m1s11_cyc ), + .m1_stb_i( m1s11_stb ), + .m1_ack_o( m1s11_ack ), + .m1_err_o( m1s11_err ), + .m1_rty_o( m1s11_rty ), + .m2_data_i( m2s11_data_o ), + .m2_data_o( m2s11_data_i ), + .m2_addr_i( m2s11_addr ), + .m2_sel_i( m2s11_sel ), + .m2_we_i( m2s11_we ), + .m2_cyc_i( m2s11_cyc ), + .m2_stb_i( m2s11_stb ), + .m2_ack_o( m2s11_ack ), + .m2_err_o( m2s11_err ), + .m2_rty_o( m2s11_rty ), + .m3_data_i( m3s11_data_o ), + .m3_data_o( m3s11_data_i ), + .m3_addr_i( m3s11_addr ), + .m3_sel_i( m3s11_sel ), + .m3_we_i( m3s11_we ), + .m3_cyc_i( m3s11_cyc ), + .m3_stb_i( m3s11_stb ), + .m3_ack_o( m3s11_ack ), + .m3_err_o( m3s11_err ), + .m3_rty_o( m3s11_rty ), + .m4_data_i( m4s11_data_o ), + .m4_data_o( m4s11_data_i ), + .m4_addr_i( m4s11_addr ), + .m4_sel_i( m4s11_sel ), + .m4_we_i( m4s11_we ), + .m4_cyc_i( m4s11_cyc ), + .m4_stb_i( m4s11_stb ), + .m4_ack_o( m4s11_ack ), + .m4_err_o( m4s11_err ), + .m4_rty_o( m4s11_rty ), + .m5_data_i( m5s11_data_o ), + .m5_data_o( m5s11_data_i ), + .m5_addr_i( m5s11_addr ), + .m5_sel_i( m5s11_sel ), + .m5_we_i( m5s11_we ), + .m5_cyc_i( m5s11_cyc ), + .m5_stb_i( m5s11_stb ), + .m5_ack_o( m5s11_ack ), + .m5_err_o( m5s11_err ), + .m5_rty_o( m5s11_rty ), + .m6_data_i( m6s11_data_o ), + .m6_data_o( m6s11_data_i ), + .m6_addr_i( m6s11_addr ), + .m6_sel_i( m6s11_sel ), + .m6_we_i( m6s11_we ), + .m6_cyc_i( m6s11_cyc ), + .m6_stb_i( m6s11_stb ), + .m6_ack_o( m6s11_ack ), + .m6_err_o( m6s11_err ), + .m6_rty_o( m6s11_rty ), + .m7_data_i( m7s11_data_o ), + .m7_data_o( m7s11_data_i ), + .m7_addr_i( m7s11_addr ), + .m7_sel_i( m7s11_sel ), + .m7_we_i( m7s11_we ), + .m7_cyc_i( m7s11_cyc ), + .m7_stb_i( m7s11_stb ), + .m7_ack_o( m7s11_ack ), + .m7_err_o( m7s11_err ), + .m7_rty_o( m7s11_rty ) + ); + +wb_conmax_slave_if #(pri_sel12,aw,dw,sw) s12( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf12 ), + .wb_data_i( s12_data_i ), + .wb_data_o( s12_data_o ), + .wb_addr_o( s12_addr_o ), + .wb_sel_o( s12_sel_o ), + .wb_we_o( s12_we_o ), + .wb_cyc_o( s12_cyc_o ), + .wb_stb_o( s12_stb_o ), + .wb_ack_i( s12_ack_i ), + .wb_err_i( s12_err_i ), + .wb_rty_i( s12_rty_i ), + .m0_data_i( m0s12_data_o ), + .m0_data_o( m0s12_data_i ), + .m0_addr_i( m0s12_addr ), + .m0_sel_i( m0s12_sel ), + .m0_we_i( m0s12_we ), + .m0_cyc_i( m0s12_cyc ), + .m0_stb_i( m0s12_stb ), + .m0_ack_o( m0s12_ack ), + .m0_err_o( m0s12_err ), + .m0_rty_o( m0s12_rty ), + .m1_data_i( m1s12_data_o ), + .m1_data_o( m1s12_data_i ), + .m1_addr_i( m1s12_addr ), + .m1_sel_i( m1s12_sel ), + .m1_we_i( m1s12_we ), + .m1_cyc_i( m1s12_cyc ), + .m1_stb_i( m1s12_stb ), + .m1_ack_o( m1s12_ack ), + .m1_err_o( m1s12_err ), + .m1_rty_o( m1s12_rty ), + .m2_data_i( m2s12_data_o ), + .m2_data_o( m2s12_data_i ), + .m2_addr_i( m2s12_addr ), + .m2_sel_i( m2s12_sel ), + .m2_we_i( m2s12_we ), + .m2_cyc_i( m2s12_cyc ), + .m2_stb_i( m2s12_stb ), + .m2_ack_o( m2s12_ack ), + .m2_err_o( m2s12_err ), + .m2_rty_o( m2s12_rty ), + .m3_data_i( m3s12_data_o ), + .m3_data_o( m3s12_data_i ), + .m3_addr_i( m3s12_addr ), + .m3_sel_i( m3s12_sel ), + .m3_we_i( m3s12_we ), + .m3_cyc_i( m3s12_cyc ), + .m3_stb_i( m3s12_stb ), + .m3_ack_o( m3s12_ack ), + .m3_err_o( m3s12_err ), + .m3_rty_o( m3s12_rty ), + .m4_data_i( m4s12_data_o ), + .m4_data_o( m4s12_data_i ), + .m4_addr_i( m4s12_addr ), + .m4_sel_i( m4s12_sel ), + .m4_we_i( m4s12_we ), + .m4_cyc_i( m4s12_cyc ), + .m4_stb_i( m4s12_stb ), + .m4_ack_o( m4s12_ack ), + .m4_err_o( m4s12_err ), + .m4_rty_o( m4s12_rty ), + .m5_data_i( m5s12_data_o ), + .m5_data_o( m5s12_data_i ), + .m5_addr_i( m5s12_addr ), + .m5_sel_i( m5s12_sel ), + .m5_we_i( m5s12_we ), + .m5_cyc_i( m5s12_cyc ), + .m5_stb_i( m5s12_stb ), + .m5_ack_o( m5s12_ack ), + .m5_err_o( m5s12_err ), + .m5_rty_o( m5s12_rty ), + .m6_data_i( m6s12_data_o ), + .m6_data_o( m6s12_data_i ), + .m6_addr_i( m6s12_addr ), + .m6_sel_i( m6s12_sel ), + .m6_we_i( m6s12_we ), + .m6_cyc_i( m6s12_cyc ), + .m6_stb_i( m6s12_stb ), + .m6_ack_o( m6s12_ack ), + .m6_err_o( m6s12_err ), + .m6_rty_o( m6s12_rty ), + .m7_data_i( m7s12_data_o ), + .m7_data_o( m7s12_data_i ), + .m7_addr_i( m7s12_addr ), + .m7_sel_i( m7s12_sel ), + .m7_we_i( m7s12_we ), + .m7_cyc_i( m7s12_cyc ), + .m7_stb_i( m7s12_stb ), + .m7_ack_o( m7s12_ack ), + .m7_err_o( m7s12_err ), + .m7_rty_o( m7s12_rty ) + ); + +wb_conmax_slave_if #(pri_sel13,aw,dw,sw) s13( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf13 ), + .wb_data_i( s13_data_i ), + .wb_data_o( s13_data_o ), + .wb_addr_o( s13_addr_o ), + .wb_sel_o( s13_sel_o ), + .wb_we_o( s13_we_o ), + .wb_cyc_o( s13_cyc_o ), + .wb_stb_o( s13_stb_o ), + .wb_ack_i( s13_ack_i ), + .wb_err_i( s13_err_i ), + .wb_rty_i( s13_rty_i ), + .m0_data_i( m0s13_data_o ), + .m0_data_o( m0s13_data_i ), + .m0_addr_i( m0s13_addr ), + .m0_sel_i( m0s13_sel ), + .m0_we_i( m0s13_we ), + .m0_cyc_i( m0s13_cyc ), + .m0_stb_i( m0s13_stb ), + .m0_ack_o( m0s13_ack ), + .m0_err_o( m0s13_err ), + .m0_rty_o( m0s13_rty ), + .m1_data_i( m1s13_data_o ), + .m1_data_o( m1s13_data_i ), + .m1_addr_i( m1s13_addr ), + .m1_sel_i( m1s13_sel ), + .m1_we_i( m1s13_we ), + .m1_cyc_i( m1s13_cyc ), + .m1_stb_i( m1s13_stb ), + .m1_ack_o( m1s13_ack ), + .m1_err_o( m1s13_err ), + .m1_rty_o( m1s13_rty ), + .m2_data_i( m2s13_data_o ), + .m2_data_o( m2s13_data_i ), + .m2_addr_i( m2s13_addr ), + .m2_sel_i( m2s13_sel ), + .m2_we_i( m2s13_we ), + .m2_cyc_i( m2s13_cyc ), + .m2_stb_i( m2s13_stb ), + .m2_ack_o( m2s13_ack ), + .m2_err_o( m2s13_err ), + .m2_rty_o( m2s13_rty ), + .m3_data_i( m3s13_data_o ), + .m3_data_o( m3s13_data_i ), + .m3_addr_i( m3s13_addr ), + .m3_sel_i( m3s13_sel ), + .m3_we_i( m3s13_we ), + .m3_cyc_i( m3s13_cyc ), + .m3_stb_i( m3s13_stb ), + .m3_ack_o( m3s13_ack ), + .m3_err_o( m3s13_err ), + .m3_rty_o( m3s13_rty ), + .m4_data_i( m4s13_data_o ), + .m4_data_o( m4s13_data_i ), + .m4_addr_i( m4s13_addr ), + .m4_sel_i( m4s13_sel ), + .m4_we_i( m4s13_we ), + .m4_cyc_i( m4s13_cyc ), + .m4_stb_i( m4s13_stb ), + .m4_ack_o( m4s13_ack ), + .m4_err_o( m4s13_err ), + .m4_rty_o( m4s13_rty ), + .m5_data_i( m5s13_data_o ), + .m5_data_o( m5s13_data_i ), + .m5_addr_i( m5s13_addr ), + .m5_sel_i( m5s13_sel ), + .m5_we_i( m5s13_we ), + .m5_cyc_i( m5s13_cyc ), + .m5_stb_i( m5s13_stb ), + .m5_ack_o( m5s13_ack ), + .m5_err_o( m5s13_err ), + .m5_rty_o( m5s13_rty ), + .m6_data_i( m6s13_data_o ), + .m6_data_o( m6s13_data_i ), + .m6_addr_i( m6s13_addr ), + .m6_sel_i( m6s13_sel ), + .m6_we_i( m6s13_we ), + .m6_cyc_i( m6s13_cyc ), + .m6_stb_i( m6s13_stb ), + .m6_ack_o( m6s13_ack ), + .m6_err_o( m6s13_err ), + .m6_rty_o( m6s13_rty ), + .m7_data_i( m7s13_data_o ), + .m7_data_o( m7s13_data_i ), + .m7_addr_i( m7s13_addr ), + .m7_sel_i( m7s13_sel ), + .m7_we_i( m7s13_we ), + .m7_cyc_i( m7s13_cyc ), + .m7_stb_i( m7s13_stb ), + .m7_ack_o( m7s13_ack ), + .m7_err_o( m7s13_err ), + .m7_rty_o( m7s13_rty ) + ); + +wb_conmax_slave_if #(pri_sel14,aw,dw,sw) s14( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf14 ), + .wb_data_i( s14_data_i ), + .wb_data_o( s14_data_o ), + .wb_addr_o( s14_addr_o ), + .wb_sel_o( s14_sel_o ), + .wb_we_o( s14_we_o ), + .wb_cyc_o( s14_cyc_o ), + .wb_stb_o( s14_stb_o ), + .wb_ack_i( s14_ack_i ), + .wb_err_i( s14_err_i ), + .wb_rty_i( s14_rty_i ), + .m0_data_i( m0s14_data_o ), + .m0_data_o( m0s14_data_i ), + .m0_addr_i( m0s14_addr ), + .m0_sel_i( m0s14_sel ), + .m0_we_i( m0s14_we ), + .m0_cyc_i( m0s14_cyc ), + .m0_stb_i( m0s14_stb ), + .m0_ack_o( m0s14_ack ), + .m0_err_o( m0s14_err ), + .m0_rty_o( m0s14_rty ), + .m1_data_i( m1s14_data_o ), + .m1_data_o( m1s14_data_i ), + .m1_addr_i( m1s14_addr ), + .m1_sel_i( m1s14_sel ), + .m1_we_i( m1s14_we ), + .m1_cyc_i( m1s14_cyc ), + .m1_stb_i( m1s14_stb ), + .m1_ack_o( m1s14_ack ), + .m1_err_o( m1s14_err ), + .m1_rty_o( m1s14_rty ), + .m2_data_i( m2s14_data_o ), + .m2_data_o( m2s14_data_i ), + .m2_addr_i( m2s14_addr ), + .m2_sel_i( m2s14_sel ), + .m2_we_i( m2s14_we ), + .m2_cyc_i( m2s14_cyc ), + .m2_stb_i( m2s14_stb ), + .m2_ack_o( m2s14_ack ), + .m2_err_o( m2s14_err ), + .m2_rty_o( m2s14_rty ), + .m3_data_i( m3s14_data_o ), + .m3_data_o( m3s14_data_i ), + .m3_addr_i( m3s14_addr ), + .m3_sel_i( m3s14_sel ), + .m3_we_i( m3s14_we ), + .m3_cyc_i( m3s14_cyc ), + .m3_stb_i( m3s14_stb ), + .m3_ack_o( m3s14_ack ), + .m3_err_o( m3s14_err ), + .m3_rty_o( m3s14_rty ), + .m4_data_i( m4s14_data_o ), + .m4_data_o( m4s14_data_i ), + .m4_addr_i( m4s14_addr ), + .m4_sel_i( m4s14_sel ), + .m4_we_i( m4s14_we ), + .m4_cyc_i( m4s14_cyc ), + .m4_stb_i( m4s14_stb ), + .m4_ack_o( m4s14_ack ), + .m4_err_o( m4s14_err ), + .m4_rty_o( m4s14_rty ), + .m5_data_i( m5s14_data_o ), + .m5_data_o( m5s14_data_i ), + .m5_addr_i( m5s14_addr ), + .m5_sel_i( m5s14_sel ), + .m5_we_i( m5s14_we ), + .m5_cyc_i( m5s14_cyc ), + .m5_stb_i( m5s14_stb ), + .m5_ack_o( m5s14_ack ), + .m5_err_o( m5s14_err ), + .m5_rty_o( m5s14_rty ), + .m6_data_i( m6s14_data_o ), + .m6_data_o( m6s14_data_i ), + .m6_addr_i( m6s14_addr ), + .m6_sel_i( m6s14_sel ), + .m6_we_i( m6s14_we ), + .m6_cyc_i( m6s14_cyc ), + .m6_stb_i( m6s14_stb ), + .m6_ack_o( m6s14_ack ), + .m6_err_o( m6s14_err ), + .m6_rty_o( m6s14_rty ), + .m7_data_i( m7s14_data_o ), + .m7_data_o( m7s14_data_i ), + .m7_addr_i( m7s14_addr ), + .m7_sel_i( m7s14_sel ), + .m7_we_i( m7s14_we ), + .m7_cyc_i( m7s14_cyc ), + .m7_stb_i( m7s14_stb ), + .m7_ack_o( m7s14_ack ), + .m7_err_o( m7s14_err ), + .m7_rty_o( m7s14_rty ) + ); + +wb_conmax_slave_if #(pri_sel15,aw,dw,sw) s15( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf15 ), + .wb_data_i( i_s15_data_i ), + .wb_data_o( i_s15_data_o ), + .wb_addr_o( i_s15_addr_o ), + .wb_sel_o( i_s15_sel_o ), + .wb_we_o( i_s15_we_o ), + .wb_cyc_o( i_s15_cyc_o ), + .wb_stb_o( i_s15_stb_o ), + .wb_ack_i( i_s15_ack_i ), + .wb_err_i( i_s15_err_i ), + .wb_rty_i( i_s15_rty_i ), + .m0_data_i( m0s15_data_o ), + .m0_data_o( m0s15_data_i ), + .m0_addr_i( m0s15_addr ), + .m0_sel_i( m0s15_sel ), + .m0_we_i( m0s15_we ), + .m0_cyc_i( m0s15_cyc ), + .m0_stb_i( m0s15_stb ), + .m0_ack_o( m0s15_ack ), + .m0_err_o( m0s15_err ), + .m0_rty_o( m0s15_rty ), + .m1_data_i( m1s15_data_o ), + .m1_data_o( m1s15_data_i ), + .m1_addr_i( m1s15_addr ), + .m1_sel_i( m1s15_sel ), + .m1_we_i( m1s15_we ), + .m1_cyc_i( m1s15_cyc ), + .m1_stb_i( m1s15_stb ), + .m1_ack_o( m1s15_ack ), + .m1_err_o( m1s15_err ), + .m1_rty_o( m1s15_rty ), + .m2_data_i( m2s15_data_o ), + .m2_data_o( m2s15_data_i ), + .m2_addr_i( m2s15_addr ), + .m2_sel_i( m2s15_sel ), + .m2_we_i( m2s15_we ), + .m2_cyc_i( m2s15_cyc ), + .m2_stb_i( m2s15_stb ), + .m2_ack_o( m2s15_ack ), + .m2_err_o( m2s15_err ), + .m2_rty_o( m2s15_rty ), + .m3_data_i( m3s15_data_o ), + .m3_data_o( m3s15_data_i ), + .m3_addr_i( m3s15_addr ), + .m3_sel_i( m3s15_sel ), + .m3_we_i( m3s15_we ), + .m3_cyc_i( m3s15_cyc ), + .m3_stb_i( m3s15_stb ), + .m3_ack_o( m3s15_ack ), + .m3_err_o( m3s15_err ), + .m3_rty_o( m3s15_rty ), + .m4_data_i( m4s15_data_o ), + .m4_data_o( m4s15_data_i ), + .m4_addr_i( m4s15_addr ), + .m4_sel_i( m4s15_sel ), + .m4_we_i( m4s15_we ), + .m4_cyc_i( m4s15_cyc ), + .m4_stb_i( m4s15_stb ), + .m4_ack_o( m4s15_ack ), + .m4_err_o( m4s15_err ), + .m4_rty_o( m4s15_rty ), + .m5_data_i( m5s15_data_o ), + .m5_data_o( m5s15_data_i ), + .m5_addr_i( m5s15_addr ), + .m5_sel_i( m5s15_sel ), + .m5_we_i( m5s15_we ), + .m5_cyc_i( m5s15_cyc ), + .m5_stb_i( m5s15_stb ), + .m5_ack_o( m5s15_ack ), + .m5_err_o( m5s15_err ), + .m5_rty_o( m5s15_rty ), + .m6_data_i( m6s15_data_o ), + .m6_data_o( m6s15_data_i ), + .m6_addr_i( m6s15_addr ), + .m6_sel_i( m6s15_sel ), + .m6_we_i( m6s15_we ), + .m6_cyc_i( m6s15_cyc ), + .m6_stb_i( m6s15_stb ), + .m6_ack_o( m6s15_ack ), + .m6_err_o( m6s15_err ), + .m6_rty_o( m6s15_rty ), + .m7_data_i( m7s15_data_o ), + .m7_data_o( m7s15_data_i ), + .m7_addr_i( m7s15_addr ), + .m7_sel_i( m7s15_sel ), + .m7_we_i( m7s15_we ), + .m7_cyc_i( m7s15_cyc ), + .m7_stb_i( m7s15_stb ), + .m7_ack_o( m7s15_ack ), + .m7_err_o( m7s15_err ), + .m7_rty_o( m7s15_rty ) + ); + +wb_conmax_rf #(rf_addr,aw,dw,sw) rf( + .clk_i( clk_i ), + .rst_i( rst_i ), + .i_wb_data_i( i_s15_data_o ), + .i_wb_data_o( i_s15_data_i ), + .i_wb_addr_i( i_s15_addr_o ), + .i_wb_sel_i( i_s15_sel_o ), + .i_wb_we_i( i_s15_we_o ), + .i_wb_cyc_i( i_s15_cyc_o ), + .i_wb_stb_i( i_s15_stb_o ), + .i_wb_ack_o( i_s15_ack_i ), + .i_wb_err_o( i_s15_err_i ), + .i_wb_rty_o( i_s15_rty_i ), + + .e_wb_data_i( s15_data_i ), + .e_wb_data_o( s15_data_o ), + .e_wb_addr_o( s15_addr_o ), + .e_wb_sel_o( s15_sel_o ), + .e_wb_we_o( s15_we_o ), + .e_wb_cyc_o( s15_cyc_o ), + .e_wb_stb_o( s15_stb_o ), + .e_wb_ack_i( s15_ack_i ), + .e_wb_err_i( s15_err_i ), + .e_wb_rty_i( s15_rty_i ), + + .conf0( conf0 ), + .conf1( conf1 ), + .conf2( conf2 ), + .conf3( conf3 ), + .conf4( conf4 ), + .conf5( conf5 ), + .conf6( conf6 ), + .conf7( conf7 ), + .conf8( conf8 ), + .conf9( conf9 ), + .conf10( conf10 ), + .conf11( conf11 ), + .conf12( conf12 ), + .conf13( conf13 ), + .conf14( conf14 ), + .conf15( conf15 ) + ); +endmodule + Index: tags/start/rtl/verilog/wb_conmax_arb.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_arb.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_arb.v (revision 3) @@ -0,0 +1,260 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// General Round Robin Arbiter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_arb.v,v 1.1.1.1 2001-10-19 11:01:40 rudi Exp $ +// +// $Date: 2001-10-19 11:01:40 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_arb(clk, rst, req, gnt, next); + +input clk; +input rst; +input [7:0] req; // Req input +output [2:0] gnt; // Grant output +input next; // Next Target + +/////////////////////////////////////////////////////////////////////// +// +// Parameters +// + +parameter [2:0] + grant0 = 3'h0, + grant1 = 3'h1, + grant2 = 3'h2, + grant3 = 3'h3, + grant4 = 3'h4, + grant5 = 3'h5, + grant6 = 3'h6, + grant7 = 3'h7; + +/////////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [2:0] state, next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign gnt = state; + +always@(posedge clk or posedge rst) + if(rst) state <= #1 grant0; + else state <= #1 next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Next State Logic +// - implements round robin arbitration algorithm +// - switches grant if current req is dropped or next is asserted +// - parks at last grant +// + +always@(state or req or next) + begin + next_state = state; // Default Keep State + case(state) // synopsys parallel_case full_case + grant0: + // if this req is dropped or next is asserted, check for other req's + if(!req[0] | next) + begin + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + end + grant1: + // if this req is dropped or next is asserted, check for other req's + if(!req[1] | next) + begin + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + end + grant2: + // if this req is dropped or next is asserted, check for other req's + if(!req[2] | next) + begin + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] | next) + begin + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + end + grant4: + // if this req is dropped or next is asserted, check for other req's + if(!req[4] | next) + begin + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + end + grant5: + // if this req is dropped or next is asserted, check for other req's + if(!req[5] | next) + begin + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + end + grant6: + // if this req is dropped or next is asserted, check for other req's + if(!req[6] | next) + begin + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + end + grant7: + // if this req is dropped or next is asserted, check for other req's + if(!req[7] | next) + begin + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + end + endcase + end + +endmodule + Index: tags/start/rtl/verilog/wb_conmax_pri_dec.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_pri_dec.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_pri_dec.v (revision 3) @@ -0,0 +1,112 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Priority Decoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_pri_dec.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $ +// +// $Date: 2001-10-19 11:01:42 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_pri_dec(valid, pri_in, pri_out); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input valid; +input [1:0] pri_in; +output [3:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [3:0] pri_out; +reg [3:0] pri_out_d0; +reg [3:0] pri_out_d1; + +//////////////////////////////////////////////////////////////////// +// +// Priority Decoder +// + +// 4 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d1 = 4'b0001; + else + if(pri_in==2'h0) pri_out_d1 = 4'b0001; + else + if(pri_in==2'h1) pri_out_d1 = 4'b0010; + else + if(pri_in==2'h2) pri_out_d1 = 4'b0100; + else pri_out_d1 = 4'b1000; + +// 2 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d0 = 4'b0001; + else + if(pri_in==2'h0) pri_out_d0 = 4'b0001; + else pri_out_d0 = 4'b0010; + +// Select Configured Priority + +assign pri_out = (pri_sel==2'd0) ? 4'h0 : ( (pri_sel==1'd1) ? pri_out_d0 : pri_out_d1 ); + +endmodule + Index: tags/start/rtl/verilog/wb_conmax_rf.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_rf.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_rf.v (revision 3) @@ -0,0 +1,304 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_ic/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_rf.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $ +// +// $Date: 2001-10-19 11:01:42 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_rf( + clk_i, rst_i, + + // Internal Wishbone Interface + i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i, + i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o, + + // External Wishbone Interface + e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o, + e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i, + + // Configuration Registers + conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7, + conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15 + + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [3:0] rf_addr = 4'hf; +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Internal Wishbone Interface +input [dw-1:0] i_wb_data_i; +output [dw-1:0] i_wb_data_o; +input [aw-1:0] i_wb_addr_i; +input [sw-1:0] i_wb_sel_i; +input i_wb_we_i; +input i_wb_cyc_i; +input i_wb_stb_i; +output i_wb_ack_o; +output i_wb_err_o; +output i_wb_rty_o; + +// External Wishbone Interface +input [dw-1:0] e_wb_data_i; +output [dw-1:0] e_wb_data_o; +output [aw-1:0] e_wb_addr_o; +output [sw-1:0] e_wb_sel_o; +output e_wb_we_o; +output e_wb_cyc_o; +output e_wb_stb_o; +input e_wb_ack_i; +input e_wb_err_i; +input e_wb_rty_i; + +// Configuration Registers +output [15:0] conf0; +output [15:0] conf1; +output [15:0] conf2; +output [15:0] conf3; +output [15:0] conf4; +output [15:0] conf5; +output [15:0] conf6; +output [15:0] conf7; +output [15:0] conf8; +output [15:0] conf9; +output [15:0] conf10; +output [15:0] conf11; +output [15:0] conf12; +output [15:0] conf13; +output [15:0] conf14; +output [15:0] conf15; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5; +reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11; +reg [15:0] conf12, conf13, conf14, conf15; + +//synopsys infer_multibit "conf0" +//synopsys infer_multibit "conf1" +//synopsys infer_multibit "conf2" +//synopsys infer_multibit "conf3" +//synopsys infer_multibit "conf4" +//synopsys infer_multibit "conf5" +//synopsys infer_multibit "conf6" +//synopsys infer_multibit "conf7" +//synopsys infer_multibit "conf8" +//synopsys infer_multibit "conf9" +//synopsys infer_multibit "conf10" +//synopsys infer_multibit "conf11" +//synopsys infer_multibit "conf12" +//synopsys infer_multibit "conf13" +//synopsys infer_multibit "conf14" +//synopsys infer_multibit "conf15" + +wire rf_sel; +reg [15:0] rf_dout; +reg rf_ack; +reg rf_we; + +//////////////////////////////////////////////////////////////////// +// +// Register File Select Logic +// + +assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr); + +//////////////////////////////////////////////////////////////////// +// +// Register File Logic +// + +always @(posedge clk_i) + rf_we <= #1 rf_sel & i_wb_we_i & !rf_we; + +always @(posedge clk_i) + rf_ack <= #1 rf_sel & !rf_ack; + +// Writre Logic +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf0 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf1 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf2 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf3 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf4 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf5 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf6 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf7 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf8 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf9 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf10 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf11 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf12 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf13 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf14 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf15 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0]; + +// Read Logic +always @(posedge clk_i) + if(!rf_sel) rf_dout <= #1 16'h0; + else + case(i_wb_addr_i[5:2]) + 4'd0: rf_dout <= #1 conf0; + 4'd1: rf_dout <= #1 conf1; + 4'd2: rf_dout <= #1 conf2; + 4'd3: rf_dout <= #1 conf3; + 4'd4: rf_dout <= #1 conf4; + 4'd5: rf_dout <= #1 conf5; + 4'd6: rf_dout <= #1 conf6; + 4'd7: rf_dout <= #1 conf7; + 4'd8: rf_dout <= #1 conf8; + 4'd9: rf_dout <= #1 conf9; + 4'd10: rf_dout <= #1 conf10; + 4'd11: rf_dout <= #1 conf11; + 4'd12: rf_dout <= #1 conf12; + 4'd13: rf_dout <= #1 conf13; + 4'd14: rf_dout <= #1 conf14; + 4'd15: rf_dout <= #1 conf15; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Register File By-Pass Logic +// + +assign e_wb_addr_o = i_wb_addr_i; +assign e_wb_sel_o = i_wb_sel_i; +assign e_wb_data_o = i_wb_data_i; + +assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i; +assign e_wb_stb_o = i_wb_stb_i; +assign e_wb_we_o = i_wb_we_i; + +assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i; +assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i; +assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i; +assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i; + +endmodule Index: tags/start/rtl/verilog/wb_conmax_slave_if.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_slave_if.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_slave_if.v (revision 3) @@ -0,0 +1,442 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Slave Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_slave_if.v,v 1.1.1.1 2001-10-19 11:01:39 rudi Exp $ +// +// $Date: 2001-10-19 11:01:39 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_slave_if( + + clk_i, rst_i, conf, + + // Slave interface + wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + // Master 0 Interface + m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, + + // Master 1 Interface + m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, + + // Master 2 Interface + m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, + + // Master 3 Interface + m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, + + // Master 4 Interface + m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, + + // Master 5 Interface + m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, + + // Master 6 Interface + m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, + + // Master 7 Interface + m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd2; +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; +input [15:0] conf; + +// Slave Interface +input [dw-1:0] wb_data_i; +output [dw-1:0] wb_data_o; +output [aw-1:0] wb_addr_o; +output [sw-1:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// Master 0 Interface +input [dw-1:0] m0_data_i; +output [dw-1:0] m0_data_o; +input [aw-1:0] m0_addr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_data_i; +output [dw-1:0] m1_data_o; +input [aw-1:0] m1_addr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_data_i; +output [dw-1:0] m2_data_o; +input [aw-1:0] m2_addr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_data_i; +output [dw-1:0] m3_data_o; +input [aw-1:0] m3_addr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_data_i; +output [dw-1:0] m4_data_o; +input [aw-1:0] m4_addr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_data_i; +output [dw-1:0] m5_data_o; +input [aw-1:0] m5_addr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_data_i; +output [dw-1:0] m6_data_o; +input [aw-1:0] m6_addr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_data_i; +output [dw-1:0] m7_data_o; +input [aw-1:0] m7_addr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [aw-1:0] wb_addr_o; +reg [dw-1:0] wb_data_o; +reg [sw-1:0] wb_sel_o; +reg wb_we_o; +reg wb_cyc_o; +reg wb_stb_o; +wire [2:0] mast_sel_simple; +wire [2:0] mast_sel_pe; +wire [2:0] mast_sel; + +reg next; +reg m0_cyc_r, m1_cyc_r, m2_cyc_r, m3_cyc_r; +reg m4_cyc_r, m5_cyc_r, m6_cyc_r, m7_cyc_r; + +//////////////////////////////////////////////////////////////////// +// +// Select logic +// + +always @(posedge clk_i) + next <= #1 ~wb_cyc_o; + + +wb_conmax_arb arb( + .clk( clk_i ), + .rst( rst_i ), + .req( { m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i } ), + .gnt( mast_sel_simple ), + .next( 1'b0 ) + ); + +wb_conmax_msel #(pri_sel) msel( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf ), + .req( { m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i} ), + .sel( mast_sel_pe ), + .next( next ) + ); + +assign mast_sel = (pri_sel == 2'd0) ? mast_sel_simple : mast_sel_pe; + +//////////////////////////////////////////////////////////////////// +// +// Address & Data Pass +// + +always @(mast_sel or m0_addr_i or m1_addr_i or m2_addr_i or m3_addr_i + or m4_addr_i or m5_addr_i or m6_addr_i or m7_addr_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_addr_o = m0_addr_i; + 3'd1: wb_addr_o = m1_addr_i; + 3'd2: wb_addr_o = m2_addr_i; + 3'd3: wb_addr_o = m3_addr_i; + 3'd4: wb_addr_o = m4_addr_i; + 3'd5: wb_addr_o = m5_addr_i; + 3'd6: wb_addr_o = m6_addr_i; + 3'd7: wb_addr_o = m7_addr_i; + default: wb_addr_o = {aw{1'bx}}; + endcase + +always @(mast_sel or m0_sel_i or m1_sel_i or m2_sel_i or m3_sel_i + or m4_sel_i or m5_sel_i or m6_sel_i or m7_sel_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_sel_o = m0_sel_i; + 3'd1: wb_sel_o = m1_sel_i; + 3'd2: wb_sel_o = m2_sel_i; + 3'd3: wb_sel_o = m3_sel_i; + 3'd4: wb_sel_o = m4_sel_i; + 3'd5: wb_sel_o = m5_sel_i; + 3'd6: wb_sel_o = m6_sel_i; + 3'd7: wb_sel_o = m7_sel_i; + default: wb_sel_o = {sw{1'bx}}; + endcase + +always @(mast_sel or m0_data_i or m1_data_i or m2_data_i or m3_data_i + or m4_data_i or m5_data_i or m6_data_i or m7_data_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_data_o = m0_data_i; + 3'd1: wb_data_o = m1_data_i; + 3'd2: wb_data_o = m2_data_i; + 3'd3: wb_data_o = m3_data_i; + 3'd4: wb_data_o = m4_data_i; + 3'd5: wb_data_o = m5_data_i; + 3'd6: wb_data_o = m6_data_i; + 3'd7: wb_data_o = m7_data_i; + default: wb_data_o = {dw{1'bx}}; + endcase + +assign m0_data_o = wb_data_i; +assign m1_data_o = wb_data_i; +assign m2_data_o = wb_data_i; +assign m3_data_o = wb_data_i; +assign m4_data_o = wb_data_i; +assign m5_data_o = wb_data_i; +assign m6_data_o = wb_data_i; +assign m7_data_o = wb_data_i; + +//////////////////////////////////////////////////////////////////// +// +// Control Signal Pass +// + +always @(mast_sel or m0_we_i or m1_we_i or m2_we_i or m3_we_i + or m4_we_i or m5_we_i or m6_we_i or m7_we_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_we_o = m0_we_i; + 3'd1: wb_we_o = m1_we_i; + 3'd2: wb_we_o = m2_we_i; + 3'd3: wb_we_o = m3_we_i; + 3'd4: wb_we_o = m4_we_i; + 3'd5: wb_we_o = m5_we_i; + 3'd6: wb_we_o = m6_we_i; + 3'd7: wb_we_o = m7_we_i; + default: wb_we_o = 1'bx; + endcase + +always @(posedge clk_i) + m0_cyc_r <= #1 m0_cyc_i; + +always @(posedge clk_i) + m1_cyc_r <= #1 m1_cyc_i; + +always @(posedge clk_i) + m2_cyc_r <= #1 m2_cyc_i; + +always @(posedge clk_i) + m3_cyc_r <= #1 m3_cyc_i; + +always @(posedge clk_i) + m4_cyc_r <= #1 m4_cyc_i; + +always @(posedge clk_i) + m5_cyc_r <= #1 m5_cyc_i; + +always @(posedge clk_i) + m6_cyc_r <= #1 m6_cyc_i; + +always @(posedge clk_i) + m7_cyc_r <= #1 m7_cyc_i; + +always @(mast_sel or m0_cyc_i or m1_cyc_i or m2_cyc_i or m3_cyc_i + or m4_cyc_i or m5_cyc_i or m6_cyc_i or m7_cyc_i + or m0_cyc_r or m1_cyc_r or m2_cyc_r or m3_cyc_r + or m4_cyc_r or m5_cyc_r or m6_cyc_r or m7_cyc_r) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_cyc_o = m0_cyc_i & m0_cyc_r; + 3'd1: wb_cyc_o = m1_cyc_i & m1_cyc_r; + 3'd2: wb_cyc_o = m2_cyc_i & m2_cyc_r; + 3'd3: wb_cyc_o = m3_cyc_i & m3_cyc_r; + 3'd4: wb_cyc_o = m4_cyc_i & m4_cyc_r; + 3'd5: wb_cyc_o = m5_cyc_i & m5_cyc_r; + 3'd6: wb_cyc_o = m6_cyc_i & m6_cyc_r; + 3'd7: wb_cyc_o = m7_cyc_i & m7_cyc_r; + default: wb_cyc_o = 1'b0; + endcase + +always @(mast_sel or m0_stb_i or m1_stb_i or m2_stb_i or m3_stb_i + or m4_stb_i or m5_stb_i or m6_stb_i or m7_stb_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_stb_o = m0_stb_i; + 3'd1: wb_stb_o = m1_stb_i; + 3'd2: wb_stb_o = m2_stb_i; + 3'd3: wb_stb_o = m3_stb_i; + 3'd4: wb_stb_o = m4_stb_i; + 3'd5: wb_stb_o = m5_stb_i; + 3'd6: wb_stb_o = m6_stb_i; + 3'd7: wb_stb_o = m7_stb_i; + default: wb_stb_o = 1'b0; + endcase + +assign m0_ack_o = (mast_sel==3'd0) & wb_ack_i; +assign m1_ack_o = (mast_sel==3'd1) & wb_ack_i; +assign m2_ack_o = (mast_sel==3'd2) & wb_ack_i; +assign m3_ack_o = (mast_sel==3'd3) & wb_ack_i; +assign m4_ack_o = (mast_sel==3'd4) & wb_ack_i; +assign m5_ack_o = (mast_sel==3'd5) & wb_ack_i; +assign m6_ack_o = (mast_sel==3'd6) & wb_ack_i; +assign m7_ack_o = (mast_sel==3'd7) & wb_ack_i; + +assign m0_err_o = (mast_sel==3'd0) & wb_err_i; +assign m1_err_o = (mast_sel==3'd1) & wb_err_i; +assign m2_err_o = (mast_sel==3'd2) & wb_err_i; +assign m3_err_o = (mast_sel==3'd3) & wb_err_i; +assign m4_err_o = (mast_sel==3'd4) & wb_err_i; +assign m5_err_o = (mast_sel==3'd5) & wb_err_i; +assign m6_err_o = (mast_sel==3'd6) & wb_err_i; +assign m7_err_o = (mast_sel==3'd7) & wb_err_i; + +assign m0_rty_o = (mast_sel==3'd0) & wb_rty_i; +assign m1_rty_o = (mast_sel==3'd1) & wb_rty_i; +assign m2_rty_o = (mast_sel==3'd2) & wb_rty_i; +assign m3_rty_o = (mast_sel==3'd3) & wb_rty_i; +assign m4_rty_o = (mast_sel==3'd4) & wb_rty_i; +assign m5_rty_o = (mast_sel==3'd5) & wb_rty_i; +assign m6_rty_o = (mast_sel==3'd6) & wb_rty_i; +assign m7_rty_o = (mast_sel==3'd7) & wb_rty_i; + +endmodule + Index: tags/start/rtl/verilog/wb_conmax_master_if.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_master_if.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_master_if.v (revision 3) @@ -0,0 +1,578 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Master Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_master_if.v,v 1.1.1.1 2001-10-19 11:01:41 rudi Exp $ +// +// $Date: 2001-10-19 11:01:41 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_master_if( + + clk_i, rst_i, + + // Master interface + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + + // Slave 0 Interface + s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, + + // Slave 1 Interface + s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, + + // Slave 2 Interface + s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, + + // Slave 3 Interface + s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, + + // Slave 4 Interface + s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, + + // Slave 5 Interface + s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, + + // Slave 6 Interface + s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, + + // Slave 7 Interface + s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, + + // Slave 8 Interface + s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o, + s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i, + + // Slave 9 Interface + s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o, + s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i, + + // Slave 10 Interface + s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o, + s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i, + + // Slave 11 Interface + s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o, + s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i, + + // Slave 12 Interface + s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o, + s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i, + + // Slave 13 Interface + s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o, + s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i, + + // Slave 14 Interface + s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o, + s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i, + + // Slave 15 Interface + s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o, + s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Master Interface +input [dw-1:0] wb_data_i; +output [dw-1:0] wb_data_o; +input [aw-1:0] wb_addr_i; +input [sw-1:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_data_i; +output [dw-1:0] s0_data_o; +output [aw-1:0] s0_addr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_data_i; +output [dw-1:0] s1_data_o; +output [aw-1:0] s1_addr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_data_i; +output [dw-1:0] s2_data_o; +output [aw-1:0] s2_addr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_data_i; +output [dw-1:0] s3_data_o; +output [aw-1:0] s3_addr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_data_i; +output [dw-1:0] s4_data_o; +output [aw-1:0] s4_addr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_data_i; +output [dw-1:0] s5_data_o; +output [aw-1:0] s5_addr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_data_i; +output [dw-1:0] s6_data_o; +output [aw-1:0] s6_addr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_data_i; +output [dw-1:0] s7_data_o; +output [aw-1:0] s7_addr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + +// Slave 8 Interface +input [dw-1:0] s8_data_i; +output [dw-1:0] s8_data_o; +output [aw-1:0] s8_addr_o; +output [sw-1:0] s8_sel_o; +output s8_we_o; +output s8_cyc_o; +output s8_stb_o; +input s8_ack_i; +input s8_err_i; +input s8_rty_i; + +// Slave 9 Interface +input [dw-1:0] s9_data_i; +output [dw-1:0] s9_data_o; +output [aw-1:0] s9_addr_o; +output [sw-1:0] s9_sel_o; +output s9_we_o; +output s9_cyc_o; +output s9_stb_o; +input s9_ack_i; +input s9_err_i; +input s9_rty_i; + +// Slave 10 Interface +input [dw-1:0] s10_data_i; +output [dw-1:0] s10_data_o; +output [aw-1:0] s10_addr_o; +output [sw-1:0] s10_sel_o; +output s10_we_o; +output s10_cyc_o; +output s10_stb_o; +input s10_ack_i; +input s10_err_i; +input s10_rty_i; + +// Slave 11 Interface +input [dw-1:0] s11_data_i; +output [dw-1:0] s11_data_o; +output [aw-1:0] s11_addr_o; +output [sw-1:0] s11_sel_o; +output s11_we_o; +output s11_cyc_o; +output s11_stb_o; +input s11_ack_i; +input s11_err_i; +input s11_rty_i; + +// Slave 12 Interface +input [dw-1:0] s12_data_i; +output [dw-1:0] s12_data_o; +output [aw-1:0] s12_addr_o; +output [sw-1:0] s12_sel_o; +output s12_we_o; +output s12_cyc_o; +output s12_stb_o; +input s12_ack_i; +input s12_err_i; +input s12_rty_i; + +// Slave 13 Interface +input [dw-1:0] s13_data_i; +output [dw-1:0] s13_data_o; +output [aw-1:0] s13_addr_o; +output [sw-1:0] s13_sel_o; +output s13_we_o; +output s13_cyc_o; +output s13_stb_o; +input s13_ack_i; +input s13_err_i; +input s13_rty_i; + +// Slave 14 Interface +input [dw-1:0] s14_data_i; +output [dw-1:0] s14_data_o; +output [aw-1:0] s14_addr_o; +output [sw-1:0] s14_sel_o; +output s14_we_o; +output s14_cyc_o; +output s14_stb_o; +input s14_ack_i; +input s14_err_i; +input s14_rty_i; + +// Slave 15 Interface +input [dw-1:0] s15_data_i; +output [dw-1:0] s15_data_o; +output [aw-1:0] s15_addr_o; +output [sw-1:0] s15_sel_o; +output s15_we_o; +output s15_cyc_o; +output s15_stb_o; +input s15_ack_i; +input s15_err_i; +input s15_rty_i; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [dw-1:0] wb_data_o; +reg wb_ack_o; +reg wb_err_o; +reg wb_rty_o; +wire [3:0] slv_sel; + +//////////////////////////////////////////////////////////////////// +// +// Select logic +// + +assign slv_sel = wb_addr_i[aw-1:aw-4]; + +//////////////////////////////////////////////////////////////////// +// +// Address & Data Pass +// + +assign s0_addr_o = wb_addr_i; +assign s1_addr_o = wb_addr_i; +assign s2_addr_o = wb_addr_i; +assign s3_addr_o = wb_addr_i; +assign s4_addr_o = wb_addr_i; +assign s5_addr_o = wb_addr_i; +assign s6_addr_o = wb_addr_i; +assign s7_addr_o = wb_addr_i; +assign s8_addr_o = wb_addr_i; +assign s9_addr_o = wb_addr_i; +assign s10_addr_o = wb_addr_i; +assign s11_addr_o = wb_addr_i; +assign s12_addr_o = wb_addr_i; +assign s13_addr_o = wb_addr_i; +assign s14_addr_o = wb_addr_i; +assign s15_addr_o = wb_addr_i; + +assign s0_sel_o = wb_sel_i; +assign s1_sel_o = wb_sel_i; +assign s2_sel_o = wb_sel_i; +assign s3_sel_o = wb_sel_i; +assign s4_sel_o = wb_sel_i; +assign s5_sel_o = wb_sel_i; +assign s6_sel_o = wb_sel_i; +assign s7_sel_o = wb_sel_i; +assign s8_sel_o = wb_sel_i; +assign s9_sel_o = wb_sel_i; +assign s10_sel_o = wb_sel_i; +assign s11_sel_o = wb_sel_i; +assign s12_sel_o = wb_sel_i; +assign s13_sel_o = wb_sel_i; +assign s14_sel_o = wb_sel_i; +assign s15_sel_o = wb_sel_i; + +assign s0_data_o = wb_data_i; +assign s1_data_o = wb_data_i; +assign s2_data_o = wb_data_i; +assign s3_data_o = wb_data_i; +assign s4_data_o = wb_data_i; +assign s5_data_o = wb_data_i; +assign s6_data_o = wb_data_i; +assign s7_data_o = wb_data_i; +assign s8_data_o = wb_data_i; +assign s9_data_o = wb_data_i; +assign s10_data_o = wb_data_i; +assign s11_data_o = wb_data_i; +assign s12_data_o = wb_data_i; +assign s13_data_o = wb_data_i; +assign s14_data_o = wb_data_i; +assign s15_data_o = wb_data_i; + +always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or + s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or + s9_data_i or s10_data_i or s11_data_i or s12_data_i or + s13_data_i or s14_data_i or s15_data_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_data_o = s0_data_i; + 4'd1: wb_data_o = s1_data_i; + 4'd2: wb_data_o = s2_data_i; + 4'd3: wb_data_o = s3_data_i; + 4'd4: wb_data_o = s4_data_i; + 4'd5: wb_data_o = s5_data_i; + 4'd6: wb_data_o = s6_data_i; + 4'd7: wb_data_o = s7_data_i; + 4'd8: wb_data_o = s8_data_i; + 4'd9: wb_data_o = s9_data_i; + 4'd10: wb_data_o = s10_data_i; + 4'd11: wb_data_o = s11_data_i; + 4'd12: wb_data_o = s12_data_i; + 4'd13: wb_data_o = s13_data_i; + 4'd14: wb_data_o = s14_data_i; + 4'd15: wb_data_o = s15_data_i; + default: wb_data_o = {dw{1'bx}}; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Control Signal Pass +// + +assign s0_we_o = wb_we_i; +assign s1_we_o = wb_we_i; +assign s2_we_o = wb_we_i; +assign s3_we_o = wb_we_i; +assign s4_we_o = wb_we_i; +assign s5_we_o = wb_we_i; +assign s6_we_o = wb_we_i; +assign s7_we_o = wb_we_i; +assign s8_we_o = wb_we_i; +assign s9_we_o = wb_we_i; +assign s10_we_o = wb_we_i; +assign s11_we_o = wb_we_i; +assign s12_we_o = wb_we_i; +assign s13_we_o = wb_we_i; +assign s14_we_o = wb_we_i; +assign s15_we_o = wb_we_i; + +assign s0_cyc_o = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0); +assign s1_cyc_o = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0); +assign s2_cyc_o = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0); +assign s3_cyc_o = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0); +assign s4_cyc_o = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0); +assign s5_cyc_o = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0); +assign s6_cyc_o = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0); +assign s7_cyc_o = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0); +assign s8_cyc_o = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0); +assign s9_cyc_o = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0); +assign s10_cyc_o = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0); +assign s11_cyc_o = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0); +assign s12_cyc_o = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0); +assign s13_cyc_o = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0); +assign s14_cyc_o = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0); +assign s15_cyc_o = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0); + +assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0; +assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0; +assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0; +assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0; +assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0; +assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0; +assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0; +assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0; +assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0; +assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0; +assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0; +assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0; +assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0; +assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0; +assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0; +assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0; + +always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or + s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or + s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or + s13_ack_i or s14_ack_i or s15_ack_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_ack_o = s0_ack_i; + 4'd1: wb_ack_o = s1_ack_i; + 4'd2: wb_ack_o = s2_ack_i; + 4'd3: wb_ack_o = s3_ack_i; + 4'd4: wb_ack_o = s4_ack_i; + 4'd5: wb_ack_o = s5_ack_i; + 4'd6: wb_ack_o = s6_ack_i; + 4'd7: wb_ack_o = s7_ack_i; + 4'd8: wb_ack_o = s8_ack_i; + 4'd9: wb_ack_o = s9_ack_i; + 4'd10: wb_ack_o = s10_ack_i; + 4'd11: wb_ack_o = s11_ack_i; + 4'd12: wb_ack_o = s12_ack_i; + 4'd13: wb_ack_o = s13_ack_i; + 4'd14: wb_ack_o = s14_ack_i; + 4'd15: wb_ack_o = s15_ack_i; + default: wb_ack_o = 1'b0; + endcase + +always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or + s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or + s9_err_i or s10_err_i or s11_err_i or s12_err_i or + s13_err_i or s14_err_i or s15_err_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_err_o = s0_err_i; + 4'd1: wb_err_o = s1_err_i; + 4'd2: wb_err_o = s2_err_i; + 4'd3: wb_err_o = s3_err_i; + 4'd4: wb_err_o = s4_err_i; + 4'd5: wb_err_o = s5_err_i; + 4'd6: wb_err_o = s6_err_i; + 4'd7: wb_err_o = s7_err_i; + 4'd8: wb_err_o = s8_err_i; + 4'd9: wb_err_o = s9_err_i; + 4'd10: wb_err_o = s10_err_i; + 4'd11: wb_err_o = s11_err_i; + 4'd12: wb_err_o = s12_err_i; + 4'd13: wb_err_o = s13_err_i; + 4'd14: wb_err_o = s14_err_i; + 4'd15: wb_err_o = s15_err_i; + default: wb_err_o = 1'b0; + endcase + +always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or + s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or + s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or + s13_rty_i or s14_rty_i or s15_rty_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_rty_o = s0_rty_i; + 4'd1: wb_rty_o = s1_rty_i; + 4'd2: wb_rty_o = s2_rty_i; + 4'd3: wb_rty_o = s3_rty_i; + 4'd4: wb_rty_o = s4_rty_i; + 4'd5: wb_rty_o = s5_rty_i; + 4'd6: wb_rty_o = s6_rty_i; + 4'd7: wb_rty_o = s7_rty_i; + 4'd8: wb_rty_o = s8_rty_i; + 4'd9: wb_rty_o = s9_rty_i; + 4'd10: wb_rty_o = s10_rty_i; + 4'd11: wb_rty_o = s11_rty_i; + 4'd12: wb_rty_o = s12_rty_i; + 4'd13: wb_rty_o = s13_rty_i; + 4'd14: wb_rty_o = s14_rty_i; + 4'd15: wb_rty_o = s15_rty_i; + default: wb_rty_o = 1'b0; + endcase + +endmodule + + Index: tags/start/rtl/verilog/wb_conmax_defines.v =================================================================== --- tags/start/rtl/verilog/wb_conmax_defines.v (nonexistent) +++ tags/start/rtl/verilog/wb_conmax_defines.v (revision 3) @@ -0,0 +1,58 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_defines.v,v 1.1.1.1 2001-10-19 11:01:40 rudi Exp $ +// +// $Date: 2001-10-19 11:01:40 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// + +`timescale 1ns / 10ps + Index: tags/start/slv3.pl =================================================================== --- tags/start/slv3.pl (nonexistent) +++ tags/start/slv3.pl (revision 3) @@ -0,0 +1,103 @@ + +for($n=0;$n<16;$n++) { + + +printf("wb_conmax_slave_if #(pri_sel%0d) s%0d(\n",$n,$n); +printf(" .clk_i( clk_i ),\n",$n); +printf(" .rst_i( rst_i ),\n",$n); +printf(" .conf( conf%0d ),\n",$n); +printf(" .wb_data_i( s%0d_data_i ),\n",$n); +printf(" .wb_data_o( s%0d_data_o ),\n",$n); +printf(" .wb_addr_o( s%0d_addr_o ),\n",$n); +printf(" .wb_sel_o( s%0d_sel_o ),\n",$n); +printf(" .wb_we_o( s%0d_we_o ),\n",$n); +printf(" .wb_cyc_o( s%0d_cyc_o ),\n",$n); +printf(" .wb_stb_o( s%0d_stb_o ),\n",$n); +printf(" .wb_ack_i( s%0d_ack_i ),\n",$n); +printf(" .wb_err_i( s%0d_err_i ),\n",$n); +printf(" .wb_rty_i( s%0d_rty_i ),\n",$n); +printf(" .m0_data_i( m0s%0d_data_o ),\n",$n); +printf(" .m0_data_o( m0s%0d_data_i ),\n",$n); +printf(" .m0_addr_i( m0s%0d_addr ),\n",$n); +printf(" .m0_sel_i( m0s%0d_sel ),\n",$n); +printf(" .m0_we_i( m0s%0d_we ),\n",$n); +printf(" .m0_cyc_i( m0s%0d_cyc ),\n",$n); +printf(" .m0_stb_i( m0s%0d_stb ),\n",$n); +printf(" .m0_ack_o( m0s%0d_ack ),\n",$n); +printf(" .m0_err_o( m0s%0d_err ),\n",$n); +printf(" .m0_rty_o( m0s%0d_rty ),\n",$n); +printf(" .m1_data_i( m1s%0d_data_o ),\n",$n); +printf(" .m1_data_o( m1s%0d_data_i ),\n",$n); +printf(" .m1_addr_i( m1s%0d_addr ),\n",$n); +printf(" .m1_sel_i( m1s%0d_sel ),\n",$n); +printf(" .m1_we_i( m1s%0d_we ),\n",$n); +printf(" .m1_cyc_i( m1s%0d_cyc ),\n",$n); +printf(" .m1_stb_i( m1s%0d_stb ),\n",$n); +printf(" .m1_ack_o( m1s%0d_ack ),\n",$n); +printf(" .m1_err_o( m1s%0d_err ),\n",$n); +printf(" .m1_rty_o( m1s%0d_rty ),\n",$n); +printf(" .m2_data_i( m2s%0d_data_o ),\n",$n); +printf(" .m2_data_o( m2s%0d_data_i ),\n",$n); +printf(" .m2_addr_i( m2s%0d_addr ),\n",$n); +printf(" .m2_sel_i( m2s%0d_sel ),\n",$n); +printf(" .m2_we_i( m2s%0d_we ),\n",$n); +printf(" .m2_cyc_i( m2s%0d_cyc ),\n",$n); +printf(" .m2_stb_i( m2s%0d_stb ),\n",$n); +printf(" .m2_ack_o( m2s%0d_ack ),\n",$n); +printf(" .m2_err_o( m2s%0d_err ),\n",$n); +printf(" .m2_rty_o( m2s%0d_rty ),\n",$n); +printf(" .m3_data_i( m3s%0d_data_o ),\n",$n); +printf(" .m3_data_o( m3s%0d_data_i ),\n",$n); +printf(" .m3_addr_i( m3s%0d_addr ),\n",$n); +printf(" .m3_sel_i( m3s%0d_sel ),\n",$n); +printf(" .m3_we_i( m3s%0d_we ),\n",$n); +printf(" .m3_cyc_i( m3s%0d_cyc ),\n",$n); +printf(" .m3_stb_i( m3s%0d_stb ),\n",$n); +printf(" .m3_ack_o( m3s%0d_ack ),\n",$n); +printf(" .m3_err_o( m3s%0d_err ),\n",$n); +printf(" .m3_rty_o( m3s%0d_rty ),\n",$n); +printf(" .m4_data_i( m4s%0d_data_o ),\n",$n); +printf(" .m4_data_o( m4s%0d_data_i ),\n",$n); +printf(" .m4_addr_i( m4s%0d_addr ),\n",$n); +printf(" .m4_sel_i( m4s%0d_sel ),\n",$n); +printf(" .m4_we_i( m4s%0d_we ),\n",$n); +printf(" .m4_cyc_i( m4s%0d_cyc ),\n",$n); +printf(" .m4_stb_i( m4s%0d_stb ),\n",$n); +printf(" .m4_ack_o( m4s%0d_ack ),\n",$n); +printf(" .m4_err_o( m4s%0d_err ),\n",$n); +printf(" .m4_rty_o( m4s%0d_rty ),\n",$n); +printf(" .m5_data_i( m5s%0d_data_o ),\n",$n); +printf(" .m5_data_o( m5s%0d_data_i ),\n",$n); +printf(" .m5_addr_i( m5s%0d_addr ),\n",$n); +printf(" .m5_sel_i( m5s%0d_sel ),\n",$n); +printf(" .m5_we_i( m5s%0d_we ),\n",$n); +printf(" .m5_cyc_i( m5s%0d_cyc ),\n",$n); +printf(" .m5_stb_i( m5s%0d_stb ),\n",$n); +printf(" .m5_ack_o( m5s%0d_ack ),\n",$n); +printf(" .m5_err_o( m5s%0d_err ),\n",$n); +printf(" .m5_rty_o( m5s%0d_rty ),\n",$n); +printf(" .m6_data_i( m6s%0d_data_o ),\n",$n); +printf(" .m6_data_o( m6s%0d_data_i ),\n",$n); +printf(" .m6_addr_i( m6s%0d_addr ),\n",$n); +printf(" .m6_sel_i( m6s%0d_sel ),\n",$n); +printf(" .m6_we_i( m6s%0d_we ),\n",$n); +printf(" .m6_cyc_i( m6s%0d_cyc ),\n",$n); +printf(" .m6_stb_i( m6s%0d_stb ),\n",$n); +printf(" .m6_ack_o( m6s%0d_ack ),\n",$n); +printf(" .m6_err_o( m6s%0d_err ),\n",$n); +printf(" .m6_rty_o( m6s%0d_rty ),\n",$n); +printf(" .m7_data_i( m7s%0d_data_o ),\n",$n); +printf(" .m7_data_o( m7s%0d_data_i ),\n",$n); +printf(" .m7_addr_i( m7s%0d_addr ),\n",$n); +printf(" .m7_sel_i( m7s%0d_sel ),\n",$n); +printf(" .m7_we_i( m7s%0d_we ),\n",$n); +printf(" .m7_cyc_i( m7s%0d_cyc ),\n",$n); +printf(" .m7_stb_i( m7s%0d_stb ),\n",$n); +printf(" .m7_ack_o( m7s%0d_ack ),\n",$n); +printf(" .m7_err_o( m7s%0d_err ),\n",$n); +printf(" .m7_rty_o( m7s%0d_rty )\n",$n); +printf(" );\n\n",$n); + + + } + Index: tags/start/doc/STATUS.txt =================================================================== --- tags/start/doc/STATUS.txt (nonexistent) +++ tags/start/doc/STATUS.txt (revision 3) @@ -0,0 +1,20 @@ +This file describes the current status of the checked in HDL code. +Please submit all bugs/comments/suggestions regarding the DMA core +to: cores@opencores.org + +Need Help +--------- +I'm looking for help in verifying the core. If you think you can help, +please send an email to the list or to me directly. +Even though I have written a test bench and a few test, I would prefer +if someone else could verify the core as well. + + +STATUS +====== + +Initial Release (10/19/2001) +--------------------------- +- No known problems +- Needs More Testing ! + Index: tags/start/doc/README.txt =================================================================== --- tags/start/doc/README.txt (nonexistent) +++ tags/start/doc/README.txt (revision 3) @@ -0,0 +1,43 @@ + +The WISHBONE CONMAX Project Page is: +http://www.opencores.org/cores/wb_conmax/ + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + +Directory Structure +------------------- +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +- verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output + + Index: tags/start/doc/conmax.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/start/doc/conmax.pdf =================================================================== --- tags/start/doc/conmax.pdf (nonexistent) +++ tags/start/doc/conmax.pdf (revision 3)
tags/start/doc/conmax.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/start/x =================================================================== --- tags/start/x (nonexistent) +++ tags/start/x (revision 3) @@ -0,0 +1,288 @@ +// Master 0 Interface +input [dw-1:0] m0_data_i; +output [dw-1:0] m0_data_o; +input [aw-1:0] m0_addr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_data_i; +output [dw-1:0] m1_data_o; +input [aw-1:0] m1_addr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_data_i; +output [dw-1:0] m2_data_o; +input [aw-1:0] m2_addr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_data_i; +output [dw-1:0] m3_data_o; +input [aw-1:0] m3_addr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_data_i; +output [dw-1:0] m4_data_o; +input [aw-1:0] m4_addr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_data_i; +output [dw-1:0] m5_data_o; +input [aw-1:0] m5_addr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_data_i; +output [dw-1:0] m6_data_o; +input [aw-1:0] m6_addr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_data_i; +output [dw-1:0] m7_data_o; +input [aw-1:0] m7_addr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_data_i; +output [dw-1:0] s0_data_o; +output [aw-1:0] s0_addr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_data_i; +output [dw-1:0] s1_data_o; +output [aw-1:0] s1_addr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_data_i; +output [dw-1:0] s2_data_o; +output [aw-1:0] s2_addr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_data_i; +output [dw-1:0] s3_data_o; +output [aw-1:0] s3_addr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_data_i; +output [dw-1:0] s4_data_o; +output [aw-1:0] s4_addr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_data_i; +output [dw-1:0] s5_data_o; +output [aw-1:0] s5_addr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_data_i; +output [dw-1:0] s6_data_o; +output [aw-1:0] s6_addr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_data_i; +output [dw-1:0] s7_data_o; +output [aw-1:0] s7_addr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + +// Slave 8 Interface +input [dw-1:0] s8_data_i; +output [dw-1:0] s8_data_o; +output [aw-1:0] s8_addr_o; +output [sw-1:0] s8_sel_o; +output s8_we_o; +output s8_cyc_o; +output s8_stb_o; +input s8_ack_i; +input s8_err_i; +input s8_rty_i; + +// Slave 9 Interface +input [dw-1:0] s9_data_i; +output [dw-1:0] s9_data_o; +output [aw-1:0] s9_addr_o; +output [sw-1:0] s9_sel_o; +output s9_we_o; +output s9_cyc_o; +output s9_stb_o; +input s9_ack_i; +input s9_err_i; +input s9_rty_i; + +// Slave 10 Interface +input [dw-1:0] s10_data_i; +output [dw-1:0] s10_data_o; +output [aw-1:0] s10_addr_o; +output [sw-1:0] s10_sel_o; +output s10_we_o; +output s10_cyc_o; +output s10_stb_o; +input s10_ack_i; +input s10_err_i; +input s10_rty_i; + +// Slave 11 Interface +input [dw-1:0] s11_data_i; +output [dw-1:0] s11_data_o; +output [aw-1:0] s11_addr_o; +output [sw-1:0] s11_sel_o; +output s11_we_o; +output s11_cyc_o; +output s11_stb_o; +input s11_ack_i; +input s11_err_i; +input s11_rty_i; + +// Slave 12 Interface +input [dw-1:0] s12_data_i; +output [dw-1:0] s12_data_o; +output [aw-1:0] s12_addr_o; +output [sw-1:0] s12_sel_o; +output s12_we_o; +output s12_cyc_o; +output s12_stb_o; +input s12_ack_i; +input s12_err_i; +input s12_rty_i; + +// Slave 13 Interface +input [dw-1:0] s13_data_i; +output [dw-1:0] s13_data_o; +output [aw-1:0] s13_addr_o; +output [sw-1:0] s13_sel_o; +output s13_we_o; +output s13_cyc_o; +output s13_stb_o; +input s13_ack_i; +input s13_err_i; +input s13_rty_i; + +// Slave 14 Interface +input [dw-1:0] s14_data_i; +output [dw-1:0] s14_data_o; +output [aw-1:0] s14_addr_o; +output [sw-1:0] s14_sel_o; +output s14_we_o; +output s14_cyc_o; +output s14_stb_o; +input s14_ack_i; +input s14_err_i; +input s14_rty_i; + +// Slave 15 Interface +input [dw-1:0] s15_data_i; +output [dw-1:0] s15_data_o; +output [aw-1:0] s15_addr_o; +output [sw-1:0] s15_sel_o; +output s15_we_o; +output s15_cyc_o; +output s15_stb_o; +input s15_ack_i; +input s15_err_i; +input s15_rty_i; + Index: tags/start/sim/rtl_sim/run/.nclog =================================================================== --- tags/start/sim/rtl_sim/run/.nclog (nonexistent) +++ tags/start/sim/rtl_sim/run/.nclog (revision 3) @@ -0,0 +1,1127 @@ + +--- + + +--- + +ncsim> source /tools/LDV33linux/tools/inca/files/ncsimrc +ncsim> source /home/rudi/.ncsimrc +no +ncsim> run + + + +***************************************************** +* WISHBONE Connection Matrix Simulation started ... * +***************************************************** + + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m0) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m1) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m2) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m3) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m4) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m5) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m6) + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m7) + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s0) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s1) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s2) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s3) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s4) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s5) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s6) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s7) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s8) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s9) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s10) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s11) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s12) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s13) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s14) + Memory Size 13 address lines 8192 words + + +INFO: WISHBONE MEMORY MODEL INSTANTIATED (test.s15) + Memory Size 13 address lines 8192 words + + ...................................................... + : : + : Regression Run ... : + :....................................................: + + + +***************************************************** +*** Datapath 1 Test ... *** +***************************************************** + +Mode: 0 +Mode: 1 +Mode: 2 +Mode: 3 +Mode: 4 +Mode: 5 +Mode: 6 +Mode: 7 +Mode: 8 +Mode: 9 +Mode: 10 +Mode: 11 +Mode: 12 +Mode: 13 +Mode: 14 +Mode: 15 + + + +--------------------+ + | Total ERRORS: 0 | + +--------------------+ +***************************************************** +*** Test DONE ... *** +***************************************************** + + + + + +***************************************************** +*** Register File Test ... *** +***************************************************** + +Mode: 0 +Mode: 1 +Mode: 2 +Mode: 3 +Mode: 4 + + + +--------------------+ + | Total ERRORS: 0 | + +--------------------+ +***************************************************** +*** Test DONE ... *** +***************************************************** + + + + + +***************************************************** +*** Arb. 1 Test ... *** +***************************************************** + +Delay: 0 +Delay: 1 +Delay: 2 +Delay: 3 +Delay: 4 + + + +--------------------+ + | Total ERRORS: 0 | + +--------------------+ +***************************************************** +*** Test DONE ... *** +***************************************************** + + + + + +***************************************************** +*** Arb. 2 Test ... *** +***************************************************** + +Mode: 0 del: 0, siz: 1 +Mode: 0 del: 0, siz: 2 +Mode: 0 del: 0, siz: 3 +Mode: 0 del: 0, siz: 4 +Mode: 0 del: 1, siz: 1 +Mode: 0 del: 1, siz: 2 +Mode: 0 del: 1, siz: 3 +Mode: 0 del: 1, siz: 4 +Mode: 0 del: 2, siz: 1 +Mode: 0 del: 2, siz: 2 +Mode: 0 del: 2, siz: 3 +Mode: 0 del: 2, siz: 4 +Mode: 0 del: 3, siz: 1 +Mode: 0 del: 3, siz: 2 +Mode: 0 del: 3, siz: 3 +Mode: 0 del: 3, siz: 4 +Mode: 0 del: 4, siz: 1 +Mode: 0 del: 4, siz: 2 +Mode: 0 del: 4, siz: 3 +Mode: 0 del: 4, siz: 4 +Mode: 0 del: 5, siz: 1 +Mode: 0 del: 5, siz: 2 +Mode: 0 del: 5, siz: 3 +Mode: 0 del: 5, siz: 4 +Mode: 0 del: 6, siz: 1 +Mode: 0 del: 6, siz: 2 +Mode: 0 del: 6, siz: 3 +Mode: 0 del: 6, siz: 4 +Mode: 1 del: 0, siz: 1 +Mode: 1 del: 0, siz: 2 +Mode: 1 del: 0, siz: 3 +Mode: 1 del: 0, siz: 4 +Mode: 1 del: 1, siz: 1 +Mode: 1 del: 1, siz: 2 +Mode: 1 del: 1, siz: 3 +Mode: 1 del: 1, siz: 4 +Mode: 1 del: 2, siz: 1 +Mode: 1 del: 2, siz: 2 +Mode: 1 del: 2, siz: 3 +Mode: 1 del: 2, siz: 4 +Mode: 1 del: 3, siz: 1 +Mode: 1 del: 3, siz: 2 +Mode: 1 del: 3, siz: 3 +Mode: 1 del: 3, siz: 4 +Mode: 1 del: 4, siz: 1 +Mode: 1 del: 4, siz: 2 +Mode: 1 del: 4, siz: 3 +Mode: 1 del: 4, siz: 4 +Mode: 1 del: 5, siz: 1 +Mode: 1 del: 5, siz: 2 +Mode: 1 del: 5, siz: 3 +Mode: 1 del: 5, siz: 4 +Mode: 1 del: 6, siz: 1 +Mode: 1 del: 6, siz: 2 +Mode: 1 del: 6, siz: 3 +Mode: 1 del: 6, siz: 4 +Mode: 2 del: 0, siz: 1 +Mode: 2 del: 0, siz: 2 +Mode: 2 del: 0, siz: 3 +Mode: 2 del: 0, siz: 4 +Mode: 2 del: 1, siz: 1 +Mode: 2 del: 1, siz: 2 +Mode: 2 del: 1, siz: 3 +Mode: 2 del: 1, siz: 4 +Mode: 2 del: 2, siz: 1 +Mode: 2 del: 2, siz: 2 +Mode: 2 del: 2, siz: 3 +Mode: 2 del: 2, siz: 4 +Mode: 2 del: 3, siz: 1 +Mode: 2 del: 3, siz: 2 +Mode: 2 del: 3, siz: 3 +Mode: 2 del: 3, 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+Mode: 27 del: 1, siz: 1 +Mode: 27 del: 1, siz: 2 +Mode: 27 del: 1, siz: 3 +Mode: 27 del: 1, siz: 4 +Mode: 27 del: 2, siz: 1 +Mode: 27 del: 2, siz: 2 +Mode: 27 del: 2, siz: 3 +Mode: 27 del: 2, siz: 4 +Mode: 27 del: 3, siz: 1 +Mode: 27 del: 3, siz: 2 +Mode: 27 del: 3, siz: 3 +Mode: 27 del: 3, siz: 4 +Mode: 27 del: 4, siz: 1 +Mode: 27 del: 4, siz: 2 +Mode: 27 del: 4, siz: 3 +Mode: 27 del: 4, siz: 4 +Mode: 27 del: 5, siz: 1 +Mode: 27 del: 5, siz: 2 +Mode: 27 del: 5, siz: 3 +Mode: 27 del: 5, siz: 4 +Mode: 27 del: 6, siz: 1 +Mode: 27 del: 6, siz: 2 +Mode: 27 del: 6, siz: 3 +Mode: 27 del: 6, siz: 4 +Mode: 28 del: 0, siz: 1 +Mode: 28 del: 0, siz: 2 +Mode: 28 del: 0, siz: 3 +Mode: 28 del: 0, siz: 4 +Mode: 28 del: 1, siz: 1 +Mode: 28 del: 1, siz: 2 +Mode: 28 del: 1, siz: 3 +Mode: 28 del: 1, siz: 4 +Mode: 28 del: 2, siz: 1 +Mode: 28 del: 2, siz: 2 +Mode: 28 del: 2, siz: 3 +Mode: 28 del: 2, siz: 4 +Mode: 28 del: 3, siz: 1 +Mode: 28 del: 3, siz: 2 +Mode: 28 del: 3, siz: 3 +Mode: 28 del: 3, siz: 4 +Mode: 28 del: 4, siz: 1 +Mode: 28 del: 4, siz: 2 +Mode: 28 del: 4, siz: 3 +Mode: 28 del: 4, siz: 4 +Mode: 28 del: 5, siz: 1 +Mode: 28 del: 5, siz: 2 +Mode: 28 del: 5, siz: 3 +Mode: 28 del: 5, siz: 4 +Mode: 28 del: 6, siz: 1 +Mode: 28 del: 6, siz: 2 +Mode: 28 del: 6, siz: 3 +Mode: 28 del: 6, siz: 4 +Mode: 29 del: 0, siz: 1 +Mode: 29 del: 0, siz: 2 +Mode: 29 del: 0, siz: 3 +Mode: 29 del: 0, siz: 4 +Mode: 29 del: 1, siz: 1 +Mode: 29 del: 1, siz: 2 +Mode: 29 del: 1, siz: 3 +Mode: 29 del: 1, siz: 4 +Mode: 29 del: 2, siz: 1 +Mode: 29 del: 2, siz: 2 +Mode: 29 del: 2, siz: 3 +Mode: 29 del: 2, siz: 4 +Mode: 29 del: 3, siz: 1 +Mode: 29 del: 3, siz: 2 +Mode: 29 del: 3, siz: 3 +Mode: 29 del: 3, siz: 4 +Mode: 29 del: 4, siz: 1 +Mode: 29 del: 4, siz: 2 +Mode: 29 del: 4, siz: 3 +Mode: 29 del: 4, siz: 4 +Mode: 29 del: 5, siz: 1 +Mode: 29 del: 5, siz: 2 +Mode: 29 del: 5, siz: 3 +Mode: 29 del: 5, siz: 4 +Mode: 29 del: 6, siz: 1 +Mode: 29 del: 6, siz: 2 +Mode: 29 del: 6, siz: 3 +Mode: 29 del: 6, siz: 4 +Mode: 30 del: 0, siz: 1 +Mode: 30 del: 0, siz: 2 +Mode: 30 del: 0, siz: 3 +Mode: 30 del: 0, siz: 4 +Mode: 30 del: 1, siz: 1 +Mode: 30 del: 1, siz: 2 +Mode: 30 del: 1, siz: 3 +Mode: 30 del: 1, siz: 4 +Mode: 30 del: 2, siz: 1 +Mode: 30 del: 2, siz: 2 +Mode: 30 del: 2, siz: 3 +Mode: 30 del: 2, siz: 4 +Mode: 30 del: 3, siz: 1 +Mode: 30 del: 3, siz: 2 +Mode: 30 del: 3, siz: 3 +Mode: 30 del: 3, siz: 4 +Mode: 30 del: 4, siz: 1 +Mode: 30 del: 4, siz: 2 +Mode: 30 del: 4, siz: 3 +Mode: 30 del: 4, siz: 4 +Mode: 30 del: 5, siz: 1 +Mode: 30 del: 5, siz: 2 +Mode: 30 del: 5, siz: 3 +Mode: 30 del: 5, siz: 4 +Mode: 30 del: 6, siz: 1 +Mode: 30 del: 6, siz: 2 +Mode: 30 del: 6, siz: 3 +Mode: 30 del: 6, siz: 4 +Mode: 31 del: 0, siz: 1 +Mode: 31 del: 0, siz: 2 +Mode: 31 del: 0, siz: 3 +Mode: 31 del: 0, siz: 4 +Mode: 31 del: 1, siz: 1 +Mode: 31 del: 1, siz: 2 +Mode: 31 del: 1, siz: 3 +Mode: 31 del: 1, siz: 4 +Mode: 31 del: 2, siz: 1 +Mode: 31 del: 2, siz: 2 +Mode: 31 del: 2, siz: 3 +Mode: 31 del: 2, siz: 4 +Mode: 31 del: 3, siz: 1 +Mode: 31 del: 3, siz: 2 +Mode: 31 del: 3, siz: 3 +Mode: 31 del: 3, siz: 4 +Mode: 31 del: 4, siz: 1 +Mode: 31 del: 4, siz: 2 +Mode: 31 del: 4, siz: 3 +Mode: 31 del: 4, siz: 4 +Mode: 31 del: 5, siz: 1 +Mode: 31 del: 5, siz: 2 +Mode: 31 del: 5, siz: 3 +Mode: 31 del: 5, siz: 4 +Mode: 31 del: 6, siz: 1 +Mode: 31 del: 6, siz: 2 +Mode: 31 del: 6, siz: 3 +Mode: 31 del: 6, siz: 4 + + + +--------------------+ + | Total ERRORS: 0 | + +--------------------+ +***************************************************** +*** Test DONE ... *** +***************************************************** + + + + + +***************************************************** +*** Datapath 2 Test ... *** +***************************************************** + +Delay: 0 +Delay: 1 +Delay: 2 +Delay: 3 +Delay: 4 + + + +--------------------+ + | Total ERRORS: 0 | + +--------------------+ +***************************************************** +*** Test DONE ... *** +***************************************************** + + +Simulation complete via $finish(1) at time 3188770 NS + 0 +/home/rudi/bender_cores/wb_conmax/bench/verilog/test_bench_top.v:398 $finish; +ncsim> exit +ncsim: Memory Usage - 4.3M program + 4.5M data = 8.9M total +ncsim: CPU Usage - 0.2s system + 62.6s user = 62.8s total (64.5s, 97.3% cpu) Index: tags/start/sim/rtl_sim/run/ncwork/.inca.db.134.linux =================================================================== Index: tags/start/sim/rtl_sim/run/ncwork/inca.linux.134.pak =================================================================== --- tags/start/sim/rtl_sim/run/ncwork/inca.linux.134.pak (nonexistent) +++ tags/start/sim/rtl_sim/run/ncwork/inca.linux.134.pak (revision 3) @@ -0,0 +1,18068 @@ +ӵЉ凄Ɂݟ˅ؒѵ贡[ +|G>P3E)F!! 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P +P + H +H +NDQP +NH +NSRыFVËA$FPA(FdAF`^hVlZ[FhFFlFSR^h‹FP1؉FP1Vd FdtF`uS XHY[Y$Q(Z[VDV,JND BXFᐐNDNDYSRWЉщ߉ËG %FGFʉكЃ +^)t^u S{WG _Z[NDAF,H ND F,@X FᐐNDiVDV,JND BXFᐐNDi] U Ӊы !ʉUTB B ]U 1ى 3 ډa E E|H u H A ~UPB B ]U 1ى 3 ډ E E|H u H A NDiVDV,JND BXFᐐNDiU E   ى 0 Y  $*UPB B ] U$ 1ى 3 ډ E$ E |H u H A UTB B ] U$ 1ى 3 ډ E$ E |H u H A UXB B ] U$ 1ى 3 ډ E$ E |H u H A ~U\B B ] U$ 1ى 3 ډ E$ E |H u H A PND ND NDQ N NSRыFVËA$FPA(FdAF`^hVlZ[FhFFlFSR^h‹FP1؉FP1Vd FdtF`uS XHY[Y$Q(Z[VDV,JND BXFᐐNDNDFiypF,N,yH_ H F, h@@F,NDHFD jdždžNjF,xNDHFD NONG@BG FHNLW_ qV^FVDzV,JND QFH$QP$ JYXFᐐNDyiNDRSyN,INDF, XB [^[ZᐐNDyi] UO1ىO3W ډUEGE DH u H A dH u H A ]ڃUNDAF,H ND@ Mh;N,S?[ F, H ND X FᐐNDFiyF,N,yH_ H F, h@@F,NDHFD jdždžNjF,xNDHFD NONG@BG FHNLW_ qV^FVDzV,JND QFH$QP$ JYXFᐐNDyiNDRSyN,INDF, XB [^[ZᐐNDyi] UO1ىO3W ډUEGE DH u H A dH u H A ]ڃUNDAF,H ND@ ;N,S?[ F, H ND X Fᐐ#@.@@`(  @@@<@\@|A@AAAB$@B<BB<C@CDCCD@D <x\|(0<P<0|DD( D,@E4E# @`@.@}@JbHX- +@D1l 8L3K}PLj- +xD1 8N3M}PN0r- +0D1 HPCO}`P`zP`- +`D1t HRSQ}`R- +XE1 XTSS}pT- +E1$ hVcU}VXh- +E1| xXsW}X - + F1 xZY}]- PG1,$dd(cHbha`_^}d`x- `G1$kk8jXixhgfe}l- G1 $rr8qXpxonml}s +Xh- G1|$z(yHxhwvuts@ +D@@ 0- @ C} @ F -@ B.@ AO@ Xh-$@ hH-1@ B.4@ eO3@ -?@ I-F@ Ih:@ Ȃ؂h@ x,IDD@z8{||pFhHHZ#`ZpZp[ [4D 4DlD lDD PDD DLE LEE EE 0EE hEF Fz؅z z z0z Hz@,A ,APz z`\A \AzZ +'@@A0AHAkA[8[X[x[[[[[\;\]pzzzz {h{{{{{H|h||||(}H}h}}}~ˁìȽѴ)7(:,8094 @  ,W^{իxDDDDDDDDTEDDDDDDDDDDDDDDDTUUU @`!CJ0B@XB@BA8C0ACHAChA]]{,{2|8}>~؁ȁDZB ڃ щ!ˋ Љ щ!ˋ + , +, + ݉# ! P +P + H +H +L +Q艆( + +NDZB ڃ щ!ˋ Љ щ!ˋ + ( +( + ݉# ! P +P + H +H +NDQP +NH +NSRыFVËA$FPA(FdAF`^hVlZ[FhFFlFSR^h‹FP1؉FP1Vd FdtF`uS XHY[Y$Q(Z[VDV,JND BXFᐐNDNDL +L +Q艆D +$ +NDPZB ځ щ!ˋ Љ +щ!ˋ$ + D +D + ݉# +!P +H +L +Q艆@ + +NDTZB ځ щ!ˋ Љ +щ!ˋ + @ +@ + ݉# +!ۉ P +P + H +H +L +Q艆< + +NDXZB ځ щ!ˋ Љ щ!ˋ + < +< + ݉# ! P +P + H +H +L +Q艆8 + +ND\ZB ځ щ!ˋ Љ щ!ˋ + 8 +8 + ݉# ! P +P + H +H +L +Q艆4 + +ND`ZB ځ щ!ˋ Љ щ!ˋ + 4 +4 + ݉# ! P +P + H +H +L +Q艆0 + +NDdZB ځ щ!ˋ Љ щ!ˋ + 0 +0 + ݉# ! P +P + H +H +L +Q艆, + +NDhZB ځ щ!ˋ Љ щ!ˋ + , +, + ݉# ! P +P + H +H +L +Q艆( + +NDlZB ځ щ!ˋ Љ щ!ˋ + ( +( + ݉# ! P +P + H +H +NDQP +NH +NSRыFVËA$FPA(FdAF`^hVlZ[FhFFlFSR^h‹FP1؉FP1Vd FdtF`uS XHY[Y$Q(Z[VDV,JND BXFᐐNDNDPL +L +Q艆D +$ +NDZB ځ щ!ˋ Љ +щ!ˋ$ + D +D + ݉# +!P +H +L +Q艆@ + +ND ZB ځ щ!ˋ Љ +щ!ˋ + @ +@ + ݉# +!ۉ P +P + H +H +L +Q艆< + +ND$ZB ځ щ!ˋ Љ щ!ˋ + < +< + ݉# ! P +P + H +H +L +Q艆8 + +ND(ZB ځ щ!ˋ Љ щ!ˋ + 8 +8 + ݉# ! P +P + H +H +L +Q艆4 + +ND,ZB ځ щ!ˋ Љ щ!ˋ + 4 +4 + ݉# ! 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DT@Tx`ܰѧ! D@Xxָ̣!(` D@\xP  DT@x  +D@  +D@ D,ܹˢĽ䆆 D-D`pD-DpD (-DpDXH.D XApDh. D XAp D x*@@Ed* `pJ! ET@bxH!XE@fx !E@jxX Ϡ! +E@nx Ѿ!E@rx8 PET@` +`E@ +pE@E@E@!  Ev!  E z.E 8A.E XA+@8 H  +¦dz  Et X ~ܸ٭ E X F8*-PF }8*PF +@ +.PF XA-PF -PFXU PFP +` +-PF }8*PF + +-PF .PF `JPF + +8*`F - pF +pF @  `  .F XAwP - F }  +Fp  -F -FJF   FF3 F  0 P .F `w - F }  +F@  -F -FJFx   FF3 Fp  + +( +.F +w - F }  +F + +-F -FJFP +` + FF3 FȞp +x + +.F Bw +- F }  +F +`-F -FJF( FF3 F 8P.F w- F }  +F8-F -FJF FF3 Fxp.F w`- F }  +F-F -FJF FF3 FПHh.F @w(- F }  +FX-F -FJF FF3 F( @.F w- F }  +F0-F -FJFhx FF3 F G GS0% GxPERROR: Illegal Master %0d8d0% retsaM lagellI :RORRE-- G0GY&-pG}H +pG(.pG XA- G +G8h.G XAwx-G}H G. Gx0.G `w-G}H G X. Gp@.G +w-G}H G. G @.G Bw-G}H G0h. G.G w-G}H G. G0P.G w -G}H G@x. G@ .G @w-G}H G. G@`.H w0-H}H HP. H- +0H * +0H.@H XAw- @H } +@H-@H -@HJ@H@P-@HJ@H`p @H@H3 @Hؠ.PH `w- PH } +PH-PH -PHJPH(8-PHJPHHX PHPH3 PH0h.`H +w- `H } +`Hx-`H -`HJ`H -`HJ`H0@ `H`H3 `HPx.pH Bw- pH } +pH`-pH -pHJpH-pHJpH( pHpH3 pH8`.H w- H } +HH-H -HJH-HJH HH3 H8 H.H wp- H } +H0-H -HJH-HJH HH3 H0h.H @wX- H } +Hx-H -HJH-HJH HH3 HPp.H w@- H } +H`-H -HJH-HJH HH3 H@ Hh.H @w(- H } +HX-H -HJH-HJH HH3 H 0 P .H 0w - H } +H@  -H -HJHx  -HJH   HH3 H !!8!.H w!- H }H(!!-H -HJH`!p!-HJH!! HH3 HH!""0".H " w!- H }H ""-H -HJHX"h"-HJHx"" HH3 H"##(#.I # w"- I }I##-I -IJIP#`#-IJIp## II3 I#$$ $.I # +w#- I }I$$-I -IJIH$X$-IJIh$x$ II3 IP$%$%. I $w$- I } I%%- I - IJ I@%P%- IJ I`%p%  I I3  I%&%&.0I %w%- 0I }0I&&-0I -0IJ0I8&H&-0IJ0IX&h& 0I0I3 0Ix&&PI&'& `IS '0$`Ih'@'ERROR: Illegal Slave %0d0d0% evalS lagellI :RORRE-+`I &pIY)-I -I R I''*I0()( JS+0>J((3ERROR: Master[%0d][%0d]: %h - Slave[%0d]: %h (%0t)h)t0%( h% :]d0%[evalS - h% :]d0%[]d0%[retsaM :RORRE-J- +J -J -J -J 6&JX0(- + JP}( J)*- JP. J `J J)) +I'( PF +p + + + X 0hxz@ +J*$hp+Q!*x*J ɬ!H+x* +J*.J 8A.J XA+@++iȩݼ*x*J<+ +x*J+,p+KS0,0K++ + + + +-p+ KS4-0@ K,P,6*****************************************************p*****************************************************.p+0KS8.0@0K-P-6*** Arb. 1 Test ... ***p*** ... tseT 1 .brA ***/p+@KS<P00B@K.P.7***************************************************** +p +*****************************************************-`K*}dp+`K/8/.`K -pK*}dpKH//. +pK XA-pK*.pK UpK//-pK*}dpK/0-pK*.pK `JpK/0dKP00(0KS@x40KP00 Delay: %0dd0% :yaleD-K*81(0 Kٻ K K1(0 KH. +K 1p +Kh1.KHpK(1."K 1p"Kh1H`(0K20091Kh2,ݿıݩ KK32KT.K XA."K XA.(K 2]%K22JK22pK2.,KHp,K83-4K*p4Kp(3.7K p7KH3ٻ L +L52 +Ld.L 1pL@3.LHpLx3-%LH+p%L4-LH+.L 1R L 4045 Lx4h5P4 +0LSp<040L844(ERROR: RF read mismatch: Exp. 0, Got %hPh% toG ,0 .pxE :hctamsim daer FR :RORRE-:0LH+- @LP}P4 +@LX55-@LP.@L `J@L5562L@4P4,ݿעκ `L`L(72`Lx.`L X6."`L XA.(`L 2]%`L`6p6J`L@66p`LH6.,`LHp,`L6-4`L*p4`L6.7`L p7`L6 pLpL082pL.pL ."pL XA.(pL 2]%pLh7x7JpLX77ppL7.,pLHp,pL87-4pL*p4pLp7.7pL p7pL7 LL2L.L x80."L XA.(L 2]%L88JL`88pLH8.,LHp,L8-4L*p4L8.7L p7L9(@1Lp9 LL:09L(.L 9."L XA.(L 2]%L99JL99pL9.,LHp,L:-4L*p4L0:.7L p7L0P: LL;09Lh.L :."L XA.(L 2]%L::JL::pLȬ;.,LHp,L(;-4L*p4L8H;.7L p7Lph; L +L=09 +L.L 1pL;.LHpL8;-%LH+p%Lp<-LH+.L 1R L0<@<= M<x=`< +MSD04M8=<(ERROR: RF read mismatch: Exp. 0, Got %hPh% toG ,0 .pxE :hctamsim daer FR :RORRE-:MH+- MP}`< + Mh==- MP. M `J M==>09LP<`< @M@M(?09@M(.@M X> ."@M XA.(@M 2]%@M`>p>J@M@>>p@M>.,@MHp,@M>-4@M*p4@M>.7@M p7@M0> PMPM09PMh.PM p?0."PM XA.(PM 2]%PMx??JPMX??pPMȬ?.,PMHp,PM?-4PM*p4PM8?.7PM p7PMp@ G1Mh@ MMA(@M.M @."M XA.(M 2]%M@@JM@@pM@.,MHp,M@A-4M*p4Mx(A.7M p7MHA MMB(@M .M A."M XA.(M 2]%MAAJMAApMHB.,MHp,M B-4M*p4M@B.7M p7M`B MMC(@M.M B ."M XA.(M 2]%MBBJMBCpMC.,MHp,M@8C-4M*p4MxXC.7M p7MxC M +ME(@ +M(,.M 1pMC.MHpMD-%MH+p%M D-MH+.M 1R M@DPDE MDEpD +MS8L04M8ED(ERROR: RF read mismatch: Exp. 0, Got %hPh% toG ,0 .pxE :hctamsim daer FR :RORRE-:MH+- NP}pD +NxEE-NP.N `JNEE F(@M`DpD  N N(@ N@. N hF0." N XA.( N 2]% NpFFJ NPFFp NHF., NHp, NF-4 N*p4 NF.7 N p7 NG(N1PN`G `N`NxH G`N(P.`N G."`N XA.(`N 2]%`NGGJ`NGGp`NG.,`NHp,`NH-4`N*p4`N H.7`N p7`N0@H pNpNI GpNh`.pN H."pN XA.(pN 2]%pNHHJpNHHppNȳH.,pNHp,pNI-4pN*p4pN88I.7pN p7pNpXI NNJ GN(p.N I ."N XA.(N 2]%NIIJNIJpNJ.,NHp,N0J-4N*p4NPJ.7N p7N0pJ NNK GNh.N J0."N XA.(N 2]%NJKJNJKpNȳ(K.,NHp,NHK-4N*p4N8hK.7N p7NpK N +NN G +N.N 1pNK.NHpN8L-%NH+p%Np0L-NH+.N 1R NPL`LN NLML +NS e07NP0ML+ERROR: RF read mismatch: Exp. a5ff, Got %hXh% toG ,ff5a .pxE :hctamsim daer FR :RORRE-=NH+- NP}L +NMM-NP.N `JNMM GNpLLR1 OhN 0O0OO(N0O.0O N."0O `.(0O 2]%0ONNJ0ONNp0ON.,0OHp,0O@O-40O*p40Ox(O.70O p70OHO @O@OP(N@O.@O O."@O `.(@O 2]%@OOOJ@OOOp@OHP.,@OHp,@O P-4@O*p4@O@P.7@O p7@O`P POPOQ(NPO.PO P ."PO `.(PO 2]%POPPJPOPQpPOQ.,POHp,PO@8Q-4PO*p4POxXQ.7PO p7POxQ `O`O(N`O.`O Q0."`O `.(`O 2]%`ORRJ`OQ Rp`OH0R.,`OHp,`OPR-4`O*p4`OpR.7`O p7`OR8W1OR OOTRO(.O 8S."O `.(O 2]%O@SPSJO S`SpOpS.,OHp,OS-4O*p4OS.7O p7O0S OO UROh.O PT."O `.(O 2]%OXThTJO8TxTpOȹT.,OHp,OT-4O*p4O8T.7O p7OpT OO8VRO(.O hU ."O `.(O 2]%OpUUJOPUUpOU.,OHp,OU-4O*p4OU.7O p7O0V OOROh.O V0."O `.(O 2]%OVVJOhVVpOȹV.,OHp,OV-4O*p4O8V.7O p7OpW[1PxW PPX8WP$.P W.#P %.)P 2]&PWWJPWWpPW.-PHp-P@X-5P*p5Px8X.8P p8PXX  P PY8W P4. P X.# P %.) P 2]& PXXJ PXYp PHY.- PHp- P0Y-5 P*p5 PPY.8 P p8 PpY 0P0PZ8W0PD.0P Y .#0P %.)0P 2]&0PYZJ0PYZp0P(Z.-0PHp-0P@HZ-50P*p50PxhZ.80P p80PZ @P@P8W@PT.@P [0.#@P %.)@P 2]&@P[ [J@PZ0[p@PH@[.-@PHp-@P`[-5@P*p5@P[.8@P p8@P[1pP\ PP][P(d.P H\.#P %.)P 2]&PP\`\JP0\p\pP\.-PHp-P\-5P*p5P\.8P p8P0\ PP0^[Pht.P `].#P %.)P 2]&Ph]x]JPH]]pPȾ].-PHp-P]-5P*p5P8].8P p8Pp] PPH_[P(.P x^ .#P %.)P 2]&P^^JP`^^pP^.-PHp-P^-5P*p5P^.8P p8P0_ PP[Ph.P _0.#P %.)P 2]&P__JPx__pPȾ_.-PHp-P_-5P*p5P8`.8P p8Pp(``(0P .P XApP`x`. +P XAp +P`. +P X6p +P`ha(0Q .Q `pQ`a. +Q XAp +Q(a. +Q X6p +QHaa(0Q .Q +pQ`a. +Q XAp +Qa. +Q X6p +Qab(0 Q . Q Bp Q`(b. + Q XAp + QHb. + Q X6p + Qhbc(00Q .0Q p0Q`b. +0Q `p +0Qb. +0Q X6p +0Qbc(0@Q .@Q p@Q`Hc. +@Q `p +@Qhc. +@Q X6p +@Qc8d(0PQ .PQ @pPQ`c. PQ %p PQc.PQ X6pPQd(0`Q .`Q p`Q`hd. `Q %p `Qd.`Q X6p`Qddp+pKX///(0 ep+ Q fp+QS f0@Qepe6*****************************************************p***************************************************** gp+QS g0@Qfpf6*** Test DONE ... ***p*** ... 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[ L& [J [p [ȗ.- [Hp- [8-5 [hp5 [p-: [hp: [(- 0[h-0[@k0[X|0[hj0[hxؘ`0[Hx @[@[ `@[l.@[ XA-$@[h.)@[ @L&@[(J@[8p@[HH.-@[Hp-@[h-5@[hp5@[-:@[hp:@[- P[h-P[@kP[ؙ| P[|jP[X`P[ș `[`[p``[.`[ XA-$`[h.)`[ #L&`[J`[p`[Ț.-`[Hp-`[8-5`[hp5`[p-:`[hp:`[(.p[ XA3p[iH}`p[X6 +p[X0h0[#8- [h-[@k[|8[j[p[ [[x[h.[ 9p[Ȭ.-[Hp-[-5[hp5[8-:[hp:[p- [h-[@k[0|x[j[@P[ P [[[(.[ 9-$[h.)[ L&[J[p[ .-[Hp-[@-5[hp5[`-:[hp:[0- [h-[@k[|[j[О0[О \\x\h.\ 9-$\h.)\ @L&\pJ\`p\Ȭ.-\Hp-\-5\hp5\8-:\hp:\p- \h-\@k\0|x\j\@P\ P  \ \ȡ \(. \ 9-$ \h.) \ #L& \J \p \ .- \Hp- \@-5 \hp5 \`-: \hp: \0.0\ `30\i}0\6 +0\XH0hh0`\%- p\h-p\@kp\H|p\jp\XhȢp\8h \\У\.\ @p\H.-\Hp-\-5\hp5\8-:\hp:\X- \h-\@k\|У\j\\x \\P\.\ @-$\h.)\ L&\HXJ\8hp\x.-\Hp-\@-5\hp5\x-:\hp:\ؤ- \h-\@k\|P\j\(\( \\Ц\ .\ @-$\h.)\ @L&\ȥإJ\p\H.-\Hp-\-5\hp5\8-:\hp:\X- \h-\@k\|Ц\j\\x \\ \ .\ @-$\h.)\ #L&\HXJ\8hp\x.-\Hp-\@-5\hp5\x-:\hp:\ا.\ +3\i}\H6 +\X0h0 ]'- 0]h-0]@k0]|0]0j0] h0] @]@](h@]h4.@] Gp@]ȳP.-@]Hp-@]p-5@]hp5@]8-:@]hp:@]p- P]h-P]@kP]|(P]DjP]`hP]Щ `]`]h`](H.`] G-$`]h.)`] L&`]J`]p`]Ъ.-`]Hp-`]-5`]hp5`]-:`]hp:`]00- p]h-p]@kp]`|p]Xjp]php]P ]](h]h\.] G-$]h.)] @L&] 0J]@p]ȳP.-]Hp-]p-5]hp5]8-:]hp:]p- ]h-]@k]|(]lj]`h]Ь ]]xh](p.] G-$]h.)] #L&]J]p]Э.-]Hp-]-5]hp5]-:]hp:]00.] B3]iP}h]`6 +]X0h0])@- ]h-]@k]|@]j]x] ^^^.^ Np^H.-^Hp-^ȯ-5^hp5^-:^hp:^- ^h-^@k^8|^j^HX^(X  ^ ^ ^. ^ N-$ ^h.) ^ L& ^J ^p ^(.- ^Hp- ^@H-5 ^hp5 ^xh-: ^hp: ^- 0^h-0^@k0^|0^j0^ȱر80^ر @^@^@^.@^ N-$@^h.)@^ @L&@^xJ@^hp@^H.-@^Hp-@^Ȳ-5@^hp5@^-:@^hp:@^- P^h-P^@kP^8|P^jP^HXP^(X `^`^д`^.`^ N-$`^h.)`^ #L&`^J`^p`^(.-`^Hp-`^@H-5`^hp5`^xh-:`^hp:`^.p^ 3p^i}p^6 +p^XP0hp0^+- ^h-^@k^P|^j^`pе^@p ^^ض^(.^ 8Sp^.-^Hp-^ -5^hp5^@-:^hp:^0`- ^h-^@k^|ض^j^^ ^^X^h.^ 8S-$^h.)^ L&^P`J^@pp^ȹ.-^Hp-^-5^hp5^8-:^hp:^p- ^h-^@k^|X^j^ 0^0 __ع_(._ 8S-$_h.)_ @L&_иJ_p_.-_Hp-_ -5_hp5_@-:_hp:_0`- _h-_@k_|ع_ j__  _ _( _h. _ 8S-$ _h.) _ #L& _P`J _@pp _ȹ.- _Hp- _-5 _hp5 _8-: _hp: _p.0_ 30_i}0_P6 +0_X0h0`_-- p_h-p_@kp_|p_ jp_Ȼ(pp_Ȼ __0p_$._ Wp_X.-_Hp-_@x-5_hp5_x-:_hp:_- _h-_@k_|0_4j_hp_ؼ __p_8._ W-$_h.)_ L&_J_Ƚp_Hؽ.-_Hp-_-5_hp5_-:_hp:_8- _h-_@k_h|_Hj_xp_X __0p_L._ W-$_h.)_ @L&_(8J_Hp_X.-_Hp-_@x-5_hp5_x-:_hp:_- _h-_@k_|0_\j_hp_ؿ __p_`._ W-$_h.)_ #L&_J_p_H.-_Hp-_-5_hp5_-:_hp:_8._ @3_iX}p_h6 +_X0h0 `/H- 0`h-0`@k0`|H0`pj0` 0`  @`@`@`(t.@` H\p@`.-@`Hp-@`-5@`hp5@`-:@`hp:@`0- P`h-P`@kP`@|P`jP`P`P`0` ``````h.`` H\-$``h.)`` L&``J`` p``Ⱦ0.-``Hp-``P-5``hp5``8p-:``hp:``p- p`h-p`@kp`|p`jp`@p` ```(.` H\-$`h.)` @L&`J`pp`.-`Hp-`-5`hp5`-:`hp:`0- `h-`@k`@|`j`P``0` ```h.` H\-$`h.)` #L&`J` p`Ⱦ0.-`Hp-`P-5`hp5`8p-:`hp:`p.` 3`i}`6 +`X0hqa .a XApa`P. +a XAp +ap-ah.a Lapaqa .a `pa`. +a XAp +a -ah.a La@Ppa`0q a . a +p a`. + a XAp + a- ah. a L ap aq0a .0a Bp0a``. +0a XAp +0a-0ah.0a L0ap0aq@a .@a p@a`. +@a XAp +@a0-@ah.@a L@aP`p@ap@qPa .Pa pPa`. +Pa XAp +Pa-Pah.Pa LPapPa q`a .`a @p`a`p. +`a XAp +`a-`ah.`a L`ap`aqpa .pa ppa` . +pa XAp +pa@-pah.pa Lpa`pppa-ai}a.a XA- ai. a @U +a- +ai}ap-ai.a `JaP`-aHi}a.a XA- aHi. a @U +a- +aHi}aP-aHi.a `Ja0@-ai3ai`-aHi3 +aiU ap-ai3aPj- aHi3aPjVaYa-)ai3'aPj0-1aHi3/aPjXP-a@hY$a h a +aS 0;apP/ERROR: Master %0d compleated before Master %0d`d0% retsaM erofeb detaelpmoc d0% retsaM :RORRE->ai-AaHi +aS,0,aH  M[%0d] pri: %0d (t: %0t)@)t0% :t( d0% :irp ]d0%[M -/ai-4ai32aPj-:ai38ai +aS<0,a`8 M[%0d] pri: %0d (t: %0t)@)t0% :t( d0% :irp ]d0%[M -/aHi-4aHi32aPj-:aHi38ai- bP} +bX-bP.b `Jb8Haahqa(PSpq(qq0@So(pHpXxj0SnHohoxj @bxjPbSL0@Pb6*****************************************************p*****************************************************xj`bSP0@`b6*** Test DONE ... ***p*** ... ENOD tseT ***xjpbST0Dpb8***************************************************** + +p + +***************************************************** hPji(x*@ bhM j!(c O.c B.c XA+@W P cSxc Zct^(cܓbPcDfxcj@#cn'c|r0chPcSX0Pc + + + +h`cS\0@`cH6*****************************************************p*****************************************************hpcS`0@pcH6*** Datapath 1 Test ... ***p*** ... tseT 1 htapataD ***hcSdp0BcH7***************************************************** +p +*****************************************************-c(}Phc0.c XA-cP}hc@x.c `-cx}hc.c +-c}(hc.c B-c}phcP.c -c}hc`.c -d}hd.d @-d@} hd(.d -0d} 0d8p.0d XA-0d. 0d X6U 0d- +0d} 0d-0d.0d `J0d @d@p Pd`dSh +0`dH +Mode: %0dd0% :edoM-`dpd0xdp ddx0dp.d XA-#d(.)d 2]&dJdpdH.-dHp-d.3d XAp3d .6d p6d@ dd0d.d X6-#d(.)d 2]&dJdpd.-dHp-d8.3d XAp3dp(.6d p6dH dd0d.d -#d(.)d 2]&dJdpdH.-dHp-d.3d XAp3d0.6d p6dP dd0d.d x8-#d(.)d 2]&dJdpd.-dHp-d8.3d XAp3dp8.6d p6dXe  e ex e(. e 9-# eP.) e 2]& eJ ep e(.- eHp- eH.3 e XAp3 eh.6 e p6 e0 0e0ex0eh.0e :-#0eP.)0e 2]&0eJ0e p0eȬ0.-0eHp-0eP.30e XAp30e8p.60e p60ep @e@ex@e(.@e X>-#@eP.)@e 2]&@eJ@e(p@e8.-@eHp-@eX.3@e XAp3@ex.6@e p6@e0 PePexPeh.Pe p?-#PeP.)Pe 2]&Pe JPe0pPeȬ@.-PeHp-Pe`.3Pe XAp3Pe8.6Pe p6Pepe eee.e @-#ex.)e 2]&e@PJe0`peHp.-eHp-e.3e XAp3e.6e p6e eee.e A-#ex.)e 2]&eHXJe8hpex.-eHp-e@.3e XAp3ex.6e p6e eee.e B-#ex.)e 2]&eP`Je@ppeH.-eHp-e.3e XAp3e.6e p6e eee .e hF-#ex.)e 2]&eXhJeHxpe.-eHp-e@.3e XAp3ex.6e p6ePeH ffPf(0.f G-#f.)f 2]&fJfxpf.-fHp-f.3f XAp3f.6f p6f0 ffXfh@.f H-#f.)f 2]&fJfpfȳ.-fHp-f.3f XAp3f8.6f p6fp   f f` f(P. f I-# f.) f 2]& fJ fp f.- fHp- f.3 f XAp3 f.6 f p6 f0( 0f0f0fh`.0f J-#0f.)0f 2]&0fJ0fp0fȳ.-0fHp-0f.30f XAp30f8.60f p60fp0`f pfpfPpfp.pf N-#pf.)pf 2]&pfJpfppfH.-pfHp-pf .3pf XAp3pf@.6pf p6pf` ffPf.f O-#f.)f 2]&fJfpf.-fHp-f@(.3f XAp3fxH.6f p6fh ffPf.f P-#f.)f 2]&fJfpfH.-fHp-f0.3f XAp3fP.6f p6fp ffPf.f Q-#f.)f 2]&fJfpf.-fHp-f@8.3f XAp3fxX.6f p6fxf fffh.f 8S-#f.)f 2]&f(Jf8pfȹH.-fHp-fh.3f XAp3f8.6f p6fp fff(.f PT-#f.)f 2]&f 0Jf@pfP.-fHp-fp.3f XAp3f.6f p6f0 gggh.g hU-#g.)g 2]&g(8JgHpgȹX.-gHp-gx.3g XAp3g8.6g p6gp ggg(.g V-#g.)g 2]&g0@Jg Ppg`.-gHp-g.3g XAp3g.6g p6g0(@g  PgPg(Pg.Pg W-#Pg.)Pg 2]&Pg`pJPgPpPg.-PgHp-Pg@.3Pg XAp3Pgx.6Pg p6Pg `g`g0`g.`g X-#`g.)`g 2]&`ghxJ`gXp`gH.-`gHp-`g.3`g XAp3`g.6`g p6`g pgpg8pg.pg Y-#pg.)pg 2]&pgpJpg`ppg.-pgHp-pg@.3pg XAp3pgx.6pg p6pg ggg .g [-#g.)g 2]&gxJghpgH.-gHp-g.3g XAp3g.6g p6ggh ggp(g(0.g H\-#g@.)g 2]&gJgpg.-gHp-g.3g XAp3g.6g p6g08 ggx(gh@.g `]-#g@.)g 2]&gJgpgȾ.-gHp-g.3g XAp3g8 .6g p6gp@ gg(g(P.g x^-#g@.)g 2]&gJgpg.-gHp-g.3g XAp3g(.6g p6g0H gg(gh`.g _-#g@.)g 2]&gJgpgȾ.-gHp-g.3g XAp3g80.6g p6gpP@h p.@h XAp@h`- @h(p @h.@h X6p@hPh |.Ph `pPh`0- PhPp PhP.Ph X6pPhp `h .`h +p`h`- `hxp `h.`h X6p`hph .ph Bpph`P- php php.ph X6pph@h .h ph`- hp h.h X6ph h .h ph`p- hp h.h X6ph`h .h @ph`- hp h .h X6ph@ h .h ph`- h@p h.h X6ph- +h@k h|H hjh  -h(} h8  -h(. h `J hp  -iP} +i  -iP. i `J i  -ix} +i +` +-ix. i `J i@ +P +- i} + ip + +- i. i `J i + +-0i}P 0i +0 -0i. 0i `J 0i  -@i} @i@  -@i. @i `J @ix  -Pi} Pi  -Pi. Pi `J Pi  -`i@} `i h -`i@. `i `J `iH X - +i@k ix |iji   h0dH +h ihiS0@i +h +6*****************************************************p*****************************************************hiS0@ih6*** Test DONE ... ***p*** ... ENOD tseT ***hiS0Dih8***************************************************** + +p + +***************************************************** @40h@ @jX3` o!( +`j* !X( pj !( +pj !(pj !H(pj !x(pjD !(pjt !(!pj !8H(%pj.j B.j XA+@4( +jdh (j`jS0j + + + +`jS0@j@6*****************************************************p*****************************************************`jS0@j@6*** Datapath 2 Test ... ***p*** ... tseT 2 htapataD ***`jSp0Bj@7***************************************************** +p +*****************************************************-kX}0`k(.k XA- kX}0 k8p. k XA- kX. k U + k- kX}0 k- kX. k `J k00k@p @kPkS00PkP Delay: %0dd0% :yaleD-PkXx0pk0k-k}kX. k XA- k.k X6U +k-k}k(-k.k `Jk kkk.k XA.$k XA-'kJ%k..k 2]+kJ k-5k.8k ]7kJ1kp1k .-p84.p `Jp==-p`40Dp>@>p?`>>.p XAwP>  pp >p.p 1-#p84.(p +]&p>>J p>>p p8>.,pHp,pp?-8p8436p58?p6pH?@??.p `w?  pp >p.p 1-#p84.(p +]&p?@J p?@p p8(@.,pHp,ppH@-8p8436p5h@p6px@A@@.p +w@  pp >p.p 1-#p84.(p +]&p(A8AJ pAHAp p8XA.,pHp,ppxA-8p8436p5Ap6pACAB.p BwA  pp >p.p 1-#p84.(p +]&pXBhBJ pHBxBp p8B.,pHp,ppB-8p8436p5Bp6pB CHC.q wC  qq >q.q 1-#q84.(q +]&qCCJ qxCCp q8C.,qHp,qpC-8q8436q5Cp6qDXK:p@=== >-0q84}XK0qXDD.0q XA- 0q84. 0q X6U +0qDD-0q84}XK0qD(E-0q84.0q `J0qEE-@q`4XK@q8EhEFEE.Pq XAwxE  PqPqHEPq.Pq 1-#Pq84.(Pq +]&PqEFJ PqEFp Pq8 F.,PqHp,Pqp@F-8Pq8436Pq5`Fp6PqpFGFF.`q `wF  `q`qHE`q.`q 1-#`q84.(`q +]&`q G0GJ `qG@Gp `qPG.,`qHp,`q8pG-8`q8436`q5Gp6`qpGHGH.pq +wG  pqpqHEpq.pq 1-#pq84.(pq +]&pqPH`HJ pq@HpHp pq8H.,pqHp,pqpH-8pq8436pq5Hp6pqH(JI@I.q BwI  qqHEq.q 1-#q84.(q +]&qIIJ qpIIp q@I.,qHp,qxI-8q8436q5Ip6qJHJpJ.q w8J  qqHEq .q 1-#q84.(q +]&qJJJ qJJp q8J.,qHp,qpK-8q8436q5 Kp6q0KO:0qhDDDHE-q84}OqKK.q XA- q84. q X6U +qKK-q84}OqKPL-q84.q `Jq0L@LOqL-q 6}L`LqLL-q843 +q5L-qX6}N`LqL0M-q843 +q5 M-r 6-rX6R rHMXMN rMxM + rS,O0A r0NM5ERROR: RF[%0d] Mismatch. Expected: %h, Got: %h (%0t)h)t0%( h% :toG ,h% :detcepxE .hctamsiM ]d0%[FR :RORRE-0r84- 0rX6-0r 660rXM4`LrhMxM:qKKL`L`O60p :x:::O6 rP6rS@P0@r PO6*****************************************************p*****************************************************Q6rSDQ0@r QP6*** Test DONE ... ***p*** ... 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B    B g\MERROR: Illegal Master g O/home/rudi/bender_cores/wb_conmax/bench/verilog/tests.v:146 $finish; +   B    B    B    B gXPERROR: Illegal Slave g Q/home/rudi/bender_cores/wb_conmax/bench/verilog/tests.v:182 $finish; +g<RERROR: Master[g pR][gR]: g(R - Slave[gR]: g R (gR)"8OPOhO O# +O; OSOkO OWZX P&xPPPFPP"Pf$Q& Q&)8Q+PQ-hQF0Q2Q5Qf7Q9Q; QX;W;Z9<XV< R= xRY=W=Z> RR>W>Z> R2?W?^? R@W@Z@ R +AWA^A RAWYBpBaC RNCWCX%` 0  0 `; ; @< < `= `= (X> `> 88? `? H@ `@ XA `A hA ``B B TC `C Dpg R + +gU*****************************************************gU*** Arb. 1 Test ... ***gU***************************************************** +g (VDelay: !xyV!8ط0yHyW!xyyHW!(yyW! @zxzW!({8{X!0p{{HX!`||]gpV*****************************************************gX*** Test DONE ... ***gX***************************************************** + +" . UnWX U&WX UW9XV 0VWX0 xVpWZYXyBHVnVWHWWW6X^HX$@B@B*@Bv@B@B @Bo @B @BP +Ah + X +W X" Xb W X Y Wu X%xt  , 0  0@  0 x  ` PP8@PH P ;Ph!P!P", P# P# P8$a +P$ + P% h P& P'| pyg Y + +g[*****************************************************g[*** Arb. 2 Test ... ***g \***************************************************** +gh\Mode: g\ del: g \, siz: r!ȁ H}0}H]!p{ 0}}]!u ~0~]!n ~~^!hh 0H^!b ^![ (0^!`U 5hhRg<\ERROR: Master gl_ compleated before Master g(8_ M[g `_] pri: gx_ (t: g_)g(_ M[g _] pri: g_ (t: g_)g`*****************************************************g`*** Test DONE ... ***gX`***************************************************** + +"X . [nWX [&WX (\W9XV p\WXrB \WWZr \W?ZZ \W'ZXI]f]]]]]] +]']?]\]y]]]]] ]" ]? ]\ ]t ] ] ] ] ] +] +]: +]R +]j +] +] +] +] +] +] ] ]9 ]V ]s ] ] ] ] ] ] ]/ ]G ]_ ]w ] ] ] ] ] ] +]. +]F +]^ +]{ +] +] +] +] +] +])]]H]]B]j^H^^^B@B@B7@B@B/@B@B'@B@B6_f#]% _%Ww&Z& @_&WM'Z'X' h_(W(Z( _(W)[) _)W-a*- _j-W-X- _".W.Z. _.W/[/ _0W3a.3 `n3W3X5A5 `86W6X6 ``6WM7Xj7 `7W8X%t * , 8+  8,@  8- P1 2\ 2 2D 2 2, 2 PS@ UF@0USP PЈHPP0@PP8P@P& |& & T' ' ( ( ( ) ) - Вp- - (. . / / 0 3 t3 3 5PX@6 6 6 T7 7  8 @8p1(g ` + +ghg*****************************************************gxg*** Datapath 1 Test ... ***gg***************************************************** +ghMode: !(hB h! 0GPhh!!K(i!P"Phi!#U(@i!$PZpi!x%_Ђ(j!0&cngPh*****************************************************ghj*** Test DONE ... ***gj***************************************************** + +" . pgnWX g&WX gW9XV hWXB XhWZXThhzhh(ihiiBij(j0@B@@B@B0 @B @B +@B +@B @BEA\ pjWX jVWX kWiX%|t  , (  (@  ( P@   @PpQPPA P  P1 +P@ +P! P` @(6@VP H \ H  Hp pg j + +gm*****************************************************gm*** Datapath 2 Test ... ***gn***************************************************** +g PnDelay: !X',QhH`n!(,Qkx0o!(),QHopo!*,Qr؃o!+,Qu o!`,,QPy8P0p!-,Q|hpp!0.(Agn*****************************************************gp*** Test DONE ... ***gp***************************************************** + +" . mnWX m&WX nW9XV XnWX.BD nWZmXnn&0oNpovoo0pppB~ A p W1 +XN + q +W +X HqF W X%Xt  ,   @   ?P@  t R@!P@ P (8 + + ( + L ( p)g @q + +gxs*****************************************************gs*** Register File Test ... ***gs***************************************************** +gtMode: 2 R g,`tERROR: RF[g\t] Mismatch. Expected: g t, Got: g t (gt)gu*****************************************************gu*** Test DONE ... ***gXu***************************************************** + +" . snWX s&WX sW9XV tWX ht_WZEXS&ttt +ti t@tt8ttttJ tW +Z& tfW^ tNW^ t6Wp'aB uWXA uW=XZ `uWX uRWX%t  , @  @@  @ d H L  P P Pm +PP@PP8P@  + l + T + < + ,  + P` D   X  p "$P%]PPlP0PH@"$P8%]PxPlPP@8"$P%]PPlP P8@"$P(%]PhPlPP@(guERROR: RF read mismatch: Exp. a5ff, Got "$P  zWi^X%$]P`PxlP P +GP  p + @ gzERROR: RF read mismatch: Exp. 0, Got "$P(& zfW^=X%$]PhPlPPl  hD P @(gzERROR: RF read mismatch: Exp. 0, Got "$P0 {WY^X%$]PpP7P ` X sPP(@0g{ERROR: RF read mismatch: Exp. 0, Got "$P P|RW^)X%$[PhPX  H0 PlP(P0@"$PȁH pt _%(@85Pd@xP@TP@ @x +PP @ȁ"$Pp{H pt _%(@{5P(|d@ }Ph}@~TP~ @  +PhP @p{"$PuH pt _%(@u5Pud@vPw@HxTPx @y +PzP @u"$PnH pt _%(@0o5Pxod@ppPp@qTP8r @ps +PsP @n"$PhhH pt _%(@h5P id@jP`j@kTPk @m +P`mP @hh"$PbH pt _%(@b5Pbd@cPd@@eTPe @f +PgP @b"$P[H pt _%(@(\5Pp\d@h]P]@^TP0_ @h` +P`P @["$P`U, pX _%(@U0PV`@WPXW@X@PXp @Z +PXZ4 @`U"$P(%PhUPpPxP@("$P%P UP(P0P8@"$P%PطUPPP@"$PP%PUPPP@P"$P%PHUPPPXP`@"$P%PUPPP@"$Px%PUPPȨPЩ@x"$P0%PpJPxPP@0"$PX%PxL@X"$P%PL@"$P(%PHL@("$P%PL@"$P%PL@"$P`%PL@`"$P%PL@"$P0%PP<@00#R(@`@NDijdždžǍGsn OOQ_ +SFFON ^F@PFDPFPF PFPFPFDdže hYdžFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@EG]W ڃ0UUH u H A U UE iU UD1"ExH u H A 1 t+UHi @u i M u]E<UUH1 t+UHi @u i M u]XND;AARNDQ t2AJIȋH9uJH B R uZUDSR Y AÉڋۍ[u +^DSQ KYPQZ[] ډGW؉у ȉGVDzV,JND BXFᐐNDyi] ډG W ؉у ȉGG1)ˋW1)ѹʉ ىOOW1ʉ1Ƀʋ_!ӋOO>[tAGӃ WLQp1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]AGӃ WLQ1 t+UHi @u i M u]$AGӃ WLQ 1 t+UHi @u i M u]4AGӃ WLQ01 t+UHi @u i M u]DAGӃ WLQ@1 t+UHi @u i M u]TAGӃ WLQP1 t+UHi @u i M u]dAGӃ WLQ`1 t+UHi @u i M u]@BGFHNL_qV^FVDzV,JND QFH$QP$ JYXFᐐNDyiE<UUH1 t+UHi @u i M u]XND;AARNDQ t2AJIȋH9uJH B R uZUDSR Y AÉڋۍ[u +^DSQ KYPQZ[] ډGW؉у ȉGVDzV,JND BXFᐐNDyi] ډGW؉у ȉG G1)ˋW 1)ѹʉ ىOO W1ʉ1Ƀʋ_!ӋO O>ZFVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@nX +FᐐnXFᐐnXFᐐnXFᐐnXFᐐdXND;AARNDQ t2AJIȋH9uJH B R uZUDSR Y AÉڋۍ[u +^DSQ KYPQZ[] ډGW؉у ȉGVDzV,JND BXFᐐNDyi] ډGW؉у ȉG G1)ˋW 1)ѹʉ ىOO W1ʉ1Ƀʋ_!ӋO O>ZŒdžFX FS?[RNDQ At2AJIȋH9uJH B R uZNDAF,H ND S,^,C,C[X FᐐNDidž @KLdž FHNL qV^FVDV,JND QFH$QP$ JYXFᐐNDiE 艆 ҉   ى 3  E FP)ȉwFPË FP)ȉwFP‰ ى # Ӌ ډUD1 "ExH u H A 1 t+UHi @u i M u]3NDiVDV,JND BXFᐐNDiӉ艆4 +0 +艆, +4 +!ى( +, +ы0 +!ˋ, + 4 +$ +( + ډ#$ +L +$ + ӹ +艆 +L +!ى + +ы +!ˋ + L + + + ډ# +H + + ӹ +艆 +H +!ى + +ы +!ˋ + H + + + ډ# +D + + ӹ +艆 D +!ى ы +!ˋ D + ډ# @ + ӹ 艆 @ +!ى ы !ˋ @ + ډ# < + ӹ 艆 < +!ى ы !ˋ < + ډ# 8 + ӹ 艆 8 +!ى ы !ˋ 8 + ډ# Ӌ щ!ʉRE ] ڃUUH u H A ]E ڃ ظ щ 1ى 3 ڃ E EH u H A NDiVDV,JND BXFᐐNDiE ] )Ⱥ؃ щ!ʉzFVF@PFDPFPFPFDdžX hYdžFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@ŒdžFX FND\ՉNDQSRWى׉ËG %FGFʉكЃt +^)t^u S{WG _Z[VDV,JND BXFᐐND`NDDՉNDQSRWى׉ËG %FGFʉكЃt +^)t^u S{WG _Z[VDV,JND BXFᐐND` FGFGFVF@PFDPFPFPFDdžX hYdžFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@]U  QF NF FF@PFDPFPF PFPFPFDdž[ hYdžFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@FVF@PFDPFPFPFDdžX hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@ FDxX Fᐐjdždž8NjFGFGShnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDi$SnhH X +FᐐNDiDS(nhH X +FᐐNDidSHnhH X +FᐐNDiShnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDiSnhH X +FᐐNDi$SnhH X +FᐐNDiDS(nhH X +FᐐNDidSHnhH X +FᐐNDihnhH XFᐐNDixnhH XFᐐNDinhH XFᐐNDinhH XFᐐNDinhH XFᐐNDinhH XFᐐNDinhH XFᐐNDinhH XFᐐNDiOoS?[X Fᐐjdždž8NjFGFG $ nX FᐐOoS?[X Fᐐ FGFG40  ً !؃ щ!ʉC    Y  4Ld| + 0  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A  +A + +A +  ى  + Ӌ + ى + +Q +A  +A + +A +  ى + Ӌ + ى  +  + ډ< 8 0  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A + +A + +A + + ى  + Ӌ + ى + +Q +A  +A  +A +  ى  Ӌ + ى  +  + ډ< 80  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A  +A + +A +  ى  + Ӌ + ى + +Q +A  +A + +A +  ى + Ӌ + ى  +  + ډ< 8 0  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A + +A + +A + + ى  + Ӌ + ى + +Q +A  +A  +A +  ى  Ӌ + ى  +  + ډ< 8 0  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A  +A + +A +  ى  + Ӌ + ى + +Q +A  +A + +A +  ى + Ӌ + ى  +  + ډ< 80  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A + +A + +A + + ى  + Ӌ + ى + +Q +A  +A  +A +  ى  Ӌ + ى  +  + ډ< 80  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A  +A + +A +  ى  + Ӌ + ى + +Q +A  +A + +A +  ى + Ӌ + ى  +  + ډ< 80  Ӌ ظ‰ ى +Ѓ  + + ȉ  + + +! ى + +ٹы +!ȉ SR1ۉZ[ʉЉ + + +A + +A + +A + + ى  + Ӌ + ى + +Q +A  +A  +A +  ى  Ӌ + ى  +  + ډ< 8xFVF@PFDPFPFPFDdžX hY +džFFDF@  BFVF FF@PFDPFPF PFPFPFDdž[ hY džFFDF@FF +F@PFDPFPFPFDdžY hY +džFFDF@ŒdžFX F,(   Y  4Je,(,@(,(,(g,(L,@(1,(,(  q& b& Y  Tt 4 Tt4!#0 ( , ʉظ + + щ $ Љ  + ډظÉ  +؃  + + ȉ  + + +! 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tags/start/sim/rtl_sim/run/ncwork/cds.lib (nonexistent) +++ tags/start/sim/rtl_sim/run/ncwork/cds.lib (revision 3) @@ -0,0 +1 @@ +DEFINE work ../ncwork Index: tags/start/sim/rtl_sim/run/ncwork/hdl.var =================================================================== --- tags/start/sim/rtl_sim/run/ncwork/hdl.var (nonexistent) +++ tags/start/sim/rtl_sim/run/ncwork/hdl.var (revision 3) @@ -0,0 +1,30 @@ +#***************************************************************************** +# NCSIM hdl.var template * +#***************************************************************************** + +#This file allows commonly used tool setups to be invoked automatically. +#All the switches may be alternatively specifed on the command line. + +#reference the tool installation hdl.var - DO NOT REMOVE + +INCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var + +# These are default settings for NCVLOG, NCVHDL, NCELAB, NCSIM +# See below for commonly used switches. + +DEFINE NCVLOGOPTS -NOCOPYRIGHT -UPDATE +DEFINE NCVHDLOPTS -NOCOPYRIGHT -UPDATE +DEFINE NCELABOPTS -NOCOPYRIGHT +DEFINE NCSIMOPTS -NOCOPYRIGHT -NOKEY -STATUS + +#Maps the work library to a logical library. +#This library will contain the compiled design units +#Can be overriden on the command line with -work +#DEFINE WORK work +DEFINE work ../ncwork + +# Define valid Verilog file extensions +DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg) + +# Define valid VHDL file extensions +DEFINE VHDL_SUFFIX (.vhd, .vhdl) Index: tags/start/sim/rtl_sim/run/waves/waves.do =================================================================== --- tags/start/sim/rtl_sim/run/waves/waves.do (nonexistent) +++ tags/start/sim/rtl_sim/run/waves/waves.do (revision 3) @@ -0,0 +1,471 @@ +// Signalscan Version 6.7p1 + + +define noactivityindicator +define analog waveform lines +define add variable default overlay off +define waveform window analogheight 1 +define terminal automatic +define buttons control \ + 1 opensimmulationfile \ + 2 executedofile \ + 3 designbrowser \ + 4 waveform \ + 5 source \ + 6 breakpoints \ + 7 definesourcessearchpath \ + 8 exit \ + 9 createbreakpoint \ + 10 creategroup \ + 11 createmarker \ + 12 closesimmulationfile \ + 13 renamesimmulationfile \ + 14 replacesimulationfiledata \ + 15 listopensimmulationfiles \ + 16 savedofile +define buttons waveform \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 zoomin \ + 7 zoomout \ + 8 zoomoutfull \ + 9 expand \ + 10 createmarker \ + 11 designbrowser:1 \ + 12 savedofile \ + 13 replacesimulationfiledata \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons designbrowser \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 cdupscope \ + 7 getallvariables \ + 8 getdeepallvariables \ + 9 addvariables \ + 10 addvarsandclosewindow \ + 11 closewindow \ + 12 scopefiltermodule \ + 13 scopefiltertask \ + 14 scopefilterfunction \ + 15 scopefilterblock \ + 16 scopefilterprimitive +define buttons event \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 move \ + 7 closewindow \ + 8 duplicate \ + 9 defineasrisingedge \ + 10 defineasfallingedge \ + 11 defineasanyedge \ + 12 variableradixbinary \ + 13 variableradixoctal \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons source \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createbreakpoint \ + 7 creategroup \ + 8 createmarker \ + 9 createevent \ + 10 createregisterpage \ + 11 closewindow \ + 12 opensimmulationfile \ + 13 closesimmulationfile \ + 14 renamesimmulationfile \ + 15 replacesimulationfiledata \ + 16 listopensimmulationfiles +define buttons register \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createregisterpage \ + 7 closewindow \ + 8 continuefor \ + 9 continueuntil \ + 10 continueforever \ + 11 stop \ + 12 previous \ + 13 next \ + 14 variableradixbinary \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define show related transactions +define exit noprompt +define event search direction forward +define variable fullhierarchy +define variable nofilenames +define variable nofullpathfilenames +include bookmark with filenames +include scope history without filenames +define waveform window listpane 10.93 +define waveform window namepane 18.98 +define multivalueindication +define pattern curpos dot +define pattern cursor1 dot +define pattern cursor2 dot +define pattern marker dot +define print designer "Rudolf Usselmann" +define print border +define print color blackonwhite +define print command "/usr/ucb/lpr -P%P" +define print printer lp +define print range visible +define print variable visible +define rise fall time low threshold percentage 10 +define rise fall time high threshold percentage 90 +define rise fall time low value 0 +define rise fall time high value 3.3 +define sendmail command "/usr/lib/sendmail" +define sequence time width 30.00 +define snap + +define source noprompt +define time units default +define userdefinedbussymbol +define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html" +define waveform window grid off +define waveform window waveheight 14 +define waveform window wavespace 6 +define web browser command netscape +define zoom outfull on initial add off +add group \ + "System" \ + test.clk \ + test.rst \ + +add group \ + "Master 0" \ + test.m0_cyc_i \ + test.m0_stb_i \ + test.m0_sel_i[3:0]'h \ + test.m0_addr_i[31:0]'h \ + test.m0_data_i[31:0]'h \ + test.m0_data_o[31:0]'h \ + test.m0_we_i \ + test.m0_ack_o \ + test.m0_err_o \ + test.m0_rty_o \ + +add group \ + "Master 1" \ + test.m1_cyc_i \ + test.m1_stb_i \ + test.m1_sel_i[3:0]'h \ + test.m1_addr_i[31:0]'h \ + test.m1_data_i[31:0]'h \ + test.m1_data_o[31:0]'h \ + test.m1_we_i \ + test.m1_ack_o \ + test.m1_err_o \ + test.m1_rty_o \ + +add group \ + "Master 2" \ + test.m2_cyc_i \ + test.m2_stb_i \ + test.m2_sel_i[3:0]'h \ + test.m2_addr_i[31:0]'h \ + test.m2_data_i[31:0]'h \ + test.m2_data_o[31:0]'h \ + test.m2_we_i \ + test.m2_ack_o \ + test.m2_err_o \ + test.m2_rty_o \ + +add group \ + "Master 3" \ + test.m3_cyc_i \ + test.m3_stb_i \ + test.m3_sel_i[3:0]'h \ + test.m3_addr_i[31:0]'h \ + test.m3_data_i[31:0]'h \ + test.m3_data_o[31:0]'h \ + test.m3_we_i \ + test.m3_ack_o \ + test.m3_err_o \ + test.m3_rty_o \ + +add group \ + "Master 4" \ + test.m4_cyc_i \ + test.m4_stb_i \ + test.m4_sel_i[3:0]'h \ + test.m4_addr_i[31:0]'h \ + test.m4_data_i[31:0]'h \ + test.m4_data_o[31:0]'h \ + test.m4_we_i \ + test.m4_ack_o \ + test.m4_err_o \ + test.m4_rty_o \ + +add group \ + "Master 5" \ + test.m5_cyc_i \ + test.m5_stb_i \ + test.m5_sel_i[3:0]'h \ + test.m5_addr_i[31:0]'h \ + test.m5_data_i[31:0]'h \ + test.m5_data_o[31:0]'h \ + test.m5_we_i \ + test.m5_ack_o \ + test.m5_err_o \ + test.m5_rty_o \ + +add group \ + "Master 6" \ + test.m6_cyc_i \ + test.m6_stb_i \ + test.m6_sel_i[3:0]'h \ + test.m6_addr_i[31:0]'h \ + test.m6_data_i[31:0]'h \ + test.m6_data_o[31:0]'h \ + test.m6_we_i \ + test.m6_ack_o \ + test.m6_err_o \ + test.m6_rty_o \ + +add group \ + "Master 7" \ + test.m7_cyc_i \ + test.m7_stb_i \ + test.m7_sel_i[3:0]'h \ + test.m7_addr_i[31:0]'h \ + test.m7_data_i[31:0]'h \ + test.m7_data_o[31:0]'h \ + test.m7_we_i \ + test.m7_ack_o \ + test.m7_err_o \ + test.m7_rty_o \ + +add group \ + "Slave 0" \ + test.s0_cyc_o \ + test.s0_stb_o \ + test.s0_sel_o[3:0]'h \ + test.s0_addr_o[31:0]'h \ + test.s0_data_i[31:0]'h \ + test.s0_data_o[31:0]'h \ + test.s0_we_o \ + test.s0_ack_i \ + test.s0_err_i \ + test.s0_rty_i \ + +add group \ + "Slave 1" \ + test.s1_cyc_o \ + test.s1_stb_o \ + test.s1_sel_o[3:0]'h \ + test.s1_addr_o[31:0]'h \ + test.s1_data_i[31:0]'h \ + test.s1_data_o[31:0]'h \ + test.s1_we_o \ + test.s1_ack_i \ + test.s1_err_i \ + test.s1_rty_i \ + +add group \ + "Slave 2" \ + test.s2_cyc_o \ + test.s2_stb_o \ + test.s2_sel_o[3:0]'h \ + test.s2_addr_o[31:0]'h \ + test.s2_data_i[31:0]'h \ + test.s2_data_o[31:0]'h \ + test.s2_we_o \ + test.s2_ack_i \ + test.s2_err_i \ + test.s2_rty_i \ + +add group \ + "Slave 3" \ + test.s3_cyc_o \ + test.s3_stb_o \ + test.s3_sel_o[3:0]'h \ + test.s3_addr_o[31:0]'h \ + test.s3_data_i[31:0]'h \ + test.s3_data_o[31:0]'h \ + test.s3_we_o \ + test.s3_ack_i \ + test.s3_err_i \ + test.s3_rty_i \ + +add group \ + "Slave 4" \ + test.s4_cyc_o \ + test.s4_stb_o \ + test.s4_sel_o[3:0]'h \ + test.s4_addr_o[31:0]'h \ + test.s4_data_i[31:0]'h \ + test.s4_data_o[31:0]'h \ + test.s4_we_o \ + test.s4_ack_i \ + test.s4_err_i \ + test.s4_rty_i \ + +add group \ + "Slave 5" \ + test.s5_cyc_o \ + test.s5_stb_o \ + test.s5_sel_o[3:0]'h \ + test.s5_addr_o[31:0]'h \ + test.s5_data_i[31:0]'h \ + test.s5_data_o[31:0]'h \ + test.s5_we_o \ + test.s5_ack_i \ + test.s5_err_i \ + test.s5_rty_i \ + +add group \ + "Slave 6" \ + test.s6_cyc_o \ + test.s6_stb_o \ + test.s6_sel_o[3:0]'h \ + test.s6_addr_o[31:0]'h \ + test.s6_data_i[31:0]'h \ + test.s6_data_o[31:0]'h \ + test.s6_we_o \ + test.s6_ack_i \ + test.s6_err_i \ + test.s6_rty_i \ + +add group \ + "Slave 7" \ + test.s7_cyc_o \ + test.s7_stb_o \ + test.s7_sel_o[3:0]'h \ + test.s7_addr_o[31:0]'h \ + test.s7_data_i[31:0]'h \ + test.s7_data_o[31:0]'h \ + test.s7_we_o \ + test.s7_ack_i \ + test.s7_err_i \ + test.s7_rty_i \ + +add group \ + "Slave 8" \ + test.s8_cyc_o \ + test.s8_stb_o \ + test.s8_sel_o[3:0]'h \ + test.s8_addr_o[31:0]'h \ + test.s8_data_i[31:0]'h \ + test.s8_data_o[31:0]'h \ + test.s8_we_o \ + test.s8_ack_i \ + test.s8_err_i \ + test.s8_rty_i \ + +add group \ + "Slave 9" \ + test.s9_cyc_o \ + test.s9_stb_o \ + test.s9_sel_o[3:0]'h \ + test.s9_addr_o[31:0]'h \ + test.s9_data_i[31:0]'h \ + test.s9_data_o[31:0]'h \ + test.s9_we_o \ + test.s9_ack_i \ + test.s9_err_i \ + test.s9_rty_i \ + +add group \ + "Slave 10" \ + test.s10_cyc_o \ + test.s10_stb_o \ + test.s10_sel_o[3:0]'h \ + test.s10_addr_o[31:0]'h \ + test.s10_data_i[31:0]'h \ + test.s10_data_o[31:0]'h \ + test.s10_we_o \ + test.s10_ack_i \ + test.s10_err_i \ + test.s10_rty_i \ + +add group \ + "Slave 11" \ + test.s11_cyc_o \ + test.s11_stb_o \ + test.s11_sel_o[3:0]'h \ + test.s11_addr_o[31:0]'h \ + test.s11_data_i[31:0]'h \ + test.s11_data_o[31:0]'h \ + test.s11_we_o \ + test.s11_ack_i \ + test.s11_err_i \ + test.s11_rty_i \ + +add group \ + "Slave 12" \ + test.s12_cyc_o \ + test.s12_stb_o \ + test.s12_sel_o[3:0]'h \ + test.s12_addr_o[31:0]'h \ + test.s12_data_i[31:0]'h \ + test.s12_data_o[31:0]'h \ + test.s12_we_o \ + test.s12_ack_i \ + test.s12_err_i \ + test.s12_rty_i \ + +add group \ + "Slave 13" \ + test.s13_cyc_o \ + test.s13_stb_o \ + test.s13_sel_o[3:0]'h \ + test.s13_addr_o[31:0]'h \ + test.s13_data_i[31:0]'h \ + test.s13_data_o[31:0]'h \ + test.s13_we_o \ + test.s13_ack_i \ + test.s13_err_i \ + test.s13_rty_i \ + +add group \ + "Slave 14" \ + test.s14_cyc_o \ + test.s14_stb_o \ + test.s14_sel_o[3:0]'h \ + test.s14_addr_o[31:0]'h \ + test.s14_data_i[31:0]'h \ + test.s14_data_o[31:0]'h \ + test.s14_we_o \ + test.s14_ack_i \ + test.s14_err_i \ + test.s14_rty_i \ + +add group \ + "Slave 15" \ + test.s15_cyc_o \ + test.s15_stb_o \ + test.s15_sel_o[3:0]'h \ + test.s15_addr_o[31:0]'h \ + test.s15_data_i[31:0]'h \ + test.s15_data_o[31:0]'h \ + test.s15_we_o \ + test.s15_ack_i \ + test.s15_err_i \ + test.s15_rty_i \ + + +deselect all +open window designbrowser 1 geometry 56 118 1075 799 +open window waveform 1 geometry 10 59 1272 919 +zoom at 274.11(0)ns 0.07173877 0.00000000 Index: tags/start/sim/rtl_sim/bin/Makefile =================================================================== --- tags/start/sim/rtl_sim/bin/Makefile (nonexistent) +++ tags/start/sim/rtl_sim/bin/Makefile (revision 3) @@ -0,0 +1,148 @@ + +all: sim + +SHELL = /bin/sh +MS=-s + +########################################################################## +# +# DUT Sources +# +########################################################################## +DUT_SRC_DIR=../../../rtl/verilog +_TARGETS_= $(DUT_SRC_DIR)/wb_conmax_top.v \ + $(DUT_SRC_DIR)/wb_conmax_slave_if.v \ + $(DUT_SRC_DIR)/wb_conmax_master_if.v \ + $(DUT_SRC_DIR)/wb_conmax_msel.v \ + $(DUT_SRC_DIR)/wb_conmax_arb.v \ + $(DUT_SRC_DIR)/wb_conmax_pri_enc.v \ + $(DUT_SRC_DIR)/wb_conmax_pri_dec.v \ + $(DUT_SRC_DIR)/wb_conmax_rf.v + + +########################################################################## +# +# Test Bench Sources +# +########################################################################## +_TOP_=test +TB_SRC_DIR=../../../bench/verilog +_TB_= $(TB_SRC_DIR)/test_bench_top.v \ + $(TB_SRC_DIR)/wb_slv_model.v \ + $(TB_SRC_DIR)/wb_mast_model.v + +########################################################################## +# +# Misc Variables +# +########################################################################## + +INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" +LOGF=-LOGFILE .nclog +NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT +UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v +GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v + +########################################################################## +# +# Make Targets +# +########################################################################## + +ss: + signalscan -do waves/waves.do -waves waves/waves.trn & + +simxl: + verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ + $(_TARGETS_) $(_TB_) + +simw: + @$(MAKE) $(MS) sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES" + +sim: + @echo "" + @echo "----- Running NCVLOG ... ----------" + @$(MAKE) $(MS) vlog \ + TARGETS="$(_TARGETS_)" \ + TB="$(_TB_)" \ + INCDIR=$(INCDIR) \ + WAVES="$(WAVES)" + @echo "" + @echo "----- Running NCELAB ... ----------" + @$(MAKE) $(MS) elab \ + ACCESS="$(ACCESS)" TOP=$(_TOP_) + @echo "" + @echo "----- Running NCSIM ... ----------" + @$(MAKE) $(MS) ncsim TOP=$(_TOP_) + @echo "" + +gatew: + @$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" + +gate: + @echo "" + @echo "----- Running NCVLOG ... ----------" + @$(MAKE) $(MS) vlog \ + TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \ + TB="$(_TB_)" \ + INCDIR=$(INCDIR) \ + WAVES="$(WAVES)" + @echo "" + @echo "----- Running NCELAB ... ----------" + @$(MAKE) $(MS) elab \ + ACCESS="$(ACCESS)" TOP=$(_TOP_) + @echo "" + @echo "----- Running NCSIM ... ----------" + @$(MAKE) $(MS) ncsim TOP=$(_TOP_) + @echo "" + +hal: + @echo "" + @echo "----- Running HAL ... ----------" + @hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ + +incdir+$(DUT_SRC_DIR) $(_TARGETS_) + @echo "----- DONE ... ----------" + +clean: + rm -rf ./waves/*.dsn ./waves/*.trn \ + ncwork/inc* ncwork/.inc* \ + ./verilog.* .nclog hal.log + +########################################################################## +# +# NCVLOG +# +########################################################################## + +vhdl: + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK count -V93 hdl/counter.vhd + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work -V93 $(TARGETS) + +vlog: + ncvlog $(NCCOMMON) $(LOGF) \ + -WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR) + +########################################################################## +# +# NCELAB +# +########################################################################## + +elab: + ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work $(ACCESS) -NOTIMINGCHECKS \ + work.$(TOP) + +########################################################################## +# +# NCSIM +# +########################################################################## + +ncsim: + ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -EXIT -ERRORMAX 10 work.$(TOP) + +
tags/start/sim/rtl_sim/bin/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/start/vim_session.vim =================================================================== --- tags/start/vim_session.vim (nonexistent) +++ tags/start/vim_session.vim (revision 3) @@ -0,0 +1,144 @@ +set nocompatible +let s:cpo_save=&cpo +set cpo&vim +map! +map! +map! +map! +map! +map! +map! +map! +map! +map! +nnoremap 6_Paste "=@+.'xy' +gPFx"_2x:echo +map +map +map +map +map +map +map +map +map +map +let &cpo=s:cpo_save +unlet s:cpo_save +set background=dark +set iskeyword=@,48-57,_,192-255,+,-,? +set mouse=a +if &syntax != 'verilog' +set syntax=verilog +endif +let s:so_save = &so | let s:siso_save = &siso | set so=0 siso=0 +let v:this_session=expand(":p") +silent only +cd ~/bender_cores/wb_conmax +set shortmess=aoO +badd +16 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_defines.v +badd +180 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_top.v +badd +18 ~/bender_cores/wb_conmax/sim/rtl_sim/bin/Makefile +badd +96 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_arb.v +badd +3 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_master_if.v +badd +103 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_slave_if.v +badd +389 ~/bender_cores/wb_conmax/bench/verilog/test_bench_top.v +badd +51 ~/bender_cores/wb_conmax/bench/verilog/wb_model_defines.v +badd +1 ~/bender_cores/wb_conmax/bench/verilog/wb_slv_model.v +badd +6 ~/bender_cores/wb_conmax/bench/verilog/wb_mast_model.v +badd +73 ~/bender_cores/wb_conmax/bench/verilog/tests.v +badd +106 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_msel.v +badd +3 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v +badd +119 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v +badd +0 ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_rf.v +silent! argdel * +set splitbelow splitright +set nosplitbelow +set nosplitright +normal t +set winheight=1 winwidth=1 +argglobal +edit ~/bender_cores/wb_conmax/rtl/verilog/wb_conmax_rf.v +setlocal noautoindent +setlocal autoread +setlocal nobinary +setlocal bufhidden= +setlocal buflisted +setlocal buftype= +setlocal nocindent +setlocal cinkeys=0{,0},:,0#,!^F,o,O,e +setlocal cinoptions= +setlocal cinwords=if,else,while,do,for,switch +setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:- +setlocal commentstring=/*%s*/ +setlocal complete=.,w,b,u,t,i +setlocal define= +setlocal dictionary= +setlocal nodiff +setlocal equalprg= +setlocal errorformat= +setlocal noexpandtab +if &filetype != 'verilog' +setlocal filetype=verilog +endif +setlocal foldcolumn=0 +setlocal foldenable +setlocal foldexpr=0 +setlocal foldignore=# +setlocal foldlevel=0 +setlocal foldmarker={{{,}}} +setlocal foldmethod=manual +setlocal foldminlines=1 +setlocal foldnestmax=20 +setlocal foldtext=foldtext() +setlocal formatoptions=tcq +setlocal grepprg= +setlocal iminsert=0 +setlocal imsearch=0 +setlocal include=^#\\s*include +setlocal includeexpr= +setlocal indentexpr= +setlocal indentkeys=0{,0},:,0#,!^F,o,O,e +setlocal noinfercase +setlocal iskeyword=@,48-57,_,192-255,+,-,? +setlocal nolinebreak +setlocal nolisp +setlocal nolist +setlocal makeprg= +setlocal matchpairs=(:),{:},[:] +setlocal modeline +setlocal modifiable +setlocal nrformats=octal,hex +setlocal nonumber +setlocal path= +setlocal nopreviewwindow +setlocal noreadonly +setlocal noscrollbind +setlocal shiftwidth=8 +setlocal noshortname +setlocal nosmartindent +setlocal softtabstop=0 +setlocal suffixesadd= +setlocal swapfile +if &syntax != 'verilog' +setlocal syntax=verilog +endif +setlocal tabstop=8 +setlocal tags= +setlocal textwidth=0 +setlocal thesaurus= +setlocal wrap +setlocal wrapmargin=0 +silent! normal zE +let s:l = 10 - ((0 * winheight(0) + 29) / 58) +if s:l < 1 | let s:l = 1 | endif +exe s:l +normal zt +10 +normal 0 +set winheight=1 winwidth=20 shortmess=filnxtToO +let s:sx = expand(":p:r")."x.vim" +if file_readable(s:sx) + exe "source " . s:sx +endif +let &so = s:so_save | let &siso = s:siso_save Index: tags/start/syn/bin/read.dc =================================================================== --- tags/start/syn/bin/read.dc (nonexistent) +++ tags/start/syn/bin/read.dc (revision 3) @@ -0,0 +1,66 @@ +############################################################################### +# +# Pre Synthesis Script +# +# This script only reads in the design and saves it in a DB file +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_pre.log" +append pre_comp_db_file ../out/$design_name "_pre.db" + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Analyzing all design files ..." >> $log_file + +foreach module $design_files { + echo "+++++++++ Reading: $module" >> $log_file + echo +++++++++ Reading: $module + set module_file_name "" + append module_file_name $module ".v" + analyze -f verilog $module_file_name >> $log_file + elaborate $module >> $log_file + } + +current_design $active_design + +echo "+++++++++ Linking Design ..." >> $log_file +link >> $log_file + +echo "+++++++++ Uniquifying Design ..." >> $log_file +uniquify >> $log_file + +echo "+++++++++ Checking Design ..." >> $log_file +check_design >> $log_file + +# ============================================== +# Save Design +echo "+++++++++ Saving Design ..." >> $log_file +write_file -hierarchy -format db -output $pre_comp_db_file + Index: tags/start/syn/bin/comp.dc =================================================================== --- tags/start/syn/bin/comp.dc (nonexistent) +++ tags/start/syn/bin/comp.dc (revision 3) @@ -0,0 +1,137 @@ +############################################################################### +# +# Actual Synthesis Script +# +# This script does the actual synthesis +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_cmp.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +append post_comp_db_file ../out/$design_name ".db" +append post_syn_verilog_file ../out/$design_name "_ps.v" +set junk_file /dev/null + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Reading Design ..." >> $log_file +read_file $pre_comp_db_file >> $log_file + +# ============================================== +# Operating conditions + +echo "+++++++++ Setting up Operation Conditions ..." >> $log_file +current_design $design_name +set_operating_conditions WORST >> $log_file + +# Turn off automatic wire load selection, as this +# always (WHY ???) defaults to "zero_load" +#set auto_wire_load_selection false +#set_wire_load_mode enclosed >> $log_file +#set_wire_load_mode top >> $log_file +#set_wire_load_model -name suggested_40K >> $log_file + +# ============================================== +# Setup Clocks and Resets + +echo "+++++++++ Setting up Clocks ..." >> $log_file + +set_drive 0 [find port {*clk_i}] + +# !!! WISHBONE Clock !!! +set clock_period 1.0 +create_clock -period $clock_period clk_i +set_clock_skew -uncertainty 0.1 clk_i +set_clock_transition 0.1 clk_i +set_dont_touch_network clk_i + + +# !!! Reset !!! +set_drive 0 [find port {rst*}] +set_dont_touch_network [find port {rst*}] + +# ============================================== +# Setup IOs + +echo "+++++++++ Setting up IOs ..." >> $log_file + +# Need to spell out external IOs + +set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file +set_load 0.2 [all_outputs] + +set_input_delay -max 0 -clock clk_i [all_inputs] +set_output_delay -max 0 -clock clk_i [all_outputs] + +# ============================================== +# Setup Area Constrains +set_max_area 0.0 +set compile_sequential_area_recovery true + +hdlin_infer_mux = all + +# ============================================== +# Force Ultra +set_ultra_optimization -f + +# ============================================== +# Compile Design + +echo "+++++++++ Starting Compile ..." >> $log_file +#compile -map_effort low -area_effort low >> $log_file +compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file + +# ============================================== +# Write Out the optimized design + +echo "+++++++++ Saving Optimized Design ..." >> $log_file +write_file -hierarchy -format verilog -output $post_syn_verilog_file +write_file -hierarchy -format db -output $post_comp_db_file + +# ============================================== +# Create Some Basic Reports + +echo "+++++++++ Reporting Final Results ..." >> $log_file +report_timing -nworst 10 >> $log_file +report_timing -from m0_data_i[0] -to s0_data_o[0] >> $log_file +report_timing -from m0_data_o[0] -to s0_data_i[0] >> $log_file +report_timing -from m0_addr_i[0] -to s0_addr_o[0] >> $log_file +report_timing -from m0_ack_o -to s0_ack_i >> $log_file +report_timing -from m0_cyc_i -to s0_cyc_o >> $log_file +report_timing -from m0_stb_i -to s0_stb_o >> $log_file + +report_timing -from m0_data_i[0] -to s15_data_o[0] >> $log_file +report_timing -from m0_data_o[0] -to s15_data_i[0] >> $log_file +report_timing -from m0_addr_i[0] -to s15_addr_o[0] >> $log_file +report_timing -from m0_ack_o -to s15_ack_i >> $log_file +report_timing -from m0_cyc_i -to s15_cyc_o >> $log_file +report_timing -from m0_stb_i -to s15_stb_o >> $log_file + +report_area >> $log_file + Index: tags/start/syn/bin/lib_spec.dc =================================================================== --- tags/start/syn/bin/lib_spec.dc (nonexistent) +++ tags/start/syn/bin/lib_spec.dc (revision 3) @@ -0,0 +1,36 @@ +############################################################################### +# +# Library Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Libraries + +set search_path [list $search_path . \ + /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ + $hdl_src_dir] + +set snps [getenv "SYNOPSYS"] + +set synthetic_library "" +append synthetic_library $snps "/libraries/syn/dw01.sldb " +append synthetic_library $snps "/libraries/syn/dw02.sldb " +append synthetic_library $snps "/libraries/syn/dw03.sldb " +append synthetic_library $snps "/libraries/syn/dw04.sldb " +append synthetic_library $snps "/libraries/syn/dw05.sldb " +append synthetic_library $snps "/libraries/syn/dw06.sldb " +append synthetic_library $snps "/libraries/syn/dw07.sldb " + +set target_library { umcl18u250t2_typ.db } +set link_library "" +append link_library $target_library " " $synthetic_library +set symbol_library { umcl18u250t2.sdb } + Index: tags/start/syn/bin/.read.dc.swp =================================================================== --- tags/start/syn/bin/.read.dc.swp (nonexistent) +++ tags/start/syn/bin/.read.dc.swp (revision 3) @@ -0,0 +1,21 @@ +b0VIM 6.0akt=;K;erudicpu0~rudi/bender_cores/wb_conmax/syn/bin/read.dc3210#"! UtpBadBTR7qW:9 + + + + + +f +0 +/ + + + \ N M   { [ . + + + + + +: +( +' + l k : , write_file -hierarchy -format db -output $pre_comp_db_fileecho "+++++++++ Saving Design ..." >> $log_file# Save Design# ==============================================check_design >> $log_fileecho "+++++++++ Checking Design ..." >> $log_fileuniquify >> $log_fileecho "+++++++++ Uniquifying Design ..." >> $log_filelink >> $log_fileecho "+++++++++ Linking Design ..." >> $log_filecurrent_design $active_design } elaborate $module >> $log_file analyze -f verilog $module_file_name >> $log_file append module_file_name $module ".v" set module_file_name "" echo +++++++++ Reading: $module echo "+++++++++ Reading: $module" >> $log_fileforeach module $design_files {echo "+++++++++ Analyzing all design files ..." >> $log_file# Read Design# ==============================================set hdlin_enable_vpp true ;# Important - this enables 'ifdefs# Setup Misc Variables# ==============================================sh rm -f $log_fileappend pre_comp_db_file ../out/$design_name "_pre.db"append log_file ../log/$active_design "_pre.log"# Setup IO Files# ==============================================source ../bin/lib_spec.dc# Setup Libraries# ==============================================source ../bin/design_spec.dc# Setup Design Parameters# ==============================================################################################################################## 3/7/01 RU Initial Sript# Revision:## rudi@asics.ws# Author: Rudolf Usselmann## This script only reads in the design and saves it in a DB file## Pre Synthesis Script################################################################################ \ No newline at end of file Index: tags/start/syn/bin/design_spec.dc =================================================================== --- tags/start/syn/bin/design_spec.dc (nonexistent) +++ tags/start/syn/bin/design_spec.dc (revision 3) @@ -0,0 +1,27 @@ +############################################################################### +# +# Design Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 17/10/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters + +set design_files {wb_conmax_pri_dec wb_conmax_pri_enc wb_conmax_arb wb_conmax_msel wb_conmax_slave_if wb_conmax_master_if wb_conmax_rf wb_conmax_top} + + +set design_name wb_conmax_top +set active_design wb_conmax_top + +# Next Statement defines all clocks and resets in the design +set special_net {rst_i clk_i} + +set hdl_src_dir ../../rtl/verilog/ + Index: tags/start/txt.pl =================================================================== --- tags/start/txt.pl (nonexistent) +++ tags/start/txt.pl (revision 3) @@ -0,0 +1,41 @@ +#!/bin/perl + + +for($n=8;$n<8;$n++) { + +printf("wb_mast m%0d( .clk( clk ),\n", $n ); +printf(" .rst( ~rst ),\n", $n ); +printf(" .adr( m%0d_addr_i ),\n", $n ); +printf(" .din( m%0d_data_o ),\n", $n ); +printf(" .dout( m%0d_data_i ),\n", $n ); +printf(" .cyc( m%0d_cyc_i ),\n", $n ); +printf(" .stb( m%0d_stb_i ),\n", $n ); +printf(" .sel( m%0d_sel_i ),\n", $n ); +printf(" .we( m%0d_we_i ),\n", $n ); +printf(" .ack( m%0d_ack_o ),\n", $n ); +printf(" .err( m%0d_err_o ),\n", $n ); +printf(" .rty( m%0d_rty_o )\n", $n ); +printf(" );\n\n", $n ); + + } + + + +for($n=0;$n<16;$n++) { + +printf("wb_slv s%0d( .clk( clk ),\n", $n ); +printf(" .rst( ~rst ),\n", $n ); +printf(" .adr( s%0d_addr_o ),\n", $n ); +printf(" .din( s%0d_data_o ),\n", $n ); +printf(" .dout( s%0d_data_i ),\n", $n ); +printf(" .cyc( s%0d_cyc_o ),\n", $n ); +printf(" .stb( s%0d_stb_o ),\n", $n ); +printf(" .sel( s%0d_sel_o ),\n", $n ); +printf(" .we( s%0d_we_o ),\n", $n ); +printf(" .ack( s%0d_ack_i ),\n", $n ); +printf(" .err( s%0d_err_i ),\n", $n ); +printf(" .rty( s%0d_rty_i )\n", $n ); +printf(" );\n\n", $n ); + + } +
tags/start/txt.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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