URL
https://opencores.org/ocsvn/wb_dma/wb_dma/trunk
Subversion Repositories wb_dma
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/tags/start/doc/STATUS.txt
0,0 → 1,23
This file describes the current status of the checked in HDL code. |
Please submit all bugs/comments/suggestions regarding the DMA core |
to: cores@opencores.org |
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Need Help |
--------- |
I'm looking for help in verifying the core. If you think you can help, |
please send an email to the list or to me directly. |
Even though I have written a test bench and a few test, I would prefer |
if someone else could verify the core as well. |
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STATUS |
====== |
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Initial Release (19/3/2001) |
--------------------------- |
- This is the very first release of the core |
- There might be still many bugs ! Only little testing has been done ! |
- Please do not modify the sources (yet !) ! I'm still working on the core. |
- Things that are not implemented yet, or are known not to work yet: |
- The DMA currently ignores the RTY_I (retry) input. |
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/tags/start/doc/README.txt
0,0 → 1,10
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The WISHBONE DMA/Bridge Project Page is: |
http://www.opencores.org/cores/wb_dma/ |
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The WISHBONE DMA/Bridge core specification can be downloaded from: |
http://www.opencores.org/cores/wb_dma/dma_doc.pdf |
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To find out more about me (Rudolf Usselmann), please visit: |
http://www.asics.ws |
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