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/wb_fifo/trunk/model/vhdl/fifo.vhdl
52,20 → 52,58
signal memory:t_memory;
signal ptr:natural range 0 to memoryDepth-1;
/*
writeRequest and readRequest are inputs. This indicate that a block is requesting to write to or
read from the FIFO.
For write requests, the external block requests to write some data into the FIFO. The data
is attached as part of the write request (writeRequest.message).
For read requests, the external block requests to read some data from the FIFO. The data will
later be attached in the read response (readResponse.message).
There is no such concept as messages attached to a write response (no writeResponse.message) or
read request (no readRequest.message).
To generate a write response, the FIFO can assert an acknowledge signal, which could be part of
the response (writeResponse.trigger). The acknowledge is generated only when the FIFO is not
full. The requester can check this flag so that it will not continue requesting a write when
the FIFO is full.
When generating a read response, the FIFO can assert an acknowledge signal as part of the
response (readResponse.trigger), while at the same time, sending data back to the external
requester (readResponse.message). The acknowledge signal is generated only when the FIFO is
not empty. The requester can check this flag so that it will not continue requesting a read
when the FIFO is empty.
Currently, response acknowledge signals (writeResponse.trigger and readResponse.trigger) are
not yet implemented.
*/
signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
signal i_full,i_empty:boolean;
signal write,read:boolean;
begin
controller: process(reset,clk) is begin
if reset then fifoInterface.readResponse.message<=(others=>'Z');
if reset then
fifoInterface.readResponse.message<=(others=>'Z');
fifoInterface.readResponse.trigger<=false;
elsif falling_edge(clk) then
if fifoInterface.writeRequest.trigger xor i_writeRequest.trigger then
/* Default assignments. */
fifoInterface.readResponse.trigger<=false;
fifoInterface.writeResponse.trigger<=false;
/* Write request.
Safety control: allow writing only when FIFO is not full.
*/
--if i_pctFilled<d"100" and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
fifoInterface.writeResponse.trigger<=true;
memory(ptr)<=fifoInterface.writeRequest.message;
end if;
if fifoInterface.readRequest.trigger xor i_readRequest.trigger then
/* Read request.
Safety control: allow reading only when FIFO is not empty.
*/
if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then
fifoInterface.readResponse.trigger<=true;
fifoInterface.readResponse.message<=memory(ptr);
end if;
end if;
end process controller;
90,9 → 128,14
end process addrPointer;
/* Registers and pipelines. */
/* TODO recheck pipelining. */
process(clk) is begin
i_writeRequest<=fifoInterface.writeRequest;
i_readRequest<=fifoInterface.readRequest;
if falling_edge(clk) then
i_writeRequest <= fifoInterface.writeRequest;
i_readRequest <= fifoInterface.readRequest;
i_full <= fifoInterface.full;
i_empty <= fifoInterface.empty;
end if;
end process;
fifoInterface.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoInterface.pctFilled'length);
/wb_fifo/trunk/model/vhdl/packages/pkg-fifo-tlm.vhdl
55,6 → 55,16
nearEmpty,empty:boolean;
overflow,underflow:boolean;
end record t_fifoTransactor;
/* Use separate FIFO structure when request and response are
made into separate structures (for different directions).
*/
type t_fifo is record
pctFilled:unsigned(7 downto 0);
nearFull,full:boolean;
nearEmpty,empty:boolean;
overflow,underflow:boolean;
end record t_fifo;
end package fifoTLM;
 
package body fifoTLM is

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