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/tags/start/doc/README.txt --- tags/start/verilog/wb_mast_model.v (nonexistent) +++ tags/start/verilog/wb_mast_model.v (revision 3) @@ -0,0 +1,734 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Master Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_mast_model.v,v 1.1.1.1 2001-07-26 08:22:36 rudi Exp $ +// +// $Date: 2001-07-26 08:22:36 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// + +/* + +task mem_fill; + +- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values. + + +task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data); + +- Performs a single WISHBONE write + + +task wb_wr4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE writes +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_wr4, except it pwrforms "count" number of write cycles. + The data is taken from the internal wr_bub[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rmw( 32 bit address, 4 bit byte select, integer delay, + integer rcount, integer wcount); + +- This task performs "rcount" read cycles, followed by wcount write cycles. +- read data is placed in to the internal rd_buf[] memory, write data is + taken from the internal wr_buf[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + +task wb_wmr( 32 bit address, 4 bit byte select, integer delay, + integer rcount, integer wcount); + +- This task performs "wcount" write cycles, followed by "rcount" read cycles. +- read data is placed in to the internal rd_buf[] memory, write data is + taken from the internal wr_buf[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + +task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data); + +- Performs a single WISHBONE write + + +task wb_rd4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE reads +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_rd4, except it pwrforms "count" number of read cycles. + The data is read in to the internal rd_buf[] memory. +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + +*/ + + +`include "wb_model_defines.v" + +module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +output [31:0] adr; +input [31:0] din; +output [31:0] dout; +output cyc, stb; +output [3:0] sel; +output we; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 4096; + +reg [31:0] adr; +reg [31:0] dout; +reg cyc, stb; +reg [3:0] sel; +reg we; + +reg [31:0] rd_mem[mem_size:0]; +reg [31:0] wr_mem[mem_size:0]; +integer rd_cnt; +integer wr_cnt; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + adr = 32'hxxxx_xxxx; + dout = 32'hxxxx_xxxx; + cyc = 0; + stb = 0; + sel = 4'hx; + we = 1'hx; + rd_cnt = 0; + wr_cnt = 0; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + + +task mem_fill; + +integer n; +begin +rd_cnt = 0; +wr_cnt = 0; +for(n=0;n

/tags/start/verilog/wb_slv_model.v

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/tags/start/verilog/wb_model_defines.v

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