URL
https://opencores.org/ocsvn/wb_to_amba/wb_to_amba/trunk
Subversion Repositories wb_to_amba
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/wb_to_amba/trunk/src/wb_arm_phase_fsm.v
6,24 → 6,30
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module wb_arm_phase_fsm( |
input ahb_hclk, |
input ahb_hreset, |
input ahb_hsel, |
input ahb_hready_in, |
input ahb_hready_out, |
output ahb_data_phase, |
output fsm_error |
); |
module |
wb_arm_phase_fsm( |
input ahb_hclk, |
input ahb_hreset, |
input ahb_hsel, |
input ahb_hready_in, |
input ahb_hready_out, |
input [1:0] ahb_htrans, |
output ahb_data_phase, |
output fsm_error |
); |
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// ----------------------------- |
// do_transfer if not IDLE or BUSY |
wire do_transfer = (ahb_htrans == 2'b10) | (ahb_htrans == 2'b11); |
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// ----------------------------- |
// state machine binary definitions |
parameter IDLE_STATE = 3'b001; |
parameter DATA_STATE = 3'b010; |
parameter ERROR_STATE = 3'b100; |
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// ----------------------------- |
// state machine flop |
reg [2:0] state; |
40,7 → 46,7
// state machine |
always @(*) |
case(state) |
IDLE_STATE: if( ahb_hsel & ahb_hready_in ) |
IDLE_STATE: if( ahb_hsel & ahb_hready_in & do_transfer) |
next_state <= DATA_STATE; |
else |
next_state <= IDLE_STATE; |
62,10 → 68,6
assign ahb_data_phase = (state == DATA_STATE); |
assign fsm_error = (state == ERROR_STATE); |
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endmodule |
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/wb_to_amba/trunk/src/wb_arm_slave_top.v
7,7 → 7,7
module |
wb_arm_slave_top |
#( |
parameter AWIDTH = 8, |
parameter AWIDTH = 32, |
parameter DWIDTH = 32 |
) |
( |
49,7 → 49,7
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// ----------------------------- |
// ahb_haddr & control flops |
wire flop_en = ahb_hready_in & ahb_hsel; |
wire flop_en = ahb_hready_in & ahb_hsel & ~ahb_data_phase; |
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reg [AWIDTH-1:0] ahb_haddr_r; |
always @ (posedge ahb_hclk) |
86,15 → 86,17
wire ahb_data_phase; |
wire fsm_error; |
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wb_arm_phase_fsm i_wb_arm_phase_fsm( |
.ahb_hclk (ahb_hclk), |
.ahb_hreset (ahb_hreset), |
.ahb_hsel (ahb_hsel), |
.ahb_hready_in (ahb_hready_in), |
.ahb_hready_out (ahb_hready_out), |
.ahb_data_phase (ahb_data_phase), |
.fsm_error (fsm_error) |
); |
wb_arm_phase_fsm |
i_wb_arm_phase_fsm( |
.ahb_hclk (ahb_hclk), |
.ahb_hreset (ahb_hreset), |
.ahb_hsel (ahb_hsel), |
.ahb_hready_in (ahb_hready_in), |
.ahb_hready_out (ahb_hready_out), |
.ahb_htrans (ahb_htrans), |
.ahb_data_phase (ahb_data_phase), |
.fsm_error (fsm_error) |
); |
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// ----------------------------- |