URL
https://opencores.org/ocsvn/wbpwmaudio/wbpwmaudio/trunk
Subversion Repositories wbpwmaudio
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Rev 2 → Rev 3
/wbpwmaudio/trunk/rtl/wbpwmaudio.v
81,11 → 81,12
// Wishbone interface |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_pwm, o_int); |
parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz |
o_pwm, o_aux, o_int); |
parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz |
//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz |
NAUX=2, // Dev control values |
VARIABLE_RATE=0; |
VARIABLE_RATE=0, |
TIMING_BITS=17; |
input i_clk; |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input i_wb_addr; |
100,30 → 101,28
|
// How often shall we create an interrupt? Every reload_value clocks! |
// If VARIABLE_RATE==0, this value will never change and will be kept |
// at the default reload rate (44.1 kHz, for a 100 MHz clock) |
// at the default reload rate (defined up top) |
wire [(TIMING_BITS-1):0] w_reload_value; |
generate |
if (VARIABLE_RATE != 0) |
begin |
reg [31:0] r_reload_value; |
reg [(TIMING_BITS-1):0] r_reload_value; |
initial r_reload_value = DEFAULT_RELOAD; |
always @(posedge i_clk) // Data write |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we)) |
reload_value <= i_wb_data; |
wire [31:0] w_reload_value; |
r_reload_value <= i_wb_data[(TIMING_BITS-1):0]; |
assign w_reload_value = r_reload_value; |
end else begin |
wire [31:0] w_reload_value; |
assign w_reload_value = DEFAULT_RELOAD; |
end endgenerate |
|
reg [31:0] reload_value, timer; |
initial reload_value = DEFAULT_RELOAD; |
reg [(TIMING_BITS-1):0] timer; |
initial timer = DEFAULT_RELOAD; |
always @(posedge i_clk) |
if (timer == 0) |
timer <= reload_value; |
timer <= w_reload_value; |
else |
timer <= timer - 1; |
timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1}; |
|
reg [15:0] sample_out; |
always @(posedge i_clk) |
155,7 → 154,7
reg [15:0] pwm_counter; |
initial pwm_counter = 16'h00; |
always @(posedge i_clk) |
pwm_counter <= pwm_counter + 1; |
pwm_counter <= pwm_counter + 16'h01; |
|
wire [15:0] br_counter; |
genvar k; |
176,7 → 175,7
reg [31:0] r_wb_data; |
always @(posedge i_clk) |
if (i_wb_addr) |
r_wb_data <= reload_value; |
r_wb_data <= w_reload_value; |
else |
r_wb_data <= { {(12-NAUX){1'b0}}, o_aux, |
3'h0, o_int, sample_out }; |