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/trunk/rtl/io_package.vhd
0,0 → 1,337
-------------------------------------------------------------------------------
---- ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- NA ----
---- ----
---- Author(s): ----
---- Andrew Mulcock, amulcock@opencores.org ----
---- ----
-------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-------------------------------------------------------------------------------
---- ----
-- CVS Revision History ----
---- ----
-- $Log: not supported by cvs2svn $ ----
---- ----
 
 
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
-- -------------------------------------------------------------------------
package io_pack is
-- -------------------------------------------------------------------------
 
constant write32_time_out : integer := 6; -- number of clocks to wait
-- on w32, before an error
 
constant read32_time_out : integer := 6; -- number of clocks to wait
-- on r32, before an error
 
constant clk_period : time := 10 ns; -- period of simulation clock
 
type cycle_type is ( unknown,
bus_rst,
bus_idle,
rd32, rd16, rd8,
wr32, wr16, wr8
);
type bus_cycle is
record
c_type : cycle_type;
add_o : std_logic_vector( 31 downto 0);
dat_o : std_logic_vector( 31 downto 0);
dat_i : std_logic_vector( 31 downto 0);
we : std_logic;
stb : std_logic;
cyc : std_logic;
ack : std_logic;
err : std_logic;
rty : std_logic;
lock : std_logic;
sel : std_logic_vector( 3 downto 0);
clk : std_logic;
end record;
 
 
 
-- define the wishbone bus signal to share
-- with main procedure
-- Need to define it as the weekest possible ( 'Z' )
-- not so that we get a tri state bus, but so that
-- procedures called can over drive the signal in the test bench.
-- else test bench gets 'U's.
--
signal bus_c : bus_cycle :=
( unknown,
(others => 'Z'),
(others => 'Z'),
(others => 'Z'),
'Z',
'Z',
'Z',
'Z',
'Z',
'Z',
'Z',
(others => 'Z'),
'Z'
);
 
-- ----------------------------------------------------------------------
-- clock_wait
-- ----------------------------------------------------------------------
-- usage clock_wait( number of cycles, bus_record ); -- wait n number of clock cycles
procedure clock_wait(
constant no_of_clocks : in integer;
signal bus_c : inout bus_cycle
);
 
 
-- ----------------------------------------------------------------------
-- wb_init
-- ----------------------------------------------------------------------
-- usage wb_init( bus_record ); -- Initalises the wishbone bus
procedure wb_init(
signal bus_c : inout bus_cycle
);
 
 
-- ----------------------------------------------------------------------
-- wb_rst
-- ----------------------------------------------------------------------
-- usage wb_rst( 10, RST_sys, bus_record ); -- reset system for 10 clocks
procedure wb_rst (
constant no_of_clocks : in integer;
signal reset : out std_logic;
signal bus_c : inout bus_cycle
);
 
 
 
-- ----------------------------------------------------------------------
-- wr_32
-- ----------------------------------------------------------------------
-- usage wr_32 ( address, data , bus_record )-- write 32 bit data to a 32 bit address
procedure wr_32 (
constant address_data : in std_logic_vector( 31 downto 0);
constant write_data : in std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
);
 
-- ----------------------------------------------------------------------
-- rd_32
-- ----------------------------------------------------------------------
-- usage rd_32 ( address, data , bus_record )-- read 32 bit data from a 32 bit address
procedure rd_32 (
constant address_data : in std_logic_vector( 31 downto 0);
signal read_data : out std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
);
 
 
-- -------------------------------------------------------------------------
end io_pack;
-- -------------------------------------------------------------------------
 
 
 
 
 
-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
-- -------------------------------------------------------------------------
package body io_pack is
-- -------------------------------------------------------------------------
 
 
-- ----------------------------------------------------------------------
-- clock_wait
-- ----------------------------------------------------------------------
-- usage clock_wait( number of cycles, bus_record ); -- wait n number of clock cycles
procedure clock_wait(
constant no_of_clocks : in integer;
signal bus_c : inout bus_cycle
) is
begin
for n in 1 to no_of_clocks loop
wait until rising_edge( bus_c.clk );
end loop;
 
end procedure clock_wait;
 
 
 
-- --------------------------------------------------------------------
-- usage wb_init( bus_record ); -- Initalises the wishbone bus
procedure wb_init(
signal bus_c : inout bus_cycle
) is
begin
 
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
bus_c.we <= '0';
bus_c.stb <= '0';
bus_c.cyc <= '0';
bus_c.lock <= '0';
 
wait until rising_edge( bus_c.clk ); -- allign to next clock
end procedure wb_init;
 
 
-- --------------------------------------------------------------------
-- usage wb_rst( 10, RST_sys, bus_record ); -- reset system for 10 clocks
procedure wb_rst (
constant no_of_clocks : in integer;
signal reset : out std_logic;
signal bus_c : inout bus_cycle
) is
begin
bus_c.c_type <= bus_rst;
bus_c.stb <= '0';
bus_c.cyc <= '0';
 
reset <= '1';
for n in 1 to no_of_clocks loop
wait until falling_edge( bus_c.clk );
end loop;
reset <= '0';
wait until rising_edge( bus_c.clk);
end procedure wb_rst;
 
-- --------------------------------------------------------------------
procedure wr_32 (
constant address_data : in std_logic_vector( 31 downto 0);
constant write_data : in std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
) is
 
variable bus_write_timer : integer;
 
begin
 
bus_c.c_type <= wr32;
bus_c.add_o <= address_data;
bus_c.dat_o <= write_data;
bus_c.we <= '1'; -- write cycle
bus_c.sel <= ( others => '1'); -- on all four banks
bus_c.cyc <= '1';
bus_c.stb <= '1';
bus_write_timer := 0;
wait until rising_edge( bus_c.clk );
while bus_c.ack = '0' loop
bus_write_timer := bus_write_timer + 1;
wait until rising_edge( bus_c.clk );
exit when bus_write_timer >= write32_time_out;
end loop;
 
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
bus_c.we <= '0';
bus_c.sel <= ( others => '0');
bus_c.cyc <= '0';
bus_c.stb <= '0';
 
end procedure wr_32;
 
 
 
-- ----------------------------------------------------------------------
-- rd_32
-- ----------------------------------------------------------------------
-- usage rd_32 ( address, data , bus_record )-- read 32 bit data from a 32 bit address
procedure rd_32 (
constant address_data : in std_logic_vector( 31 downto 0);
signal read_data : out std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
) is
 
variable bus_read_timer : integer;
 
begin
 
bus_c.c_type <= rd32;
bus_c.add_o <= address_data;
bus_c.we <= '0'; -- read cycle
bus_c.sel <= ( others => '1'); -- on all four banks
bus_c.cyc <= '1';
bus_c.stb <= '1';
bus_read_timer := 0;
 
wait until rising_edge( bus_c.clk );
while bus_c.ack = '0' loop
bus_read_timer := bus_read_timer + 1;
wait until rising_edge( bus_c.clk );
exit when bus_read_timer >= read32_time_out;
end loop;
 
read_data <= bus_c.dat_i;
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
bus_c.we <= '0';
bus_c.sel <= ( others => '0');
bus_c.cyc <= '0';
bus_c.stb <= '0';
 
end procedure rd_32;
 
-- -------------------------------------------------------------------------
end io_pack;
-- -------------------------------------------------------------------------
/trunk/rtl/wb_master.vhd
0,0 → 1,178
-------------------------------------------------------------------------------
---- ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- NA ----
---- ----
---- Author(s): ----
---- Andrew Mulcock, amulcock@opencores.org ----
---- ----
-------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-------------------------------------------------------------------------------
---- ----
-- CVS Revision History ----
---- ----
-- $Log: not supported by cvs2svn $ ----
---- ----
 
 
-- file to 'exercise' the Wishbone bus.
--
-- Idea is to look like a wishbone master,
-- and provide procedures to exercise the bus.
--
-- syscon is an external module that provides the reset and clocks
-- to all the other modules in the design.
--
-- to enable the test script in this master to control
-- the syscon reset and clock stop,
-- this master provides tow 'extra' outputs
-- rst_i and clk_stop
--
-- when rst_sys is high, then syscon will issue a reset
-- when clk_stop is high, then syscon will stop the clock
-- on the next low transition. i.e. stopped clock is low.
 
use work.io_pack.all;
 
library ieee;
use ieee.std_logic_1164.all;
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
 
entity wb_master is
port(
-- sys_con control ports
RST_sys : out std_logic;
CLK_stop : out std_logic;
-- WISHBONE master interface:
RST_I : in std_logic;
CLK_I : in std_logic;
 
ADR_O : out std_logic_vector( 31 downto 0 );
DAT_I : in std_logic_vector( 31 downto 0 );
DAT_O : out std_logic_vector( 31 downto 0 );
WE_O : out std_logic;
 
STB_O : out std_logic;
CYC_O : out std_logic;
ACK_I : in std_logic;
ERR_I : in std_logic;
RTY_I : in std_logic;
LOCK_O : out std_logic;
SEL_O : out std_logic_vector( 3 downto 0 );
CYCLE_IS : out cycle_type
);
end entity wb_master;
 
-- --------------------------------------------------------------------
architecture Behavioral of wb_master is
-- --------------------------------------------------------------------
 
signal reset_int : std_logic;
signal slv_32 : std_logic_vector( 31 downto 0);
 
-- --------------------------------------------------------------------
begin
-- --------------------------------------------------------------------
 
-- concurrent assignemente to map record to the wishbone bus
 
ADR_O <= bus_c.add_o; -- address bus out of master
DAT_O <= bus_c.dat_o; -- data bus out of master
WE_O <= bus_c.we; -- wite enable out of master
STB_O <= bus_c.stb; -- wishbone strobe out of master
CYC_O <= bus_c.cyc; -- wishbone cycle out of master
LOCK_O <= bus_c.lock; -- wishbone Lock out of master
SEL_O <= bus_c.sel; -- slelects which of the 4 bytes to use for 32 bit
CYCLE_IS <= bus_c.c_type; -- monitor output, to know what master is up to
 
bus_c.dat_i <= DAT_I;
bus_c.ack <= ACK_I;
bus_c.err <= ERR_I;
bus_c.rty <= RTY_I;
bus_c.clk <= CLK_I;
 
 
-- concurent signal as can't pass out port to procedure ?
RST_sys <= reset_int;
 
-- --------------------------------------------------------------------
test_loop : process
begin
 
-- Wait 100 ns for global reset to finish
wait for 100 ns;
 
--clock_wait( 2, bus_c );
 
 
wb_init( bus_c); -- initalise wishbone bus
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 
wr_32( x"8000_0001", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
 
clock_wait( 1, bus_c );
 
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
 
 
clock_wait( 5, bus_c );
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 
 
 
 
 
 
-- --------------------------------------------------------------------
-- and stop the test running
-- --------------------------------------------------------------------
 
CLK_stop <= '1';
wait;
 
end process test_loop;
 
 
 
 
 
-- --------------------------------------------------------------------
end architecture Behavioral;
-- --------------------------------------------------------------------
/trunk/rtl/syscon.vhd
0,0 → 1,109
-------------------------------------------------------------------------------
---- ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- NA ----
---- ----
---- Author(s): ----
---- Andrew Mulcock, amulcock@opencores.org ----
---- ----
-------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-------------------------------------------------------------------------------
---- ----
-- CVS Revision History ----
---- ----
-- $Log: not supported by cvs2svn $ ----
---- ----
 
 
use work.io_pack.all; -- contains the clock frequency integer
 
 
library ieee;
use ieee.std_logic_1164.all;
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
 
entity syscon is
port(
-- sys_con ports
RST_sys : in std_logic;
CLK_stop : in std_logic;
RST_O : out std_logic;
CLK_O : out std_logic
);
 
end syscon;
 
architecture Behavioral of syscon is
 
signal clk_internal : std_logic;
signal rst_internal : std_logic := '0'; -- not reset
 
begin
 
 
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
-- sys con siumulator
clock_loop : process
begin
clk_internal <= '0';
if CLK_stop = '1' then
wait;
end if;
wait for clk_period/2;
clk_internal <= '1';
wait for clk_period/2;
end process clock_loop;
 
 
CLK_O <= clk_internal;
 
rst_loop : process ( RST_sys, clk_internal )
begin
if ( RST_sys = '1' ) then
rst_internal <= '1';
elsif rising_edge( clk_internal ) then
if RST_sys = '0' then
rst_internal <= '0';
end if;
end if;
end process rst_loop;
 
RST_O <= rst_internal;
 
end Behavioral;
/trunk/rtl/wbtb_1m_1s.vhd
0,0 → 1,161
-------------------------------------------------------------------------------
---- ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- NA ----
---- ----
---- Author(s): ----
---- Andrew Mulcock, amulcock@opencores.org ----
---- ----
-------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-------------------------------------------------------------------------------
---- ----
-- CVS Revision History ----
---- ----
-- $Log: not supported by cvs2svn $ ----
---- ----
 
--
-- wbtb_1m_1s
--
-- this testbench joins together
-- one wishbone master and one wishbone slave,
-- along with the required sys_con module
--
-- having only on emaster and one slave, no logic is
-- required, outputs of one connect to inputs of the other.
--
 
 
use work.io_pack.all;
 
library ieee;
use ieee.std_logic_1164.all;
 
ENTITY wbtb_1m_1s_vhd IS
END wbtb_1m_1s_vhd;
 
ARCHITECTURE behavior OF wbtb_1m_1s_vhd IS
 
-- Component Declaration for wishbone system controler
COMPONENT syscon
PORT(
RST_sys : in std_logic;
CLK_stop : in std_logic;
RST_O : out std_logic;
CLK_O : out std_logic
);
END COMPONENT;
 
-- Component Declaration for wishbone master
COMPONENT wb_master
PORT(
RST_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(31 downto 0);
ACK_I : IN std_logic;
ERR_I : IN std_logic;
RTY_I : IN std_logic;
SEL_O : OUT std_logic_vector(3 downto 0);
RST_sys : OUT std_logic;
CLK_stop : OUT std_logic;
ADR_O : OUT std_logic_vector(31 downto 0);
DAT_O : OUT std_logic_vector(31 downto 0);
WE_O : OUT std_logic;
STB_O : OUT std_logic;
CYC_O : OUT std_logic;
LOCK_O : OUT std_logic;
CYCLE_IS : OUT cycle_type
);
END COMPONENT;
 
 
--Inputs
SIGNAL RST_I : std_logic := '0';
SIGNAL CLK_I : std_logic := '0';
SIGNAL ACK_I : std_logic := '0';
SIGNAL ERR_I : std_logic := '0';
SIGNAL RTY_I : std_logic := '0';
SIGNAL DAT_I : std_logic_vector(31 downto 0) := (others=>'0');
 
--Outputs
SIGNAL RST_sys : std_logic;
SIGNAL CLK_stop : std_logic;
SIGNAL ADR_O : std_logic_vector(31 downto 0);
SIGNAL DAT_O : std_logic_vector(31 downto 0);
SIGNAL WE_O : std_logic;
SIGNAL STB_O : std_logic;
SIGNAL CYC_O : std_logic;
SIGNAL LOCK_O : std_logic;
SIGNAL SEL_O : std_logic_vector(3 downto 0);
SIGNAL CYCLE_IS : cycle_type;
 
 
-- ---------------------------------------------------------------
BEGIN
-- ---------------------------------------------------------------
 
-- Instantiate the system controler
sys_con: syscon PORT MAP(
RST_sys => RST_sys,
CLK_stop => CLK_stop,
RST_O => RST_I,
CLK_O => CLK_I
);
 
-- Instantiate the wishbone master
wb_m1: wb_master PORT MAP(
RST_sys => RST_sys,
CLK_stop => CLK_stop,
RST_I => RST_I,
CLK_I => CLK_I,
ADR_O => ADR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
STB_O => STB_O,
CYC_O => CYC_O,
ACK_I => ACK_I,
ERR_I => ERR_I,
RTY_I => RTY_I,
LOCK_O => LOCK_O,
SEL_O => SEL_O,
CYCLE_IS => CYCLE_IS
);
 
ACK_I <= STB_O; -- temp wire strobe to ack
 
 
END;

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