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/tags/initial/rtl/include/defines.v
0,0 → 1,124
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "defines.v" ////
//// ////
//// This file is part of the "10GE MAC" project ////
//// http://www.opencores.org/cores/xge_mac/ ////
//// ////
//// Author(s): ////
//// - A. Tanguay (antanguay@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// CPU Registers
 
`define CPUREG_CONFIG0 8'h00
`define CPUREG_INT_PENDING 8'h08
`define CPUREG_INT_STATUS 8'h0c
`define CPUREG_INT_MASK 8'h10
 
 
// Ethernet codes
 
`define IDLE 8'h07
`define PREAMBLE 8'h55
`define SEQUENCE 8'h9c
`define SFD 8'hd5
`define START 8'hfb
`define TERMINATE 8'hfd
`define ERROR 8'hfe
 
 
 
`define LINK_FAULT_OK 2'd0
`define LINK_FAULT_LOCAL 2'd1
`define LINK_FAULT_REMOTE 2'd2
 
`define FAULT_SEQ_LOCAL 1'b0
`define FAULT_SEQ_REMOTE 1'b1
 
`define LOCAL_FAULT 8'd1
`define REMOTE_FAULT 8'd2
 
`define PAUSE_FRAME 48'h010000c28001
 
`define LANE0 7:0
`define LANE1 15:8
`define LANE2 23:16
`define LANE3 31:24
`define LANE4 39:32
`define LANE5 47:40
`define LANE6 55:48
`define LANE7 63:56
 
 
`define TXSTATUS_NONE 8'h00
`define TXSTATUS_EOP0 8'h01
`define TXSTATUS_EOP1 8'h02
`define TXSTATUS_EOP2 8'h04
`define TXSTATUS_EOP3 8'h08
`define TXSTATUS_EOP4 8'h10
`define TXSTATUS_EOP5 8'h20
`define TXSTATUS_EOP6 8'h40
`define TXSTATUS_EOP7 8'h80
`define TXSTATUS_SOP 8'hff
 
`define RXSTATUS_NONE 4'h0
`define RXSTATUS_EOP0 4'h1
`define RXSTATUS_EOP1 4'h2
`define RXSTATUS_EOP2 4'h3
`define RXSTATUS_EOP3 4'h4
`define RXSTATUS_EOP4 4'h5
`define RXSTATUS_EOP5 4'h6
`define RXSTATUS_EOP6 4'h7
`define RXSTATUS_EOP7 4'h8
`define RXSTATUS_SOP 4'h9
 
`define RXSTATUS_ERR 4'h1
 
 
//
// FIFO Size: 8 * (2^AWIDTH) will be the size in bytes
// 7 --> 128 entries, 1024 bytes for data fifo
//
`define TX_DATA_FIFO_AWIDTH 7
`define RX_DATA_FIFO_AWIDTH 7
 
//
// FIFO Size: Holding FIFOs are 16 deep
//
`define TX_HOLD_FIFO_AWIDTH 4
`define RX_HOLD_FIFO_AWIDTH 4
 
 
// Memory types
`define MEM_AUTO_SMALL 1
`define MEM_AUTO_MEDIUM 2
 
 
tags/initial/rtl/include/defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/include/utils.v =================================================================== --- tags/initial/rtl/include/utils.v (nonexistent) +++ tags/initial/rtl/include/utils.v (revision 3) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "utils.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +function [63:0] reverse_64b; + input [63:0] data; + integer i; + begin + for (i = 0; i < 64; i = i + 1) begin + reverse_64b[i] = data[63 - i]; + end + end +endfunction + + +function [31:0] reverse_32b; + input [31:0] data; + integer i; + begin + for (i = 0; i < 32; i = i + 1) begin + reverse_32b[i] = data[31 - i]; + end + end +endfunction + + +function [7:0] reverse_8b; + input [7:0] data; + integer i; + begin + for (i = 0; i < 8; i = i + 1) begin + reverse_8b[i] = data[7 - i]; + end + end +endfunction + +
tags/initial/rtl/include/utils.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/include/timescale.v =================================================================== --- tags/initial/rtl/include/timescale.v (nonexistent) +++ tags/initial/rtl/include/timescale.v (revision 3) @@ -0,0 +1,2 @@ +`timescale 1ps / 1ps +
tags/initial/rtl/include/timescale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/include/CRC32_D8.v =================================================================== --- tags/initial/rtl/include/CRC32_D8.v (nonexistent) +++ tags/initial/rtl/include/CRC32_D8.v (revision 3) @@ -0,0 +1,100 @@ +/////////////////////////////////////////////////////////////////////// +// File: CRC32_D8.v +// Date: Fri Feb 8 19:26:59 2008 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 8 +// +// Info: tools@easics.be +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// + + +//module CRC32_D8; + + // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + // data width: 8 + // convention: the first serial data bit is D[7] + function [31:0] nextCRC32_D8; + + input [7:0] Data; + input [31:0] CRC; + + reg [7:0] D; + reg [31:0] C; + reg [31:0] NewCRC; + + begin + + D = Data; + C = CRC; + + NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30]; + NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ + C[31]; + NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ + C[26] ^ C[30] ^ C[31]; + NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ + C[31]; + NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[28] ^ C[30]; + NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ + C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ + C[27] ^ C[29] ^ C[31]; + NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ + C[28] ^ C[29]; + NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ + C[27] ^ C[29]; + NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ + C[27] ^ C[28]; + NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ + C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30]; + NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ + C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ + C[28] ^ C[30] ^ C[31]; + NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29]; + NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30]; + NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31]; + NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31]; + NewCRC[20] = D[4] ^ C[12] ^ C[28]; + NewCRC[21] = D[5] ^ C[13] ^ C[29]; + NewCRC[22] = D[0] ^ C[14] ^ C[24]; + NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30]; + NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31]; + NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27]; + NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ + C[28] ^ C[30]; + NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ + C[29] ^ C[31]; + NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30]; + NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31]; + NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31]; + NewCRC[31] = D[5] ^ C[23] ^ C[29]; + + nextCRC32_D8 = NewCRC; + + end + + endfunction + +//endmodule +
tags/initial/rtl/include/CRC32_D8.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/include/CRC32_D64.v =================================================================== --- tags/initial/rtl/include/CRC32_D64.v (nonexistent) +++ tags/initial/rtl/include/CRC32_D64.v (revision 3) @@ -0,0 +1,266 @@ +/////////////////////////////////////////////////////////////////////// +// File: CRC32_D64.v +// Date: Fri Feb 8 19:30:02 2008 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 64 +// +// Info: tools@easics.be +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// + + +//module CRC32_D64; + + // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + // data width: 64 + // convention: the first serial data bit is D[63] + function [31:0] nextCRC32_D64; + + input [63:0] Data; + input [31:0] CRC; + + reg [63:0] D; + reg [31:0] C; + reg [31:0] NewCRC; + + begin + + D = Data; + C = CRC; + + NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^ + D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^ + D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ + D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^ + C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ + C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^ + C[31]; + NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ + D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^ + D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^ + D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^ + D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^ + C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ + C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31]; + NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ + D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^ + D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^ + D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^ + D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ + C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^ + C[27]; + NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^ + D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^ + D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^ + D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^ + D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ + C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^ + C[27] ^ C[28]; + NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^ + D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^ + D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^ + D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^ + D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^ + C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^ + C[25] ^ C[26] ^ C[27] ^ C[31]; + NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^ + D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^ + D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^ + D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ + D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ + C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^ + C[23] ^ C[27] ^ C[29] ^ C[31]; + NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^ + D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^ + D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^ + D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ + D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ + C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^ + C[24] ^ C[28] ^ C[30]; + NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^ + D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ + D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^ + D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^ + D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^ + C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ + C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^ + C[26] ^ C[28]; + NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^ + D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^ + D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^ + D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^ + D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ + C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ + C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ + C[31]; + NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ + D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^ + D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^ + D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^ + D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ + C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ + C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29]; + NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ + D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^ + D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^ + D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^ + D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^ + C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^ + C[30] ^ C[31]; + NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^ + D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ + D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^ + D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ + D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^ + C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ + C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^ + C[27]; + NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^ + D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^ + D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^ + D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^ + D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^ + C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ + C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31]; + NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^ + D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^ + D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^ + D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ + D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^ + C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ + C[25] ^ C[26] ^ C[28] ^ C[30]; + NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^ + D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^ + D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^ + D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ + D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^ + C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ + C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31]; + NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ + D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^ + D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^ + D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^ + D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^ + C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ + C[27] ^ C[28] ^ C[30]; + NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^ + D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^ + D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^ + D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^ + C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25]; + NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^ + D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^ + D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^ + D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^ + C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26]; + NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^ + D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^ + D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^ + D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^ + C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27]; + NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ + D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^ + D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^ + D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^ + C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28]; + NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^ + D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^ + D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^ + D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^ + C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29]; + NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^ + D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ + D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^ + D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^ + C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30]; + NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ + D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ + D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ + D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^ + D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ + C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ + C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ + C[30]; + NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^ + D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^ + D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^ + D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^ + D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^ + C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^ + C[27] ^ C[28] ^ C[30]; + NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^ + D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^ + D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^ + D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^ + D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^ + C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^ + C[25] ^ C[28] ^ C[29] ^ C[31]; + NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^ + D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^ + D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^ + D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^ + D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^ + C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^ + C[29] ^ C[30]; + NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^ + D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^ + D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^ + D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^ + D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^ + C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^ + C[27] ^ C[28] ^ C[29] ^ C[30]; + NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^ + D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^ + D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^ + D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^ + D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ + C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^ + C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ + D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ + D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ + D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^ + D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ + C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^ + C[27] ^ C[29] ^ C[30] ^ C[31]; + NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ + D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^ + D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ + D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^ + D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^ + C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ + C[30] ^ C[31]; + NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^ + D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^ + D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^ + D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^ + C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^ + C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^ + C[31]; + NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^ + D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^ + D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^ + D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^ + C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^ + C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30]; + + nextCRC32_D64 = NewCRC; + + end + + endfunction + +//endmodule +
tags/initial/rtl/include/CRC32_D64.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/sync_clk_core.v =================================================================== --- tags/initial/rtl/verilog/sync_clk_core.v (nonexistent) +++ tags/initial/rtl/verilog/sync_clk_core.v (revision 3) @@ -0,0 +1,77 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sync_clk_core.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module sync_clk_core(/*AUTOARG*/ + // Inputs + clk_xgmii_tx, reset_xgmii_tx_n + ); + +input clk_xgmii_tx; +input reset_xgmii_tx_n; + +//input ctrl_tx_disable_padding; + +//output ctrl_tx_disable_padding_ccr; + + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +//wire [0:0] sig_out; + +//assign {ctrl_tx_disable_padding_ccr} = sig_out; + +//meta_sync #(.DWIDTH (1)) meta_sync0 ( +// // Outputs +// .out (sig_out), +// // Inputs +// .clk (clk_xgmii_tx), +// .reset_n (reset_xgmii_tx_n), +// .in ({ +// ctrl_tx_disable_padding +// })); + +endmodule +
tags/initial/rtl/verilog/sync_clk_core.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/sync_clk_xgmii_tx.v =================================================================== --- tags/initial/rtl/verilog/sync_clk_xgmii_tx.v (nonexistent) +++ tags/initial/rtl/verilog/sync_clk_xgmii_tx.v (revision 3) @@ -0,0 +1,90 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sync_clk_xgmii.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module sync_clk_xgmii_tx(/*AUTOARG*/ + // Outputs + ctrl_tx_enable_ctx, status_local_fault_ctx, + status_remote_fault_ctx, + // Inputs + clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable, + status_local_fault_crx, status_remote_fault_crx + ); + +input clk_xgmii_tx; +input reset_xgmii_tx_n; + +input ctrl_tx_enable; + +input status_local_fault_crx; +input status_remote_fault_crx; + +output ctrl_tx_enable_ctx; + +output status_local_fault_ctx; +output status_remote_fault_ctx; + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +wire [2:0] sig_out; + +assign {ctrl_tx_enable_ctx, + status_local_fault_ctx, + status_remote_fault_ctx} = sig_out; + +meta_sync #(.DWIDTH (3)) meta_sync0 ( + // Outputs + .out (sig_out), + // Inputs + .clk (clk_xgmii_tx), + .reset_n (reset_xgmii_tx_n), + .in ({ + ctrl_tx_enable, + status_local_fault_crx, + status_remote_fault_crx + })); + +endmodule +
tags/initial/rtl/verilog/sync_clk_xgmii_tx.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/generic_fifo.v =================================================================== --- tags/initial/rtl/verilog/generic_fifo.v (nonexistent) +++ tags/initial/rtl/verilog/generic_fifo.v (revision 3) @@ -0,0 +1,179 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "generic_fifo.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module generic_fifo( + + wclk, + wrst_n, + wen, + wdata, + wfull, + walmost_full, + + rclk, + rrst_n, + ren, + rdata, + rempty, + ralmost_empty +); + +//--- +// Parameters + +parameter DWIDTH = 32; +parameter AWIDTH = 3; +parameter RAM_DEPTH = (1 << AWIDTH); +parameter SYNC_WRITE = 1; +parameter SYNC_READ = 1; +parameter REGISTER_READ = 0; +parameter EARLY_READ = 0; +parameter CLOCK_CROSSING = 1; +parameter ALMOST_EMPTY_THRESH = 1; +parameter ALMOST_FULL_THRESH = RAM_DEPTH-2; +parameter MEM_TYPE = `MEM_AUTO_SMALL; + +//--- +// Ports + +input wclk; +input wrst_n; +input wen; +input [DWIDTH-1:0] wdata; +output wfull; +output walmost_full; + +input rclk; +input rrst_n; +input ren; +output [DWIDTH-1:0] rdata; +output rempty; +output ralmost_empty; + +// Wires + +wire mem_wen; +wire [AWIDTH:0] mem_waddr; + +wire mem_ren; +wire [AWIDTH:0] mem_raddr; + + +generic_fifo_ctrl #(.AWIDTH (AWIDTH), + .RAM_DEPTH (RAM_DEPTH), + .EARLY_READ (EARLY_READ), + .CLOCK_CROSSING (CLOCK_CROSSING), + .ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH), + .ALMOST_FULL_THRESH (ALMOST_FULL_THRESH) + ) + ctrl0(.wclk (wclk), + .wrst_n (wrst_n), + .wen (wen), + .wfull (wfull), + .walmost_full (walmost_full), + + .mem_wen (mem_wen), + .mem_waddr (mem_waddr), + + .rclk (rclk), + .rrst_n (rrst_n), + .ren (ren), + .rempty (rempty), + .ralmost_empty (ralmost_empty), + + .mem_ren (mem_ren), + .mem_raddr (mem_raddr) + ); + + +generate + if (MEM_TYPE == `MEM_AUTO_SMALL) begin + + generic_mem_small #(.DWIDTH (DWIDTH), + .AWIDTH (AWIDTH), + .RAM_DEPTH (RAM_DEPTH), + .SYNC_WRITE (SYNC_WRITE), + .SYNC_READ (SYNC_READ), + .REGISTER_READ (REGISTER_READ) + ) + mem0(.wclk (wclk), + .wrst_n (wrst_n), + .wen (mem_wen), + .waddr (mem_waddr), + .wdata (wdata), + + .rclk (rclk), + .rrst_n (rrst_n), + .ren (mem_ren), + .roen (ren), + .raddr (mem_raddr), + .rdata (rdata) + ); + + end + + if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin + + generic_mem_medium #(.DWIDTH (DWIDTH), + .AWIDTH (AWIDTH), + .RAM_DEPTH (RAM_DEPTH), + .SYNC_WRITE (SYNC_WRITE), + .SYNC_READ (SYNC_READ), + .REGISTER_READ (REGISTER_READ) + ) + mem0(.wclk (wclk), + .wrst_n (wrst_n), + .wen (mem_wen), + .waddr (mem_waddr), + .wdata (wdata), + + .rclk (rclk), + .rrst_n (rrst_n), + .ren (mem_ren), + .raddr (mem_raddr), + .rdata (rdata) + ); + + end + +endgenerate + +endmodule + + +
tags/initial/rtl/verilog/generic_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/rx_enqueue.v =================================================================== --- tags/initial/rtl/verilog/rx_enqueue.v (nonexistent) +++ tags/initial/rtl/verilog/rx_enqueue.v (revision 3) @@ -0,0 +1,758 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "rx_enqueue.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module rx_enqueue(/*AUTOARG*/ + // Outputs + rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren, + rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det, + remote_fault_msg_det, status_crc_error_tog, + status_fragment_error_tog, status_rxdfifo_ovflow_tog, + status_pause_frame_rx_tog, + // Inputs + clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, + rxdfifo_wfull, rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty, + rxhfifo_ralmost_empty + ); + +`include "CRC32_D64.v" +`include "CRC32_D8.v" +`include "utils.v" + +input clk_xgmii_rx; +input reset_xgmii_rx_n; + +input [63:0] xgmii_rxd; +input [7:0] xgmii_rxc; + +input rxdfifo_wfull; + +input [63:0] rxhfifo_rdata; +input [7:0] rxhfifo_rstatus; +input rxhfifo_rempty; +input rxhfifo_ralmost_empty; + +output [63:0] rxdfifo_wdata; +output [7:0] rxdfifo_wstatus; +output rxdfifo_wen; + +output rxhfifo_ren; + +output [63:0] rxhfifo_wdata; +output [7:0] rxhfifo_wstatus; +output rxhfifo_wen; + +output [1:0] local_fault_msg_det; +output [1:0] remote_fault_msg_det; + +output status_crc_error_tog; +output status_fragment_error_tog; +output status_rxdfifo_ovflow_tog; + +output status_pause_frame_rx_tog; + + + + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg [1:0] local_fault_msg_det; +reg [1:0] remote_fault_msg_det; +reg [63:0] rxdfifo_wdata; +reg rxdfifo_wen; +reg [7:0] rxdfifo_wstatus; +reg rxhfifo_ren; +reg [63:0] rxhfifo_wdata; +reg rxhfifo_wen; +reg [7:0] rxhfifo_wstatus; +reg status_crc_error_tog; +reg status_fragment_error_tog; +reg status_pause_frame_rx_tog; +reg status_rxdfifo_ovflow_tog; +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + + +reg [63:32] xgmii_rxd_d1; +reg [7:4] xgmii_rxc_d1; + +reg [63:0] xgxs_rxd_barrel; +reg [7:0] xgxs_rxc_barrel; + +reg [63:0] xgxs_rxd_barrel_d1; +reg [7:0] xgxs_rxc_barrel_d1; + +reg barrel_shift; + +reg [31:0] crc32_d64; +reg [31:0] crc32_d8; + +reg [3:0] crc_bytes; +reg [3:0] next_crc_bytes; + +reg [63:0] crc_shift_data; +reg crc_start_8b; +reg crc_done; +reg crc_good; +reg crc_clear; + +reg [31:0] crc_rx; +reg [31:0] next_crc_rx; + +reg [2:0] curr_state; +reg [2:0] next_state; + +reg [13:0] curr_byte_cnt; +reg [13:0] next_byte_cnt; + +reg fragment_error; +reg rxd_ovflow_error; + +reg coding_error; +reg next_coding_error; + +reg [7:0] addmask; +reg [7:0] datamask; + +reg pause_frame; +reg next_pause_frame; +reg pause_frame_hold; + +reg good_pause_frame; + +reg drop_data; +reg next_drop_data; + +reg pkt_pending; + +reg rxhfifo_ralmost_empty_d1; + + +parameter [2:0] + SM_IDLE = 3'd0, + SM_RX = 3'd1; + +always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin + + if (reset_xgmii_rx_n == 1'b0) begin + + xgmii_rxd_d1 <= 32'b0; + xgmii_rxc_d1 <= 4'b0; + + xgxs_rxd_barrel <= 64'b0; + xgxs_rxc_barrel <= 8'b0; + + xgxs_rxd_barrel_d1 <= 64'b0; + xgxs_rxc_barrel_d1 <= 8'b0; + + barrel_shift <= 1'b0; + + local_fault_msg_det <= 2'b0; + remote_fault_msg_det <= 2'b0; + + crc32_d64 <= 32'b0; + crc32_d8 <= 32'b0; + crc_bytes <= 4'b0; + + crc_shift_data <= 64'b0; + crc_done <= 1'b0; + crc_rx <= 32'b0; + + pause_frame_hold <= 1'b0; + + status_crc_error_tog <= 1'b0; + status_fragment_error_tog <= 1'b0; + status_rxdfifo_ovflow_tog <= 1'b0; + + status_pause_frame_rx_tog <= 1'b0; + + end + else begin + + //--- + // Link status RC layer + // Look for local/remote messages on lower 4 lanes and upper + // 4 lanes. This is a 64-bit interface but look at each 32-bit + // independantly. + + local_fault_msg_det[1] <= (xgmii_rxd[63:32] == + {`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} && + xgmii_rxc[7:4] == 4'b0001); + + local_fault_msg_det[0] <= (xgmii_rxd[31:0] == + {`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} && + xgmii_rxc[3:0] == 4'b0001); + + remote_fault_msg_det[1] <= (xgmii_rxd[63:32] == + {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} && + xgmii_rxc[7:4] == 4'b0001); + + remote_fault_msg_det[0] <= (xgmii_rxd[31:0] == + {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} && + xgmii_rxc[3:0] == 4'b0001); + + + //--- + // Rotating barrel. This function allow us to always align the start of + // a frame with LANE0. If frame starts in LANE4, it will be shifted 4 bytes + // to LANE0, thus reducing the amount of logic needed at the next stage. + + xgmii_rxd_d1[63:32] <= xgmii_rxd[63:32]; + xgmii_rxc_d1[7:4] <= xgmii_rxc[7:4]; + + if (xgmii_rxd[`LANE0] == `START && xgmii_rxc[0]) begin + + xgxs_rxd_barrel <= xgmii_rxd; + xgxs_rxc_barrel <= xgmii_rxc; + + barrel_shift <= 1'b0; + + end + else if (xgmii_rxd[`LANE4] == `START && xgmii_rxc[4]) begin + + xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]}; + xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]}; + + barrel_shift <= 1'b1; + + end + else if (barrel_shift) begin + + xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]}; + xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]}; + + end + else begin + + xgxs_rxd_barrel <= xgmii_rxd; + xgxs_rxc_barrel <= xgmii_rxc; + + end + + xgxs_rxd_barrel_d1 <= xgxs_rxd_barrel; + xgxs_rxc_barrel_d1 <= xgxs_rxc_barrel; + + + //--- + // When final CRC calculation begins we capture info relevant to + // current frame CRC claculation continues while next frame is + // being received. + + if (crc_start_8b) begin + + pause_frame_hold <= pause_frame; + + end + + //--- + // CRC Checking + + crc_rx <= next_crc_rx; + + if (crc_clear) begin + + // CRC is cleared at the beginning of the frame, calculate + // 64-bit at a time otherwise + + crc32_d64 <= 32'hffffffff; + + end + else begin + + crc32_d64 <= nextCRC32_D64(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64); + + end + + if (crc_bytes != 4'b0) begin + + // When reaching the end of the frame we switch from 64-bit mode + // to 8-bit mode to accomodate odd number of bytes in the frame. + // crc_bytes indicated the number of remaining payload byte to + // compute CRC on. Calculate and decrement until it reaches 0. + + if (crc_bytes == 4'b1) begin + crc_done <= 1'b1; + end + + crc32_d8 <= nextCRC32_D8(reverse_8b(crc_shift_data[7:0]), crc32_d8); + crc_shift_data <= {8'h00, crc_shift_data[63:8]}; + crc_bytes <= crc_bytes - 4'b1; + + end + else if (crc_bytes == 4'b0) begin + + // Per Clause 46. Control code during data must be reported + // as a CRC error. Indicated here by coding_error. Corrupt CRC + // if coding error is detected. + + if (coding_error || next_coding_error) begin + crc32_d8 <= ~crc32_d64; + end + else begin + crc32_d8 <= crc32_d64; + end + + crc_done <= 1'b0; + + crc_shift_data <= xgxs_rxd_barrel_d1; + crc_bytes <= next_crc_bytes; + + end + + //--- + // Error detection + + if (crc_done && !crc_good) begin + status_crc_error_tog <= ~status_crc_error_tog; + end + + if (fragment_error) begin + status_fragment_error_tog <= ~status_fragment_error_tog; + end + + if (rxd_ovflow_error) begin + status_rxdfifo_ovflow_tog <= ~status_rxdfifo_ovflow_tog; + end + + //--- + // Frame receive indication + + if (good_pause_frame) begin + status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog; + end + + end + +end + + +always @(/*AS*/crc32_d8 or crc_done or crc_rx or pause_frame_hold) begin + + + crc_good = 1'b0; + good_pause_frame = 1'b0; + + if (crc_done) begin + + // Check CRC. If this is a pause frame, report it to cpu. + + if (crc_rx == ~reverse_32b(crc32_d8)) begin + crc_good = 1'b1; + good_pause_frame = pause_frame_hold; + end + + end + +end + +always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin + + if (reset_xgmii_rx_n == 1'b0) begin + + curr_state <= SM_IDLE; + curr_byte_cnt <= 14'b0; + coding_error <= 1'b0; + pause_frame <= 1'b0; + + end + else begin + + curr_state <= next_state; + curr_byte_cnt <= next_byte_cnt; + coding_error <= next_coding_error; + pause_frame <= next_pause_frame; + + end + +end + + +always @(/*AS*/coding_error or crc_rx or curr_byte_cnt or curr_state + or pause_frame or xgxs_rxc_barrel or xgxs_rxc_barrel_d1 + or xgxs_rxd_barrel or xgxs_rxd_barrel_d1) begin + + next_state = curr_state; + + rxhfifo_wdata = xgxs_rxd_barrel_d1; + rxhfifo_wstatus = {`RXSTATUS_NONE, `RXSTATUS_NONE}; + rxhfifo_wen = 1'b0; + + addmask[0] = !(xgxs_rxd_barrel_d1[`LANE0] == `TERMINATE && xgxs_rxc_barrel_d1[0]); + addmask[1] = !(xgxs_rxd_barrel_d1[`LANE1] == `TERMINATE && xgxs_rxc_barrel_d1[1]); + addmask[2] = !(xgxs_rxd_barrel_d1[`LANE2] == `TERMINATE && xgxs_rxc_barrel_d1[2]); + addmask[3] = !(xgxs_rxd_barrel_d1[`LANE3] == `TERMINATE && xgxs_rxc_barrel_d1[3]); + addmask[4] = !(xgxs_rxd_barrel_d1[`LANE4] == `TERMINATE && xgxs_rxc_barrel_d1[4]); + addmask[5] = !(xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && xgxs_rxc_barrel_d1[5]); + addmask[6] = !(xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && xgxs_rxc_barrel_d1[6]); + addmask[7] = !(xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE && xgxs_rxc_barrel_d1[7]); + + datamask[0] = addmask[0]; + datamask[1] = &addmask[1:0]; + datamask[2] = &addmask[2:0]; + datamask[3] = &addmask[3:0]; + datamask[4] = &addmask[4:0]; + datamask[5] = &addmask[5:0]; + datamask[6] = &addmask[6:0]; + datamask[7] = &addmask[7:0]; + + next_crc_bytes = 4'b0; + next_crc_rx = crc_rx; + crc_start_8b = 1'b0; + crc_clear = 1'b0; + + next_byte_cnt = curr_byte_cnt; + + fragment_error = 1'b0; + + next_coding_error = coding_error; + next_pause_frame = pause_frame; + + case (curr_state) + + SM_IDLE: + begin + + next_byte_cnt = 14'b0; + crc_clear = 1'b1; + next_coding_error = 1'b0; + next_pause_frame = 1'b0; + + + // Detect the start of a frame + + if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] && + xgxs_rxd_barrel_d1[`LANE1] == `PREAMBLE && !xgxs_rxc_barrel_d1[1] && + xgxs_rxd_barrel_d1[`LANE2] == `PREAMBLE && !xgxs_rxc_barrel_d1[2] && + xgxs_rxd_barrel_d1[`LANE3] == `PREAMBLE && !xgxs_rxc_barrel_d1[3] && + xgxs_rxd_barrel_d1[`LANE4] == `PREAMBLE && !xgxs_rxc_barrel_d1[4] && + xgxs_rxd_barrel_d1[`LANE5] == `PREAMBLE && !xgxs_rxc_barrel_d1[5] && + xgxs_rxd_barrel_d1[`LANE6] == `PREAMBLE && !xgxs_rxc_barrel_d1[6] && + xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7]) begin + + next_state = SM_RX; + end + + end + + SM_RX: + begin + + // Pause frames are filtered + + rxhfifo_wen = !pause_frame; + + + if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] && + xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7]) begin + + // Fragment received, if we are still at SOP stage don't store + // the frame. If not, write a fake EOP and flag frame as bad. + + next_byte_cnt = 14'b0; + crc_clear = 1'b1; + next_coding_error = 1'b0; + + fragment_error = 1'b1; + rxhfifo_wstatus[7:4] = `RXSTATUS_ERR; + + if (curr_byte_cnt == 14'b0) begin + rxhfifo_wen = 1'b0; + end + else begin + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP0; + end + + end + else if (curr_byte_cnt > 14'd9900) begin + + // Frame too long, TERMMINATE must have been corrupted. + // Abort transfer, write a fake EOP, report as fragment. + + fragment_error = 1'b1; + rxhfifo_wstatus[7:4] = `RXSTATUS_ERR; + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP0; + next_state = SM_IDLE; + + end + else begin + + // Pause frame receive, these frame will be filtered + + if (curr_byte_cnt == 14'd0 && + xgxs_rxd_barrel_d1[47:0] == `PAUSE_FRAME) begin + + rxhfifo_wen = 1'b0; + next_pause_frame = 1'b1; + end + + + // Control character during data phase, force CRC error + + if (|(xgxs_rxc_barrel_d1 & datamask)) begin + + next_coding_error = 1'b1; + end + + + // Write SOP to status bits during first byte + + if (curr_byte_cnt == 14'b0) begin + rxhfifo_wstatus[3:0] = `RXSTATUS_SOP; + end + + /* verilator lint_off WIDTH */ + next_byte_cnt = curr_byte_cnt + + addmask[0] + addmask[1] + addmask[2] + addmask[3] + + addmask[4] + addmask[5] + addmask[6] + addmask[7]; + /* verilator lint_on WIDTH */ + + + + // We will not write to the fifo if all is left + // are four or less bytes of crc. We also strip off the + // crc, which requires looking one cycle ahead + // wstatus: + // [3:0] end of frame postion or sop + + // Look one cycle ahead for TERMINATE in lanes 0 to 4 + + if (xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP7; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd8; + next_crc_rx = xgxs_rxd_barrel[31:0]; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP6; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd7; + next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]}; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP5; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd6; + next_crc_rx = {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]}; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP4; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd5; + next_crc_rx = {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]}; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP3; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd4; + next_crc_rx = xgxs_rxd_barrel_d1[63:32]; + + next_state = SM_IDLE; + + end + + // Look at current cycle for TERMINATE in lanes 5 to 7 + + if (xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE && + xgxs_rxc_barrel_d1[7]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP2; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd3; + next_crc_rx = xgxs_rxd_barrel_d1[55:24]; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && + xgxs_rxc_barrel_d1[6]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP1; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd2; + next_crc_rx = xgxs_rxd_barrel_d1[47:16]; + + next_state = SM_IDLE; + + end + + if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && + xgxs_rxc_barrel_d1[5]) begin + + rxhfifo_wstatus[3:0] = `RXSTATUS_EOP0; + + crc_start_8b = 1'b1; + next_crc_bytes = 4'd1; + next_crc_rx = xgxs_rxd_barrel_d1[39:8]; + + next_state = SM_IDLE; + + end + end + end + + default: + begin + next_state = SM_IDLE; + end + + endcase + +end + + +always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin + + if (reset_xgmii_rx_n == 1'b0) begin + + rxhfifo_ralmost_empty_d1 <= 1'b1; + + drop_data <= 1'b0; + + pkt_pending <= 1'b0; + + end + else begin + + rxhfifo_ralmost_empty_d1 <= rxhfifo_ralmost_empty; + + drop_data <= next_drop_data; + + pkt_pending <= rxhfifo_ren && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP0 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP1 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP2 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP3 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP4 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP5 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP6 && + rxhfifo_rstatus[3:0] != `RXSTATUS_EOP7; + + end + +end + +always @(/*AS*/crc_done or crc_good or drop_data or pkt_pending + or rxdfifo_wfull or rxhfifo_ralmost_empty_d1 or rxhfifo_rdata + or rxhfifo_rstatus) begin + + rxd_ovflow_error = 1'b0; + + rxdfifo_wdata = rxhfifo_rdata; + rxdfifo_wstatus = rxhfifo_rstatus; + + next_drop_data = drop_data; + + + // There must be at least 8 words in holding FIFO before we start reading. + // This provides enough time for CRC calculation. + + rxhfifo_ren = !rxhfifo_ralmost_empty_d1 || pkt_pending; + + + + if (rxhfifo_ren && rxhfifo_rstatus[3:0] == `RXSTATUS_SOP) begin + + // Reset drop flag on SOP + + next_drop_data = 1'b0; + + end + + if (rxhfifo_ren && rxdfifo_wfull && !next_drop_data) begin + + // FIFO overflow, abort transfer. The rest of the frame + // will be dropped. Since we can't put an EOP indication + // in a fifo already full, there will be no EOP and receive + // side will need to sync on next SOP. + + rxd_ovflow_error = 1'b1; + next_drop_data = 1'b1; + + end + + + rxdfifo_wen = rxhfifo_ren && !next_drop_data; + + + + if (crc_done && !crc_good) begin + + // Flag packet with error when CRC error is detected + + rxdfifo_wstatus[7:4] = rxhfifo_rstatus[7:4] | `RXSTATUS_ERR; + + end + +end + +endmodule +
tags/initial/rtl/verilog/rx_enqueue.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/tx_enqueue.v =================================================================== --- tags/initial/rtl/verilog/tx_enqueue.v (nonexistent) +++ tags/initial/rtl/verilog/tx_enqueue.v (revision 3) @@ -0,0 +1,194 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "tx_enqueue.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module tx_enqueue(/*AUTOARG*/ + // Outputs + pkt_tx_full, txdfifo_wdata, txdfifo_wstatus, txdfifo_wen, + status_txdfifo_ovflow_tog, + // Inputs + clk_156m25, reset_156m25_n, pkt_tx_data, pkt_tx_val, pkt_tx_sop, + pkt_tx_eop, txdfifo_wfull, txdfifo_walmost_full + ); + +`include "CRC32_D64.v" +`include "CRC32_D8.v" +`include "utils.v" + +input clk_156m25; +input reset_156m25_n; + +input [63:0] pkt_tx_data; +input pkt_tx_val; +input pkt_tx_sop; +input [7:0] pkt_tx_eop; + +input txdfifo_wfull; +input txdfifo_walmost_full; + +output pkt_tx_full; + +output [63:0] txdfifo_wdata; +output [7:0] txdfifo_wstatus; +output txdfifo_wen; + +output status_txdfifo_ovflow_tog; + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg status_txdfifo_ovflow_tog; +reg [63:0] txdfifo_wdata; +reg txdfifo_wen; +reg [7:0] txdfifo_wstatus; +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + + +reg txd_ovflow; +reg next_txd_ovflow; + + + +// Full status if data fifo is almost full. +// Current packet can complete transfer since data input rate +// matches output rate. But next packet must wait for more headroom. + +assign pkt_tx_full = txdfifo_walmost_full; + + + +always @(posedge clk_156m25 or negedge reset_156m25_n) begin + + if (reset_156m25_n == 1'b0) begin + + txd_ovflow <= 1'b0; + + status_txdfifo_ovflow_tog <= 1'b0; + + end + else begin + + txd_ovflow <= next_txd_ovflow; + + //--- + // FIFO errors, used to generate interrupts + + if (next_txd_ovflow && !txd_ovflow) begin + status_txdfifo_ovflow_tog <= ~status_txdfifo_ovflow_tog; + end + + end + +end + +always @(/*AS*/pkt_tx_data or pkt_tx_eop or pkt_tx_sop or pkt_tx_val + or txd_ovflow or txdfifo_wfull) begin + + txdfifo_wstatus = `TXSTATUS_NONE; + txdfifo_wdata = pkt_tx_data; + txdfifo_wen = pkt_tx_val; + + next_txd_ovflow = txd_ovflow; + + + // Write SOP marker to fifo. + + if (pkt_tx_val && pkt_tx_sop) begin + + txdfifo_wstatus = `TXSTATUS_SOP; + + end + + + // Write EOP marker to fifo. + + if (pkt_tx_val) begin + + if (pkt_tx_eop[0]) begin + txdfifo_wstatus = `TXSTATUS_EOP0; + end + else if (pkt_tx_eop[1]) begin + txdfifo_wstatus = `TXSTATUS_EOP1; + end + else if (pkt_tx_eop[2]) begin + txdfifo_wstatus = `TXSTATUS_EOP2; + end + else if (pkt_tx_eop[3]) begin + txdfifo_wstatus = `TXSTATUS_EOP3; + end + else if (pkt_tx_eop[4]) begin + txdfifo_wstatus = `TXSTATUS_EOP4; + end + else if (pkt_tx_eop[5]) begin + txdfifo_wstatus = `TXSTATUS_EOP5; + end + else if (pkt_tx_eop[6]) begin + txdfifo_wstatus = `TXSTATUS_EOP6; + end + else if (pkt_tx_eop[7]) begin + txdfifo_wstatus = `TXSTATUS_EOP7; + end + + end + + + // Overflow indication + + if (pkt_tx_val) begin + + if (txdfifo_wfull) begin + + next_txd_ovflow = 1'b1; + + end + else if (pkt_tx_sop) begin + + next_txd_ovflow = 1'b0; + + end + end + +end + + +endmodule +
tags/initial/rtl/verilog/tx_enqueue.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/meta_sync.v =================================================================== --- tags/initial/rtl/verilog/meta_sync.v (nonexistent) +++ tags/initial/rtl/verilog/meta_sync.v (revision 3) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "meta_sync.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module meta_sync(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, reset_n, in + ); + +parameter DWIDTH = 1; +parameter EDGE_DETECT = 0; + +input clk; +input reset_n; + +input [DWIDTH-1:0] in; + +output [DWIDTH-1:0] out; + +generate +genvar i; + + for (i = 0; i < DWIDTH; i = i + 1) begin : meta + + meta_sync_single #(.EDGE_DETECT (EDGE_DETECT)) + meta_sync_single0 ( + // Outputs + .out (out[i]), + // Inputs + .clk (clk), + .reset_n (reset_n), + .in (in[i])); + + end + +endgenerate + +endmodule +
tags/initial/rtl/verilog/meta_sync.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/meta_sync_single.v =================================================================== --- tags/initial/rtl/verilog/meta_sync_single.v (nonexistent) +++ tags/initial/rtl/verilog/meta_sync_single.v (revision 3) @@ -0,0 +1,105 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "meta_sync_single.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module meta_sync_single(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, reset_n, in + ); + +parameter EDGE_DETECT = 0; + +input clk; +input reset_n; + +input in; + +output out; + +reg out; + + + +generate + + if (EDGE_DETECT) begin + + reg meta; + reg edg1; + reg edg2; + + always @(posedge clk or negedge reset_n) begin + + if (reset_n == 1'b0) begin + meta <= 1'b0; + edg1 <= 1'b0; + edg2 <= 1'b0; + out <= 1'b0; + end + else begin + meta <= in; + edg1 <= meta; + edg2 <= edg1; + out <= edg1 ^ edg2; + end + end + + end + else begin + + reg meta; + + always @(posedge clk or negedge reset_n) begin + + if (reset_n == 1'b0) begin + meta <= 1'b0; + out <= 1'b0; + end + else begin + meta <= in; + out <= meta; + end + end + + end + +endgenerate + +endmodule +
tags/initial/rtl/verilog/meta_sync_single.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/rx_data_fifo.v =================================================================== --- tags/initial/rtl/verilog/rx_data_fifo.v (nonexistent) +++ tags/initial/rtl/verilog/rx_data_fifo.v (revision 3) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "rx_data_fifo.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module rx_data_fifo(/*AUTOARG*/ + // Outputs + rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty, + rxdfifo_ralmost_empty, + // Inputs + clk_xgmii_rx, clk_156m25, reset_xgmii_rx_n, reset_156m25_n, + rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxdfifo_ren + ); + +input clk_xgmii_rx; +input clk_156m25; +input reset_xgmii_rx_n; +input reset_156m25_n; + +input [63:0] rxdfifo_wdata; +input [7:0] rxdfifo_wstatus; +input rxdfifo_wen; + +input rxdfifo_ren; + +output rxdfifo_wfull; + +output [63:0] rxdfifo_rdata; +output [7:0] rxdfifo_rstatus; +output rxdfifo_rempty; +output rxdfifo_ralmost_empty; + +generic_fifo #( + .DWIDTH (72), + .AWIDTH (`RX_DATA_FIFO_AWIDTH), + .REGISTER_READ (0), + .EARLY_READ (1), + .CLOCK_CROSSING (1), + .ALMOST_EMPTY_THRESH (4), + .MEM_TYPE (`MEM_AUTO_MEDIUM) +) +fifo0( + .wclk (clk_xgmii_rx), + .wrst_n (reset_xgmii_rx_n), + .wen (rxdfifo_wen), + .wdata ({rxdfifo_wstatus, rxdfifo_wdata}), + .wfull (rxdfifo_wfull), + .walmost_full (), + + .rclk (clk_156m25), + .rrst_n (reset_156m25_n), + .ren (rxdfifo_ren), + .rdata ({rxdfifo_rstatus, rxdfifo_rdata}), + .rempty (rxdfifo_rempty), + .ralmost_empty (rxdfifo_ralmost_empty) +); + + +endmodule +
tags/initial/rtl/verilog/rx_data_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/tx_data_fifo.v =================================================================== --- tags/initial/rtl/verilog/tx_data_fifo.v (nonexistent) +++ tags/initial/rtl/verilog/tx_data_fifo.v (revision 3) @@ -0,0 +1,96 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "tx_data_fifo.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module tx_data_fifo(/*AUTOARG*/ + // Outputs + txdfifo_wfull, txdfifo_walmost_full, txdfifo_rdata, + txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty, + // Inputs + clk_xgmii_tx, clk_156m25, reset_xgmii_tx_n, reset_156m25_n, + txdfifo_wdata, txdfifo_wstatus, txdfifo_wen, txdfifo_ren + ); + +input clk_xgmii_tx; +input clk_156m25; +input reset_xgmii_tx_n; +input reset_156m25_n; + +input [63:0] txdfifo_wdata; +input [7:0] txdfifo_wstatus; +input txdfifo_wen; + +input txdfifo_ren; + +output txdfifo_wfull; +output txdfifo_walmost_full; + +output [63:0] txdfifo_rdata; +output [7:0] txdfifo_rstatus; +output txdfifo_rempty; +output txdfifo_ralmost_empty; + +generic_fifo #( + .DWIDTH (72), + .AWIDTH (`TX_DATA_FIFO_AWIDTH), + .REGISTER_READ (0), + .EARLY_READ (1), + .CLOCK_CROSSING (1), + .ALMOST_EMPTY_THRESH (7), + .ALMOST_FULL_THRESH (12), + .MEM_TYPE (`MEM_AUTO_MEDIUM) +) +fifo0( + .wclk (clk_156m25), + .wrst_n (reset_156m25_n), + .wen (txdfifo_wen), + .wdata ({txdfifo_wstatus, txdfifo_wdata}), + .wfull (txdfifo_wfull), + .walmost_full (txdfifo_walmost_full), + + .rclk (clk_xgmii_tx), + .rrst_n (reset_xgmii_tx_n), + .ren (txdfifo_ren), + .rdata ({txdfifo_rstatus, txdfifo_rdata}), + .rempty (txdfifo_rempty), + .ralmost_empty (txdfifo_ralmost_empty) +); + +endmodule +
tags/initial/rtl/verilog/tx_data_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/wishbone_if.v =================================================================== --- tags/initial/rtl/verilog/wishbone_if.v (nonexistent) +++ tags/initial/rtl/verilog/wishbone_if.v (revision 3) @@ -0,0 +1,230 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "wishbone.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module wishbone_if(/*AUTOARG*/ + // Outputs + wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable, + // Inputs + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, + wb_cyc_i, status_crc_error, status_fragment_error, + status_txdfifo_ovflow, status_txdfifo_udflow, + status_rxdfifo_ovflow, status_rxdfifo_udflow, + status_pause_frame_rx, status_local_fault, status_remote_fault + ); + + +input wb_clk_i; +input wb_rst_i; + +input [7:0] wb_adr_i; +input [31:0] wb_dat_i; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; + +output [31:0] wb_dat_o; +output wb_ack_o; +output wb_int_o; + +input status_crc_error; +input status_fragment_error; + +input status_txdfifo_ovflow; + +input status_txdfifo_udflow; + +input status_rxdfifo_ovflow; + +input status_rxdfifo_udflow; + +input status_pause_frame_rx; + +input status_local_fault; +input status_remote_fault; + +output ctrl_tx_enable; + + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg [31:0] wb_dat_o; +reg wb_int_o; +// End of automatics + +reg [0:0] cpureg_config0; +reg [8:0] cpureg_int_pending; +reg [8:0] cpureg_int_mask; + +reg cpuack; + +reg status_remote_fault_d1; +reg status_local_fault_d1; + + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +wire [8:0] int_sources; + + +//--- +// Source of interrupts, some are edge sensitive, others +// expect a pulse signal. + +assign int_sources = { + status_fragment_error, + status_crc_error, + + status_pause_frame_rx, + + status_remote_fault ^ status_remote_fault_d1, + status_local_fault ^ status_local_fault_d1, + + status_rxdfifo_udflow, + status_rxdfifo_ovflow, + status_txdfifo_udflow, + status_txdfifo_ovflow + }; + +//--- +// Config Register 0 + +assign ctrl_tx_enable = cpureg_config0[0]; + + + +//--- +// Wishbone signals + +assign wb_ack_o = cpuack && wb_stb_i; + +always @(posedge wb_clk_i or posedge wb_rst_i) begin + + if (wb_rst_i == 1'b1) begin + + cpureg_config0 <= 1'h1; + cpureg_int_pending <= 9'b0; + cpureg_int_mask <= 9'b0; + + wb_dat_o <= 32'b0; + wb_int_o <= 1'b0; + + cpuack <= 1'b0; + + status_remote_fault_d1 <= status_remote_fault; + status_local_fault_d1 <= status_local_fault; + + end + else begin + + wb_int_o <= |(cpureg_int_pending & cpureg_int_mask); + + cpureg_int_pending <= cpureg_int_pending | int_sources; + + cpuack <= wb_cyc_i && wb_stb_i; + + status_remote_fault_d1 <= status_remote_fault; + status_local_fault_d1 <= status_local_fault; + + //--- + // Read access + + if (wb_cyc_i && wb_stb_i && !wb_we_i) begin + + case ({wb_adr_i[7:2], 2'b0}) + + `CPUREG_CONFIG0: begin + wb_dat_o <= {31'b0, cpureg_config0}; + end + + `CPUREG_INT_PENDING: begin + wb_dat_o <= {23'b0, cpureg_int_pending}; + cpureg_int_pending <= int_sources; + wb_int_o <= 1'b0; + end + + `CPUREG_INT_STATUS: begin + wb_dat_o <= {23'b0, int_sources}; + end + + `CPUREG_INT_MASK: begin + wb_dat_o <= {23'b0, cpureg_int_mask}; + end + + default: begin + end + + endcase + + end + + //--- + // Write access + + if (wb_cyc_i && wb_stb_i && wb_we_i) begin + + case ({wb_adr_i[7:2], 2'b0}) + + `CPUREG_CONFIG0: begin + cpureg_config0 <= wb_dat_i[0:0]; + end + + `CPUREG_INT_PENDING: begin + cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources; + end + + `CPUREG_INT_MASK: begin + cpureg_int_mask <= wb_dat_i[8:0]; + end + + default: begin + end + + endcase + + end + + end + +end + +endmodule +
tags/initial/rtl/verilog/wishbone_if.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/sync_clk_wb.v =================================================================== --- tags/initial/rtl/verilog/sync_clk_wb.v (nonexistent) +++ tags/initial/rtl/verilog/sync_clk_wb.v (revision 3) @@ -0,0 +1,140 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sync_clk_wb.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module sync_clk_wb(/*AUTOARG*/ + // Outputs + status_crc_error, status_fragment_error, status_txdfifo_ovflow, + status_txdfifo_udflow, status_rxdfifo_ovflow, + status_rxdfifo_udflow, status_pause_frame_rx, status_local_fault, + status_remote_fault, + // Inputs + wb_clk_i, wb_rst_i, status_crc_error_tog, + status_fragment_error_tog, status_txdfifo_ovflow_tog, + status_txdfifo_udflow_tog, status_rxdfifo_ovflow_tog, + status_rxdfifo_udflow_tog, status_pause_frame_rx_tog, + status_local_fault_crx, status_remote_fault_crx + ); + +input wb_clk_i; +input wb_rst_i; + +input status_crc_error_tog; +input status_fragment_error_tog; + +input status_txdfifo_ovflow_tog; + +input status_txdfifo_udflow_tog; + +input status_rxdfifo_ovflow_tog; + +input status_rxdfifo_udflow_tog; + +input status_pause_frame_rx_tog; + +input status_local_fault_crx; +input status_remote_fault_crx; + +output status_crc_error; +output status_fragment_error; + +output status_txdfifo_ovflow; + +output status_txdfifo_udflow; + +output status_rxdfifo_ovflow; + +output status_rxdfifo_udflow; + +output status_pause_frame_rx; + +output status_local_fault; +output status_remote_fault; + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +wire [6:0] sig_out1; +wire [1:0] sig_out2; + +assign {status_crc_error, + status_fragment_error, + status_txdfifo_ovflow, + status_txdfifo_udflow, + status_rxdfifo_ovflow, + status_rxdfifo_udflow, + status_pause_frame_rx} = sig_out1; + +assign {status_local_fault, + status_remote_fault} = sig_out2; + +meta_sync #(.DWIDTH (7), .EDGE_DETECT (1)) meta_sync0 ( + // Outputs + .out (sig_out1), + // Inputs + .clk (wb_clk_i), + .reset_n (~wb_rst_i), + .in ({ + status_crc_error_tog, + status_fragment_error_tog, + status_txdfifo_ovflow_tog, + status_txdfifo_udflow_tog, + status_rxdfifo_ovflow_tog, + status_rxdfifo_udflow_tog, + status_pause_frame_rx_tog + })); + +meta_sync #(.DWIDTH (2), .EDGE_DETECT (0)) meta_sync1 ( + // Outputs + .out (sig_out2), + // Inputs + .clk (wb_clk_i), + .reset_n (~wb_rst_i), + .in ({ + status_local_fault_crx, + status_remote_fault_crx + })); + +endmodule +
tags/initial/rtl/verilog/sync_clk_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/generic_mem_small.v =================================================================== --- tags/initial/rtl/verilog/generic_mem_small.v (nonexistent) +++ tags/initial/rtl/verilog/generic_mem_small.v (revision 3) @@ -0,0 +1,183 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "generic_mem_small.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +/* synthesis ramstyle = "M512" */ + +module generic_mem_small( + + wclk, + wrst_n, + wen, + waddr, + wdata, + + rclk, + rrst_n, + ren, + roen, + raddr, + rdata +); + +//--- +// Parameters + +parameter DWIDTH = 32; +parameter AWIDTH = 3; +parameter RAM_DEPTH = (1 << AWIDTH); +parameter SYNC_WRITE = 1; +parameter SYNC_READ = 1; +parameter REGISTER_READ = 0; + +//--- +// Ports + +input wclk; +input wrst_n; +input wen; +input [AWIDTH:0] waddr; +input [DWIDTH-1:0] wdata; + +input rclk; +input rrst_n; +input ren; +input roen; +input [AWIDTH:0] raddr; +output [DWIDTH-1:0] rdata; + +// Registered outputs +reg [DWIDTH-1:0] rdata; + + +//--- +// Local declarations + +// Registers + +reg [DWIDTH-1:0] mem_rdata; + + +// Memory + +reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1]; + +// Variables + +integer i; + + +//--- +// Memory Write + +generate + if (SYNC_WRITE) begin + + // Generate synchronous write + always @(posedge wclk) + begin + if (wen) begin + mem[waddr[AWIDTH-1:0]] <= wdata; + end + end + end + else begin + + // Generate asynchronous write + always @(wen, waddr, wdata) + begin + if (wen) begin + mem[waddr[AWIDTH-1:0]] = wdata; + end + end + end +endgenerate + +//--- +// Memory Read + +generate + if (SYNC_READ) begin + + // Generate registered memory read + always @(posedge rclk or negedge rrst_n) + begin + if (!rrst_n) begin + mem_rdata <= {(DWIDTH){1'b0}}; + end else if (ren) begin + mem_rdata <= mem[raddr[AWIDTH-1:0]]; + end + end + end + else begin + + // Generate unregisters memory read + always @(raddr, rclk) + begin + mem_rdata = mem[raddr[AWIDTH-1:0]]; + end + end +endgenerate + +generate + if (REGISTER_READ) begin + + // Generate registered output + always @(posedge rclk or negedge rrst_n) + begin + if (!rrst_n) begin + rdata <= {(DWIDTH){1'b0}}; + end else if (roen) begin + rdata <= mem_rdata; + end + end + + end + else begin + + // Generate unregisters output + always @(mem_rdata) + begin + rdata = mem_rdata; + end + + end +endgenerate + +endmodule + + +
tags/initial/rtl/verilog/generic_mem_small.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/rx_hold_fifo.v =================================================================== --- tags/initial/rtl/verilog/rx_hold_fifo.v (nonexistent) +++ tags/initial/rtl/verilog/rx_hold_fifo.v (revision 3) @@ -0,0 +1,91 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "rx_hold_fifo.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module rx_hold_fifo(/*AUTOARG*/ + // Outputs + rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty, + rxhfifo_ralmost_empty, + // Inputs + clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus, + rxhfifo_wen, rxhfifo_ren + ); + +input clk_xgmii_rx; +input reset_xgmii_rx_n; + +input [63:0] rxhfifo_wdata; +input [7:0] rxhfifo_wstatus; +input rxhfifo_wen; + +input rxhfifo_ren; + +output [63:0] rxhfifo_rdata; +output [7:0] rxhfifo_rstatus; +output rxhfifo_rempty; +output rxhfifo_ralmost_empty; + +generic_fifo #( + .DWIDTH (72), + .AWIDTH (`RX_HOLD_FIFO_AWIDTH), + .REGISTER_READ (0), + .EARLY_READ (1), + .CLOCK_CROSSING (0), + .ALMOST_EMPTY_THRESH (7), + .MEM_TYPE (`MEM_AUTO_SMALL) +) +fifo0( + .wclk (clk_xgmii_rx), + .wrst_n (reset_xgmii_rx_n), + .wen (rxhfifo_wen), + .wdata ({rxhfifo_wstatus, rxhfifo_wdata}), + .wfull (), + .walmost_full (), + + .rclk (clk_xgmii_rx), + .rrst_n (reset_xgmii_rx_n), + .ren (rxhfifo_ren), + .rdata ({rxhfifo_rstatus, rxhfifo_rdata}), + .rempty (rxhfifo_rempty), + .ralmost_empty (rxhfifo_ralmost_empty) +); + + +endmodule +
tags/initial/rtl/verilog/rx_hold_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/xge_mac.v =================================================================== --- tags/initial/rtl/verilog/xge_mac.v (nonexistent) +++ tags/initial/rtl/verilog/xge_mac.v (revision 3) @@ -0,0 +1,388 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "xge_mac.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module xge_mac(/*AUTOARG*/ + // Outputs + xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full, + pkt_rx_val, pkt_rx_sop, pkt_rx_err, pkt_rx_eop, pkt_rx_data, + pkt_rx_avail, + // Inputs + xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i, + wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n, + reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_eop, pkt_tx_data, + pkt_rx_ren, clk_xgmii_tx, clk_xgmii_rx, clk_156m25 + ); + +/*AUTOINPUT*/ +// Beginning of automatic inputs (from unused autoinst inputs) +input clk_156m25; // To rx_dq0 of rx_dequeue.v, ... +input clk_xgmii_rx; // To rx_eq0 of rx_enqueue.v, ... +input clk_xgmii_tx; // To tx_dq0 of tx_dequeue.v, ... +input pkt_rx_ren; // To rx_dq0 of rx_dequeue.v +input [63:0] pkt_tx_data; // To tx_eq0 of tx_enqueue.v +input [7:0] pkt_tx_eop; // To tx_eq0 of tx_enqueue.v +input pkt_tx_sop; // To tx_eq0 of tx_enqueue.v +input pkt_tx_val; // To tx_eq0 of tx_enqueue.v +input reset_156m25_n; // To rx_dq0 of rx_dequeue.v, ... +input reset_xgmii_rx_n; // To rx_eq0 of rx_enqueue.v, ... +input reset_xgmii_tx_n; // To tx_dq0 of tx_dequeue.v, ... +input [7:0] wb_adr_i; // To wishbone_if0 of wishbone_if.v +input wb_clk_i; // To sync_clk_wb0 of sync_clk_wb.v, ... +input wb_cyc_i; // To wishbone_if0 of wishbone_if.v +input [31:0] wb_dat_i; // To wishbone_if0 of wishbone_if.v +input wb_rst_i; // To sync_clk_wb0 of sync_clk_wb.v, ... +input wb_stb_i; // To wishbone_if0 of wishbone_if.v +input wb_we_i; // To wishbone_if0 of wishbone_if.v +input [7:0] xgmii_rxc; // To rx_eq0 of rx_enqueue.v +input [63:0] xgmii_rxd; // To rx_eq0 of rx_enqueue.v +// End of automatics + +/*AUTOOUTPUT*/ +// Beginning of automatic outputs (from unused autoinst outputs) +output pkt_rx_avail; // From rx_dq0 of rx_dequeue.v +output [63:0] pkt_rx_data; // From rx_dq0 of rx_dequeue.v +output [7:0] pkt_rx_eop; // From rx_dq0 of rx_dequeue.v +output pkt_rx_err; // From rx_dq0 of rx_dequeue.v +output pkt_rx_sop; // From rx_dq0 of rx_dequeue.v +output pkt_rx_val; // From rx_dq0 of rx_dequeue.v +output pkt_tx_full; // From tx_eq0 of tx_enqueue.v +output wb_ack_o; // From wishbone_if0 of wishbone_if.v +output [31:0] wb_dat_o; // From wishbone_if0 of wishbone_if.v +output wb_int_o; // From wishbone_if0 of wishbone_if.v +output [7:0] xgmii_txc; // From tx_dq0 of tx_dequeue.v +output [63:0] xgmii_txd; // From tx_dq0 of tx_dequeue.v +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +wire ctrl_tx_enable; // From wishbone_if0 of wishbone_if.v +wire ctrl_tx_enable_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v +wire [1:0] local_fault_msg_det; // From rx_eq0 of rx_enqueue.v +wire [1:0] remote_fault_msg_det; // From rx_eq0 of rx_enqueue.v +wire rxdfifo_ralmost_empty; // From rx_data_fifo0 of rx_data_fifo.v +wire [63:0] rxdfifo_rdata; // From rx_data_fifo0 of rx_data_fifo.v +wire rxdfifo_rempty; // From rx_data_fifo0 of rx_data_fifo.v +wire rxdfifo_ren; // From rx_dq0 of rx_dequeue.v +wire [7:0] rxdfifo_rstatus; // From rx_data_fifo0 of rx_data_fifo.v +wire [63:0] rxdfifo_wdata; // From rx_eq0 of rx_enqueue.v +wire rxdfifo_wen; // From rx_eq0 of rx_enqueue.v +wire rxdfifo_wfull; // From rx_data_fifo0 of rx_data_fifo.v +wire [7:0] rxdfifo_wstatus; // From rx_eq0 of rx_enqueue.v +wire rxhfifo_ralmost_empty; // From rx_hold_fifo0 of rx_hold_fifo.v +wire [63:0] rxhfifo_rdata; // From rx_hold_fifo0 of rx_hold_fifo.v +wire rxhfifo_rempty; // From rx_hold_fifo0 of rx_hold_fifo.v +wire rxhfifo_ren; // From rx_eq0 of rx_enqueue.v +wire [7:0] rxhfifo_rstatus; // From rx_hold_fifo0 of rx_hold_fifo.v +wire [63:0] rxhfifo_wdata; // From rx_eq0 of rx_enqueue.v +wire rxhfifo_wen; // From rx_eq0 of rx_enqueue.v +wire [7:0] rxhfifo_wstatus; // From rx_eq0 of rx_enqueue.v +wire status_crc_error; // From sync_clk_wb0 of sync_clk_wb.v +wire status_crc_error_tog; // From rx_eq0 of rx_enqueue.v +wire status_fragment_error; // From sync_clk_wb0 of sync_clk_wb.v +wire status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v +wire status_local_fault; // From sync_clk_wb0 of sync_clk_wb.v +wire status_local_fault_crx; // From fault_sm0 of fault_sm.v +wire status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v +wire status_pause_frame_rx; // From sync_clk_wb0 of sync_clk_wb.v +wire status_pause_frame_rx_tog;// From rx_eq0 of rx_enqueue.v +wire status_remote_fault; // From sync_clk_wb0 of sync_clk_wb.v +wire status_remote_fault_crx;// From fault_sm0 of fault_sm.v +wire status_remote_fault_ctx;// From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v +wire status_rxdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v +wire status_rxdfifo_ovflow_tog;// From rx_eq0 of rx_enqueue.v +wire status_rxdfifo_udflow; // From sync_clk_wb0 of sync_clk_wb.v +wire status_rxdfifo_udflow_tog;// From rx_dq0 of rx_dequeue.v +wire status_txdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v +wire status_txdfifo_ovflow_tog;// From tx_eq0 of tx_enqueue.v +wire status_txdfifo_udflow; // From sync_clk_wb0 of sync_clk_wb.v +wire status_txdfifo_udflow_tog;// From tx_dq0 of tx_dequeue.v +wire txdfifo_ralmost_empty; // From tx_data_fifo0 of tx_data_fifo.v +wire [63:0] txdfifo_rdata; // From tx_data_fifo0 of tx_data_fifo.v +wire txdfifo_rempty; // From tx_data_fifo0 of tx_data_fifo.v +wire txdfifo_ren; // From tx_dq0 of tx_dequeue.v +wire [7:0] txdfifo_rstatus; // From tx_data_fifo0 of tx_data_fifo.v +wire txdfifo_walmost_full; // From tx_data_fifo0 of tx_data_fifo.v +wire [63:0] txdfifo_wdata; // From tx_eq0 of tx_enqueue.v +wire txdfifo_wen; // From tx_eq0 of tx_enqueue.v +wire txdfifo_wfull; // From tx_data_fifo0 of tx_data_fifo.v +wire [7:0] txdfifo_wstatus; // From tx_eq0 of tx_enqueue.v +wire txhfifo_ralmost_empty; // From tx_hold_fifo0 of tx_hold_fifo.v +wire [63:0] txhfifo_rdata; // From tx_hold_fifo0 of tx_hold_fifo.v +wire txhfifo_rempty; // From tx_hold_fifo0 of tx_hold_fifo.v +wire txhfifo_ren; // From tx_dq0 of tx_dequeue.v +wire [7:0] txhfifo_rstatus; // From tx_hold_fifo0 of tx_hold_fifo.v +wire txhfifo_walmost_full; // From tx_hold_fifo0 of tx_hold_fifo.v +wire [63:0] txhfifo_wdata; // From tx_dq0 of tx_dequeue.v +wire txhfifo_wen; // From tx_dq0 of tx_dequeue.v +wire txhfifo_wfull; // From tx_hold_fifo0 of tx_hold_fifo.v +wire [7:0] txhfifo_wstatus; // From tx_dq0 of tx_dequeue.v +// End of automatics + +rx_enqueue rx_eq0(/*AUTOINST*/ + // Outputs + .rxdfifo_wdata (rxdfifo_wdata[63:0]), + .rxdfifo_wstatus (rxdfifo_wstatus[7:0]), + .rxdfifo_wen (rxdfifo_wen), + .rxhfifo_ren (rxhfifo_ren), + .rxhfifo_wdata (rxhfifo_wdata[63:0]), + .rxhfifo_wstatus (rxhfifo_wstatus[7:0]), + .rxhfifo_wen (rxhfifo_wen), + .local_fault_msg_det (local_fault_msg_det[1:0]), + .remote_fault_msg_det (remote_fault_msg_det[1:0]), + .status_crc_error_tog (status_crc_error_tog), + .status_fragment_error_tog(status_fragment_error_tog), + .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog), + .status_pause_frame_rx_tog(status_pause_frame_rx_tog), + // Inputs + .clk_xgmii_rx (clk_xgmii_rx), + .reset_xgmii_rx_n (reset_xgmii_rx_n), + .xgmii_rxd (xgmii_rxd[63:0]), + .xgmii_rxc (xgmii_rxc[7:0]), + .rxdfifo_wfull (rxdfifo_wfull), + .rxhfifo_rdata (rxhfifo_rdata[63:0]), + .rxhfifo_rstatus (rxhfifo_rstatus[7:0]), + .rxhfifo_rempty (rxhfifo_rempty), + .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty)); + +rx_dequeue rx_dq0(/*AUTOINST*/ + // Outputs + .rxdfifo_ren (rxdfifo_ren), + .pkt_rx_data (pkt_rx_data[63:0]), + .pkt_rx_val (pkt_rx_val), + .pkt_rx_sop (pkt_rx_sop), + .pkt_rx_eop (pkt_rx_eop[7:0]), + .pkt_rx_err (pkt_rx_err), + .pkt_rx_avail (pkt_rx_avail), + .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog), + // Inputs + .clk_156m25 (clk_156m25), + .reset_156m25_n (reset_156m25_n), + .rxdfifo_rdata (rxdfifo_rdata[63:0]), + .rxdfifo_rstatus (rxdfifo_rstatus[7:0]), + .rxdfifo_rempty (rxdfifo_rempty), + .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty), + .pkt_rx_ren (pkt_rx_ren)); + +rx_data_fifo rx_data_fifo0(/*AUTOINST*/ + // Outputs + .rxdfifo_wfull(rxdfifo_wfull), + .rxdfifo_rdata(rxdfifo_rdata[63:0]), + .rxdfifo_rstatus(rxdfifo_rstatus[7:0]), + .rxdfifo_rempty(rxdfifo_rempty), + .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty), + // Inputs + .clk_xgmii_rx(clk_xgmii_rx), + .clk_156m25 (clk_156m25), + .reset_xgmii_rx_n(reset_xgmii_rx_n), + .reset_156m25_n(reset_156m25_n), + .rxdfifo_wdata(rxdfifo_wdata[63:0]), + .rxdfifo_wstatus(rxdfifo_wstatus[7:0]), + .rxdfifo_wen (rxdfifo_wen), + .rxdfifo_ren (rxdfifo_ren)); + +rx_hold_fifo rx_hold_fifo0(/*AUTOINST*/ + // Outputs + .rxhfifo_rdata(rxhfifo_rdata[63:0]), + .rxhfifo_rstatus(rxhfifo_rstatus[7:0]), + .rxhfifo_rempty(rxhfifo_rempty), + .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty), + // Inputs + .clk_xgmii_rx(clk_xgmii_rx), + .reset_xgmii_rx_n(reset_xgmii_rx_n), + .rxhfifo_wdata(rxhfifo_wdata[63:0]), + .rxhfifo_wstatus(rxhfifo_wstatus[7:0]), + .rxhfifo_wen (rxhfifo_wen), + .rxhfifo_ren (rxhfifo_ren)); + +tx_enqueue tx_eq0 (/*AUTOINST*/ + // Outputs + .pkt_tx_full (pkt_tx_full), + .txdfifo_wdata (txdfifo_wdata[63:0]), + .txdfifo_wstatus (txdfifo_wstatus[7:0]), + .txdfifo_wen (txdfifo_wen), + .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog), + // Inputs + .clk_156m25 (clk_156m25), + .reset_156m25_n (reset_156m25_n), + .pkt_tx_data (pkt_tx_data[63:0]), + .pkt_tx_val (pkt_tx_val), + .pkt_tx_sop (pkt_tx_sop), + .pkt_tx_eop (pkt_tx_eop[7:0]), + .txdfifo_wfull (txdfifo_wfull), + .txdfifo_walmost_full(txdfifo_walmost_full)); + +tx_dequeue tx_dq0(/*AUTOINST*/ + // Outputs + .txdfifo_ren (txdfifo_ren), + .txhfifo_ren (txhfifo_ren), + .txhfifo_wdata (txhfifo_wdata[63:0]), + .txhfifo_wstatus (txhfifo_wstatus[7:0]), + .txhfifo_wen (txhfifo_wen), + .xgmii_txd (xgmii_txd[63:0]), + .xgmii_txc (xgmii_txc[7:0]), + .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog), + // Inputs + .clk_xgmii_tx (clk_xgmii_tx), + .reset_xgmii_tx_n (reset_xgmii_tx_n), + .ctrl_tx_enable_ctx (ctrl_tx_enable_ctx), + .status_local_fault_ctx(status_local_fault_ctx), + .status_remote_fault_ctx(status_remote_fault_ctx), + .txdfifo_rdata (txdfifo_rdata[63:0]), + .txdfifo_rstatus (txdfifo_rstatus[7:0]), + .txdfifo_rempty (txdfifo_rempty), + .txdfifo_ralmost_empty(txdfifo_ralmost_empty), + .txhfifo_rdata (txhfifo_rdata[63:0]), + .txhfifo_rstatus (txhfifo_rstatus[7:0]), + .txhfifo_rempty (txhfifo_rempty), + .txhfifo_ralmost_empty(txhfifo_ralmost_empty), + .txhfifo_wfull (txhfifo_wfull), + .txhfifo_walmost_full (txhfifo_walmost_full)); + +tx_data_fifo tx_data_fifo0(/*AUTOINST*/ + // Outputs + .txdfifo_wfull(txdfifo_wfull), + .txdfifo_walmost_full(txdfifo_walmost_full), + .txdfifo_rdata(txdfifo_rdata[63:0]), + .txdfifo_rstatus(txdfifo_rstatus[7:0]), + .txdfifo_rempty(txdfifo_rempty), + .txdfifo_ralmost_empty(txdfifo_ralmost_empty), + // Inputs + .clk_xgmii_tx(clk_xgmii_tx), + .clk_156m25 (clk_156m25), + .reset_xgmii_tx_n(reset_xgmii_tx_n), + .reset_156m25_n(reset_156m25_n), + .txdfifo_wdata(txdfifo_wdata[63:0]), + .txdfifo_wstatus(txdfifo_wstatus[7:0]), + .txdfifo_wen (txdfifo_wen), + .txdfifo_ren (txdfifo_ren)); + +tx_hold_fifo tx_hold_fifo0(/*AUTOINST*/ + // Outputs + .txhfifo_wfull(txhfifo_wfull), + .txhfifo_walmost_full(txhfifo_walmost_full), + .txhfifo_rdata(txhfifo_rdata[63:0]), + .txhfifo_rstatus(txhfifo_rstatus[7:0]), + .txhfifo_rempty(txhfifo_rempty), + .txhfifo_ralmost_empty(txhfifo_ralmost_empty), + // Inputs + .clk_xgmii_tx(clk_xgmii_tx), + .reset_xgmii_tx_n(reset_xgmii_tx_n), + .txhfifo_wdata(txhfifo_wdata[63:0]), + .txhfifo_wstatus(txhfifo_wstatus[7:0]), + .txhfifo_wen (txhfifo_wen), + .txhfifo_ren (txhfifo_ren)); + +fault_sm fault_sm0(/*AUTOINST*/ + // Outputs + .status_local_fault_crx(status_local_fault_crx), + .status_remote_fault_crx(status_remote_fault_crx), + // Inputs + .clk_xgmii_rx (clk_xgmii_rx), + .reset_xgmii_rx_n (reset_xgmii_rx_n), + .local_fault_msg_det (local_fault_msg_det[1:0]), + .remote_fault_msg_det(remote_fault_msg_det[1:0])); + +sync_clk_wb sync_clk_wb0(/*AUTOINST*/ + // Outputs + .status_crc_error(status_crc_error), + .status_fragment_error(status_fragment_error), + .status_txdfifo_ovflow(status_txdfifo_ovflow), + .status_txdfifo_udflow(status_txdfifo_udflow), + .status_rxdfifo_ovflow(status_rxdfifo_ovflow), + .status_rxdfifo_udflow(status_rxdfifo_udflow), + .status_pause_frame_rx(status_pause_frame_rx), + .status_local_fault(status_local_fault), + .status_remote_fault(status_remote_fault), + // Inputs + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .status_crc_error_tog(status_crc_error_tog), + .status_fragment_error_tog(status_fragment_error_tog), + .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog), + .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog), + .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog), + .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog), + .status_pause_frame_rx_tog(status_pause_frame_rx_tog), + .status_local_fault_crx(status_local_fault_crx), + .status_remote_fault_crx(status_remote_fault_crx)); + +sync_clk_xgmii_tx sync_clk_xgmii_tx0(/*AUTOINST*/ + // Outputs + .ctrl_tx_enable_ctx(ctrl_tx_enable_ctx), + .status_local_fault_ctx(status_local_fault_ctx), + .status_remote_fault_ctx(status_remote_fault_ctx), + // Inputs + .clk_xgmii_tx(clk_xgmii_tx), + .reset_xgmii_tx_n(reset_xgmii_tx_n), + .ctrl_tx_enable(ctrl_tx_enable), + .status_local_fault_crx(status_local_fault_crx), + .status_remote_fault_crx(status_remote_fault_crx)); + +sync_clk_core sync_clk_core0(/*AUTOINST*/ + // Inputs + .clk_xgmii_tx(clk_xgmii_tx), + .reset_xgmii_tx_n(reset_xgmii_tx_n)); + +wishbone_if wishbone_if0(/*AUTOINST*/ + // Outputs + .wb_dat_o (wb_dat_o[31:0]), + .wb_ack_o (wb_ack_o), + .wb_int_o (wb_int_o), + .ctrl_tx_enable(ctrl_tx_enable), + // Inputs + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wb_adr_i (wb_adr_i[7:0]), + .wb_dat_i (wb_dat_i[31:0]), + .wb_we_i (wb_we_i), + .wb_stb_i (wb_stb_i), + .wb_cyc_i (wb_cyc_i), + .status_crc_error(status_crc_error), + .status_fragment_error(status_fragment_error), + .status_txdfifo_ovflow(status_txdfifo_ovflow), + .status_txdfifo_udflow(status_txdfifo_udflow), + .status_rxdfifo_ovflow(status_rxdfifo_ovflow), + .status_rxdfifo_udflow(status_rxdfifo_udflow), + .status_pause_frame_rx(status_pause_frame_rx), + .status_local_fault(status_local_fault), + .status_remote_fault(status_remote_fault)); + +endmodule +
tags/initial/rtl/verilog/xge_mac.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/generic_fifo_ctrl.v =================================================================== --- tags/initial/rtl/verilog/generic_fifo_ctrl.v (nonexistent) +++ tags/initial/rtl/verilog/generic_fifo_ctrl.v (revision 3) @@ -0,0 +1,270 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "generic_fifo_ctrl.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module generic_fifo_ctrl( + + wclk, + wrst_n, + wen, + wfull, + walmost_full, + + mem_wen, + mem_waddr, + + rclk, + rrst_n, + ren, + rempty, + ralmost_empty, + + mem_ren, + mem_raddr +); + +//--- +// Parameters + +parameter AWIDTH = 3; +parameter RAM_DEPTH = (1 << AWIDTH); +parameter EARLY_READ = 0; +parameter CLOCK_CROSSING = 1; +parameter ALMOST_EMPTY_THRESH = 1; +parameter ALMOST_FULL_THRESH = RAM_DEPTH-2; + +//--- +// Ports + +input wclk; +input wrst_n; +input wen; +output wfull; +output walmost_full; + +output mem_wen; +output [AWIDTH:0] mem_waddr; + +input rclk; +input rrst_n; +input ren; +output rempty; +output ralmost_empty; + +output mem_ren; +output [AWIDTH:0] mem_raddr; + + + +//--- +// Local declarations + +// Registers + +reg [AWIDTH:0] wr_ptr; +reg [AWIDTH:0] rd_ptr; +reg [AWIDTH:0] next_rd_ptr; + +// Combinatorial + +wire [AWIDTH:0] wr_gray; +reg [AWIDTH:0] wr_gray_meta; +reg [AWIDTH:0] wr_gray_sync; +reg [AWIDTH:0] wck_rd_ptr; +wire [AWIDTH:0] wck_level; + +wire [AWIDTH:0] rd_gray; +reg [AWIDTH:0] rd_gray_meta; +reg [AWIDTH:0] rd_gray_sync; +reg [AWIDTH:0] rck_wr_ptr; +wire [AWIDTH:0] rck_level; + +wire [AWIDTH:0] depth; +wire [AWIDTH:0] empty_thresh; +wire [AWIDTH:0] full_thresh; + +// Variables + +integer i; + +//--- +// Assignments + +assign depth = RAM_DEPTH[AWIDTH:0]; +assign empty_thresh = ALMOST_EMPTY_THRESH[AWIDTH:0]; +assign full_thresh = ALMOST_FULL_THRESH[AWIDTH:0]; + +assign wfull = (wck_level == depth); +assign walmost_full = (wck_level >= (depth - full_thresh)); +assign rempty = (rck_level == 0); +assign ralmost_empty = (rck_level <= empty_thresh); + +//--- +// Write Pointer + +always @(posedge wclk or negedge wrst_n) +begin + if (!wrst_n) begin + wr_ptr <= {(AWIDTH+1){1'b0}}; + end + else if (wen && !wfull) begin + wr_ptr <= wr_ptr + {{(AWIDTH){1'b0}}, 1'b1}; + end +end + +//--- +// Read Pointer + +always @(ren, rd_ptr, rck_wr_ptr) +begin + next_rd_ptr = rd_ptr; + if (ren && rd_ptr != rck_wr_ptr) begin + next_rd_ptr = rd_ptr + {{(AWIDTH){1'b0}}, 1'b1}; + end +end + +always @(posedge rclk or negedge rrst_n) +begin + if (!rrst_n) begin + rd_ptr <= {(AWIDTH+1){1'b0}}; + end + else begin + rd_ptr <= next_rd_ptr; + end +end + +//--- +// Binary to Gray conversion + +assign wr_gray = wr_ptr ^ (wr_ptr >> 1); +assign rd_gray = rd_ptr ^ (rd_ptr >> 1); + +//--- +// Gray to Binary conversion + +always @(wr_gray_sync) +begin + rck_wr_ptr[AWIDTH] = wr_gray_sync[AWIDTH]; + for (i = 0; i < AWIDTH; i = i + 1) begin + rck_wr_ptr[AWIDTH-i-1] = rck_wr_ptr[AWIDTH-i] ^ wr_gray_sync[AWIDTH-i-1]; + end +end + +always @(rd_gray_sync) +begin + wck_rd_ptr[AWIDTH] = rd_gray_sync[AWIDTH]; + for (i = 0; i < AWIDTH; i = i + 1) begin + wck_rd_ptr[AWIDTH-i-1] = wck_rd_ptr[AWIDTH-i] ^ rd_gray_sync[AWIDTH-i-1]; + end +end + +//--- +// Clock-Domain Crossing + +generate + if (CLOCK_CROSSING) begin + + // Instantiate metastability flops + always @(posedge rclk or negedge rrst_n) + begin + if (!rrst_n) begin + wr_gray_meta <= {(AWIDTH+1){1'b0}}; + wr_gray_sync <= {(AWIDTH+1){1'b0}}; + end + else begin + wr_gray_meta <= wr_gray; + wr_gray_sync <= wr_gray_meta; + end + end + + always @(posedge wclk or negedge wrst_n) + begin + if (!wrst_n) begin + rd_gray_meta <= {(AWIDTH+1){1'b0}}; + rd_gray_sync <= {(AWIDTH+1){1'b0}}; + end + else begin + rd_gray_meta <= rd_gray; + rd_gray_sync <= rd_gray_meta; + end + end + end + else begin + + // No clock domain crossing + always @(wr_gray or rd_gray) + begin + wr_gray_sync = wr_gray; + rd_gray_sync = rd_gray; + end + end +endgenerate + +//--- +// FIFO Level + +assign wck_level = wr_ptr - wck_rd_ptr; +assign rck_level = rck_wr_ptr - rd_ptr; + +//--- +// Memory controls + +assign mem_waddr = wr_ptr; +assign mem_wen = wen && !wfull; + +generate + if (EARLY_READ) begin + + // With early read, data will be present at output + // before ren is asserted. Usufull if we want to add + // an output register and not add latency. + assign mem_raddr = next_rd_ptr; + assign mem_ren = 1'b1; + + end + else begin + + assign mem_raddr = rd_ptr; + assign mem_ren = ren; + + end +endgenerate + +endmodule + + +
tags/initial/rtl/verilog/generic_fifo_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/tx_hold_fifo.v =================================================================== --- tags/initial/rtl/verilog/tx_hold_fifo.v (nonexistent) +++ tags/initial/rtl/verilog/tx_hold_fifo.v (revision 3) @@ -0,0 +1,94 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "tx_hold_fifo.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module tx_hold_fifo(/*AUTOARG*/ + // Outputs + txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata, + txhfifo_rstatus, txhfifo_rempty, txhfifo_ralmost_empty, + // Inputs + clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus, + txhfifo_wen, txhfifo_ren + ); + +input clk_xgmii_tx; +input reset_xgmii_tx_n; + +input [63:0] txhfifo_wdata; +input [7:0] txhfifo_wstatus; +input txhfifo_wen; + +input txhfifo_ren; + +output txhfifo_wfull; +output txhfifo_walmost_full; + +output [63:0] txhfifo_rdata; +output [7:0] txhfifo_rstatus; +output txhfifo_rempty; +output txhfifo_ralmost_empty; + +generic_fifo #( + .DWIDTH (72), + .AWIDTH (`TX_HOLD_FIFO_AWIDTH), + .REGISTER_READ (1), + .EARLY_READ (1), + .CLOCK_CROSSING (0), + .ALMOST_EMPTY_THRESH (7), + .ALMOST_FULL_THRESH (6), + .MEM_TYPE (`MEM_AUTO_SMALL) +) +fifo0( + .wclk (clk_xgmii_tx), + .wrst_n (reset_xgmii_tx_n), + .wen (txhfifo_wen), + .wdata ({txhfifo_wstatus, txhfifo_wdata}), + .wfull (txhfifo_wfull), + .walmost_full (txhfifo_walmost_full), + + .rclk (clk_xgmii_tx), + .rrst_n (reset_xgmii_tx_n), + .ren (txhfifo_ren), + .rdata ({txhfifo_rstatus, txhfifo_rdata}), + .rempty (txhfifo_rempty), + .ralmost_empty (txhfifo_ralmost_empty) +); + +endmodule +
tags/initial/rtl/verilog/tx_hold_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/rx_dequeue.v =================================================================== --- tags/initial/rtl/verilog/rx_dequeue.v (nonexistent) +++ tags/initial/rtl/verilog/rx_dequeue.v (revision 3) @@ -0,0 +1,207 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "rx_dequeue.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module rx_dequeue(/*AUTOARG*/ + // Outputs + rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop, + pkt_rx_err, pkt_rx_avail, status_rxdfifo_udflow_tog, + // Inputs + clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus, + rxdfifo_rempty, rxdfifo_ralmost_empty, pkt_rx_ren + ); + +input clk_156m25; +input reset_156m25_n; + +input [63:0] rxdfifo_rdata; +input [7:0] rxdfifo_rstatus; +input rxdfifo_rempty; +input rxdfifo_ralmost_empty; + +input pkt_rx_ren; + +output rxdfifo_ren; + +output [63:0] pkt_rx_data; +output pkt_rx_val; +output pkt_rx_sop; +output [7:0] pkt_rx_eop; +output pkt_rx_err; +output pkt_rx_avail; + +output status_rxdfifo_udflow_tog; + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg pkt_rx_avail; +reg [63:0] pkt_rx_data; +reg [7:0] pkt_rx_eop; +reg pkt_rx_err; +reg pkt_rx_sop; +reg pkt_rx_val; +reg status_rxdfifo_udflow_tog; +// End of automatics + +reg end_eop; + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +wire [7:0] eop; + + +// End eop to force one cycle between packets + +assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop; + + + +// EOP position is stored in status portion of rx data fifo. +// If we read an EOP indicator, set the corresponding eop line. + +assign eop[0] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP0; +assign eop[1] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP1; +assign eop[2] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP2; +assign eop[3] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP3; +assign eop[4] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP4; +assign eop[5] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP5; +assign eop[6] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP6; +assign eop[7] = rxdfifo_rstatus[3:0] == `RXSTATUS_EOP7; + + +always @(posedge clk_156m25 or negedge reset_156m25_n) begin + + if (reset_156m25_n == 1'b0) begin + + pkt_rx_avail <= 1'b0; + + pkt_rx_data <= 64'b0; + pkt_rx_sop <= 1'b0; + pkt_rx_eop <= 8'b0; + pkt_rx_err <= 1'b0; + + pkt_rx_val <= 1'b0; + + end_eop <= 1'b0; + + status_rxdfifo_udflow_tog <= 1'b0; + + end + else begin + + pkt_rx_avail <= !rxdfifo_ralmost_empty; + + + + // If eop shows up at the output of the fifo, we drive eop on + // the bus on the next read. This will be the last read for this + // packet. The fifo is designed to output data early. On last read, + // data from next packet will appear at the output of fifo. + + pkt_rx_eop <= {8{rxdfifo_ren}} & eop; + + + pkt_rx_val <= rxdfifo_ren; + + if (rxdfifo_ren) begin + + pkt_rx_data <= rxdfifo_rdata; + + end + + + if (rxdfifo_ren && rxdfifo_rstatus[3:0] == `RXSTATUS_SOP) begin + + // SOP indication on first word + + pkt_rx_sop <= 1'b1; + pkt_rx_err <= 1'b0; + + end + else begin + + pkt_rx_sop <= 1'b0; + + + // Give an error if FIFO is to underflow + + if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin + pkt_rx_val <= 1'b1; + pkt_rx_eop <= 8'b1; + pkt_rx_err <= 1'b1; + end + + end + + + if (rxdfifo_ren && |(rxdfifo_rstatus[7:4] & `RXSTATUS_ERR)) begin + + // Status stored in FIFO is propagated to error signal. + + pkt_rx_err <= 1'b1; + + end + + + //--- + // EOP indication at the end of the frame. Cleared otherwise. + + if (rxdfifo_ren && |eop) begin + end_eop <= 1'b1; + end + else if (pkt_rx_ren) begin + end_eop <= 1'b0; + end + + + + //--- + // FIFO errors, used to generate interrupts + + if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin + status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog; + end + + end +end + +endmodule +
tags/initial/rtl/verilog/rx_dequeue.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/tx_dequeue.v =================================================================== --- tags/initial/rtl/verilog/tx_dequeue.v (nonexistent) +++ tags/initial/rtl/verilog/tx_dequeue.v (revision 3) @@ -0,0 +1,913 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "tx_dequeue.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module tx_dequeue(/*AUTOARG*/ + // Outputs + txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus, + txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog, + // Inputs + clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx, + status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata, + txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty, + txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty, + txhfifo_ralmost_empty, txhfifo_wfull, txhfifo_walmost_full + ); +`include "CRC32_D64.v" +`include "CRC32_D8.v" +`include "utils.v" + +input clk_xgmii_tx; +input reset_xgmii_tx_n; + +input ctrl_tx_enable_ctx; + +input status_local_fault_ctx; +input status_remote_fault_ctx; + +input [63:0] txdfifo_rdata; +input [7:0] txdfifo_rstatus; +input txdfifo_rempty; +input txdfifo_ralmost_empty; + +input [63:0] txhfifo_rdata; +input [7:0] txhfifo_rstatus; +input txhfifo_rempty; +input txhfifo_ralmost_empty; + +input txhfifo_wfull; +input txhfifo_walmost_full; + +output txdfifo_ren; + +output txhfifo_ren; + +output [63:0] txhfifo_wdata; +output [7:0] txhfifo_wstatus; +output txhfifo_wen; + +output [63:0] xgmii_txd; +output [7:0] xgmii_txc; + +output status_txdfifo_udflow_tog; + + + + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg status_txdfifo_udflow_tog; +reg txdfifo_ren; +reg txhfifo_ren; +reg [63:0] txhfifo_wdata; +reg txhfifo_wen; +reg [7:0] txhfifo_wstatus; +reg [7:0] xgmii_txc; +reg [63:0] xgmii_txd; +// End of automatics + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + + +reg [63:0] xgxs_txd; +reg [7:0] xgxs_txc; + +reg [63:0] next_xgxs_txd; +reg [7:0] next_xgxs_txc; + +reg [2:0] curr_state; +reg [2:0] next_state; + +reg [1:0] curr_state_rd; +reg [1:0] next_state_rd; + +reg start_on_lane0; +reg next_start_on_lane0; + +reg [2:0] ifg_deficit; +reg [2:0] next_ifg_deficit; + +reg ifg_4b_add; +reg next_ifg_4b_add; + +reg ifg_8b_add; +reg next_ifg_8b_add; + +reg ifg_8b2_add; +reg next_ifg_8b2_add; + +reg [63:32] xgxs_txd_barrel; +reg [7:4] xgxs_txc_barrel; + +reg [63:0] txhfifo_rdata_d1; + +reg txdfifo_ralmost_empty_d1; +reg txdfifo_ralmost_empty_d2; + +reg [13:0] byte_cnt; + +reg [31:0] crc32_d64; +reg [31:0] crc32_d8; +reg [31:0] crc32_tx; + +reg [63:0] shift_crc_data; +reg [7:0] shift_crc_eop; +reg [2:0] shift_crc_cnt; + +reg [31:0] crc_data; + +reg frame_available; +reg next_frame_available; + +reg [63:0] next_txhfifo_wdata; +reg [7:0] next_txhfifo_wstatus; +reg next_txhfifo_wen; + +parameter [2:0] + SM_IDLE = 3'd0, + SM_PREAMBLE = 3'd1, + SM_TX = 3'd2, + SM_EOP = 3'd3, + SM_TERM = 3'd4, + SM_TERM_FAIL = 3'd5, + SM_IFG = 3'd6; + +parameter [1:0] + SM_RD_IDLE = 2'd0, + SM_RD_EQ = 2'd1, + SM_RD_PAD = 2'd2; + + +//--- +// RC layer + +always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin + + if (reset_xgmii_tx_n == 1'b0) begin + + xgmii_txd <= {8{`IDLE}}; + xgmii_txc <= 8'hff; + + end + else begin + + + //--- + // RC Layer, insert local or remote fault messages based on status + // of fault state-machine + + if (status_local_fault_ctx) begin + + // If local fault detected, send remote fault message to + // link partner + + xgmii_txd <= {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE, + `REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE}; + xgmii_txc <= {4'b0001, 4'b0001}; + end + else if (status_remote_fault_ctx) begin + + // If remote fault detected, inhibit transmission and send + // idle codes + + xgmii_txd <= {8{`IDLE}}; + xgmii_txc <= 8'hff; + end + else begin + xgmii_txd <= xgxs_txd; + xgmii_txc <= xgxs_txc; + end + end + +end + + +always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin + + if (reset_xgmii_tx_n == 1'b0) begin + + curr_state <= SM_IDLE; + + start_on_lane0 <= 1'b1; + ifg_deficit <= 3'b0; + ifg_4b_add <= 1'b0; + ifg_8b_add <= 1'b0; + ifg_8b2_add <= 1'b0; + + txhfifo_rdata_d1 <= 64'b0; + + xgxs_txd_barrel <= {4{`IDLE}}; + xgxs_txc_barrel <= 4'hf; + + txdfifo_ralmost_empty_d1 <= 1'b1; + txdfifo_ralmost_empty_d2 <= 1'b1; + + frame_available <= 1'b0; + + xgxs_txd <= {8{`IDLE}}; + xgxs_txc <= 8'hff; + + status_txdfifo_udflow_tog <= 1'b0; + + end + else begin + + curr_state <= next_state; + + start_on_lane0 <= next_start_on_lane0; + ifg_deficit <= next_ifg_deficit; + ifg_4b_add <= next_ifg_4b_add; + ifg_8b_add <= next_ifg_8b_add; + ifg_8b2_add <= next_ifg_8b2_add; + + txhfifo_rdata_d1 <= txhfifo_rdata; + + xgxs_txd_barrel <= next_xgxs_txd[63:32]; + xgxs_txc_barrel <= next_xgxs_txc[7:4]; + + txdfifo_ralmost_empty_d1 <= txdfifo_ralmost_empty; + txdfifo_ralmost_empty_d2 <= txdfifo_ralmost_empty_d1; + + frame_available <= next_frame_available; + + //--- + // Barrel shifter. Previous stage always align packet with LANE0. + // This stage allow us to shift packet to align with LANE4 if needed + // for correct inter frame gap (IFG). + + if (next_start_on_lane0) begin + + xgxs_txd <= next_xgxs_txd; + xgxs_txc <= next_xgxs_txc; + + end + else begin + + xgxs_txd <= {next_xgxs_txd[31:0], xgxs_txd_barrel}; + xgxs_txc <= {next_xgxs_txc[3:0], xgxs_txc_barrel}; + + end + + //--- + // FIFO errors, used to generate interrupts. + + if (txdfifo_ren && txdfifo_rempty) begin + status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog; + end + + end + +end + +always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state + or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add + or ifg_deficit or start_on_lane0 or status_local_fault_ctx + or txhfifo_ralmost_empty or txhfifo_rdata_d1 + or txhfifo_rempty or txhfifo_rstatus) begin + + next_state = curr_state; + + next_start_on_lane0 = start_on_lane0; + next_ifg_deficit = ifg_deficit; + next_ifg_4b_add = ifg_4b_add; + next_ifg_8b_add = ifg_8b_add; + next_ifg_8b2_add = ifg_8b2_add; + + next_xgxs_txd = {8{`IDLE}}; + next_xgxs_txc = 8'hff; + + txhfifo_ren = 1'b0; + + next_frame_available = frame_available; + + case (curr_state) + + SM_IDLE: + begin + + // Wait for frame to be available. There should be a least N bytes in the + // data fifo or a crc in the control fifo. The N bytes in the data fifo + // give time to the enqueue engine to calculate crc and write it to the + // control fifo. If crc is already in control fifo we can start transmitting + // with no concern. Transmission is inhibited if local or remote faults + // are detected. + + if (ctrl_tx_enable_ctx && frame_available && + !status_local_fault_ctx && !status_local_fault_ctx) begin + + txhfifo_ren = 1'b1; + next_state = SM_PREAMBLE; + + end + else begin + + next_frame_available = !txhfifo_ralmost_empty; + next_ifg_4b_add = 1'b0; + + end + + end + + SM_PREAMBLE: + begin + + txhfifo_ren = 1'b1; + + + // On reading SOP from fifo, send SFD and preamble characters + + if (txhfifo_rstatus == `TXSTATUS_SOP) begin + + next_xgxs_txd = {`SFD, {6{`PREAMBLE}}, `START}; + next_xgxs_txc = 8'h01; + + end + + + // Depending on deficit idle count calculations, add 4 bytes + // or IFG or not. This will determine on which lane start the + // next frame. + + if (ifg_4b_add) begin + next_start_on_lane0 = 1'b0; + end + else begin + next_start_on_lane0 = 1'b1; + end + + next_state = SM_TX; + + end + + SM_TX: + begin + + next_xgxs_txd = txhfifo_rdata_d1; + next_xgxs_txc = 8'h00; + + txhfifo_ren = 1'b1; + + + // Wait for EOP indication to be read from the fifo, then + // transition to next state. + + if (txhfifo_rstatus == `TXSTATUS_EOP0 || + txhfifo_rstatus == `TXSTATUS_EOP1 || + txhfifo_rstatus == `TXSTATUS_EOP2 || + txhfifo_rstatus == `TXSTATUS_EOP3 || + txhfifo_rstatus == `TXSTATUS_EOP4 || + txhfifo_rstatus == `TXSTATUS_EOP5 || + txhfifo_rstatus == `TXSTATUS_EOP6 || + txhfifo_rstatus == `TXSTATUS_EOP7) begin + + txhfifo_ren = 1'b0; + next_frame_available = !txhfifo_ralmost_empty; + next_state = SM_EOP; + end + else if (txhfifo_rempty) begin + + // Failure condition, we did not see EOP and there + // is no more data in fifo, force end of packet transmit. + + next_state = SM_TERM_FAIL; + + end + + end + + SM_EOP: + begin + + // Insert TERMINATE character in correct lane depending on position + // of EOP read from fifo. Also insert CRC read from control fifo. + + if (txhfifo_rstatus[0]) begin + next_xgxs_txd = {{2{`IDLE}}, `TERMINATE, + crc32_tx[31:0], txhfifo_rdata_d1[7:0]}; + next_xgxs_txc = 8'b11100000; + end + + if (txhfifo_rstatus[1]) begin + next_xgxs_txd = {`IDLE, `TERMINATE, + crc32_tx[31:0], txhfifo_rdata_d1[15:0]}; + next_xgxs_txc = 8'b11000000; + end + + if (txhfifo_rstatus[2]) begin + next_xgxs_txd = {`TERMINATE, crc32_tx[31:0], txhfifo_rdata_d1[23:0]}; + next_xgxs_txc = 8'b10000000; + end + + if (txhfifo_rstatus[3]) begin + next_xgxs_txd = {crc32_tx[31:0], txhfifo_rdata_d1[31:0]}; + next_xgxs_txc = 8'b00000000; + end + + if (txhfifo_rstatus[4]) begin + next_xgxs_txd = {crc32_tx[23:0], txhfifo_rdata_d1[39:0]}; + next_xgxs_txc = 8'b00000000; + end + + if (txhfifo_rstatus[5]) begin + next_xgxs_txd = {crc32_tx[15:0], txhfifo_rdata_d1[47:0]}; + next_xgxs_txc = 8'b00000000; + end + + if (txhfifo_rstatus[6]) begin + next_xgxs_txd = {crc32_tx[7:0], txhfifo_rdata_d1[55:0]}; + next_xgxs_txc = 8'b00000000; + end + + if (txhfifo_rstatus[7]) begin + next_xgxs_txd = {txhfifo_rdata_d1[63:0]}; + next_xgxs_txc = 8'b00000000; + end + + if (!frame_available) begin + + // If there is not another frame ready to be transmitted, interface + // will go idle and idle deficit idle count calculation is irrelevant. + // Set deficit to 0. + + next_ifg_deficit = 3'b0; + + end + else begin + + // Idle deficit count calculated based on number of "wasted" bytes + // between TERMINATE and alignment of next frame in LANE0. + + next_ifg_deficit = ifg_deficit + + {2'b0, txhfifo_rstatus[0] | txhfifo_rstatus[4]} + + {1'b0, txhfifo_rstatus[1] | txhfifo_rstatus[5], 1'b0} + + {1'b0, txhfifo_rstatus[2] | txhfifo_rstatus[6], + txhfifo_rstatus[2] | txhfifo_rstatus[6]}; + end + + // IFG corrections based on deficit count and previous starting lane + // Calculated based on following table: + // + // DIC=0 DIC=1 DIC=2 DIC=3 + // ------------- ------------- ------------- ------------- + // PktLen IFG Next IFG Next IFG Next IFG Next + // Modulus Length DIC Length DIC Length DIC Length DIC + // ----------------------------------------------------------------------- + // 0 12 0 12 1 12 2 12 3 + // 1 11 1 11 2 11 3 15 0 + // 2 10 2 10 3 14 0 14 1 + // 3 9 3 13 0 13 1 13 2 + // + // + // In logic it translates into adding 4, 8, or 12 bytes of IFG relative + // to LANE0. + // IFG and Add columns assume no deficit applied + // IFG+DIC and Add+DIC assume deficit must be applied + // + // Start lane 0 Start lane 4 + // EOP Pads IFG IFG+DIC Add Add+DIC Add Add IFG + // 0 3 11 15 8 12 12 16 + // 1 2 10 14 8 12 12 16 + // 2 1 9 13 8 12 12 16 + // 3 8 12 12 4 4 8 8 + // 4 7 11 15 4 8 8 12 + // 5 6 10 14 4 8 8 12 + // 6 5 9 13 4 8 8 12 + // 7 4 12 12 8 8 12 12 + + if (!frame_available) begin + + // If there is not another frame ready to be transmitted, interface + // will go idle and idle deficit idle count calculation is irrelevant. + + next_ifg_4b_add = 1'b0; + next_ifg_8b_add = 1'b0; + next_ifg_8b2_add = 1'b0; + + end + else if (next_ifg_deficit[2] == ifg_deficit[2]) begin + + // Add 4 bytes IFG + + next_ifg_4b_add = (txhfifo_rstatus[0] & !start_on_lane0) | + (txhfifo_rstatus[1] & !start_on_lane0) | + (txhfifo_rstatus[2] & !start_on_lane0) | + (txhfifo_rstatus[3] & start_on_lane0) | + (txhfifo_rstatus[4] & start_on_lane0) | + (txhfifo_rstatus[5] & start_on_lane0) | + (txhfifo_rstatus[6] & start_on_lane0) | + (txhfifo_rstatus[7] & !start_on_lane0); + + // Add 8 bytes IFG + + next_ifg_8b_add = (txhfifo_rstatus[0]) | + (txhfifo_rstatus[1]) | + (txhfifo_rstatus[2]) | + (txhfifo_rstatus[3] & !start_on_lane0) | + (txhfifo_rstatus[4] & !start_on_lane0) | + (txhfifo_rstatus[5] & !start_on_lane0) | + (txhfifo_rstatus[6] & !start_on_lane0) | + (txhfifo_rstatus[7]); + + // Add another 8 bytes IFG + + next_ifg_8b2_add = 1'b0; + + end + else begin + + // Add 4 bytes IFG + + next_ifg_4b_add = (txhfifo_rstatus[0] & start_on_lane0) | + (txhfifo_rstatus[1] & start_on_lane0) | + (txhfifo_rstatus[2] & start_on_lane0) | + (txhfifo_rstatus[3] & start_on_lane0) | + (txhfifo_rstatus[4] & !start_on_lane0) | + (txhfifo_rstatus[5] & !start_on_lane0) | + (txhfifo_rstatus[6] & !start_on_lane0) | + (txhfifo_rstatus[7] & !start_on_lane0); + + // Add 8 bytes IFG + + next_ifg_8b_add = (txhfifo_rstatus[0]) | + (txhfifo_rstatus[1]) | + (txhfifo_rstatus[2]) | + (txhfifo_rstatus[3] & !start_on_lane0) | + (txhfifo_rstatus[4]) | + (txhfifo_rstatus[5]) | + (txhfifo_rstatus[6]) | + (txhfifo_rstatus[7]); + + // Add another 8 bytes IFG + + next_ifg_8b2_add = (txhfifo_rstatus[0] & !start_on_lane0) | + (txhfifo_rstatus[1] & !start_on_lane0) | + (txhfifo_rstatus[2] & !start_on_lane0); + + end + + if (|txhfifo_rstatus[2:0]) begin + + if (frame_available) begin + + // Next state depends on number of IFG bytes to be inserted. + // Skip idle state if needed. + + if (next_ifg_8b2_add) begin + next_state = SM_IFG; + end + else if (next_ifg_8b_add) begin + next_state = SM_IDLE; + end + else begin + txhfifo_ren = 1'b1; + next_state = SM_PREAMBLE; + end + + end + else begin + next_state = SM_IFG; + end + end + + if (|txhfifo_rstatus[7:3]) begin + next_state = SM_TERM; + end + + end + + SM_TERM: + begin + + // Insert TERMINATE character in correct lane depending on position + // of EOP read from fifo. Also insert CRC read from control fifo. + + if (txhfifo_rstatus[3]) begin + next_xgxs_txd = {{7{`IDLE}}, `TERMINATE}; + next_xgxs_txc = 8'b11111111; + end + + if (txhfifo_rstatus[4]) begin + next_xgxs_txd = {{6{`IDLE}}, `TERMINATE, crc32_tx[31:24]}; + next_xgxs_txc = 8'b11111110; + end + + if (txhfifo_rstatus[5]) begin + next_xgxs_txd = {{5{`IDLE}}, `TERMINATE, crc32_tx[31:16]}; + next_xgxs_txc = 8'b11111100; + end + + if (txhfifo_rstatus[6]) begin + next_xgxs_txd = {{4{`IDLE}}, `TERMINATE, crc32_tx[31:8]}; + next_xgxs_txc = 8'b11111000; + end + + if (txhfifo_rstatus[7]) begin + next_xgxs_txd = {{3{`IDLE}}, `TERMINATE, crc32_tx[31:0]}; + next_xgxs_txc = 8'b11110000; + end + + // Next state depends on number of IFG bytes to be inserted. + // Skip idle state if needed. + + if (frame_available && !ifg_8b_add) begin + txhfifo_ren = 1'b1; + next_state = SM_PREAMBLE; + end + else if (frame_available) begin + next_state = SM_IDLE; + end + else begin + next_state = SM_IFG; + end + + end + + SM_TERM_FAIL: + begin + + next_xgxs_txd = {{7{`IDLE}}, `TERMINATE}; + next_xgxs_txc = 8'b11111111; + next_state = SM_IFG; + + end + + SM_IFG: + begin + + next_state = SM_IDLE; + + end + + default: + begin + next_state = SM_IDLE; + end + + endcase + +end + + +always @(/*AS*/crc32_d64 or txhfifo_wen or txhfifo_wstatus) begin + + if (txhfifo_wen && txhfifo_wstatus == `TXSTATUS_SOP) begin + crc_data = 32'hffffffff; + end + else begin + crc_data = crc32_d64; + end + +end + +always @(/*AS*/byte_cnt or curr_state_rd or txdfifo_rdata + or txdfifo_rempty or txdfifo_rstatus or txhfifo_ren + or txhfifo_walmost_full) begin + + next_state_rd = curr_state_rd; + + next_txhfifo_wdata = txdfifo_rdata; + next_txhfifo_wstatus = txdfifo_rstatus; + + txdfifo_ren = 1'b0; + next_txhfifo_wen = 1'b0; + + case (curr_state_rd) + + SM_RD_IDLE: begin + + if (!txdfifo_rempty && !txhfifo_walmost_full) begin + + txdfifo_ren = 1'b1; + next_txhfifo_wen = 1'b1; + next_state_rd = SM_RD_EQ; + + end + + end + + SM_RD_EQ: begin + + if (!txhfifo_walmost_full || txhfifo_ren) begin + + txdfifo_ren = 1'b1; + next_txhfifo_wen = 1'b1; + + if (txdfifo_rempty) begin + + // If FIFO empty, do a last read and abort + + next_state_rd = SM_RD_IDLE; + + end + else if (txdfifo_rstatus == `TXSTATUS_EOP0 || + txdfifo_rstatus == `TXSTATUS_EOP1 || + txdfifo_rstatus == `TXSTATUS_EOP2 || + txdfifo_rstatus == `TXSTATUS_EOP3 || + txdfifo_rstatus == `TXSTATUS_EOP4 || + txdfifo_rstatus == `TXSTATUS_EOP5 || + txdfifo_rstatus == `TXSTATUS_EOP6 || + txdfifo_rstatus == `TXSTATUS_EOP7) begin + + if (byte_cnt < 14'd48) begin + + next_txhfifo_wstatus = `TXSTATUS_NONE; + next_state_rd = SM_RD_PAD; + + end + else if (byte_cnt == 14'd48 && + (txdfifo_rstatus == `TXSTATUS_EOP0 || + txdfifo_rstatus == `TXSTATUS_EOP1 || + txdfifo_rstatus == `TXSTATUS_EOP2)) begin + + // Pad up to LANE3, keep the other 4 bytes for crc that will + // be inserted by dequeue engine. + + next_txhfifo_wstatus = `TXSTATUS_EOP3; + + // Pad end bytes with zeros. + + if (txdfifo_rstatus == `TXSTATUS_EOP0) + next_txhfifo_wdata[31:8] = 24'b0; + if (txdfifo_rstatus == `TXSTATUS_EOP1) + next_txhfifo_wdata[31:16] = 16'b0; + if (txdfifo_rstatus == `TXSTATUS_EOP2) + next_txhfifo_wdata[31:24] = 8'b0; + + next_state_rd = SM_RD_IDLE; + + end + else begin + + next_state_rd = SM_RD_IDLE; + + end + + end + + end + + end + + SM_RD_PAD: begin + + if (!txhfifo_walmost_full || txhfifo_ren) begin + + next_txhfifo_wdata = 64'b0; + next_txhfifo_wstatus = `TXSTATUS_NONE; + next_txhfifo_wen = 1'b1; + + if (byte_cnt == 14'd48) begin + + + // Pad up to LANE3, keep the other 4 bytes for crc that will + // be inserted by dequeue engine. + + next_txhfifo_wstatus = `TXSTATUS_EOP3; + + next_state_rd = SM_RD_IDLE; + + end + + end + + end + + default: + begin + next_state_rd = SM_RD_IDLE; + end + + endcase + +end + + +always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin + + if (reset_xgmii_tx_n == 1'b0) begin + + curr_state_rd <= SM_RD_IDLE; + + txhfifo_wdata <= 64'b0; + txhfifo_wstatus <= 8'b0; + txhfifo_wen <= 1'b0; + + byte_cnt <= 14'b0; + + shift_crc_data <= 64'b0; + shift_crc_eop <= 8'b0; + shift_crc_cnt <= 3'b0; + + end + else begin + + curr_state_rd <= next_state_rd; + + txhfifo_wdata <= next_txhfifo_wdata; + txhfifo_wstatus <= next_txhfifo_wstatus; + txhfifo_wen <= next_txhfifo_wen; + + if (txhfifo_wen) begin + + if (txhfifo_wstatus == `TXSTATUS_SOP) begin + + byte_cnt <= 14'd8; + + end + else begin + + byte_cnt <= byte_cnt + 14'd8; + + end + + end + + if (txhfifo_wen) begin + + crc32_d64 <= nextCRC32_D64(reverse_64b(txhfifo_wdata), crc_data); + + end + + if (txhfifo_wen && + (txhfifo_wstatus == `TXSTATUS_EOP0 || + txhfifo_wstatus == `TXSTATUS_EOP1 || + txhfifo_wstatus == `TXSTATUS_EOP2 || + txhfifo_wstatus == `TXSTATUS_EOP3 || + txhfifo_wstatus == `TXSTATUS_EOP4 || + txhfifo_wstatus == `TXSTATUS_EOP5 || + txhfifo_wstatus == `TXSTATUS_EOP6 || + txhfifo_wstatus == `TXSTATUS_EOP7)) begin + + // Last bytes calculated 8-bit at a time instead of 64-bit. Start + // this process at the end of the frame. + + crc32_d8 <= crc32_d64; + + shift_crc_data <= txhfifo_wdata; + shift_crc_eop <= txhfifo_wstatus; + shift_crc_cnt <= 3'd7; + + end + else if (shift_crc_eop != 8'b0) begin + + // Complete crc calculation 8-bit at a time until finished. This can + // be 1 to 8 bytes long. + + crc32_d8 <= nextCRC32_D8(reverse_8b(shift_crc_data[7:0]), crc32_d8); + + shift_crc_data <= {8'b0, shift_crc_data[63:8]}; + shift_crc_eop <= {1'b0, shift_crc_eop[7:1]}; + + end + + if (shift_crc_cnt == 3'b0) begin + crc32_tx <= ~reverse_32b(crc32_d8); + end + else begin + shift_crc_cnt <= shift_crc_cnt - 3'd1; + end + + end + +end + +endmodule +
tags/initial/rtl/verilog/tx_dequeue.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/generic_mem_medium.v =================================================================== --- tags/initial/rtl/verilog/generic_mem_medium.v (nonexistent) +++ tags/initial/rtl/verilog/generic_mem_medium.v (revision 3) @@ -0,0 +1,183 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "generic_mem_medium.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +/* synthesis ramstyle = "M4K" */ + +module generic_mem_medium( + + wclk, + wrst_n, + wen, + waddr, + wdata, + + rclk, + rrst_n, + ren, + roen, + raddr, + rdata +); + +//--- +// Parameters + +parameter DWIDTH = 32; +parameter AWIDTH = 3; +parameter RAM_DEPTH = (1 << AWIDTH); +parameter SYNC_WRITE = 1; +parameter SYNC_READ = 1; +parameter REGISTER_READ = 0; + +//--- +// Ports + +input wclk; +input wrst_n; +input wen; +input [AWIDTH:0] waddr; +input [DWIDTH-1:0] wdata; + +input rclk; +input rrst_n; +input ren; +input roen; +input [AWIDTH:0] raddr; +output [DWIDTH-1:0] rdata; + +// Registered outputs +reg [DWIDTH-1:0] rdata; + + +//--- +// Local declarations + +// Registers + +reg [DWIDTH-1:0] mem_rdata; + + +// Memory + +reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1]; + +// Variables + +integer i; + + +//--- +// Memory Write + +generate + if (SYNC_WRITE) begin + + // Generate synchronous write + always @(posedge wclk) + begin + if (wen) begin + mem[waddr[AWIDTH-1:0]] <= wdata; + end + end + end + else begin + + // Generate asynchronous write + always @(wen, waddr, wdata) + begin + if (wen) begin + mem[waddr[AWIDTH-1:0]] = wdata; + end + end + end +endgenerate + +//--- +// Memory Read + +generate + if (SYNC_READ) begin + + // Generate registered memory read + always @(posedge rclk or negedge rrst_n) + begin + if (!rrst_n) begin + mem_rdata <= {(DWIDTH){1'b0}}; + end else if (ren) begin + mem_rdata <= mem[raddr[AWIDTH-1:0]]; + end + end + end + else begin + + // Generate unregisters memory read + always @(raddr, rclk) + begin + mem_rdata = mem[raddr[AWIDTH-1:0]]; + end + end +endgenerate + +generate + if (REGISTER_READ) begin + + // Generate registered output + always @(posedge rclk or negedge rrst_n) + begin + if (!rrst_n) begin + rdata <= {(DWIDTH){1'b0}}; + end else if (roen) begin + rdata <= mem_rdata; + end + end + + end + else begin + + // Generate unregisters output + always @(mem_rdata) + begin + rdata = mem_rdata; + end + + end +endgenerate + +endmodule + + +
tags/initial/rtl/verilog/generic_mem_medium.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/verilog/fault_sm.v =================================================================== --- tags/initial/rtl/verilog/fault_sm.v (nonexistent) +++ tags/initial/rtl/verilog/fault_sm.v (revision 3) @@ -0,0 +1,289 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "fault_sm.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "defines.v" + +module fault_sm(/*AUTOARG*/ + // Outputs + status_local_fault_crx, status_remote_fault_crx, + // Inputs + clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det, + remote_fault_msg_det + ); + +input clk_xgmii_rx; +input reset_xgmii_rx_n; + +input [1:0] local_fault_msg_det; +input [1:0] remote_fault_msg_det; + +output status_local_fault_crx; +output status_remote_fault_crx; + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +reg status_local_fault_crx; +reg status_remote_fault_crx; +// End of automatics + +reg [1:0] curr_state; + +reg [7:0] col_cnt; +reg [1:0] fault_sequence; +reg [1:0] last_seq_type; +reg [1:0] link_fault; +reg [2:0] seq_cnt; +reg [1:0] seq_type; + +reg [1:0] seq_add; + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + + +parameter [1:0] + SM_INIT = 2'd0, + SM_COUNT = 2'd1, + SM_FAULT = 2'd2, + SM_NEW_FAULT = 2'd3; + + +always @(/*AS*/local_fault_msg_det or remote_fault_msg_det) begin + + //--- + // Fault indication. Indicate remote or local fault + + fault_sequence = local_fault_msg_det | remote_fault_msg_det; + + + //--- + // Sequence type, local, remote, or ok + + if (|local_fault_msg_det) begin + seq_type = `LINK_FAULT_LOCAL; + end + else if (|remote_fault_msg_det) begin + seq_type = `LINK_FAULT_REMOTE; + end + else begin + seq_type = `LINK_FAULT_OK; + end + + + //--- + // Adder for number of faults, if detected in lower 4 lanes and + // upper 4 lanes, add 2. That's because we process 64-bit at a time + // instead of typically 32-bit xgmii. + + if (|remote_fault_msg_det) begin + seq_add = remote_fault_msg_det[1] + remote_fault_msg_det[0]; + end + else begin + seq_add = local_fault_msg_det[1] + local_fault_msg_det[0]; + end + +end + +always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin + + if (reset_xgmii_rx_n == 1'b0) begin + + + status_local_fault_crx <= 1'b0; + status_remote_fault_crx <= 1'b0; + + end + else begin + + //--- + // Status signal to generate local/remote fault interrupts + + status_local_fault_crx <= curr_state == SM_FAULT && + link_fault == `LINK_FAULT_LOCAL; + + status_remote_fault_crx <= curr_state == SM_FAULT && + link_fault == `LINK_FAULT_REMOTE; + + end + +end + +always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin + + if (reset_xgmii_rx_n == 1'b0) begin + + curr_state <= SM_INIT; + + col_cnt <= 8'b0; + last_seq_type <= `LINK_FAULT_OK; + link_fault <= `LINK_FAULT_OK; + seq_cnt <= 3'b0; + + end + else begin + + case (curr_state) + + SM_INIT: + begin + + last_seq_type <= seq_type; + + if (|fault_sequence) begin + + // If a fault is detected, capture the type of + // fault and start column counter. We need 4 fault + // messages in 128 columns to accept the fault. + + if (fault_sequence[0]) begin + col_cnt <= 8'd2; + end + else begin + col_cnt <= 8'd1; + end + seq_cnt <= {1'b0, seq_add}; + curr_state <= SM_COUNT; + + end + else begin + + // If no faults, stay in INIT and clear counters + + col_cnt <= 8'b0; + seq_cnt <= 3'b0; + + end + end + + SM_COUNT: + begin + + col_cnt <= col_cnt + 8'd2; + seq_cnt <= seq_cnt + {1'b0, seq_add}; + + if (!fault_sequence[0] && col_cnt >= 8'd127) begin + + // No new fault in lower lanes and almost + // reached the 128 columns count, abort fault. + + curr_state <= SM_INIT; + + end + else if (col_cnt > 8'd127) begin + + // Reached the 128 columns count, abort fault. + + curr_state <= SM_INIT; + + end + else if (|fault_sequence) begin + + // If fault type has changed, move to NEW_FAULT. + // If not, after detecting 4 fault messages move to + // FAULT state. + + if (seq_type != last_seq_type) begin + curr_state <= SM_NEW_FAULT; + end + else begin + if ((seq_cnt + {1'b0, seq_add}) > 3'd3) begin + col_cnt <= 8'b0; + link_fault <= seq_type; + curr_state <= SM_FAULT; + end + end + + end + end + + SM_FAULT: + begin + + col_cnt <= col_cnt + 8'd2; + + if (!fault_sequence[0] && col_cnt >= 8'd127) begin + + // No new fault in lower lanes and almost + // reached the 128 columns count, abort fault. + + curr_state <= SM_INIT; + + end + else if (col_cnt > 8'd127) begin + + // Reached the 128 columns count, abort fault. + + curr_state <= SM_INIT; + + end + else if (|fault_sequence) begin + + // Clear the column count each time we see a fault, + // if fault changes, go no next state. + + col_cnt <= 8'd0; + + if (seq_type != last_seq_type) begin + curr_state <= SM_NEW_FAULT; + end + end + + end + + SM_NEW_FAULT: + begin + + // Capture new fault type. Start counters. + + col_cnt <= 8'b0; + last_seq_type <= seq_type; + + seq_cnt <= {1'b0, seq_add}; + curr_state <= SM_COUNT; + + end + + endcase + + end + +end + +endmodule +
tags/initial/rtl/verilog/fault_sm.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/auto_verilog.sh =================================================================== --- tags/initial/rtl/auto_verilog.sh (nonexistent) +++ tags/initial/rtl/auto_verilog.sh (revision 3) @@ -0,0 +1,30 @@ + +xemacs -batch verilog/sync_clk_wb.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/sync_clk_xgmii_tx.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/sync_clk_core.v -l ../custom.el -f verilog-auto -f save-buffer + +xemacs -batch verilog/wishbone_if.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/fault_sm.v -l ../custom.el -f verilog-auto -f save-buffer + +xemacs -batch verilog/rx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/rx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/rx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/rx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer + +xemacs -batch verilog/tx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/tx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/tx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer +xemacs -batch verilog/tx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer + +xemacs -batch verilog/xge_mac.v -l ../custom.el -f verilog-auto -f save-buffer + +#xemacs -batch verilog/top_altera.v -l ../custom.el -f verilog-auto -f save-buffer +#xemacs -batch verilog/top_altera_loopback.v -l ../custom.el -f verilog-auto -f save-buffer + +#xemacs -batch verilog/loopback_block.v -l ../custom.el -f verilog-auto -f save-buffer + + +#xemacs -batch ../tbench/verilog/tb_altera.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer +#xemacs -batch ../tbench/verilog/tb_altera_loopback.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer +xemacs -batch ../tbench/verilog/tb_xge_mac.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer +
tags/initial/rtl/auto_verilog.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/rtl/custom.el =================================================================== --- tags/initial/rtl/custom.el (nonexistent) +++ tags/initial/rtl/custom.el (revision 3) @@ -0,0 +1,15 @@ +(custom-set-variables + '(auto-revert-interval 1) + '(global-auto-revert-mode t nil (autorevert)) + '(indent-tabs-mode nil) + '(verilog-auto-endcomments nil) + '(verilog-auto-indent-on-newline nil) + '(verilog-auto-newline nil) + '(verilog-auto-sense-defines-constant t) + '(verilog-indent-level 4) + '(verilog-indent-level-behavioral 4) + '(verilog-indent-level-declaration 2) + '(verilog-indent-level-module 0) + '(verilog-library-directories (quote ("../../rtl/include" "../../rtl/verilog" "."))) + '(verilog-tab-always-indent nil)) +(custom-set-faces)
tags/initial/rtl/custom.el Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_pkt_generator.h =================================================================== --- tags/initial/tbench/systemc/sc_pkt_generator.h (nonexistent) +++ tags/initial/tbench/systemc/sc_pkt_generator.h (revision 3) @@ -0,0 +1,105 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_pkt_generator.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef GENERATOR_H +#define GENERATOR_H + +#include "systemc.h" + +#include "sc_packet.h" + +SC_MODULE(pkt_generator) { + + private: + + //--- + // Variables + + sc_fifo * tx_fifo; + + int tx_bucket; + + int min_pkt_size; + int max_pkt_size; + + int crc_interval; + int fragment_interval; + int coding_interval; + int local_fault_interval; + int remote_fault_interval; + int inject_pause_interval; + + public: + + //--- + // Functions + + void init(void); + + void connect_fifo(sc_fifo * fifo); + + void set_tx_bucket(int cnt); + int get_tx_bucket(void); + + void set_pkt_size(int min, int max); + + void set_crc_errors(int interval); + void set_fragment_errors(int interval); + void set_coding_errors(int interval); + void set_local_fault(int interval); + void set_remote_fault(int interval); + void set_inject_pause(int interval); + + //--- + // Threads + + void gen_packet(); + + SC_CTOR(pkt_generator) { + + tx_bucket = 0; + + min_pkt_size = 64; + max_pkt_size = 72; + + SC_THREAD (gen_packet); + + } + +}; + +#endif
tags/initial/tbench/systemc/sc_pkt_generator.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_cpu_if.h =================================================================== --- tags/initial/tbench/systemc/sc_cpu_if.h (nonexistent) +++ tags/initial/tbench/systemc/sc_cpu_if.h (revision 3) @@ -0,0 +1,144 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_cpu_if.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef CPU_IF_H +#define CPU_IF_H + +#include "systemc.h" + +#include "sc_scoreboard.h" +#include "sc_cpu_if.h" + +SC_MODULE(cpu_if) { + + public: + + //--- + // Ports + + sc_in wb_clk_i; + + sc_in wb_rst_i; + + sc_in wb_ack_o; + sc_in wb_dat_o; + sc_in wb_int_o; + + sc_out wb_adr_i; + sc_out wb_cyc_i; + sc_out wb_dat_i; + sc_out wb_stb_i; + sc_out wb_we_i; + + //--- + // Types + + enum paramId { + TX_ENABLE, + }; + + enum intId { + INT_TXD_FIFO_OVFLOW = 0, + INT_TXD_FIFO_UDFLOW = 1, + INT_RXD_FIFO_OVFLOW = 2, + INT_RXD_FIFO_UDFLOW = 3, + INT_LOCAL_FAULT = 4, + INT_REMOTE_FAULT = 5, + INT_PAUSE_FRAME = 6, + INT_CRC_ERROR = 7, + INT_FRAGMENT_ERROR = 8, + }; + + enum regId { + CPUREG_CONFIG0 = 0x0, + + CPUREG_INT_PENDING = 0x8, + CPUREG_INT_STATUS = 0xc, + CPUREG_INT_MASK = 0x10, + }; + + private: + + //--- + // Variables + + scoreboard *sb; + scoreboard::sbSourceId sb_id; + + sc_mutex bus_lock; + sc_event bus_start; + sc_semaphore bus_done; + + uint bus_addr; + uint bus_data; + bool bus_write; + + public: + + //--- + // Variables + + //--- + // Functions + + void init(); + void connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid); + void set_param(cpu_if::paramId param, int value); + void set_interrupt(cpu_if::intId intr); + void set_interrupt_mask(cpu_if::intId intr, bool value); + void enable_all_interrupts(void); + + uint read(uint addr); + void write(uint addr, uint data); + void writebits(uint addr, uint hbit, uint lbit, uint value); + + //--- + // Threads + + void transactor(); + void monitor(); + + SC_CTOR(cpu_if): bus_done(0) { + + SC_CTHREAD (monitor, wb_clk_i.pos()); + SC_CTHREAD (transactor, wb_clk_i.pos()); + + } + +}; + +#endif
tags/initial/tbench/systemc/sc_cpu_if.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_packet.h =================================================================== --- tags/initial/tbench/systemc/sc_packet.h (nonexistent) +++ tags/initial/tbench/systemc/sc_packet.h (revision 3) @@ -0,0 +1,88 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_packet.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef PACKET_H +#define PACKET_H + +#include "systemc.h" + + +#define PKT_FLAG_ERR_SIG 0x0001 +#define PKT_FLAG_ERR_SOP 0x0002 +#define PKT_FLAG_ERR_CRC 0x0004 +#define PKT_FLAG_ERR_FRG 0x0008 +#define PKT_FLAG_ERR_CODING 0x0010 +#define PKT_FLAG_LOCAL_FAULT 0x0020 +#define PKT_FLAG_REMOTE_FAULT 0x0040 + + +struct packet_t { + + int length; + + // Packet fields + + sc_uint<48> dest_addr; + sc_uint<48> src_addr; + sc_uint<8> payload [12000]; + sc_uint<32> crc; + + sc_uint<32> crc_rx; + sc_uint<32> err_flags; + sc_uint<32> err_info; + + sc_uint<32> ifg; + sc_uint<32> start_lane; + + sc_uint<8> data [10000]; +}; + +ostream& operator<<(ostream& os, const packet_t& p); + +void pack(packet_t* p); +void unpack(packet_t* p); + +void add_crc(packet_t* p); +void strip_crc(packet_t* p); + +void calc_crc(packet_t* p); + +void pad(packet_t* p, int len); + +bool compare(packet_t* pkta, packet_t* pktb); + +#endif
tags/initial/tbench/systemc/sc_packet.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_pkt_if.cpp =================================================================== --- tags/initial/tbench/systemc/sc_pkt_if.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_pkt_if.cpp (revision 3) @@ -0,0 +1,221 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_pkt_if.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "sc_pkt_if.h" + +sc_fifo * pkt_if::get_tx_fifo_ptr() { + return &tx_fifo; +} + +sc_fifo * pkt_if::get_rx_fifo_ptr() { + return &rx_fifo; +} + +void pkt_if::init(void) { + disable_rx = false; + allow_rx_sop_err = false; +} + +void pkt_if::connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid) { + sb = sbptr; + sb_id = sid; +} + +void pkt_if::transmit() { + + packet_t* pkt; + + while (true) { + + wait(); + + if (tx_fifo.nb_read(pkt)) { + + pack(pkt); + + //cout << "Transmit PKT_IF packet:\n" << * pkt << endl; + + pkt_tx_val = 1; + + for (int i = 0; i < pkt->length; i += 8) { + + pkt_tx_data = pkt->data[i+7] << 56 | + pkt->data[i+6] << 48 | + pkt->data[i+5] << 40 | + pkt->data[i+4] << 32 | + pkt->data[i+3] << 24 | + pkt->data[i+2] << 16 | + pkt->data[i+1] << 8 | + pkt->data[i]; + + if (i == 0) { + pkt_tx_sop = 1; + } + else { + pkt_tx_sop = 0; + } + + if (i + 8 >= pkt->length) { + pkt_tx_eop = 0x1 << ((pkt->length - 1) % 8); + } + else { + pkt_tx_eop = 0; + } + + wait(); + } + + pkt_tx_val = 0; + + + //--- + // Pass packet to scoreboard + + sb->notify_packet_tx(sb_id, pkt); + + //--- + // Enforce minimum spacing between SOP's + + for (int i = (pkt->length+7)/8; i < 8; i++) { + wait(); + } + } + } +}; + + +void pkt_if::receive() { + + packet_t* pkt; + + sc_uint<64> data; + + wait(); + + while (true) { + + if (pkt_rx_avail && !disable_rx) { + + pkt = new(packet_t); + pkt->length = 0; + + // If reading already selected just keep going, + // if not we must enable ren + if (!pkt_rx_ren) { + pkt_rx_ren = 1; + wait(); + }; + + while (true) { + + wait(); + + if (!pkt_rx_val) { + continue; + } + + // Check SOP + + if (pkt->length != 0 && pkt_rx_sop) { + if (allow_rx_sop_err) { + cout << "INFO: SOP errors allowed" << endl; + pkt->length = 0; + pkt->err_flags = 0; + } + else { + pkt->err_flags |= PKT_FLAG_ERR_SOP; + } + } + + // Check error line + + if (pkt_rx_err) { + pkt->err_flags |= PKT_FLAG_ERR_SIG; + } + + // Capture data + + data = pkt_rx_data; + + for (int lane = 0; lane < 8; lane++) { + + pkt->data[pkt->length++] = (data >> (8 * lane)) & 0xff; + + if (pkt->length >= 10000) { + cout << "ERROR: Packet too long" << endl; + sc_stop(); + } + + if ((pkt_rx_eop >> lane) & 0x1 == 1) { + break; + } + } + + // Stop on EOP + + if (pkt_rx_eop) { + break; + } + } + + //--- + // Store packet + + unpack(pkt); + //rx_fifo.write(pkt); + + //cout << "Receive PKT_IF packet:\n" << * pkt << endl; + + //--- + // Pass packet to scoreboard + + sb->notify_packet_rx(sb_id, pkt); + + } + else { + pkt_rx_ren = 0; + wait(); + } + } +};
tags/initial/tbench/systemc/sc_pkt_if.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_testbench.cpp =================================================================== --- tags/initial/tbench/systemc/sc_testbench.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_testbench.cpp (revision 3) @@ -0,0 +1,46 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_testbench.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + + +
tags/initial/tbench/systemc/sc_testbench.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_pkt_if.h =================================================================== --- tags/initial/tbench/systemc/sc_pkt_if.h (nonexistent) +++ tags/initial/tbench/systemc/sc_pkt_if.h (revision 3) @@ -0,0 +1,119 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_pkt_if.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef PKT_IF_H +#define PKT_IF_H + +#include "systemc.h" + +#include "sc_packet.h" +#include "sc_scoreboard.h" + +SC_MODULE(pkt_if) { + + public: + + //--- + // Ports + + sc_in clk_156m25; + + sc_in reset_156m25_n; + + sc_out > pkt_tx_data; + sc_out pkt_tx_eop; + sc_out pkt_tx_sop; + sc_out pkt_tx_val; + + sc_in pkt_tx_full; + + sc_in pkt_rx_avail; + sc_in > pkt_rx_data; + sc_in pkt_rx_eop; + sc_in pkt_rx_err; + sc_in pkt_rx_sop; + sc_in pkt_rx_val; + + sc_out pkt_rx_ren; + + private: + + //--- + // Variables + + sc_fifo tx_fifo; + sc_fifo rx_fifo; + + scoreboard *sb; + scoreboard::sbSourceId sb_id; + + public: + + //--- + // Variables + + bool disable_rx; + bool allow_rx_sop_err; + + //--- + // Functions + + sc_fifo * get_tx_fifo_ptr(); + sc_fifo * get_rx_fifo_ptr(); + + void init(void); + void connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid); + + //--- + // Threads + + void transmit(); + void receive(); + + SC_CTOR(pkt_if) : + tx_fifo (2), + rx_fifo (2) { + + SC_CTHREAD (transmit, clk_156m25.pos()); + + SC_CTHREAD (receive, clk_156m25.pos()); + + } + +}; + +#endif
tags/initial/tbench/systemc/sc_pkt_if.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/crc.cpp =================================================================== --- tags/initial/tbench/systemc/crc.cpp (nonexistent) +++ tags/initial/tbench/systemc/crc.cpp (revision 3) @@ -0,0 +1,72 @@ +/* + * efone - Distributed internet phone system. + * + * (c) 1999,2000 Krzysztof Dabrowski + * (c) 1999,2000 ElysiuM deeZine + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +/* based on implementation by Finn Yannick Jacobs */ + +#include +#include + +#include + +/* crc_tab[] -- this crcTable is being build by chksum_crc32GenTab(). + * so make sure, you call it before using the other + * functions! + */ +u_int32_t crc_tab[256]; + +/* chksum_crc() -- to a given block, this one calculates the + * crc32-checksum until the length is + * reached. the crc32-checksum will be + * the result. + */ +u_int32_t chksum_crc32 (sc_uint<8> *block, unsigned int length) +{ + register unsigned long crc; + unsigned long i; + + crc = 0xFFFFFFFF; + for (i = 0; i < length; i++) + { + crc = ((crc >> 8) & 0x00FFFFFF) ^ crc_tab[(crc ^ *block++) & 0xFF]; + } + return (crc ^ 0xFFFFFFFF); +} + +/* chksum_crc32gentab() -- to a global crc_tab[256], this one will + * calculate the crcTable for crc32-checksums. + * it is generated to the polynom [..] + */ + +void chksum_crc32gentab () +{ + unsigned long crc, poly; + int i, j; + + poly = 0xEDB88320L; + for (i = 0; i < 256; i++) + { + crc = i; + for (j = 8; j > 0; j--) + { + if (crc & 1) + { + crc = (crc >> 1) ^ poly; + } + else + { + crc >>= 1; + } + } + crc_tab[i] = crc; + } +}
tags/initial/tbench/systemc/crc.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_scoreboard.cpp =================================================================== --- tags/initial/tbench/systemc/sc_scoreboard.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_scoreboard.cpp (revision 3) @@ -0,0 +1,511 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_scoreboard.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "sc_scoreboard.h" + + +void scoreboard::init(void) { + disable_padding = false; + disable_crc_check = false; + disable_packet_check = false; + disable_flags_check = false; + disable_signal_check = false; +} + +void scoreboard::notify_packet_tx(sbSourceId sid, packet_t* pkt) { + + //--- + // Save packet to a fifo + + if (sid == SB_PIF_ID) { + cout << "SCOREBOARD PACKET INTERFACE TX (" + << pkt->length << ")" << endl; + + //--- + // Store packet in scoreboard + + pif_fifo.write(pkt); + pif_stats.tx_pkt_cnt++; + + } + + if (sid == SB_XGM_ID) { + + cout << "SCOREBOARD XGMII INTERFACE TX (" + << pkt->length << ")" << endl; + + //--- + // Store packet in scoreboard + + if (sid == SB_XGM_ID && (pkt->dest_addr & 0xffff) == 0x000001 && + ((pkt->dest_addr >> 24) & 0xffffff) == 0x0180c2) { + + // Pause frames will be dropped + cout << "SCOREBOARD PAUSE INJECTED" << endl; + xgm_stats.inject_pause_frame_cnt++; + + } + else { + + xgm_fifo.write(pkt); + xgm_stats.tx_pkt_cnt++; + + } + + } + + //--- + // Update stats + + if (sid == SB_XGM_ID && pkt->err_flags & PKT_FLAG_ERR_CODING) { + xgm_stats.crc_error_cnt++; + } + + if (sid == SB_XGM_ID && pkt->err_flags & PKT_FLAG_LOCAL_FAULT) { + // If less than 4 faults in 128 columns, it will not be detected + if (pkt->err_info <= (128 - 4)) { + xgm_stats.inject_local_fault_cnt++; + } + } + + if (sid == SB_XGM_ID && pkt->err_flags & PKT_FLAG_REMOTE_FAULT) { + // If less than 4 faults in 128 columns, it will not be detected + if (pkt->err_info <= (128 - 4)) { + xgm_stats.inject_remote_fault_cnt++; + } + } + + //cout << *pkt << endl; +} + +void scoreboard::notify_packet_rx(sbSourceId sid, packet_t* pkt) { + + sbStats_t* stats; + + packet_t* pkt_tx; + bool status; + + //--- + // Read matching packet from fifo + + if (sid == SB_PIF_ID) { + status = xgm_fifo.nb_read(pkt_tx); + if (status) { + cout << "SCOREBOARD PACKET INTERFACE RX (TX SIZE=" + << pkt_tx->length << " RX SIZE=" + << pkt->length << ")" << endl; + } + } + + if (sid == SB_XGM_ID) { + status = pif_fifo.nb_read(pkt_tx); + if (status) { + cout << "SCOREBOARD XGMII INTERFACE RX (TX SIZE=" + << pkt_tx->length << " RX SIZE=" + << pkt->length << ")" << endl; + } + } + + if (!status) { + cout << "ERROR: FIFO EMPTY" << endl; + sc_stop(); + } + + //--- + // Update stats + + if (sid == SB_PIF_ID) { + stats = &pif_stats; + } + + if (sid == SB_XGM_ID) { + stats = &xgm_stats; + } + + stats->rx_pkt_cnt++; + + if (stats->timestamp_first_pkt == 0) { + stats->timestamp_first_pkt = sc_simulation_time(); + } + + stats->timestamp_last_pkt = sc_simulation_time(); + + //--- + // Pad packet if it expected to be padded by MAC + + if (sid == SB_XGM_ID && !disable_padding) { + pad(pkt_tx, 60); + } + + //--- + // Calculate CRC + + calc_crc(pkt_tx); + calc_crc(pkt); + + //cout << *pkt_tx << *pkt << endl; + + //--- + // Compare TX and RX packets + + if (disable_packet_check) { + + cout << "INFO: Packet check disabled" << endl; + + } + else if ((pkt_tx->err_flags & PKT_FLAG_ERR_FRG) && + (pkt->err_flags |= PKT_FLAG_ERR_SIG)) { + + cout << "INFO: Fragment detected" << endl; + + } + else if ((pkt_tx->err_flags & PKT_FLAG_ERR_CODING) && + (pkt->err_flags |= PKT_FLAG_ERR_SIG)) { + + cout << "INFO: Coding error detected:" << pkt_tx->err_info << endl; + + } + else if ((sid == SB_PIF_ID || pkt->crc == pkt->crc_rx || disable_crc_check) && + compare(pkt_tx, pkt)) { + + //cout << "GOOD: Packets are matching" << endl; + + } + else { + + cout << "ERROR: Packets don't match or bad CRC" << endl; + + cout << "<<<" << endl; + cout << *pkt_tx << endl; + cout << *pkt << endl; + cout << ">>>" << endl; + + sc_stop(); + + } + + //--- + // Check IFG against predicted IFG + + if (sid == SB_XGM_ID) { + + cout << "PKTMOD " << pkt->length % 4 \ + << " LANE " << pkt->start_lane \ + << " DIC " << stats->deficit_idle_count \ + << " IFGLEN " << stats->next_ifg_length << endl; + + if (pkt->ifg < 1000 && stats->next_ifg_length != 1000) { + if (pkt->ifg != stats->next_ifg_length) { + cout << "ERROR: DIC IFG " << pkt->ifg \ + << " Predicted: " << stats->next_ifg_length << endl; + sc_stop(); + } + } + + } + + //--- + // Update deficit idle count and predict IFG + + if (sid == SB_XGM_ID) { + + stats->next_ifg_length = 12 - (pkt->length % 4); + stats->deficit_idle_count += (pkt->length % 4); + if (stats->deficit_idle_count > 3) { + stats->next_ifg_length += 4; + stats->deficit_idle_count = stats->deficit_idle_count % 4; + } + } + + //--- + // Check error flags + + // CRC ERRORS + + if (sid == SB_PIF_ID && (pkt_tx->err_flags & PKT_FLAG_ERR_CRC)) { + + if (pkt->err_flags & PKT_FLAG_ERR_SIG) { + + cout << "SCOREBOARD CRC ERROR CHECKED" << endl; + pif_stats.crc_error_cnt++; + + if (cpu_stats.crc_error_cnt+1 < pif_stats.crc_error_cnt) { + cout << "ERROR: CRC error not reported to cpu" << endl; + sc_stop(); + } + } + else { + cout << "ERROR: CRC error not detected: " << hex << pkt->err_flags << dec << endl; + sc_stop(); + } + + pkt->err_flags &= ~PKT_FLAG_ERR_SIG; + } + + + // FRAGMENT ERRORS + + if (sid == SB_PIF_ID && (pkt_tx->err_flags & PKT_FLAG_ERR_FRG)) { + + if (pkt->err_flags & PKT_FLAG_ERR_SIG) { + + cout << "SCOREBOARD FRAGMENT ERROR CHECKED" << endl; + pif_stats.fragment_error_cnt++; + + if ((cpu_stats.fragment_error_cnt + cpu_stats.crc_error_cnt + 1) + < pif_stats.fragment_error_cnt) { + cout << "ERROR: FRAGMENT error not reported to cpu" << endl; + sc_stop(); + } + } + else { + cout << "ERROR: FRAGMENT error not detected: " + << hex << pkt->err_flags << dec << endl; + sc_stop(); + } + + pkt->err_flags &= ~PKT_FLAG_ERR_SIG; + } + + + // CODING ERRORS + + if (sid == SB_PIF_ID && (pkt_tx->err_flags & PKT_FLAG_ERR_CODING)) { + + if (pkt->err_flags & PKT_FLAG_ERR_SIG) { + + cout << "SCOREBOARD CODING ERROR CHECKED" << endl; + + if (cpu_stats.crc_error_cnt+1 < xgm_stats.crc_error_cnt) { + cout << "CPU Count: " << cpu_stats.crc_error_cnt << + " XGM Count: " << xgm_stats.crc_error_cnt << endl; + cout << "ERROR: CODING error not reported to cpu" << endl; + sc_stop(); + } + } + else { + cout << "ERROR: CODING error not detected: " + << hex << pkt->err_flags << dec << endl; + sc_stop(); + } + + pkt->err_flags &= ~PKT_FLAG_ERR_SIG; + } + + + if (pkt->err_flags != 0) { + stats->flags_error_cnt++; + if (!disable_flags_check) { + cout << "ERROR: Error flags set: " << hex << pkt->err_flags << dec << endl; + sc_stop(); + } + else { + cout << "INFO: Error flags set: " << hex << pkt->err_flags << dec << endl; + } + } + + //--- + // Delete packets + + delete(pkt_tx); + delete(pkt); +} + +void scoreboard::notify_status(sbSourceId sid, sbStatusId statusId) { + + //--- + // Detect errors + + if (sid == SB_CPU_ID && statusId == CRC_ERROR) { + cout << "SCOREBOARD CRC_ERROR SIGNAL" << endl; + cpu_stats.crc_error_cnt++; + } + + if (sid == SB_CPU_ID && statusId == FRAGMENT_ERROR) { + cout << "SCOREBOARD FRAGMENT_ERROR SIGNAL" << endl; + cpu_stats.fragment_error_cnt++; + } + + if (sid == SB_CPU_ID && statusId == LOCAL_FAULT) { + cout << "SCOREBOARD LOCAL_FAULT SIGNAL" << endl; + cpu_stats.local_fault_cnt++; + + if (cpu_stats.local_fault_cnt != xgm_stats.inject_local_fault_cnt) { + cout << "ERROR: Local fault not reported to cpu " + << cpu_stats.local_fault_cnt << " " + << xgm_stats.inject_local_fault_cnt << endl; + sc_stop(); + } + + if (cpu_stats.local_fault_cnt != xgm_stats.detect_remote_fault_cnt) { + cout << "ERROR: Remote fault not detected " + << cpu_stats.local_fault_cnt << " " + << xgm_stats.detect_remote_fault_cnt << endl; + sc_stop(); + } + } + + if (sid == SB_CPU_ID && statusId == REMOTE_FAULT) { + cout << "SCOREBOARD REMOTE_FAULT SIGNAL" << endl; + cpu_stats.remote_fault_cnt++; + + if (cpu_stats.remote_fault_cnt != xgm_stats.inject_remote_fault_cnt) { + cout << "ERROR: Remote fault not reported to cpu " + << cpu_stats.remote_fault_cnt << " " + << xgm_stats.inject_remote_fault_cnt << endl; + sc_stop(); + } + + } + + if (sid == SB_CPU_ID && statusId == RXD_FIFO_OVFLOW) { + cout << "SCOREBOARD RXD_FIFO_OVFLOW SIGNAL" << endl; + cpu_stats.rxd_fifo_ovflow_cnt++; + } + + if (sid == SB_CPU_ID && statusId == RXD_FIFO_UDFLOW) { + cout << "SCOREBOARD RXD_FIFO_UDFLOW SIGNAL" << endl; + cpu_stats.rxd_fifo_udflow_cnt++; + } + + if (sid == SB_CPU_ID && statusId == TXD_FIFO_OVFLOW) { + cout << "SCOREBOARD TXD_FIFO_OVFLOW SIGNAL" << endl; + cpu_stats.txd_fifo_ovflow_cnt++; + } + + if (sid == SB_CPU_ID && statusId == TXD_FIFO_UDFLOW) { + cout << "SCOREBOARD TXD_FIFO_UDFLOW SIGNAL" << endl; + cpu_stats.txd_fifo_udflow_cnt++; + } + + //--- + // Detect XGMII local/remote faults + + if (sid == SB_XGM_ID && statusId == LOCAL_FAULT) { + cout << "SCOREBOARD RX LOCAL FAULT" << endl; + xgm_stats.detect_local_fault_cnt++; + sc_stop(); + } + + if (sid == SB_XGM_ID && statusId == REMOTE_FAULT) { + cout << "SCOREBOARD RX REMOTE FAULT" << endl; + xgm_stats.detect_remote_fault_cnt++; + } + + //--- + // Packet receive indication + + if (sid == SB_CPU_ID && statusId == RX_GOOD_PAUSE_FRAME) { + cout << "SCOREBOARD RX GOOD PAUSE FRAME SIGNAL" << endl; + cpu_stats.rx_pause_frame_cnt++; + + if (cpu_stats.rx_pause_frame_cnt != xgm_stats.inject_pause_frame_cnt) { + cout << "ERROR: Pause frame not reported " + << cpu_stats.rx_pause_frame_cnt << " " + << xgm_stats.inject_pause_frame_cnt << endl; + sc_stop(); + } + } + + + if (!disable_signal_check) { + cout << "ERROR: Signal Active" << endl; + sc_stop(); + } +} + +sbStats_t* scoreboard::get_pif_stats(void) { + return &pif_stats; +} + +sbStats_t* scoreboard::get_xgm_stats(void) { + return &xgm_stats; +} + +sbCpuStats_t* scoreboard::get_cpu_stats(void) { + return &cpu_stats; +} + +void scoreboard::clear_stats(void) { + + //--- + // Clear FIFOs + + while (pif_fifo.num_available() != 0) { + delete(pif_fifo.read()); + } + + while (xgm_fifo.num_available() != 0) { + delete(xgm_fifo.read()); + } + + //--- + // Clear stats + + pif_stats.tx_pkt_cnt = 0; + pif_stats.rx_pkt_cnt = 0; + pif_stats.crc_error_cnt = 0; + pif_stats.flags_error_cnt = 0; + + xgm_stats.tx_pkt_cnt = 0; + xgm_stats.rx_pkt_cnt = 0; + xgm_stats.crc_error_cnt = 0; + xgm_stats.flags_error_cnt = 0; + + pif_stats.timestamp_first_pkt = 0; + pif_stats.timestamp_last_pkt = 0; + + xgm_stats.timestamp_first_pkt = 0; + xgm_stats.timestamp_last_pkt = 0; + + xgm_stats.next_ifg_length = 1000; + xgm_stats.deficit_idle_count = 0; + + cpu_stats.crc_error_cnt = 0; + cpu_stats.fragment_error_cnt = 0; + cpu_stats.rxd_fifo_ovflow_cnt = 0; + cpu_stats.rxd_fifo_udflow_cnt = 0; + cpu_stats.txd_fifo_ovflow_cnt = 0; + cpu_stats.txd_fifo_udflow_cnt = 0; +}
tags/initial/tbench/systemc/sc_scoreboard.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_main.cpp =================================================================== --- tags/initial/tbench/systemc/sc_main.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_main.cpp (revision 3) @@ -0,0 +1,249 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_main.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" // SystemC global header +#include "SpTraceVcd.h" + +#include "crc.h" + +#include "Vxge_mac.h" // Top level header, generated from verilog + +#include "sc_testbench.h" +#include "sc_testcases.h" + + +int sc_main(int argc, char* argv[]) { + + chksum_crc32gentab(); + + Verilated::randReset(2); + Verilated::debug(0); // We compiled with it on for testing, turn it back off + + // General logfile + ios::sync_with_stdio(); + + cout << ("Defining Clocks\n"); + + sc_clock clk_156m25 ("clk_156m25", 10, 0.5, 3, true); + sc_clock clk_wb ("clk_wb", 29, 0.5, 3, true); + sc_clock clk_xgmii ("clk_xgmii", 10, 0.5, 3, true); + + sc_signal pkt_rx_ren; + sc_signal > pkt_tx_data; + sc_signal pkt_tx_eop; + sc_signal pkt_tx_sop; + sc_signal pkt_tx_val; + sc_signal reset_156m25_n; + sc_signal reset_xgmii_n; + sc_signal wb_adr_i; + sc_signal wb_cyc_i; + sc_signal wb_dat_i; + sc_signal wb_rst_i; + sc_signal wb_stb_i; + sc_signal wb_we_i; + sc_signal xgmii_rxc; + sc_signal > xgmii_rxd; + + sc_signal pkt_rx_avail; + sc_signal > pkt_rx_data; + sc_signal pkt_rx_eop; + sc_signal pkt_rx_sop; + sc_signal pkt_rx_val; + sc_signal pkt_rx_err; + sc_signal pkt_tx_full; + sc_signal wb_ack_o; + sc_signal wb_dat_o; + sc_signal wb_int_o; + sc_signal xgmii_txc; + sc_signal > xgmii_txd; + + //========== + // Part under test + + Vxge_mac* top = new Vxge_mac("top"); + + top->clk_156m25 (clk_156m25); + top->clk_xgmii_rx (clk_xgmii); + top->clk_xgmii_tx (clk_xgmii); + + top->pkt_rx_ren (pkt_rx_ren); + top->pkt_tx_data (pkt_tx_data); + top->pkt_tx_eop (pkt_tx_eop); + top->pkt_tx_sop (pkt_tx_sop); + top->pkt_tx_val (pkt_tx_val); + top->reset_156m25_n (reset_156m25_n); + top->reset_xgmii_rx_n (reset_xgmii_n); + top->reset_xgmii_tx_n (reset_xgmii_n); + top->wb_adr_i (wb_adr_i); + top->wb_clk_i (clk_wb); + top->wb_cyc_i (wb_cyc_i); + top->wb_dat_i (wb_dat_i); + top->wb_rst_i (wb_rst_i); + top->wb_stb_i (wb_stb_i); + top->wb_we_i (wb_we_i); + top->xgmii_rxc (xgmii_rxc); + top->xgmii_rxd (xgmii_rxd); + + top->pkt_rx_avail (pkt_rx_avail); + top->pkt_rx_data (pkt_rx_data); + top->pkt_rx_eop (pkt_rx_eop); + top->pkt_rx_err (pkt_rx_err); + top->pkt_rx_sop (pkt_rx_sop); + top->pkt_rx_val (pkt_rx_val); + top->pkt_tx_full (pkt_tx_full); + top->wb_ack_o (wb_ack_o); + top->wb_dat_o (wb_dat_o); + top->wb_int_o (wb_int_o); + top->xgmii_txc (xgmii_txc); + top->xgmii_txd (xgmii_txd); + + //========== + // Testbench + + testbench* tb = new testbench("tb"); + + tb->clk_156m25 (clk_156m25); + tb->clk_xgmii (clk_xgmii); + tb->wb_clk_i (clk_wb); + + tb->reset_156m25_n (reset_156m25_n); + tb->reset_xgmii_n (reset_xgmii_n); + tb->wb_rst_i (wb_rst_i); + + tb->wb_ack_o (wb_ack_o); + tb->wb_dat_o (wb_dat_o); + tb->wb_int_o (wb_int_o); + + tb->wb_adr_i (wb_adr_i); + tb->wb_cyc_i (wb_cyc_i); + tb->wb_dat_i (wb_dat_i); + tb->wb_stb_i (wb_stb_i); + tb->wb_we_i (wb_we_i); + + tb->xgmii_rxc (xgmii_rxc); + tb->xgmii_rxd (xgmii_rxd); + + tb->xgmii_txc (xgmii_txc); + tb->xgmii_txd (xgmii_txd); + + tb->pkt_tx_data (pkt_tx_data); + tb->pkt_tx_eop (pkt_tx_eop); + tb->pkt_tx_sop (pkt_tx_sop); + tb->pkt_tx_val (pkt_tx_val); + + tb->pkt_tx_full (pkt_tx_full); + + tb->pkt_rx_avail (pkt_rx_avail); + tb->pkt_rx_data (pkt_rx_data); + tb->pkt_rx_eop (pkt_rx_eop); + tb->pkt_rx_err (pkt_rx_err); + tb->pkt_rx_sop (pkt_rx_sop); + tb->pkt_rx_val (pkt_rx_val); + + tb->pkt_rx_ren (pkt_rx_ren); + + //========== + // Testcases + testcases* tc = new testcases("tc"); + + tc->connect_testbench(tb); + + +#if WAVES + // Before any evaluation, need to know to calculate those signals only used for tracing + Verilated::traceEverOn(true); +#endif + + // You must do one evaluation before enabling waves, in order to allow + // SystemC to interconnect everything for testing. + cout <<("Test initialization...\n"); + + sc_start(1); + + reset_156m25_n = 0; + wb_rst_i = 1; + reset_xgmii_n = 0; + + sc_start(1); + +#if WAVES + cout << "Enabling waves...\n"; + SpTraceFile* tfp = new SpTraceFile; + top->trace (tfp, 99); + tfp->open ("vl_dump.vcd"); +#endif + + //========== + // Start of Test + + cout <<("Test beginning...\n"); + + reset_156m25_n = 0; + wb_rst_i = 1; + reset_xgmii_n = 0; + + while (!tc->done) { + +#if WAVES + tfp->flush(); +#endif + if (VL_TIME_Q() > 10) { + reset_156m25_n = 1; + wb_rst_i = 0; + reset_xgmii_n = 1; + } + + sc_start(1); + } + + top->final(); + +#if WAVES + tfp->close(); +#endif + + cout << "*-* All Finished *-*\n"; + + return(0); +} + +
tags/initial/tbench/systemc/sc_main.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_testbench.h =================================================================== --- tags/initial/tbench/systemc/sc_testbench.h (nonexistent) +++ tags/initial/tbench/systemc/sc_testbench.h (revision 3) @@ -0,0 +1,190 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_testbench.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef TESTBENCH_H +#define TESTBENCH_H + +#include "systemc.h" // SystemC global header + +#include "sc_cpu_if.h" +#include "sc_pkt_if.h" +#include "sc_xgmii_if.h" +#include "sc_pkt_generator.h" +#include "sc_scoreboard.h" + +SC_MODULE(testbench) { + + public: + + //--- + // Ports + + sc_in clk_156m25; + sc_in clk_xgmii; + sc_in wb_clk_i; + + sc_in reset_156m25_n; + sc_in reset_xgmii_n; + sc_in wb_rst_i; + + sc_in wb_ack_o; + sc_in wb_dat_o; + sc_in wb_int_o; + + sc_out wb_adr_i; + sc_out wb_cyc_i; + sc_out wb_dat_i; + sc_out wb_stb_i; + sc_out wb_we_i; + + sc_out xgmii_rxc; + sc_out > xgmii_rxd; + + sc_in xgmii_txc; + sc_in > xgmii_txd; + + sc_out > pkt_tx_data; + sc_out pkt_tx_eop; + sc_out pkt_tx_sop; + sc_out pkt_tx_val; + + sc_in pkt_tx_full; + + sc_in pkt_rx_avail; + sc_in > pkt_rx_data; + sc_in pkt_rx_eop; + sc_in pkt_rx_err; + sc_in pkt_rx_sop; + sc_in pkt_rx_val; + + sc_out pkt_rx_ren; + + //--- + // Instances + + cpu_if cpu_if0; + + pkt_if pkt_if0; + xgmii_if xgm_if0; + + pkt_generator pif_gen0; + pkt_generator xgm_gen0; + + scoreboard sb; + + //--- + // Functions + + SC_CTOR(testbench) : + cpu_if0("cpu_if0"), + pkt_if0("pkt_if0"), + xgm_if0("xgm_if0"), + pif_gen0("pif_gen0"), + xgm_gen0("xgm_gen0"), + sb("sb") { + + //-- + // CPU Interface + + cpu_if0.wb_clk_i (wb_clk_i); + + cpu_if0.wb_rst_i (wb_rst_i); + + cpu_if0.wb_ack_o (wb_ack_o); + cpu_if0.wb_dat_o (wb_dat_o); + cpu_if0.wb_int_o (wb_int_o); + + cpu_if0.wb_adr_i (wb_adr_i); + cpu_if0.wb_cyc_i (wb_cyc_i); + cpu_if0.wb_dat_i (wb_dat_i); + cpu_if0.wb_stb_i (wb_stb_i); + cpu_if0.wb_we_i (wb_we_i); + + //--- + // Packet Interface + + pkt_if0.clk_156m25 (clk_156m25); + + pkt_if0.reset_156m25_n (reset_156m25_n); + + pkt_if0.pkt_tx_data (pkt_tx_data); + pkt_if0.pkt_tx_eop (pkt_tx_eop); + pkt_if0.pkt_tx_sop (pkt_tx_sop); + pkt_if0.pkt_tx_val (pkt_tx_val); + + pkt_if0.pkt_tx_full (pkt_tx_full); + + pkt_if0.pkt_rx_avail (pkt_rx_avail); + pkt_if0.pkt_rx_data (pkt_rx_data); + pkt_if0.pkt_rx_eop (pkt_rx_eop); + pkt_if0.pkt_rx_err (pkt_rx_err); + pkt_if0.pkt_rx_sop (pkt_rx_sop); + pkt_if0.pkt_rx_val (pkt_rx_val); + + pkt_if0.pkt_rx_ren (pkt_rx_ren); + + //--- + // XGMII Interface + + xgm_if0.clk_xgmii (clk_xgmii); + + xgm_if0.reset_xgmii_n (reset_xgmii_n); + + xgm_if0.xgmii_rxc (xgmii_rxc); + xgm_if0.xgmii_rxd (xgmii_rxd); + + xgm_if0.xgmii_txc (xgmii_txc); + xgm_if0.xgmii_txd (xgmii_txd); + + //--- + // Connect packet generators to physical interfaces + + pif_gen0.connect_fifo(pkt_if0.get_tx_fifo_ptr()); + xgm_gen0.connect_fifo(xgm_if0.get_tx_fifo_ptr()); + + //--- + // Connector scoreboard to components + + pkt_if0.connect_scoreboard(&sb, scoreboard::SB_PIF_ID); + xgm_if0.connect_scoreboard(&sb, scoreboard::SB_XGM_ID); + cpu_if0.connect_scoreboard(&sb, scoreboard::SB_CPU_ID); + + } + +}; + +#endif
tags/initial/tbench/systemc/sc_testbench.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/crc.h =================================================================== --- tags/initial/tbench/systemc/crc.h (nonexistent) +++ tags/initial/tbench/systemc/crc.h (revision 3) @@ -0,0 +1,18 @@ +/* + * efone - Distributed internet phone system. + * + * (c) 1999,2000 Krzysztof Dabrowski + * (c) 1999,2000 ElysiuM deeZine + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +/* based on implementation by Finn Yannick Jacobs. */ + +void chksum_crc32gentab (); +u_int32_t chksum_crc32 (sc_uint<8> *block, unsigned int length); +//extern u_int32_t crc_tab[256];
tags/initial/tbench/systemc/crc.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_scoreboard.h =================================================================== --- tags/initial/tbench/systemc/sc_scoreboard.h (nonexistent) +++ tags/initial/tbench/systemc/sc_scoreboard.h (revision 3) @@ -0,0 +1,157 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_scoreboard.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef SCOREBOARD_H +#define SCOREBOARD_H + +#include "systemc.h" + +#include "sc_packet.h" + + +struct sbStats_t { + int tx_pkt_cnt; + int rx_pkt_cnt; + + int crc_error_cnt; + int fragment_error_cnt; + int coding_error_cnt; + int flags_error_cnt; + + int inject_local_fault_cnt; + int inject_remote_fault_cnt; + + int inject_pause_frame_cnt; + + int detect_local_fault_cnt; + int detect_remote_fault_cnt; + + double timestamp_first_pkt; + double timestamp_last_pkt; + + int next_ifg_length; + int deficit_idle_count; +}; + +struct sbCpuStats_t { + int crc_error_cnt; + int fragment_error_cnt; + + int rxd_fifo_ovflow_cnt; + int rxd_fifo_udflow_cnt; + int txd_fifo_ovflow_cnt; + int txd_fifo_udflow_cnt; + + int rx_pause_frame_cnt; + + int local_fault_cnt; + int remote_fault_cnt; +}; + +SC_MODULE(scoreboard) { + + public: + + //--- + // Types + + enum sbSourceId { + SB_PIF_ID, + SB_XGM_ID, + SB_CPU_ID, + }; + + enum sbStatusId { + CRC_ERROR, + FRAGMENT_ERROR, + LOCAL_FAULT, + REMOTE_FAULT, + RXD_FIFO_OVFLOW, + RXD_FIFO_UDFLOW, + TXD_FIFO_OVFLOW, + TXD_FIFO_UDFLOW, + RX_GOOD_PAUSE_FRAME, + }; + + private: + + //--- + // Variables + + sc_fifo pif_fifo; + sc_fifo xgm_fifo; + + sbStats_t pif_stats; + sbStats_t xgm_stats; + sbCpuStats_t cpu_stats; + + public: + + //--- + // Variables + + bool disable_padding; + bool disable_crc_check; + bool disable_packet_check; + bool disable_flags_check; + bool disable_signal_check; + + //--- + // Functions + + void init(void); + + void notify_packet_tx(sbSourceId sid, packet_t* pkt); + void notify_packet_rx(sbSourceId sid, packet_t* pkt); + void notify_status(sbSourceId sid, sbStatusId statusId); + + sbStats_t* get_pif_stats(void); + sbStats_t* get_xgm_stats(void); + sbCpuStats_t* get_cpu_stats(void); + + void clear_stats(void); + + SC_CTOR(scoreboard): + pif_fifo (2000), + xgm_fifo (2000) { + + } + +}; + + +#endif
tags/initial/tbench/systemc/sc_scoreboard.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_xgmii_if.cpp =================================================================== --- tags/initial/tbench/systemc/sc_xgmii_if.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_xgmii_if.cpp (revision 3) @@ -0,0 +1,504 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_xgmii_if.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "sc_xgmii_if.h" + +sc_fifo * xgmii_if::get_tx_fifo_ptr() { + return &tx_fifo; +} + +sc_fifo * xgmii_if::get_rx_fifo_ptr() { + return &rx_fifo; +} + +void xgmii_if::init(void) { + allow_idle_errors = false; + disable_padding = false; +} + +void xgmii_if::connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid) { + sb = sbptr; + sb_id = sid; +} + +void xgmii_if::transmit() { + + packet_t* pkt; + + sc_uint<64> txd = 0; + sc_uint<8> txc = 0; + + int lane = 0; + int bytecnt = 0; + int length = 0; + int preamblecnt = 0; + int ifg = 0; + int fragment_size = 8; + int coding_offset = 0; + int fault_cnt = 0; + int fault_byte = 0; + int fault_spacing; + int fault_spacing_cnt = 0; + + while (true) { + + if (length == 0 && tx_fifo.nb_read(pkt)) { + + if (!disable_padding) { + pad(pkt, 60); + } + pack(pkt); + + calc_crc(pkt); + + //--- + // Inject errors + + if (pkt->err_flags & PKT_FLAG_ERR_CRC) { + pkt->crc++; + } + + if (pkt->err_flags & PKT_FLAG_ERR_FRG) { + pkt->length = fragment_size; + fragment_size++; + if (fragment_size > 64) { + fragment_size = 8; + } + } + + if (pkt->err_flags & PKT_FLAG_ERR_CODING) { + if (coding_offset >= pkt->length) { + pkt->err_info = pkt->length-1; + } + else { + pkt->err_info = coding_offset; + } + coding_offset++; + if (coding_offset >= 70) { + coding_offset = 0; + } + } + + //--- + // Inject local / remote faults + + if (pkt->err_flags & PKT_FLAG_LOCAL_FAULT || + pkt->err_flags & PKT_FLAG_REMOTE_FAULT) { + fault_cnt = 4; + fault_byte = 4; + fault_spacing_cnt = 0; + + fault_spacing = pkt->err_info; + cout << "INFO: Fault insert, spacing: " << fault_spacing << endl; + } + + //--- + // Pass packet to scoreboard + + sb->notify_packet_tx(sb_id, pkt); + + add_crc(pkt); + strip_crc(pkt); + length = pkt->length + 4; + + //cout << "Transmit XGMII packet:\n" << * pkt << endl; + + } + + + if (ifg != 0) { + txd |= ((sc_uint<64>)0x07) << (8 * lane); + txc |= 0x01 << lane; + ifg--; + + } + else if (fault_spacing_cnt != 0) { + + txd |= ((sc_uint<64>)0x07) << (8 * lane); + txc |= 0x01 << lane; + + fault_spacing_cnt--; + + } + else if ((lane == 0 || lane == 4) && fault_byte == 4) { + + txd |= ((sc_uint<64>)0x9c) << (8 * lane); + txc |= 0x01 << lane; + + fault_byte--; + + } + else if (fault_byte == 3 || fault_byte == 2) { + + fault_byte--; + + } + else if (fault_byte == 1) { + + if (pkt->err_flags & PKT_FLAG_LOCAL_FAULT) { + txd |= ((sc_uint<64>)0x01) << (8 * lane); + } + else { + txd |= ((sc_uint<64>)0x02) << (8 * lane); + } + fault_byte--; + + fault_cnt--; + if (fault_cnt > 0) { + fault_byte = 4; + } + + if (fault_cnt == 1) { + fault_spacing_cnt = 4 * fault_spacing; + } + } + else if ((lane == 0 || lane == 4) && bytecnt != length && preamblecnt == 0) { + + txd |= ((sc_uint<64>)0xfb) << (8 * lane); + txc |= 0x01 << lane; + + preamblecnt++; + + } + else if (preamblecnt > 0 && preamblecnt < 7) { + + txd |= ((sc_uint<64>)0x55) << (8 * lane); + + preamblecnt++; + + } + else if (preamblecnt == 7) { + + txd |= ((sc_uint<64>)0xd5) << (8 * lane); + + preamblecnt++; + + } + else if (preamblecnt > 7 && (bytecnt == (length-4)) && + (pkt->err_flags & PKT_FLAG_ERR_FRG)) { + + //--- + // Fragment insertion + + bytecnt = 0; + length = 0; + preamblecnt = 0; + ifg = 0; + + } + else if (preamblecnt >7 && bytecnt == pkt->err_info && + (pkt->err_flags & PKT_FLAG_ERR_CODING)) { + + //--- + // Coding error insertion + + txc |= 0x01 << lane; + txd |= ((sc_uint<64>)pkt->data[bytecnt]) << (8 * lane); + bytecnt++; + + } + else if (preamblecnt > 7 && bytecnt < length) { + + txd |= ((sc_uint<64>)pkt->data[bytecnt]) << (8 * lane); + bytecnt++; + + } + else if (preamblecnt > 7 && bytecnt == length) { + + //--- + // End of frame TERMINATE + + txd |= ((sc_uint<64>)0xfd) << (8 * lane); + txc |= 0x01 << lane; + + bytecnt = 0; + length = 0; + preamblecnt = 0; + + // Minimum IFG is 5 including TERMINATE + ifg = 4; + + } + else { + txd |= ((sc_uint<64>)0x07) << (8 * lane); + txc |= 0x01 << lane; + } + if (lane == 7) { + xgmii_rxd = txd; + xgmii_rxc = txc; + txd = 0; + txc = 0; + wait(); + } + lane = (lane + 1) % 8; + + } +}; + + +void xgmii_if::receive() { + + packet_t* pkt; + + sc_uint<64> rxd; + sc_uint<8> rxc; + + int lane, bytecnt, ifgcnt; + + lane = 0; + + wait(); + + while (true) { + + ifgcnt = 1; + + rxd = xgmii_txd; + rxc = xgmii_txc; + + + //--- + // Wait for START code in lane0 or lane4 + + while (true) { + + // Check for START character + if (((rxd >> (8*lane)) & 0xff) == 0xfb && ((rxc >> lane) & 0x1) == 1) { + if (disable_receive) { + cout << "INFO: XGMII Receive Disabled" << endl; + } + else { + break; + } + }; + + // Check IDLE character and control lines + if (((rxd >> (8*lane)) & 0xff) != 0x07 || ((rxc >> lane) & 0x1) != 1) { + if (allow_idle_errors) { + cout << "INFO: IDLE check disabled" << endl; + } + else { + cout << "ERROR: IDLE character " << hex << rxd << " " << rxc << dec << lane << endl; + sc_stop(); + } + }; + + ifgcnt++; + + lane = (lane + 1) % 8; + if (lane == 0) { + wait(); + rxd = xgmii_txd; + rxc = xgmii_txc; + } + } + + //cout << "START in lane " << lane << " IFG " << ifgcnt << endl; + + // Check starting lane + if (lane != 0 && lane != 4) { + cout << "ERROR: Lane aligment" << endl; + sc_stop(); + } + + // Check for minimum inter frame gap + if (ifgcnt < 9) { + cout << "ERROR: MINIMUM IFG " << ifgcnt << endl; + sc_stop(); + } + + //--- + // Capture data until end of frame is detected (TERMINATE) + + pkt = new(packet_t); + pkt->ifg = ifgcnt; + pkt->start_lane = lane; + pkt->length = 0; + + bytecnt = 0; + while (true) { + + // Look for end of frame delimiter in any lane + if (((rxd >> (8*lane)) & 0xff) == 0xfd && ((rxc >> lane) & 0x1) == 1) { + break; + }; + + // Stop if packet is too long + if (bytecnt >= 10000) { + break; + } + + // Validate preamble bytes + if (bytecnt > 0 && bytecnt <= 6 && ((rxd >> (8*lane)) & 0xff) != 0x55) { + cout << "ERROR: Invalid preamble byte: " << bytecnt << endl; + sc_stop(); + } + + // Validate SFD code in preamble + if (bytecnt == 7 && ((rxd >> (8*lane)) & 0xff) != 0xd5) { + cout << "ERROR: Invalid preamble byte: " << bytecnt << endl; + sc_stop(); + } + + // Store all bytes after preamble + if (bytecnt > 7) { + if (((rxc >> lane) & 0x1) == 0) { + pkt->data[pkt->length] = ((rxd >> (8*lane)) & 0xff); + pkt->length++; + } + else { + cout << "ERROR: RXC high during data cycle" << endl; + sc_stop(); + } + } + else if (bytecnt > 0) { + if (((rxc >> lane) & 0x1) == 1) { + cout << "ERROR: RXC high during preamble" << endl; + sc_stop(); + } + } + + bytecnt++; + lane = (lane + 1) % 8; + if (lane == 0) { + wait(); + rxd = xgmii_txd; + rxc = xgmii_txc; + } + } + + + lane = (lane + 1) % 8; + if (lane == 0) { + wait(); + rxd = xgmii_txd; + rxc = xgmii_txc; + } + + //--- + // Store packet + + strip_crc(pkt); + + unpack(pkt); + //rx_fifo.write(pkt); + //cout << "Received XGMII packet:" << * pkt << endl; + + //--- + // Pass packet to scoreboard + + sb->notify_packet_rx(sb_id, pkt); + + } +}; + + +void xgmii_if::monitor() { + + sc_uint<64> rxd; + sc_uint<8> rxc; + + wait(); + + while (true) { + + rxd = xgmii_txd; + rxc = xgmii_txc; + + //--- + // Check for local/remote fault + + if (((rxd & 0xffffffff) == 0x0100009c && (rxc & 0xf) == 0x1) && + (((rxd >> 32) & 0xffffffff) == 0x0100009c && ((rxc > 4) & 0xf) == 0x1)) { + + //-- + // Local fault detection + + if (!rx_local_fault) { + cout << "XGMII Local Fault Asserted" << endl; + + // Notify Scoreboard + sb->notify_status(sb_id, scoreboard::LOCAL_FAULT); + } + rx_local_fault = true; + + } + else { + + if (rx_local_fault) { + cout << "XGMII Local Fault De-Asserted" << endl; + } + rx_local_fault = false; + + } + + if (((rxd & 0xffffffff) == 0x0200009c && (rxc & 0xf) == 0x1) && + (((rxd >> 32) & 0xffffffff) == 0x0200009c && ((rxc > 4) & 0xf) == 0x1)) { + + //-- + // Remote fault detection + + if (!rx_remote_fault) { + cout << "XGMII Remote Fault Asserted" << endl; + + // Notify Scoreboard + sb->notify_status(sb_id, scoreboard::REMOTE_FAULT); + } + rx_remote_fault = true; + + } + else { + + if (rx_remote_fault) { + cout << "XGMII Remote Fault De-Asserted" << endl; + } + rx_remote_fault = false; + + } + + wait(); + } +}; + +
tags/initial/tbench/systemc/sc_xgmii_if.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_testcases.cpp =================================================================== --- tags/initial/tbench/systemc/sc_testcases.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_testcases.cpp (revision 3) @@ -0,0 +1,749 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_testcases.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include "sc_testcases.h" + + +void testcases::connect_testbench(testbench* tbptr) { + tb = tbptr; +} + +void testcases::run_tests(void) { + + //--- + // Init + + tb->pkt_if0.init(); + tb->xgm_if0.init(); + tb->cpu_if0.init(); + tb->pif_gen0.init(); + tb->xgm_gen0.init(); + tb->sb.init(); + + wait(300, SC_NS); + + tb->cpu_if0.enable_all_interrupts(); + + + + +// done = true; +// return; + //--- + // Testcases + + test_packet_size(50, 90, 50); + test_packet_size(9000, 9020, 20); + + test_deficit_idle_count(); + + test_crc_errors(50, 90, 300, 2); + test_crc_errors(9000, 9020, 20, 1); + + test_txdfifo_ovflow(); + test_rxdfifo_ovflow(); + + test_rx_fragments(55, 90, 300, 2); + test_rx_coding_err(400, 4); + + test_rx_local_fault(55, 90, 600, 15); + test_rx_remote_fault(55, 90, 600, 15); + + test_rx_pause(64, 70, 600, 5); + + test_interrupt_mask(); + + done = true; + +} + + +void testcases::test_deficit_idle_count(void) { + + int range; + int size; + + cout << "-----------------------" << endl; + cout << "Deficit IDLE count" << endl; + cout << "-----------------------" << endl; + + for (range = 0; range < 8; range++) { + for (size = 60; size < 68; size++) { + packet_dic(size, size + range); + } + } + +} + + +void testcases::packet_dic(int minsize, int maxsize) { + + sbStats_t* pif_stats; + sbStats_t* xgm_stats; + + int cnt = 6; + float delta; + float cycletime = 6.4; + float rate; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->pif_gen0.set_pkt_size(minsize, maxsize); + tb->xgm_gen0.set_pkt_size(minsize, maxsize); + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(cnt); + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->pif_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(1000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + xgm_stats = tb->sb.get_xgm_stats(); + + if (pif_stats->rx_pkt_cnt != cnt || xgm_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received." << endl; + sc_stop(); + } + +} + + +void testcases::test_packet_size(int min, int max, int cnt) { + + sbStats_t* pif_stats; + sbStats_t* xgm_stats; + + cout << "-----------------------" << endl; + cout << "Packet size" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->pif_gen0.set_pkt_size(min, max); + tb->xgm_gen0.set_pkt_size(min, max); + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(cnt); + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->pif_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + xgm_stats = tb->sb.get_xgm_stats(); + + if (pif_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } + + if (xgm_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by XGM." << endl; + cout << xgm_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } +} + +void testcases::test_crc_errors(int min, int max, int cnt, int interval) { + + sbStats_t* pif_stats; + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "CRC errors" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->xgm_gen0.set_pkt_size(min, max); + tb->xgm_gen0.set_crc_errors(interval); + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + cpu_stats = tb->sb.get_cpu_stats(); + + if (pif_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } + + if (cpu_stats->crc_error_cnt != pif_stats->crc_error_cnt) { + cout << "ERROR: Not all CRC errors reported to cpu" << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_crc_errors(0); + tb->sb.disable_signal_check = false; +} + +void testcases::test_txdfifo_ovflow() { + + sbStats_t* xgm_stats; + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "TXD FIFO overflow" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->pif_gen0.set_pkt_size(1000, 1000); + + tb->cpu_if0.set_param(cpu_if::TX_ENABLE, 0); + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(2); + + //--- + // Wait for packets to be sent + + while (tb->pif_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + wait(30000, SC_NS); + + //--- + // Check errors reported + + cpu_stats = tb->sb.get_cpu_stats(); + cout << "Count: " << cpu_stats->txd_fifo_ovflow_cnt << endl; + sc_assert(cpu_stats->txd_fifo_ovflow_cnt == 1); + + //--- + // Flush out bad packets + + tb->xgm_if0.allow_idle_errors = true; + tb->sb.disable_packet_check = true; + tb->cpu_if0.set_param(cpu_if::TX_ENABLE, 1); + + wait(30000, SC_NS); + tb->xgm_if0.allow_idle_errors = false; + tb->sb.disable_packet_check = false; + + //--- + // Check errors reported + + cpu_stats = tb->sb.get_cpu_stats(); + sc_assert(cpu_stats->txd_fifo_udflow_cnt == 1); + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(2); + + //--- + // Wait for packets to be sent + + while (tb->pif_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + wait(30000, SC_NS); + + xgm_stats = tb->sb.get_xgm_stats(); + sc_assert(xgm_stats->rx_pkt_cnt == 4); + + //--- + // Return parameters to default state + + tb->cpu_if0.set_param(cpu_if::TX_ENABLE, 1); + tb->sb.disable_signal_check = false; +} + +void testcases::test_rxdfifo_ovflow() { + + sbStats_t* pif_stats; + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "RXD FIFO overflow" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->xgm_gen0.set_pkt_size(1000, 1000); + + tb->pkt_if0.disable_rx = true; + tb->pkt_if0.allow_rx_sop_err = true; + tb->sb.disable_flags_check = true; + tb->sb.disable_packet_check = true; + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(3); + + //--- + // Wait for packets to be sent + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + wait(30000, SC_NS); + + //--- + // Check errors reported + + cpu_stats = tb->sb.get_cpu_stats(); + sc_assert(cpu_stats->rxd_fifo_ovflow_cnt == 2); + + //--- + // Flush out bad packets + + tb->pkt_if0.disable_rx = false; + + wait(30000, SC_NS); + + //--- + // Check errors reported + + cpu_stats = tb->sb.get_cpu_stats(); + tb->sb.clear_stats(); + tb->sb.disable_flags_check = false; + tb->sb.disable_packet_check = false; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(2); + + //--- + // Wait for packets to be sent + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + sc_assert(pif_stats->rx_pkt_cnt == 2); + + //--- + // Return parameters to default state + + tb->pkt_if0.allow_rx_sop_err = false; + tb->sb.disable_signal_check = false; +} + +void testcases::test_rx_fragments(int min, int max, int cnt, int interval) { + + sbStats_t* pif_stats; + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "Fragments errors" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->xgm_gen0.set_pkt_size(min, max); + tb->xgm_gen0.set_fragment_errors(interval); + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + cpu_stats = tb->sb.get_cpu_stats(); + + if (pif_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } + + if ((cpu_stats->fragment_error_cnt + cpu_stats->crc_error_cnt) + != pif_stats->fragment_error_cnt) { + cout << "ERROR: Not all fragment errors reported to cpu" << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_fragment_errors(0); + tb->sb.disable_signal_check = false; +} + +void testcases::test_rx_coding_err(int cnt, int interval) { + + sbStats_t* pif_stats; + sbStats_t* xgm_stats; + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "Coding errors" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->xgm_gen0.set_pkt_size(64, 69); + tb->xgm_gen0.set_coding_errors(interval); + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + xgm_stats = tb->sb.get_xgm_stats(); + cpu_stats = tb->sb.get_cpu_stats(); + + if (pif_stats->rx_pkt_cnt != xgm_stats->tx_pkt_cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << xgm_stats->tx_pkt_cnt << endl; + sc_stop(); + } + + if (cpu_stats->crc_error_cnt != xgm_stats->crc_error_cnt) { + cout << "ERROR: Not all coding errors reported to cpu" << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_coding_errors(0); + tb->sb.disable_signal_check = false; +} + +void testcases::test_rx_local_fault(int min, int max, int cnt, int interval) { + + sbStats_t* pif_stats; + + cout << "-----------------------" << endl; + cout << "Local fault" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->pif_gen0.set_pkt_size(min, max); + tb->xgm_gen0.set_pkt_size(min, max); + + tb->xgm_gen0.set_local_fault(interval); + tb->sb.disable_signal_check = true; + tb->xgm_if0.allow_idle_errors = true; + tb->xgm_if0.disable_receive = true; + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(cnt); + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + + if (pif_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_local_fault(0); + tb->sb.disable_signal_check = false; + tb->xgm_if0.allow_idle_errors = false; + tb->xgm_if0.disable_receive = false; +} + +void testcases::test_rx_remote_fault(int min, int max, int cnt, int interval) { + + sbStats_t* pif_stats; + + cout << "-----------------------" << endl; + cout << "Remote fault" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->pif_gen0.set_pkt_size(min, max); + tb->xgm_gen0.set_pkt_size(min, max); + + tb->xgm_gen0.set_remote_fault(interval); + tb->sb.disable_signal_check = true; + tb->xgm_if0.allow_idle_errors = true; + tb->xgm_if0.disable_receive = true; + + //--- + // Enable traffic + + tb->pif_gen0.set_tx_bucket(cnt); + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + pif_stats = tb->sb.get_pif_stats(); + + if (pif_stats->rx_pkt_cnt != cnt) { + cout << "ERROR: Not all packets received by PIF." << endl; + cout << pif_stats->rx_pkt_cnt << " " << cnt << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_remote_fault(0); + tb->sb.disable_signal_check = false; + tb->xgm_if0.allow_idle_errors = false; + tb->xgm_if0.disable_receive = false; +} + +void testcases::test_rx_pause(int min, int max, int cnt, int interval) { + + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "Receive Pause" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + + tb->xgm_gen0.set_pkt_size(min, max); + + tb->xgm_gen0.set_inject_pause(interval); + tb->sb.disable_signal_check = true; + + //--- + // Enable traffic + + tb->xgm_gen0.set_tx_bucket(cnt); + + //--- + // Wait for test to complete + + while (tb->xgm_gen0.get_tx_bucket() != 0) { + wait(10, SC_NS); + } + + //--- + // Check traffic + + wait(30000, SC_NS); + + cpu_stats = tb->sb.get_cpu_stats(); + + if (cpu_stats->rx_pause_frame_cnt == 0) { + cout << "ERROR: No pause frames received." << endl; + sc_stop(); + } + + //--- + // Return parameters to default state + + tb->xgm_gen0.set_inject_pause(0); + tb->sb.disable_signal_check = false; +} + +void testcases::test_interrupt_mask() { + + sbCpuStats_t* cpu_stats; + + cout << "-----------------------" << endl; + cout << "Interrupt Mask" << endl; + cout << "-----------------------" << endl; + + //--- + // Setup parameters + + tb->sb.clear_stats(); + tb->sb.disable_signal_check = true; + + + //--- + // Test unmasked + + tb->cpu_if0.set_interrupt(cpu_if::INT_CRC_ERROR); + + wait(300, SC_NS); + + cpu_stats = tb->sb.get_cpu_stats(); + sc_assert(cpu_stats->crc_error_cnt == 1); + + + //--- + // Test masked + + tb->cpu_if0.set_interrupt_mask(cpu_if::INT_CRC_ERROR, 0); + tb->cpu_if0.set_interrupt(cpu_if::INT_CRC_ERROR); + + wait(300, SC_NS); + + cpu_stats = tb->sb.get_cpu_stats(); + sc_assert(cpu_stats->crc_error_cnt == 1); + + + //--- + // Return parameters to default state + + tb->sb.disable_signal_check = false; + tb->cpu_if0.set_interrupt_mask(cpu_if::INT_CRC_ERROR, 1); +} +
tags/initial/tbench/systemc/sc_testcases.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_xgmii_if.h =================================================================== --- tags/initial/tbench/systemc/sc_xgmii_if.h (nonexistent) +++ tags/initial/tbench/systemc/sc_xgmii_if.h (revision 3) @@ -0,0 +1,115 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_xgmii_if.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#ifndef XGMII_IF_H +#define XGMII_IF_H + +#include "systemc.h" + +#include "sc_packet.h" +#include "sc_scoreboard.h" + +SC_MODULE(xgmii_if) { + + public: + + //--- + // Ports + + sc_in clk_xgmii; + + sc_in reset_xgmii_n; + + sc_out xgmii_rxc; + sc_out > xgmii_rxd; + + sc_in xgmii_txc; + sc_in > xgmii_txd; + + private: + + //--- + // Variables + + sc_fifo tx_fifo; + sc_fifo rx_fifo; + + scoreboard *sb; + scoreboard::sbSourceId sb_id; + + public: + + //--- + // Variables + + bool allow_idle_errors; + bool disable_receive; + bool disable_padding; + + bool rx_local_fault; + bool rx_remote_fault; + + //--- + // Functions + + sc_fifo * get_tx_fifo_ptr(); + sc_fifo * get_rx_fifo_ptr(); + + void init(void); + void connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid); + + //--- + // Threads + + void transmit(); + void receive(); + void monitor(); + + SC_CTOR(xgmii_if) : + tx_fifo (2), + rx_fifo (2) { + + SC_CTHREAD (transmit, clk_xgmii.pos()); + + SC_CTHREAD (receive, clk_xgmii.pos()); + + SC_CTHREAD (monitor, clk_xgmii.pos()); + } + +}; + +#endif
tags/initial/tbench/systemc/sc_xgmii_if.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_testcases.h =================================================================== --- tags/initial/tbench/systemc/sc_testcases.h (nonexistent) +++ tags/initial/tbench/systemc/sc_testcases.h (revision 3) @@ -0,0 +1,96 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_testcases.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include "systemc.h" + +#include "sc_testbench.h" + + + +SC_MODULE(testcases) { + + public: + + //--- + // Variables + + bool done; + + private: + + testbench* tb; + + public: + + //--- + // Functions + + void connect_testbench(testbench* tbptr); + + void test_deficit_idle_count(void); + void packet_dic(int minsize, int maxsize); + + void test_packet_size(int min, int max, int cnt); + + void test_crc_errors(int min, int max, int cnt, int interval); + + void test_txdfifo_ovflow(); + void test_rxdfifo_ovflow(); + + void test_rx_fragments(int min, int max, int cnt, int interval); + void test_rx_coding_err(int cnt, int interval); + void test_rx_local_fault(int min, int max, int cnt, int interval); + void test_rx_remote_fault(int min, int max, int cnt, int interval); + + void test_rx_pause(int min, int max, int cnt, int interval); + + void test_interrupt_mask(); + + //--- + // Threads + + void run_tests(void); + + SC_CTOR(testcases) { + + done = false; + + SC_THREAD (run_tests); + + } + +};
tags/initial/tbench/systemc/sc_testcases.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_pkt_generator.cpp =================================================================== --- tags/initial/tbench/systemc/sc_pkt_generator.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_pkt_generator.cpp (revision 3) @@ -0,0 +1,265 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_pkt_generator.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "sc_pkt_generator.h" + + +void pkt_generator::init(void) { + crc_interval = 0; + fragment_interval = 0; + coding_interval = 0; + local_fault_interval = 0; + remote_fault_interval = 0; +} + +void pkt_generator::connect_fifo(sc_fifo * fifo) { + tx_fifo = fifo; +} + + +void pkt_generator::gen_packet() { + + int len = 0; + int crc_int = 0; + int fragment_int = 0; + int coding_int = 0; + int local_fault_int = 0; + int remote_fault_int = 0; + int fault_spacing = 120; + int pause_int = 0; + char running_cnt = 0; + + while (true) { + + wait(5, SC_NS); + + if (tx_bucket != 0 && tx_fifo->num_available() == 0) { + + //-- + // Check fifo + + if (tx_fifo == NULL || tx_fifo->num_free() == 0) { + cout << "ERROR: FIFO not defined or full" << endl; + sc_stop(); + } + + //--- + // Update constraints + + if (len < min_pkt_size) { + len = min_pkt_size; + } + + if (len > max_pkt_size) { + len = min_pkt_size; + } + + //-- + // Generate packet + + packet_t* pkt = new(packet_t); + + for (int i = 0; i < len+8; i++) { + pkt->payload[i] = len+i; + } + pkt->payload[0] = running_cnt; + running_cnt++; + + pkt->length = len; + + //--- + // Inject errors + + if (crc_interval != 0) { + if (crc_int >= crc_interval) { + pkt->err_flags |= PKT_FLAG_ERR_CRC; + crc_int = 0; + } + else { + crc_int++; + } + } + else { + crc_int = 0; + } + + if (fragment_interval != 0) { + if (fragment_int >= fragment_interval) { + pkt->err_flags |= PKT_FLAG_ERR_FRG; + fragment_int = 0; + } + else { + fragment_int++; + } + } + else { + fragment_int = 0; + } + + if (coding_interval != 0) { + if (coding_int >= coding_interval) { + pkt->err_flags |= PKT_FLAG_ERR_CODING; + coding_int = 0; + } + else { + coding_int++; + } + } + else { + coding_int = 0; + } + + //-- + // Inject local / remote faults + + if (local_fault_interval != 0) { + if (local_fault_int >= local_fault_interval) { + + pkt->err_flags |= PKT_FLAG_LOCAL_FAULT; + local_fault_int = 0; + + fault_spacing++; + if (fault_spacing > (132 - 4)) { + fault_spacing = 120; + } + pkt->err_info = fault_spacing; + } + else { + local_fault_int++; + } + } + else { + local_fault_int = 0; + } + + if (remote_fault_interval != 0) { + if (remote_fault_int >= remote_fault_interval) { + + pkt->err_flags |= PKT_FLAG_REMOTE_FAULT; + remote_fault_int = 0; + + fault_spacing++; + if (fault_spacing > (132 - 4)) { + fault_spacing = 120; + } + pkt->err_info = fault_spacing; + } + else { + remote_fault_int++; + } + } + else { + remote_fault_int = 0; + } + + //-- + // Inject PAUSE frames + + if (inject_pause_interval != 0) { + if (pause_int >= inject_pause_interval) { + + pkt->dest_addr = 0x0180c2; + pkt->dest_addr = (pkt->dest_addr << 24) | 0x000001; + pause_int = 0; + + } + else { + pause_int++; + } + } + + //-- + // Send packet + + tx_fifo->write(pkt); + + tx_bucket--; + len++; + + } + else { + wait(50, SC_NS); + } + + } +} + +void pkt_generator::set_tx_bucket(int cnt) { + tx_bucket = cnt; +} + +int pkt_generator::get_tx_bucket(void) { + return tx_bucket; +} + +void pkt_generator::set_pkt_size(int min, int max) { + + min_pkt_size = min; + max_pkt_size = max; + +} + +void pkt_generator::set_crc_errors(int interval) { + crc_interval = interval; +} + +void pkt_generator::set_fragment_errors(int interval) { + fragment_interval = interval; +} + +void pkt_generator::set_coding_errors(int interval) { + coding_interval = interval; +} + +void pkt_generator::set_local_fault(int interval) { + local_fault_interval = interval; +} + +void pkt_generator::set_remote_fault(int interval) { + remote_fault_interval = interval; +} + +void pkt_generator::set_inject_pause(int interval) { + inject_pause_interval = interval; +}
tags/initial/tbench/systemc/sc_pkt_generator.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_cpu_if.cpp =================================================================== --- tags/initial/tbench/systemc/sc_cpu_if.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_cpu_if.cpp (revision 3) @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_cpu_if.h" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "sc_cpu_if.h" + +void cpu_if::init() { +}; + +void cpu_if::connect_scoreboard(scoreboard *sbptr, scoreboard::sbSourceId sid) { + sb = sbptr; + sb_id = sid; +} + +void cpu_if::set_param(cpu_if::paramId param, int value) { + + switch (param) { + + case TX_ENABLE: + writebits(cpu_if::CPUREG_CONFIG0, 0, 0, value); + break; + + } + +}; + +void cpu_if::set_interrupt(cpu_if::intId intr) { + + writebits(cpu_if::CPUREG_INT_PENDING, intr, intr, 1); +}; + +void cpu_if::set_interrupt_mask(cpu_if::intId intr, bool value) { + + writebits(cpu_if::CPUREG_INT_MASK, intr, intr, value); +}; + +void cpu_if::enable_all_interrupts(void) { + + write(cpu_if::CPUREG_INT_MASK, 0xffffffff); +}; + +uint cpu_if::read(uint addr) { + + uint data; + + //-- + // Wait for bus to be free, lock it, start transaction + + bus_lock.lock(); + bus_addr = addr; + bus_write = false; + bus_start.notify(); + + //-- + // Wait for transaction to complete + + while (bus_done.trywait()) { + wait(10, SC_NS); + }; + + //-- + // Get the data, free the bus + + data = bus_data; + cout << hex << "READ ADDR 0x" << addr << ": 0x" << data << dec << endl; + bus_lock.unlock(); + + return data; +}; + +void cpu_if::write(uint addr, uint data) { + + //-- + // Wait for bus to be free, lock it, start transaction + + bus_lock.lock(); + bus_addr = addr; + bus_data = data; + bus_write = true; + bus_start.notify(); + + //-- + // Wait for transaction to complete + + while (bus_done.trywait()) { + wait(10, SC_NS); + }; + + //-- + // Free the bus + + cout << hex << "WRITE ADDR 0x" << addr << ": 0x" << data << dec << endl; + bus_lock.unlock(); +}; + +void cpu_if::writebits(uint addr, uint hbit, uint lbit, uint value) { + + uint data; + uint mask; + + mask = ~((0xffffffff << lbit) & (0xffffffff >> (31-lbit))); + + data = mask & read(addr); + data = data | ((value << lbit) & ~mask); + + write(addr, data); +}; + +void cpu_if::transactor() { + + + while (true) { + + // Wait for a transaction + wait(bus_start); + + if (!bus_write) { + + //--- + // Read access + + // Start of access + wb_adr_i = bus_addr; + wb_dat_i = 0; + + wb_cyc_i = 1; + wb_stb_i = 1; + wb_we_i = 0; + + // Wait for ack + while (wb_ack_o != 1) { + wait(); + } + + // Capture data + bus_data = wb_dat_o; + + wb_adr_i = 0; + wb_dat_i = 0; + + wb_cyc_i = 0; + wb_stb_i = 0; + + } + else { + + //--- + // Write access + + // Start of access + wb_adr_i = bus_addr; + wb_dat_i = bus_data; + + wb_cyc_i = 1; + wb_stb_i = 1; + wb_we_i = 1; + + // Wait for ack + while (wb_ack_o != 1) { + wait(); + } + + // End cycle + wb_adr_i = 0; + wb_dat_i = 0; + + wb_cyc_i = 0; + wb_stb_i = 0; + wb_we_i = 0; + + } + + bus_done.post(); + } +}; + +void cpu_if::monitor() { + + uint data; + + wait(); + + while (true) { + + if (wb_int_o) { + + //--- + // Read interrupt register when interrupt signal is asserted + + data = read(cpu_if::CPUREG_INT_PENDING); + + cout << "READ INTERRUPTS: 0x" << hex << data << dec << endl; + + //--- + // Notify scoreboard + + if ((data >> cpu_if::INT_CRC_ERROR) & 0x1) { + sb->notify_status(sb_id, scoreboard::CRC_ERROR); + } + + if ((data >> cpu_if::INT_FRAGMENT_ERROR) & 0x1) { + sb->notify_status(sb_id, scoreboard::FRAGMENT_ERROR); + } + + if ((data >> cpu_if::INT_LOCAL_FAULT) & 0x1) { + + data = read(cpu_if::CPUREG_INT_STATUS); + + if ((data >> cpu_if::INT_LOCAL_FAULT) & 0x1) { + sb->notify_status(sb_id, scoreboard::LOCAL_FAULT); + } + } + + if ((data >> cpu_if::INT_REMOTE_FAULT) & 0x1) { + + data = read(cpu_if::CPUREG_INT_STATUS); + + if ((data >> cpu_if::INT_REMOTE_FAULT) & 0x1) { + sb->notify_status(sb_id, scoreboard::REMOTE_FAULT); + } + } + + if ((data >> cpu_if::INT_RXD_FIFO_OVFLOW) & 0x1) { + sb->notify_status(sb_id, scoreboard::RXD_FIFO_OVFLOW); + } + + if ((data >> cpu_if::INT_RXD_FIFO_UDFLOW) & 0x1) { + sb->notify_status(sb_id, scoreboard::RXD_FIFO_UDFLOW); + } + + if ((data >> cpu_if::INT_TXD_FIFO_OVFLOW) & 0x1) { + sb->notify_status(sb_id, scoreboard::TXD_FIFO_OVFLOW); + } + + if ((data >> cpu_if::INT_TXD_FIFO_UDFLOW) & 0x1) { + sb->notify_status(sb_id, scoreboard::TXD_FIFO_UDFLOW); + } + + if ((data >> cpu_if::INT_PAUSE_FRAME) & 0x1) { + sb->notify_status(sb_id, scoreboard::RX_GOOD_PAUSE_FRAME); + } + + } + + wait(); + } +};
tags/initial/tbench/systemc/sc_cpu_if.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/systemc/sc_packet.cpp =================================================================== --- tags/initial/tbench/systemc/sc_packet.cpp (nonexistent) +++ tags/initial/tbench/systemc/sc_packet.cpp (revision 3) @@ -0,0 +1,151 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sc_packet.cpp" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +#include "systemc.h" + +#include "crc.h" +#include "sc_packet.h" + +ostream& operator<<(ostream& os, const packet_t& p) { + os << "\n=====================\n" + << dec + << " length : " << p.length << "\n" + << hex + << " src_addr : 0x" << p.src_addr << "\n" + << " dest_addr: 0x" << p.dest_addr << "\n" + << " crc : 0x" << p.crc << "\n" + << " crc_rx : 0x" << p.crc_rx << "\n" + << " err_flags: 0x" << p.err_flags << "\n" + << " payload : " << "\n"; + + for (int i = 0; i < p.length; i++) { + os << p.payload[i] << " "; + } + + cout << "\n--\n"; + + for (int i = 0; i < p.length; i++) { + os << p.data[i] << " "; + } + + os << dec << "\n" << endl; + + return os; +} + +void pack(packet_t* p) { + if (p->dest_addr != 0) { + for (int i = 0; i < 6; i++) { + p->payload[i] = p->dest_addr >> ((5-i)*8); + } + } + for (int i = 0; i < p->length; i++) { + p->data[i] = p->payload[i]; + } +} + + +void unpack(packet_t* p) { + for (int i = 0; i < p->length; i++) { + p->payload[i] = p->data[i]; + } +} + +void add_crc(packet_t* p) { + for (int i = p->length; i < p->length + 4; i++) { + p->data[i] = p->crc >> (8 * (i - p->length)); + } + p->length += 4; +} + +void strip_crc(packet_t* p) { + if (p->length >= 4) { + p->crc_rx = 0; + for (int i = p->length - 4; i < p->length; i++) { + p->crc_rx |= p->data[i] << (8 * (i - p->length - 4)); + } + p->length -= 4; + } +} + +void calc_crc(packet_t* p) { + + u_int32_t crc; + + p->crc = chksum_crc32(p->data, p->length); +} + +void pad(packet_t* p, int len) { + if (p->length < len) { + for (int i = p->length; i < len; i++) { + p->payload[i] = 0; + } + p->length = len; + }; +} + +bool compare(packet_t* pkta, packet_t* pktb) { + + bool good = true; + + if (pkta->length != pktb->length) { + + good = false; + + } + else { + + if (pkta->crc != pktb->crc) { + good = false; + } + + for (int i = 0; i < pkta->length; i++) { + if (pkta->payload[i] != pktb->payload[i]) { + good = false; + } + } + + } + + return good; +} +
tags/initial/tbench/systemc/sc_packet.cpp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/verilog/packets_tx.txt =================================================================== --- tags/initial/tbench/verilog/packets_tx.txt (nonexistent) +++ tags/initial/tbench/verilog/packets_tx.txt (revision 3) @@ -0,0 +1,73 @@ +SEND_PKT +59 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c + +SEND_PKT +60 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d + +SEND_PKT +61 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e + +SEND_PKT +62 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f + +SEND_PKT +63 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 + +SEND_PKT +64 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 + +SEND_PKT +65 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 +32 + +SEND_PKT +66 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 +32 33 + +SEND_PKT +67 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 +32 33 34 + +SEND_PKT +68 +00 00 01 00 00 01 00 10 94 00 00 02 88 b5 00 01 +02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 +12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 +22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 +32 33 34 35 \ No newline at end of file
tags/initial/tbench/verilog/packets_tx.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/tbench/verilog/tb_xge_mac.v =================================================================== --- tags/initial/tbench/verilog/tb_xge_mac.v (nonexistent) +++ tags/initial/tbench/verilog/tb_xge_mac.v (revision 3) @@ -0,0 +1,383 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "tb_xge_mac.v" //// +//// //// +//// This file is part of the "10GE MAC" project //// +//// http://www.opencores.org/cores/xge_mac/ //// +//// //// +//// Author(s): //// +//// - A. Tanguay (antanguay@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 AUTHORS. All rights reserved. //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "timescale.v" +`include "defines.v" + +module tb; + + +/*AUTOREG*/ +// Beginning of automatic regs (for this module's undeclared outputs) +// End of automatics + +reg [7:0] tx_buffer[0:10000]; +integer tx_length; + +reg clk_156m25; +reg clk_xgmii_rx; +reg clk_xgmii_tx; + +reg reset_156m25_n; +reg reset_xgmii_rx_n; +reg reset_xgmii_tx_n; + +reg pkt_rx_ren; + +reg [63:0] pkt_tx_data; +reg pkt_tx_val; +reg pkt_tx_sop; +reg [7:0] pkt_tx_eop; + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +wire pkt_rx_avail; // From dut of xge_mac.v +wire [63:0] pkt_rx_data; // From dut of xge_mac.v +wire [7:0] pkt_rx_eop; // From dut of xge_mac.v +wire pkt_rx_err; // From dut of xge_mac.v +wire pkt_rx_sop; // From dut of xge_mac.v +wire pkt_rx_val; // From dut of xge_mac.v +wire pkt_tx_full; // From dut of xge_mac.v +wire wb_ack_o; // From dut of xge_mac.v +wire [31:0] wb_dat_o; // From dut of xge_mac.v +wire wb_int_o; // From dut of xge_mac.v +wire [7:0] xgmii_txc; // From dut of xge_mac.v +wire [63:0] xgmii_txd; // From dut of xge_mac.v +// End of automatics + +wire [7:0] wb_adr_i; +wire [31:0] wb_dat_i; + +wire [7:0] xgmii_rxc; +wire [63:0] xgmii_rxd; + + +xge_mac dut(/*AUTOINST*/ + // Outputs + .pkt_rx_avail (pkt_rx_avail), + .pkt_rx_data (pkt_rx_data[63:0]), + .pkt_rx_eop (pkt_rx_eop[7:0]), + .pkt_rx_err (pkt_rx_err), + .pkt_rx_sop (pkt_rx_sop), + .pkt_rx_val (pkt_rx_val), + .pkt_tx_full (pkt_tx_full), + .wb_ack_o (wb_ack_o), + .wb_dat_o (wb_dat_o[31:0]), + .wb_int_o (wb_int_o), + .xgmii_txc (xgmii_txc[7:0]), + .xgmii_txd (xgmii_txd[63:0]), + // Inputs + .clk_156m25 (clk_156m25), + .clk_xgmii_rx (clk_xgmii_rx), + .clk_xgmii_tx (clk_xgmii_tx), + .pkt_rx_ren (pkt_rx_ren), + .pkt_tx_data (pkt_tx_data[63:0]), + .pkt_tx_eop (pkt_tx_eop[7:0]), + .pkt_tx_sop (pkt_tx_sop), + .pkt_tx_val (pkt_tx_val), + .reset_156m25_n (reset_156m25_n), + .reset_xgmii_rx_n (reset_xgmii_rx_n), + .reset_xgmii_tx_n (reset_xgmii_tx_n), + .wb_adr_i (wb_adr_i[7:0]), + .wb_clk_i (wb_clk_i), + .wb_cyc_i (wb_cyc_i), + .wb_dat_i (wb_dat_i[31:0]), + .wb_rst_i (wb_rst_i), + .wb_stb_i (wb_stb_i), + .wb_we_i (wb_we_i), + .xgmii_rxc (xgmii_rxc[7:0]), + .xgmii_rxd (xgmii_rxd[63:0])); + + +//--- +// Unused for this testbench + +assign wb_adr_i = 8'b0; +assign wb_clk_i = 1'b0; +assign wb_cyc_i = 1'b0; +assign wb_dat_i = 32'b0; +assign wb_rst_i = 1'b1; +assign wb_stb_i = 1'b0; +assign wb_we_i = 1'b0; + + +//--- +// XGMII Loopback +// This test is done with loopback on XGMII + +assign xgmii_rxc = xgmii_txc; +assign xgmii_rxd = xgmii_txd; + + +//--- +// Clock generation + +initial begin + clk_156m25 = 1'b0; + clk_xgmii_rx = 1'b0; + clk_xgmii_tx = 1'b0; + forever begin + WaitPS(3200); + clk_156m25 = ~clk_156m25; + clk_xgmii_rx = ~clk_xgmii_rx; + clk_xgmii_tx = ~clk_xgmii_tx; + end +end + + +//--- +// Reset Generation + +initial begin + reset_156m25_n = 1'b0; + reset_xgmii_rx_n = 1'b0; + reset_xgmii_tx_n = 1'b0; + WaitNS(20); + reset_156m25_n = 1'b1; + reset_xgmii_rx_n = 1'b1; + reset_xgmii_tx_n = 1'b1; +end + + +//--- +// Init signals + +initial begin + + for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin + tx_buffer[tx_length] = 0; + end + + pkt_rx_ren = 1'b0; + + pkt_tx_data = 64'b0; + pkt_tx_val = 1'b0; + pkt_tx_sop = 1'b0; + pkt_tx_eop = 8'b0; + +end + +task WaitNS; + input [31:0] delay; + begin + #(1000*delay); + end +endtask + +task WaitPS; + input [31:0] delay; + begin + #(delay); + end +endtask + + +//--- +// Task to send a single packet + +task TxPacket; + integer i; + begin + + $display("Transmit packet with length: %d", tx_length); + + @(posedge clk_156m25); + WaitNS(1); + pkt_tx_val = 1'b1; + + for (i = 0; i < tx_length; i = i + 8) begin + + pkt_tx_sop = 1'b0; + pkt_tx_eop = 8'b0; + + if (i == 0) pkt_tx_sop = 1'b1; + if (i + 8 >= tx_length) pkt_tx_eop[tx_length-i-1] = 1'b1; + + pkt_tx_data[`LANE0] = tx_buffer[i]; + pkt_tx_data[`LANE1] = tx_buffer[i+1]; + pkt_tx_data[`LANE2] = tx_buffer[i+2]; + pkt_tx_data[`LANE3] = tx_buffer[i+3]; + pkt_tx_data[`LANE4] = tx_buffer[i+4]; + pkt_tx_data[`LANE5] = tx_buffer[i+5]; + pkt_tx_data[`LANE6] = tx_buffer[i+6]; + pkt_tx_data[`LANE7] = tx_buffer[i+7]; + + @(posedge clk_156m25); + WaitNS(1); + + end + + pkt_tx_val = 1'b0; + pkt_tx_eop = 8'b0; + + end + +endtask + + +//--- +// Task to read a single packet from command file and transmit + +task CmdTxPacket; + input [31:0] file; + integer count; + integer data; + integer i; + begin + + count = $fscanf(file, "%2d", tx_length); + + if (count == 1) begin + + for (i = 0; i < tx_length; i = i + 1) begin + + count = $fscanf(file, "%2X", data); + if (count) begin + tx_buffer[i] = data; + end + + end + + TxPacket(); + + end + end + +endtask + + +//--- +// Task to read commands from file and stop when complete + +task ProcessCmdFile; + integer file_cmd; + integer count; + reg [8*8-1:0] str; + begin + + file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r"); + if (!file_cmd) $stop; + + while (!$feof(file_cmd)) begin + + count = $fscanf(file_cmd, "%s", str); + if (count != 1) $stop; + + $display("CMD %s", str); + + case (str) + + "SEND_PKT": + begin + CmdTxPacket(file_cmd); + end + + endcase + + end + + $fclose(file_cmd); + + WaitNS(2000); + $stop; + + end +endtask + +initial begin + WaitNS(2000); + ProcessCmdFile(); +end + + +//--- +// Task to read a single packet from receive interface and display + +task RxPacket; + reg done; + begin + + done = 0; + + pkt_rx_ren <= 1'b1; + @(posedge clk_156m25); + + while (!done) begin + + if (pkt_rx_val) begin + + if (pkt_rx_sop) begin + $display("\n\n------------------------"); + end + + $display("%x", pkt_rx_data); + + if (pkt_rx_eop) begin + done <= 1; + pkt_rx_ren <= 1'b0; + end + + if (pkt_rx_eop) begin + $display("------------------------\n\n"); + end + + end + + @(posedge clk_156m25); + + end + + end +endtask + +initial begin + + forever begin + + if (pkt_rx_avail) begin + RxPacket(); + end + + @(posedge clk_156m25); + + end + +end + +endmodule +
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J ~ؖeSEiGIVDq:!m=wfeH +v[OQxRdqXm()àx_fNpiZ D1O(~R< +ѣl>OI>˃ءp܀QaE9V 5=b H 4يF_^ԕM⬾䲮6;s%d* DKWQw^^qLFм9>1cדa PKm PK<8^2 ''mimetypePK<8MConfigurations2/statusbar/PK<8'Configurations2/accelerator/current.xmlPK<8Configurations2/floater/PK<8Configurations2/popupmenu/PK<8JConfigurations2/progressbar/PK<8Configurations2/menubar/PK<8Configurations2/toolbar/PK<8Configurations2/images/Bitmaps/PK<8&--Pictures/2000000F000017E000000CD1E2168C13.wmfPK<8V$-lPictures/2000000700000408000004578E0D74AD.wmfPK<8'zz- Pictures/100000000000036D000000CD833096E0.pngPK<8kBL +L +-Pictures/10000000000002E80000007CD11577C4.pngPK<8J,33-y)Pictures/1000000000000413000000B717CE026C.pngPK<8dw-EPictures/10000000000003A300000099ABB65687.pngPK<8iR +R +-[Pictures/10000000000002F8000000703BB66046.pngPK<8ߦ tilayout-cachePK<8) +4 +jObjectReplacements/Object 1PK<8S:(MG wcontent.xmlPK<8歒 +"styles.xmlPK<8͈Object 1PK<8}Dmeta.xmlPK<8u V Thumbnails/thumbnail.pngPK<8"m&#]! settings.xmlPK<8m META-INF/manifest.xmlPK$W \ No newline at end of file Index: tags/initial/sim/systemc/compile.sh =================================================================== --- tags/initial/sim/systemc/compile.sh (nonexistent) +++ tags/initial/sim/systemc/compile.sh (revision 3) @@ -0,0 +1,40 @@ + +clear + +verilator --trace-dups -f verilator.cmd + +cd obj_dir + +#$SYSTEMPERL/sp_preproc --preproc *.sp + +make -f Vxge_mac.mk Vxge_mac__ALL.a + +make -f ../sc.mk crc.o + +make -f ../sc.mk sc_packet.o + +make -f ../sc.mk sc_pkt_generator.o + +make -f ../sc.mk sc_scoreboard.o + +make -f ../sc.mk sc_xgmii_if.o + +make -f ../sc.mk sc_pkt_if.o + +make -f ../sc.mk sc_cpu_if.o + +make -f ../sc.mk sc_testbench.o + +make -f ../sc.mk sc_testcases.o + +make -f ../sc.mk sc_main.o + +make -f ../sc.mk verilated.o + +make -f ../sc.mk SpTraceVcd.o + +make -f ../sc.mk SpTraceVcdC.o + +g++ -L$SYSTEMC/lib-linux sc_main.o sc_testcases.o sc_testbench.o sc_pkt_if.o sc_xgmii_if.o sc_cpu_if.o sc_pkt_generator.o sc_scoreboard.o sc_packet.o crc.o Vxge_mac__ALLcls.o Vxge_mac__ALLsup.o verilated.o SpTraceVcdC.o SpTraceVcd.o -o Vxge_mac -lsystemc + +cd ..
tags/initial/sim/systemc/compile.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/sim/systemc/verilator.cmd =================================================================== --- tags/initial/sim/systemc/verilator.cmd (nonexistent) +++ tags/initial/sim/systemc/verilator.cmd (revision 3) @@ -0,0 +1,11 @@ + +--sc +--trace +../../rtl/verilog/xge_mac.v ++incdir+../../rtl/include ++incdir+../../rtl/verilog ++incdir+../../rtl/megafunctions_altera + ++define+SIM_NO_PCS + +
tags/initial/sim/systemc/verilator.cmd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/sim/systemc/sc.mk =================================================================== --- tags/initial/sim/systemc/sc.mk (nonexistent) +++ tags/initial/sim/systemc/sc.mk (revision 3) @@ -0,0 +1,47 @@ +# Verilated -*- Makefile -*- + +default: Vxge_mac__ALL.a + +# Constants... +PERL = perl +#VERILATOR_ROOT = /opt/verilator-3.656 +#SYSTEMPERL = /opt/SystemPerl-1.282 + +# Switches... +VM_SP = 0 +VM_SC = 1 +VM_SP_OR_SC = 1 +VM_PCLI = 0 +VM_SC_TARGET_ARCH = linux + +# Vars... +VM_PREFIX = Vxge_mac +VM_MODPREFIX = Vxge_mac +VM_USER_CLASSES = \ + +VM_USER_DIR = \ + + +CPPFLAGS += -I.. +CPPFLAGS += -I. +CPPFLAGS += -I$(SYSTEMC)/include +#CPPFLAGS += -I$(VERILATOR_ROOT)/include +CPPFLAGS += -I$(SYSTEMPERL)/src +# -DSYSTEMPERL + + +include Vxge_mac_classes.mk +include $(VERILATOR_ROOT)/include/verilated.mk + +# Local rules... + +#SOURCES=../../tb_sc/sc_packet.cpp +#OBJECTS=$(SOURCES:.cpp=.o) + +#all: $(OBJECTS) + +%.o: ../../tbench/systemc/%.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $< + + +# Verilated -*- Makefile -*-
tags/initial/sim/systemc/sc.mk Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/sim/systemc/run.sh =================================================================== --- tags/initial/sim/systemc/run.sh (nonexistent) +++ tags/initial/sim/systemc/run.sh (revision 3) @@ -0,0 +1,2 @@ + +obj_dir/Vxge_mac
tags/initial/sim/systemc/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/sim/verilog/sim.do =================================================================== --- tags/initial/sim/verilog/sim.do (nonexistent) +++ tags/initial/sim/verilog/sim.do (revision 3) @@ -0,0 +1,85 @@ + + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/fault_sm.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/generic_fifo.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/meta_sync.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/meta_sync_single.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/rx_hold_fifo.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/rx_data_fifo.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/rx_dequeue.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/rx_enqueue.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/sync_clk_core.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/sync_clk_wb.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/sync_clk_xgmii_tx.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/tx_hold_fifo.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/tx_data_fifo.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/tx_dequeue.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/tx_enqueue.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/wishbone_if.v + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/rtl/verilog/xge_mac.v + + + +vlog -timescale 1ps/1ps +incdir+y:/xge_mac/rtl/include y:/xge_mac/tbench/verilog/tb_xge_mac.v + + + +vsim -voptargs="+acc" work.tb + +add wave sim:/tb/* + +add wave -divider + +add wave sim:/tb/dut/* + +add wave -divider + +add wave sim:/tb/dut/rx_eq0/* + +add wave -divider + +add wave sim:/tb/dut/rx_data_fifo0/* + +add wave -divider + +add wave sim:/tb/dut/rx_dq0/* + +add wave -divider +add wave -divider +add wave -divider + +add wave sim:/tb/dut/tx_eq0/* + +add wave -divider + +add wave sim:/tb/dut/tx_data_fifo0/* + +add wave -divider + +add wave sim:/tb/dut/tx_dq0/* + +add wave -divider + +add wave sim:/tb/dut/fault_sm0/* + +add wave -divider + +add wave sim:/tb/dut/wishbone_if0/* + +#run 1000ns
tags/initial/sim/verilog/sim.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/initial/README.TXT ===================================================================

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