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URL https://opencores.org/ocsvn/mdct/mdct/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 20 to Rev 21
    ↔ Reverse comparison
  •

Rev 20 → Rev 21

/trunk/source/ROME.VHD
25,8 → 25,8
-- 3:0 = select precomputed MAC ( 1 out of 16)
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
 
entity ROME is
41,96 → 41,93
 
architecture RTL of ROME is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( AP ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP+AP+AP ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
std_logic_vector( BM ),
std_logic_vector( CM ),
std_logic_vector( CM+BM ),
std_logic_vector( CP ),
std_logic_vector( CP+BM ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
std_logic_vector( BM ),
std_logic_vector( BP ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
std_logic_vector( BP+CM ),
std_logic_vector( CM ),
std_logic_vector( BP+CP ),
std_logic_vector( CP ),
std_logic_vector( BP ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
std_logic_vector( AP ),
std_logic_vector( AM ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
std_logic_vector( AM ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
std_logic_vector( AM+AM ),
std_logic_vector( AM ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
std_logic_vector( AP ),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
std_logic_vector( AP ),
std_logic_vector( AM ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
std_logic_vector( CM ),
std_logic_vector( BP ),
std_logic_vector( BP+CM ),
std_logic_vector( BM ),
std_logic_vector( BM+CM ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
std_logic_vector( CM ),
std_logic_vector( CP ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
std_logic_vector( CP+BP ),
std_logic_vector( BP ),
std_logic_vector( CP+BM ),
std_logic_vector( BM ),
std_logic_vector( CP ),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
 
datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
 
 
/trunk/source/ROMO.VHD
13,6 → 13,8
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
26,7 → 28,8
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
-- use ieee.STD_LOGIC_signed.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
 
entity ROMO is
45,83 → 48,80
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( GP ),
std_logic_vector( FP ),
std_logic_vector( FP+GP ),
std_logic_vector( EP ),
std_logic_vector( EP+GP ),
std_logic_vector( EP+FP ),
std_logic_vector( EP+FP+GP ),
std_logic_vector( DP ),
std_logic_vector( DP+GP ),
std_logic_vector( DP+FP ),
std_logic_vector( DP+FP+GP ),
std_logic_vector( DP+EP ),
std_logic_vector( DP+EP+GP ),
std_logic_vector( DP+EP+FP ),
std_logic_vector( DP+EP+FP+GP ),
conv_std_logic_vector( GP,ROMDATA_W ),
conv_std_logic_vector( FP,ROMDATA_W ),
conv_std_logic_vector( FP+GP,ROMDATA_W ),
conv_std_logic_vector( EP,ROMDATA_W ),
conv_std_logic_vector( EP+GP,ROMDATA_W ),
conv_std_logic_vector( EP+FP,ROMDATA_W ),
conv_std_logic_vector( EP+FP+GP,ROMDATA_W ),
conv_std_logic_vector( DP,ROMDATA_W ),
conv_std_logic_vector( DP+GP,ROMDATA_W ),
conv_std_logic_vector( DP+FP,ROMDATA_W ),
conv_std_logic_vector( DP+FP+GP,ROMDATA_W ),
conv_std_logic_vector( DP+EP,ROMDATA_W ),
conv_std_logic_vector( DP+EP+GP,ROMDATA_W ),
conv_std_logic_vector( DP+EP+FP,ROMDATA_W ),
conv_std_logic_vector( DP+EP+FP+GP,ROMDATA_W ),
(others => '0'),
std_logic_vector( FM ),
std_logic_vector( DM ),
std_logic_vector( DM+FM ),
std_logic_vector( GM ),
std_logic_vector( GM+FM ),
std_logic_vector( GM+DM ),
std_logic_vector( GM+DM+FM ),
std_logic_vector( EP ),
std_logic_vector( EP+FM ),
std_logic_vector( EP+DM ),
std_logic_vector( EP+DM+FM ),
std_logic_vector( EP+GM ),
std_logic_vector( EP+GM+FM ),
std_logic_vector( EP+GM+DM ),
std_logic_vector( EP+GM+DM+FM ),
conv_std_logic_vector( FM,ROMDATA_W ),
conv_std_logic_vector( DM,ROMDATA_W ),
conv_std_logic_vector( DM+FM,ROMDATA_W ),
conv_std_logic_vector( GM,ROMDATA_W ),
conv_std_logic_vector( GM+FM,ROMDATA_W ),
conv_std_logic_vector( GM+DM,ROMDATA_W ),
conv_std_logic_vector( GM+DM+FM,ROMDATA_W ),
conv_std_logic_vector( EP,ROMDATA_W ),
conv_std_logic_vector( EP+FM,ROMDATA_W ),
conv_std_logic_vector( EP+DM,ROMDATA_W ),
conv_std_logic_vector( EP+DM+FM,ROMDATA_W ),
conv_std_logic_vector( EP+GM,ROMDATA_W ),
conv_std_logic_vector( EP+GM+FM,ROMDATA_W ),
conv_std_logic_vector( EP+GM+DM,ROMDATA_W ),
conv_std_logic_vector( EP+GM+DM+FM,ROMDATA_W ),
(others => '0'),
std_logic_vector( EP ),
std_logic_vector( GP ),
std_logic_vector( EP+GP ),
std_logic_vector( DM ),
std_logic_vector( DM+EP ),
std_logic_vector( DM+GP ),
std_logic_vector( DM+GP+EP ),
std_logic_vector( FP ),
std_logic_vector( FP+EP ),
std_logic_vector( FP+GP ),
std_logic_vector( FP+GP+EP ),
std_logic_vector( FP+DM ),
std_logic_vector( FP+DM+EP ),
std_logic_vector( FP+DM+GP ),
std_logic_vector( FP+DM+GP+EP ),
conv_std_logic_vector( EP,ROMDATA_W ),
conv_std_logic_vector( GP,ROMDATA_W ),
conv_std_logic_vector( EP+GP,ROMDATA_W ),
conv_std_logic_vector( DM,ROMDATA_W ),
conv_std_logic_vector( DM+EP,ROMDATA_W ),
conv_std_logic_vector( DM+GP,ROMDATA_W ),
conv_std_logic_vector( DM+GP+EP,ROMDATA_W ),
conv_std_logic_vector( FP,ROMDATA_W ),
conv_std_logic_vector( FP+EP,ROMDATA_W ),
conv_std_logic_vector( FP+GP,ROMDATA_W ),
conv_std_logic_vector( FP+GP+EP,ROMDATA_W ),
conv_std_logic_vector( FP+DM,ROMDATA_W ),
conv_std_logic_vector( FP+DM+EP,ROMDATA_W ),
conv_std_logic_vector( FP+DM+GP,ROMDATA_W ),
conv_std_logic_vector( FP+DM+GP+EP,ROMDATA_W ),
(others => '0'),
std_logic_vector( DM ),
std_logic_vector( EP ),
std_logic_vector( EP+DM ),
std_logic_vector( FM ),
std_logic_vector( FM+DM ),
std_logic_vector( FM+EP ),
std_logic_vector( FM+EP+DM ),
std_logic_vector( GP ),
std_logic_vector( GP+DM ),
std_logic_vector( GP+EP ),
std_logic_vector( GP+EP+DM ),
std_logic_vector( GP+FM ),
std_logic_vector( GP+FM+DM ),
std_logic_vector( GP+FM+EP ),
std_logic_vector( GP+FM+EP+DM )
conv_std_logic_vector( DM,ROMDATA_W ),
conv_std_logic_vector( EP,ROMDATA_W ),
conv_std_logic_vector( EP+DM,ROMDATA_W ),
conv_std_logic_vector( FM,ROMDATA_W ),
conv_std_logic_vector( FM+DM,ROMDATA_W ),
conv_std_logic_vector( FM+EP,ROMDATA_W ),
conv_std_logic_vector( FM+EP+DM,ROMDATA_W ),
conv_std_logic_vector( GP,ROMDATA_W ),
conv_std_logic_vector( GP+DM,ROMDATA_W ),
conv_std_logic_vector( GP+EP,ROMDATA_W ),
conv_std_logic_vector( GP+EP+DM,ROMDATA_W ),
conv_std_logic_vector( GP+FM,ROMDATA_W ),
conv_std_logic_vector( GP+FM+DM,ROMDATA_W ),
conv_std_logic_vector( GP+FM+EP,ROMDATA_W ),
conv_std_logic_vector( GP+FM+EP+DM,ROMDATA_W )
);
 
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
datao <= rom( CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;

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