URL
https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk
Subversion Repositories sdram_controller
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/sdram_controller/trunk/Xilinx_ISE_11.1_project.tar.gz
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Index: sdram_controller/trunk/scratch.vhd
===================================================================
--- sdram_controller/trunk/scratch.vhd (revision 20)
+++ sdram_controller/trunk/scratch.vhd (revision 21)
@@ -123,7 +123,6 @@
SDRAM: entity work.sdram_controller
port map(
clk100mhz => clk100mhz,
- en => '1',
reset => rst,
op => op,
addr => addr,
Index: sdram_controller/trunk/boards/StarterKit500E/SDRAM_TB.xise
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--- sdram_controller/trunk/boards/StarterKit500E/SDRAM_TB.xise (nonexistent)
+++ sdram_controller/trunk/boards/StarterKit500E/SDRAM_TB.xise (revision 21)
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Index: sdram_controller/trunk/boards/StarterKit500E/scratch.ucf
===================================================================
--- sdram_controller/trunk/boards/StarterKit500E/scratch.ucf (nonexistent)
+++ sdram_controller/trunk/boards/StarterKit500E/scratch.ucf (revision 21)
@@ -0,0 +1,84 @@
+# clocking stuff
+NET "clk" IOSTANDARD = LVCMOS33 | LOC = "C9";
+
+NET "rst" IOSTANDARD = LVTTL | LOC = "H13" | PULLDOWN;
+NET "clke" IOSTANDARD = LVTTL | LOC = "L13" | PULLUP;
+
+# led pinouts
+NET "led<7>" IOSTANDARD = LVTTL | LOC = "F9" | SLEW = SLOW | DRIVE = 8;
+NET "led<6>" IOSTANDARD = LVTTL | LOC = "E9" | SLEW = SLOW | DRIVE = 8;
+NET "led<5>" IOSTANDARD = LVTTL | LOC = "D11" | SLEW = SLOW | DRIVE = 8;
+NET "led<4>" IOSTANDARD = LVTTL | LOC = "C11" | SLEW = SLOW | DRIVE = 8;
+NET "led<3>" IOSTANDARD = LVTTL | LOC = "F11" | SLEW = SLOW | DRIVE = 8;
+NET "led<2>" IOSTANDARD = LVTTL | LOC = "E11" | SLEW = SLOW | DRIVE = 8;
+NET "led<1>" IOSTANDARD = LVTTL | LOC = "E12" | SLEW = SLOW | DRIVE = 8;
+NET "led<0>" IOSTANDARD = LVTTL | LOC = "F12" | SLEW = SLOW | DRIVE = 8;
+
+
+#
+# sdram pinouts
+#
+# address lines
+NET "dram_addr<12>" LOC = "P2" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<11>" LOC = "N5" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<10>" LOC = "T2" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<9>" LOC = "N4" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<8>" LOC = "H2" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<7>" LOC = "H1" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<6>" LOC = "H3" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<5>" LOC = "H4" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<4>" LOC = "F4" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<3>" LOC = "P1" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<2>" LOC = "R2" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<1>" LOC = "R3" |IOSTANDARD = SSTL2_I;
+NET "dram_addr<0>" LOC = "T1" |IOSTANDARD = SSTL2_I;
+
+# data lines
+NET "dram_dq<15>" LOC = "H5" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<14>" LOC = "H6" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<13>" LOC = "G5" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<12>" LOC = "G6" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<11>" LOC = "F2" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<10>" LOC = "F1" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<9>" LOC = "E1" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<8>" LOC = "E2" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<7>" LOC = "M6" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<6>" LOC = "M5" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<5>" LOC = "M4" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<4>" LOC = "M3" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<3>" LOC = "L4" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<2>" LOC = "L3" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<1>" LOC = "L1" |IOSTANDARD = SSTL2_I;
+NET "dram_dq<0>" LOC = "L2" |IOSTANDARD = SSTL2_I;
+
+# bank lines
+NET "dram_bank<0>" LOC = "K5" |IOSTANDARD = SSTL2_I;
+NET "dram_bank<1>" LOC = "K6" |IOSTANDARD = SSTL2_I;
+
+# command lines
+NET "dram_cs" LOC = "K4" |IOSTANDARD = SSTL2_I; #cs_n
+NET "dram_cmd<0>" LOC = "C1" |IOSTANDARD = SSTL2_I; #ras_n
+NET "dram_cmd<1>" LOC = "C2" |IOSTANDARD = SSTL2_I; #cas_n
+NET "dram_cmd<2>" LOC = "D1" |IOSTANDARD = SSTL2_I; #we_n
+# clocks
+NET "dram_clkn" LOC = "J4" |IOSTANDARD = SSTL2_I;
+NET "dram_clkp" LOC = "J5" |IOSTANDARD = SSTL2_I;
+NET "dram_clke" LOC = "K3" |IOSTANDARD = SSTL2_I;
+
+# U/D data masks and data strobes
+NET "dram_dm<1>" LOC = "J1" |IOSTANDARD = SSTL2_I;
+NET "dram_dm<0>" LOC = "J2" |IOSTANDARD = SSTL2_I;
+NET "dram_dqs<1>" LOC = "G3" |IOSTANDARD = SSTL2_I;
+NET "dram_dqs<0>" LOC = "L6" |IOSTANDARD = SSTL2_I;
+
+# prohibited pins related to SDRAM
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+#
+#end sdram pinouts
+#
+