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/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/Address_Path.vhd
0,0 → 1,136
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Address_Path - Structural
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Structural description for Address path for Memory Access Controller.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Address_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
read_enable_in : in std_logic_vector(num_of_ports downto 0);
write_enable_in : in std_logic_vector(num_of_ports downto 0);
Memory_Access_in : in Memory_Access_Port_in;
burst_addresses : in v_adr_i;
read_address : in v_adr_i;
acknowledge_read_data_in : in STD_LOGIC;
read_index : out integer range 0 to num_of_ports;
read_err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
write_err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
Decoded_write_address_out : out std_logic_vector(physical_address_width -1 downto 0);
Write_enable_out : out STD_LOGIC_VECTOR (num_of_ports downto 0);
Decoded_Read_address_out : out std_logic_vector(physical_address_width -1 downto 0);
read_enable_out : out STD_LOGIC;
Read_Acknowledge_out : out STD_LOGIC_VECTOR(num_of_ports downto 0)
);
end Address_Path;
 
architecture Behavioral of Address_Path is
 
component read_address_decoder is
Port ( reset : in std_logic;
clock : in STD_LOGIC;
read_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
adr_i : in v_adr_i;
id_i : in ID_type;
read_index : out integer range 0 to num_of_ports;
decoded_read_address_out : out STD_LOGIC_VECTOR(physical_address_width -1 downto 0);
err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
read_enable_out : out STD_LOGIC);
end component;
 
component write_address_decoder is
Port ( clock : std_logic;
ports_in : memory_access_port_in;
burst_addresses : v_adr_i;
write_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
decoded_write_address : out STD_LOGIC_VECTOR (physical_address_width -1 downto 0);
write_enable_out : out STD_LOGIC_VECTOR (num_of_ports downto 0);
write_error_out : out STD_LOGIC_VECTOR (num_of_ports downto 0)
);
end component;
 
component Acknowledge_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
read_index : in integer range 0 to num_of_ports;
read_index_out : out integer range 0 to num_of_ports;
read_enable : in STD_LOGIC;
acknowledge_read_data_in : in STD_LOGIC;
read_acknowledge : out STD_LOGIC_VECTOR (num_of_ports downto 0));
end component;
 
signal read_index_s,read_index_out_s : integer range 0 to num_of_ports;
signal read_enable_out_s : std_logic;
signal write_enable_out_s : std_logic_vector(num_of_ports downto 0);
--signal burst_addresses_s : v_adr_i;
 
begin
A0 : read_address_decoder
Port Map( reset => reset,
clock => clock,
read_enable_in => read_enable_in,
adr_i => read_address,
id_i => Memory_Access_in.ID_i,
read_index => read_index_s,
decoded_read_address_out => decoded_read_address_out,
err_o => read_err_o,
read_enable_out => read_enable_out_s
);
 
A1 : write_address_decoder
Port Map( clock => clock,
ports_in => Memory_Access_in,
burst_addresses => burst_addresses,
write_enable_in => write_enable_in,
decoded_write_address => decoded_write_address_out,
write_enable_out => write_enable_out_s,
write_error_out => write_err_o
);
 
A2 : Acknowledge_Path
Port Map ( clock => clock,
reset => reset,
read_index => read_index_s,
read_index_out => read_index_out_s,
read_enable => read_enable_out_s,
acknowledge_read_data_in => acknowledge_read_data_in,
read_acknowledge => Read_Acknowledge_out);
read_index <= read_index_out_s;
read_enable_out <= read_enable_out_s;
write_enable_out <= write_enable_out_s;
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/Burst_data_Buffer.vhd
0,0 → 1,595
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Burst_data_Buffer - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for burst data buffer.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
entity Burst_data_Buffer is
Port (clock : in STD_LOGIC;
device_clock : in STD_LOGIC;
reset : in std_logic;
we_i : in std_logic;
data_in : in std_logic_vector(data_width -1 downto 0);
address_in : in std_logic_vector(virtual_address_width -1 downto 0);
data_out : out std_logic_vector((data_width + virtual_address_width)-1 downto 0);
read_address : out std_logic_vector(virtual_address_width -1 downto 0);
pop : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
lock_i : in std_logic;
read_err_i : in std_logic;
write_err_i : in std_logic;
err_o : out std_logic;
read_buffer_full : in std_logic;
read_serviced : in std_logic;
read_acknowledge : in std_logic;
reset_pop_count_in : in std_logic;
buffer_full : out std_logic;
buffer_empty : out std_logic;
write_enable_out : out std_logic;
read_enable_out : out std_logic;
acknowledge : out std_logic;
reset_buffer : out std_logic;
acknowledge_read_data : out std_logic
);
end Burst_data_Buffer;
 
architecture Behavioral of Burst_data_Buffer is
 
--type Burst_Data_Array is
-- array (0 to burst_length -1) of std_logic_vector((data_width + virtual_address_width) -1 downto 0);
signal full_s,empty_s,push_s,clear_push_count: std_logic;
signal address_in_s, read_address_s : std_logic_vector(virtual_address_width -1 downto 0);
signal buffer_input_data_s : std_logic_vector((data_width + virtual_address_width) -1 downto 0);
type StateType is (idle,pull_data,check_lock,check_buff_status,send_data,check_full,acknowledge_data,
send_data_0,check_buff_status_0,send_acknowledge,send_acknowledge_wait,single_write,write_error_0);
signal CurrentState,NextState: StateType;
type StateType_read is (reset_idle,assert_read_enable,check_lock_and_bits,check_lock_and_bits_1,clear_buffer,
wait_buffer_full,acknowledge_single_read,acknowledge_block_read,error_state,acknowledge_single_read_0);
signal CurrentState_read,NextState_read: StateType_read;
signal var_a, var_b : integer range 0 to burst_length -1 := 0;
signal Data_array_v : burst_data_array;
signal push_count,pop_count : std_logic_vector(2 downto 0) := "000";
 
begin
buffer_input_data : process(clock, reset,cyc_i, stb_i,data_in,address_in,read_acknowledge,read_address_s)
variable buffer_input_data_v : std_logic_vector((data_width + virtual_address_width) -1 downto 0);
variable address_in_v : std_logic_vector(virtual_address_width -1 downto 0);
begin
if clock='1' and clock'event then
if(reset = '1' OR read_acknowledge = '1') then
address_in_v := "0000000000000000000000";
read_address_s <= (others => '0');
elsif(cyc_i = '1' AND stb_i = '1') then
if(we_i = '1') then
-- buffer_input_data_v := data_in & address_in;
buffer_input_data_s <= data_in & address_in;
address_in_v := address_in;
read_address_s <= read_address_s;
elsif(we_i = '0')then
buffer_input_data_s <= (others => '0');
address_in_v := address_in;
read_address_s <= address_in;
end if;
else
buffer_input_data_s <= buffer_input_data_s;
address_in_v := address_in_v;
read_address_s <= read_address_s;
end if;
 
end if;
--buffer_input_data_s <= buffer_input_data_v;
address_in_s <= address_in_v;
read_address <= read_address_s;
end process buffer_input_data;
 
 
process(clock,read_err_i,write_err_i)
begin
if clock='1' and clock'event then
for i in 0 to num_of_ports loop
if(read_err_i = '1') then
err_o <= '1';
elsif(write_err_i = '1') then
err_o <= '1';
else
err_o <= '0';
end if;
end loop;
end if;
end process;
 
 
read_communication: process(CurrentState_read, lock_i, cyc_i, stb_i, read_buffer_full,read_serviced,read_address_s,we_i,read_err_i)
begin
case (CurrentState_read) is
when reset_idle =>
if (we_i = '0' AND cyc_i = '1' AND stb_i = '1') then
NextState_read <= assert_read_enable;
else
NextState_read <= reset_idle;
end if;
reset_buffer <= '1';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when assert_read_enable =>
if (read_serviced = '1') then
NextState_read <= wait_buffer_full;
else
NextState_read <= assert_read_enable;
end if;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '1';
-- err_o <= '0';
-- read_address <= read_address_s;
 
 
when wait_buffer_full =>
if (read_buffer_full = '1') then
NextState_read <= check_lock_and_bits;
elsif(read_err_i = '1') then
NextState_read <= error_state;
else
NextState_read <= wait_buffer_full;
end if;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= read_address_s;
when check_lock_and_bits =>
if (lock_i = '0') then
NextState_read <= acknowledge_single_read;
elsif(read_address_s(1 downto 0) = "11") then
NextState_read <= acknowledge_single_read;
else
NextState_read <= acknowledge_block_read;
end if;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when acknowledge_single_read =>
NextState_read <= acknowledge_single_read_0;
reset_buffer <= '0';
acknowledge_read_data <= '1';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when acknowledge_single_read_0 =>
NextState_read <= reset_idle;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when acknowledge_block_read =>
NextState_read <= check_lock_and_bits_1;
reset_buffer <= '0';
acknowledge_read_data <= '1';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when check_lock_and_bits_1 =>
if (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '1') then
NextState_read <= check_lock_and_bits;
elsif (we_i = '0' AND cyc_i = '0' AND stb_i = '0' AND lock_i = '1') then
NextState_read <= check_lock_and_bits_1;
elsif (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '0') then
NextState_read <= clear_buffer;
else
NextState_read <= reset_idle;
end if;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when error_state =>
NextState_read <= reset_idle;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '1';
-- read_address <= (others => '0');
when clear_buffer =>
NextState_read <= assert_read_enable;
reset_buffer <= '1';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
when others =>
NextState_read <= reset_idle;
reset_buffer <= '0';
acknowledge_read_data <= '0';
read_enable_out <= '0';
-- err_o <= '0';
-- read_address <= (others => '0');
end case;
end process read_communication;
 
nextstatelogic_read: process
--(clock,reset)
begin
wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE
-- if(rising_edge(clock)) then
-- INITIALIZATION
if (Reset = '1') then
CurrentState_read <= reset_idle;
else
CurrentState_read <= NextState_read;
end if;
-- end if;
end process nextstatelogic_read;
 
buffer_communication: process(CurrentState, lock_i, cyc_i, stb_i, empty_s, we_i,full_s,write_err_i)
begin
case (CurrentState) is
when idle=>
if (we_i = '1' AND lock_i = '1' AND cyc_i = '1' AND stb_i = '1') then
NextState <= pull_data;
elsif (we_i = '1' AND cyc_i = '1' AND stb_i = '1') then
NextState <= single_write;
else
NextState <= idle;
end if;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when pull_data =>
NextState <= check_full;
push_s <= '1';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when check_full =>
if(full_s = '1') then
NextState <= send_data_0;
else
NextState <= acknowledge_data;
end if;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when acknowledge_data =>
NextState <= check_lock;
push_s <= '0';
acknowledge <= '1';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when check_lock =>
if (lock_i = '0') then
NextState <= send_data;
else
NextState <= idle;
end if;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when send_data =>
NextState <= check_buff_status;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '1';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when send_data_0 =>
NextState <= check_buff_status_0;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '1';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when check_buff_status =>
if (empty_s = '1') then
NextState <= idle;
else
NextState <= check_buff_status;
end if;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '1';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when check_buff_status_0 =>
if (empty_s = '1') then
NextState <= send_acknowledge;
elsif (write_err_i = '1') then
NextState <= write_error_0;
else
NextState <= check_buff_status_0;
end if;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '1';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when write_error_0 =>
NextState <= send_acknowledge_wait;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '1';
when send_acknowledge =>
NextState <= send_acknowledge_wait;
push_s <= '0';
acknowledge <= '1';
write_enable_out <= '0';
clear_push_count <= '1';
-- clear_pop_count <= '1';
 
when send_acknowledge_wait =>
NextState <= idle;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '1';
when single_write =>
NextState <= send_data_0;
push_s <= '1';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
when others =>
NextState <= idle;
push_s <= '0';
acknowledge <= '0';
write_enable_out <= '0';
clear_push_count <= '0';
-- clear_pop_count <= '0';
end case;
end process buffer_communication;
 
nextstatelogic: process
--(clock,reset)
begin
wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE
-- if(rising_edge(clock)) then
-- INITIALIZATION
if (Reset = '1') then
CurrentState <= idle;
else
CurrentState <= NextState;
end if;
-- end if;
end process nextstatelogic;
pop_buffer_burst_data : process(clock,reset,pop,push_s,address_in,pop_count,data_array_v,reset_pop_count_in)
--variable Data_array_v : burst_data_array;
--variable var_a, var_b : integer range 0 to burst_length -1;
--variable count_v : std_logic_vector(2 downto 0);
begin
if (clock='1' and clock'event) then
 
if reset='1' then
-- var_a <= 0;
-- var_b <= 0;
-- count_v <= "000";
-- for i in 0 to (burst_length -1) loop
-- data_array_v(i) <= (others => '0');
-- end loop;
else
-- if(push_s = '1') then -- AND full_s = '0') then
-- if(count_v < "100") then
-- Data_array_v(var_a) <= buffer_input_data_s;
-- count_v <= count_v +1;
-- if(var_a = burst_length -1) then
-- var_a <= 0;
-- else
-- var_a <= var_a +1;
-- end if;
-- end if;
-- els
if(reset_pop_count_in = '1') then
pop_count <= "000";
elsif(pop = '1' AND push_s = '0') then -- AND empty_s = '0') then
if(empty_s = '0') then
-- if(pop_count = "011") then
-- pop_count <= "000";
-- else
pop_count <= pop_count +1;
-- end if;
if(var_b = burst_length -1) then
var_b <= 0;
else
var_b <= var_b +1;
end if;
end if;
else
pop_count <= pop_count;
-- var_a <= var_a;
var_b <= var_b;
end if;
end if;
end if;
 
data_out <= Data_array_v(var_b);
 
end process pop_buffer_burst_data;
 
 
 
 
 
 
push_buffer_burst_data : process(device_clock,reset,push_s,address_in,push_count,buffer_input_data_s,clear_push_count)
--variable Data_array_v : burst_data_array;
--variable var_a, var_b : integer range 0 to burst_length -1;
--variable count_v : std_logic_vector(2 downto 0);
begin
if (device_clock='1' and device_clock'event) then
 
if reset='1' then
-- var_a <= 0;
-- var_b <= 0;
-- count_v <= "000";
-- for i in 0 to (burst_length -1) loop
-- data_array_v(i) <= (others => '0');
-- end loop;
else
-- if(pop = '1') then
-- if(push_count = "100") then
-- push_count <= "000";
-- els
if(clear_push_count = '1') then
push_count <= "000";
elsif(push_s = '1' and pop = '0') then -- AND full_s = '0') then
-- if(count_v < "100") then
if(push_count = "100") then
push_count <= "000";
else
push_count <= push_count +1;
end if;
Data_array_v(var_a) <= buffer_input_data_s;
if(var_a = burst_length -1) then
var_a <= 0;
else
var_a <= var_a +1;
-- end if;
end if;
-- elsif(pop = '1') then -- AND empty_s = '0') then
-- if(empty_s = '0') then
-- count_v <= count_v -1;
-- if(var_b = burst_length -1) then
-- var_b <= 0;
-- else
-- var_b <= var_b +1;
-- end if;
-- end if;
else
push_count <= push_count;
var_a <= var_a;
-- var_b <= var_b;
end if;
end if;
end if;
 
--count_v_s <= count_v;
--data_out <= Data_array_v(var_b);
--
end process push_buffer_burst_data;
 
 
 
 
 
FULL_s <= '1' when ((conv_integer(push_count) = 1) OR (Data_array_v(var_b)(1 downto 0) = "11")
OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';
EMPTY_s <= '1' when (pop_count = "100" OR pop_count = push_count) else '0';
 
--FULL_s <= '1' when ((conv_integer(push_count) = stack_depth) OR (Data_array_v(var_b)(1 downto 0) = "11")
-- OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';
--EMPTY_s <= '1' when (pop_count = "100" OR pop_count = push_count) else '0';
 
 
buffer_full <= full_s;
buffer_empty <= empty_s;
 
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/Data_Fetch.vhd
0,0 → 1,212
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Burst_write_data_fetcher - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for writing data to memory.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity burst_data_fetch is
Port ( reset : in std_logic;
clock : in STD_LOGIC;
buffer_empty : in STD_LOGIC_VECTOR (num_of_ports downto 0);
write_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
pop_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
burst_write_enable : out STD_LOGIC_VECTOR (num_of_ports downto 0);
reset_pop_count : out STD_LOGIC_VECTOR (num_of_ports downto 0)
);
end burst_data_fetch;
 
architecture Behavioral of burst_data_fetch is
type StateType is (reset_state,idle_0,enable_burst_write,pop_0,wait_0,clear_pop_count);
signal CurrentState,NextState: StateType;
signal index_i : integer range 0 to num_of_ports;
signal pop_s : STD_LOGIC_VECTOR (num_of_ports downto 0);
signal count : integer range 0 to burst_length;
signal inc_count,reset_count,stop : std_logic;
begin
 
store_index_value : process(clock,write_enable_in) --(clock,store_index) --reset_index,store_index)
--variable index_i_v_v : integer range 0 to num_of_ports;
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
if(reset = '1') then
index_i <= 0;
pop_s <= "000000000";
elsif(write_enable_in = "000000001") then
index_i <= 0;
pop_s <= "000000001";
elsif(write_enable_in = "000000010") then
index_i <= 1;
pop_s <= "000000010";
elsif(write_enable_in = "000000100") then
index_i <= 2;
pop_s <= "000000100";
elsif(write_enable_in = "000001000") then
index_i <= 3;
pop_s <= "000001000";
elsif(write_enable_in = "000010000") then
index_i <= 4;
pop_s <= "000010000";
elsif(write_enable_in = "000100000") then
index_i <= 5;
pop_s <= "000100000";
elsif(write_enable_in = "001000000") then
index_i <= 6;
pop_s <= "001000000";
elsif(write_enable_in = "010000000") then
index_i <= 7;
pop_s <= "010000000";
elsif(write_enable_in = "100000000") then
index_i <= 8;
pop_s <= "100000000";
else
index_i <= index_i;
pop_s <= pop_s;
end if;
end if;
end process;
 
counter : process(clock,inc_count) --(clock,store_index) --reset_index,store_index)
--variable index_i_v_v : integer range 0 to num_of_ports;
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
if(reset_count = '1') then
count <= 0;
elsif(inc_count = '0') then
count <= count;
elsif(inc_count = '1') then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
 
burst_access_process: process(CurrentState,write_enable_in,stop,pop_s)--,Memory_access_in)
variable index_i : integer;
begin
case (CurrentState) is
when reset_state =>
NextState <= idle_0;
reset_count <= '1';
pop_o <= "000000000";
inc_count <= '0';
burst_write_enable <= "000000000";
reset_pop_count <= (others => '0');
when idle_0 =>
if(write_enable_in = "000000000") then
NextState <= idle_0;
else
NextState <= enable_burst_write;
end if;
reset_count <= '0';
pop_o <= "000000000";
inc_count <= '0';
burst_write_enable <= "000000000";
reset_pop_count <= (others => '0');
when enable_burst_write =>
NextState <= wait_0;
reset_count <= '0';
pop_o <= pop_s;
inc_count <= '1';
burst_write_enable <= pop_s;
reset_pop_count <= (others => '0');
-- when pop_0 =>
-- NextState <= wait_0;
--
-- reset_count <= '0';
-- pop_o <= pop_s;
-- inc_count <= '1';
-- burst_write_enable <= "000000000";
when wait_0 =>
if(stop = '1') then
NextState <= clear_pop_count;
else
NextState <= enable_burst_write;
end if;
reset_count <= '0';
pop_o <= "000000000";
inc_count <= '0';
burst_write_enable <= "000000000";
reset_pop_count <= (others => '0');
when clear_pop_count =>
NextState <= reset_state;
 
reset_count <= '0';
pop_o <= "000000000";
inc_count <= '0';
burst_write_enable <= "000000000";
reset_pop_count <= pop_s;
when others =>
NextState <= reset_state;
reset_count <= '0';
pop_o <= "000000000";
inc_count <= '0';
burst_write_enable <= "000000000";
reset_pop_count <= (others => '0');
end case;
end process burst_access_process;
nextstatelogic: process
begin
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
if (Reset = '1') then
CurrentState <= reset_state;
else
CurrentState <= NextState;
end if;
end process nextstatelogic;
 
stop <= '1'when buffer_empty(index_i) = '1' else '0';
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/burst_read_data_fetcher.vhd
0,0 → 1,123
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: burst_read_data_fetcher - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for burst read data fetcher.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity burst_read_data_fetcher is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
acknowledge_read_data_in : in STD_LOGIC;
data_in : in std_logic_vector(data_width -1 downto 0);
data_out : out std_logic_vector(data_width -1 downto 0);
pop_index : out STD_LOGIC;
store_data : out STD_LOGIC
);
end burst_read_data_fetcher;
 
architecture Behavioral of burst_read_data_fetcher is
type StateType is (idle, store_read_data
);
 
signal CurrentState,NextState: StateType;
signal count_s : integer range 0 to 4;
--signal count_s : integer range 0 to burst_length;
signal data_s : std_logic_vector(data_width -1 downto 0);
begin
read_counter : process(clock,reset,acknowledge_read_data_in,data_s,count_s)
begin
if(clock = '1' and clock'event) then
if(reset = '1') then
count_s <= 0;
data_s <= (others => '0');
elsif(count_s = 2 or count_s = 4) then
-- elsif(count_s = burst_length) then
count_s <= 0;
data_s <= data_s;
elsif(acknowledge_read_data_in = '1') then
count_s <= count_s + 1;
data_s <= data_in;
else
count_s <= count_s;
data_s <= data_s;
end if;
end if;
data_out <= data_s;
end process read_counter;
 
pop_index <= '1' when (count_s = 2 OR count_s = 4) else '0';
 
--pop_index <= '1' when (count_s = burst_length) else '0';
 
read_data_storage: process(CurrentState,acknowledge_read_data_in)--,Memory_access_in)
 
begin
case (CurrentState) is
when idle =>
if(acknowledge_read_data_in = '1') then
NextState <= store_read_data;
else
NextState <= idle;
end if;
store_data <= '0';
when store_read_data =>
NextState <= idle;
store_data <= '1';
when others =>
NextState <= idle;
store_data <= '0';
end case;
end process read_data_storage;
 
nextstatelogic: process
begin
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
-- INITIALIZATION
if (Reset = '1') then
CurrentState <= idle;
else
CurrentState <= NextState;
end if;
end process nextstatelogic;
 
 
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/write_address_decoder.vhd
0,0 → 1,194
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: write_address_decoder - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for write address decoder.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity write_address_decoder is
Port ( clock : std_logic;
ports_in : memory_access_port_in;
burst_addresses : v_adr_i;
write_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
decoded_write_address : out STD_LOGIC_VECTOR (physical_address_width -1 downto 0);
write_enable_out : out STD_LOGIC_VECTOR (num_of_ports downto 0);
write_error_out : out STD_LOGIC_VECTOR (num_of_ports downto 0)
);
end write_address_decoder;
 
architecture Behavioral of write_address_decoder is
signal decoded_addresses : v_adr_i;
 
begin
decode_write_addresses : process(clock,ports_in.adr_i)
variable decoded_addresses_v : v_adr_i;
begin
if(clock'event and clock = '1') then
for i in 0 to (num_of_ports) loop
decoded_addresses_v(i) := burst_addresses(i);
end loop;
decoded_addresses <= decoded_addresses_v;
end if;
end process;
 
--transmit_write_enables : process(clock,ports_in.adr_i,write_enable_in)
--variable write_enable_out_v : STD_LOGIC_VECTOR (8 downto 0);
--begin
-- if(clock'event and clock = '1') then
-- for i in 0 to (num_of_ports -1) loop
-- if(ports_in.adr_i(i) < "0111110000000000000000" AND write_enable_in(i) = '1') then
-- write_enable_out_v(i) := '1';
-- else
-- write_enable_out_v(i) := '0';
-- end if;
-- end loop;
-- if(ports_in.adr_i(num_of_ports) < "0010000000000000000000" AND write_enable_in(num_of_ports) = '1') then
-- write_enable_out_v(num_of_ports) := '1';
-- else
-- write_enable_out_v(num_of_ports) := '0';
-- end if;
---- write_enable_out <= write_enable_out_v;
-- end if;
-- write_enable_out <= write_enable_out_v;
--end process;
 
transmit_write_enables : process(clock,burst_addresses,write_enable_in)
variable write_enable_out_v : STD_LOGIC_VECTOR (8 downto 0);
begin
if(clock'event and clock = '1') then
if(write_enable_in(0) = '1') then
if(decoded_addresses(0)(20 downto 18) < "111") then
write_enable_out_v(0) := '1';
end if;
elsif(write_enable_in(1) = '1') then
if(decoded_addresses(1)(20 downto 18) < "111") then
write_enable_out_v(1) := '1';
end if;
elsif(write_enable_in(2) = '1') then
if(decoded_addresses(2)(20 downto 18) < "111") then
write_enable_out_v(2) := '1';
end if;
elsif(write_enable_in(3) = '1') then
if(decoded_addresses(3)(20 downto 18) < "111") then
write_enable_out_v(3) := '1';
end if;
elsif(write_enable_in(4) = '1') then
if(decoded_addresses(4)(20 downto 18) < "111") then
write_enable_out_v(4) := '1';
end if;
elsif(write_enable_in(5) = '1') then
if(decoded_addresses(5)(20 downto 18) < "111") then
write_enable_out_v(5) := '1';
end if;
elsif(write_enable_in(6) = '1') then
if(decoded_addresses(6)(20 downto 18) < "111") then
write_enable_out_v(6) := '1';
end if;
elsif(write_enable_in(7) = '1') then
if(decoded_addresses(7)(20 downto 18) < "111") then
write_enable_out_v(7) := '1';
end if;
elsif(write_enable_in(8) = '1') then
-- if(burst_addresses(num_of_ports) < "0010000000000000000000") then
write_enable_out_v(8) := '1';
-- else
-- write_enable_out_v(8) := '0';
-- end if;
else
write_enable_out_v := "000000000";
end if;
 
-- if(burst_addresses(num_of_ports) < "0010000000000000000000" AND write_enable_in(num_of_ports) = '1') then
-- write_enable_out_v(num_of_ports) := '1';
-- else
-- write_enable_out_v(num_of_ports) := '0';
-- end if;
write_enable_out <= write_enable_out_v;
end if;
-- write_enable_out <= write_enable_out_v;
end process;
 
select_write_enable : process(clock,write_enable_in,decoded_addresses)
begin
if(clock'event and clock = '1') then
if(write_enable_in < "100000000") then
case write_enable_in is
when "000000001" => decoded_write_address <= "000" & decoded_addresses(0)(20 downto 0);
when "000000010" => decoded_write_address <= "001" & decoded_addresses(1)(20 downto 0);
when "000000100" => decoded_write_address <= "010" & decoded_addresses(2)(20 downto 0);
when "000001000" => decoded_write_address <= "011" & decoded_addresses(3)(20 downto 0);
when "000010000" => decoded_write_address <= "100" & decoded_addresses(4)(20 downto 0);
when "000100000" => decoded_write_address <= "101" & decoded_addresses(5)(20 downto 0);
when "001000000" => decoded_write_address <= "110" & decoded_addresses(6)(20 downto 0);
when "010000000" => decoded_write_address <= "111" & decoded_addresses(7)(20 downto 0);
when others => decoded_write_address <= "000000000000000000000000";
end case;
else
case (decoded_addresses(8)(18 downto 16)) is
when "000" => decoded_write_address <= "00011" & decoded_addresses(num_of_ports)(18 downto 0);
when "001" => decoded_write_address <= "00111" & decoded_addresses(num_of_ports)(18 downto 0);
when "010" => decoded_write_address <= "01011" & decoded_addresses(num_of_ports)(18 downto 0);
when "011" => decoded_write_address <= "01111" & decoded_addresses(num_of_ports)(18 downto 0);
when "100" => decoded_write_address <= "10011" & decoded_addresses(num_of_ports)(18 downto 0);
when "101" => decoded_write_address <= "10111" & decoded_addresses(num_of_ports)(18 downto 0);
when "110" => decoded_write_address <= "11011" & decoded_addresses(num_of_ports)(18 downto 0);
when "111" => decoded_write_address <= "11111" & decoded_addresses(num_of_ports)(18 downto 0);
when others => decoded_write_address <= "000000000000000000000000";
end case;
end if;
end if;
end process select_write_enable;
 
transmit_errors : process(clock,write_enable_in,decoded_addresses)
begin
if(clock'event and clock = '1') then
for i in 0 to (num_of_ports -1) loop
if(write_enable_in(i) = '1') then
if(decoded_addresses(i)(20 downto 18) = "111") then
write_error_out(i) <= '1';
end if;
else
write_error_out(i) <= '0';
end if;
end loop;
write_error_out(num_of_ports) <= '0';
end if;
end process transmit_errors;
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/read_address_decoder.vhd
0,0 → 1,371
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: read_address_decoder - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for read address decoder.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity read_address_decoder is
Port ( reset : in std_logic;
clock : in STD_LOGIC;
read_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
adr_i : in v_adr_i;
id_i : in ID_type;
read_index : out integer range 0 to num_of_ports;
decoded_read_address_out : out STD_LOGIC_VECTOR(physical_address_width -1 downto 0);
err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
read_enable_out : out STD_LOGIC);
end read_address_decoder;
 
architecture Behavioral of read_address_decoder is
type StateType is (reset_state,idle_0,read_requested,check_availability,
check_type, error_state,local_read, shared_read,
check_availability_1, find_port, find_port_0, send_read, send_read_0);
signal CurrentState,NextState: StateType;
signal store_index,store_port,send_error : std_logic;
signal index_i_v, port_i_v : integer range 0 to num_of_ports;
signal read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports downto 0);
signal BA,BA_0 : std_logic_vector(2 downto 0);
begin
 
--store_index_value : process(clock,read_enable_in) --(clock,store_index) --reset_index,store_index)
--begin
-- case(read_enable_in) is
-- when "00000001" => index_i_v <= 0;
-- when "00000010" => index_i_v <= 1;
-- when "00000100" => index_i_v <= 2;
-- when "00001000" => index_i_v <= 3;
-- when "00010000" => index_i_v <= 4;
-- when "00100000" => index_i_v <= 5;
-- when "01000000" => index_i_v <= 6;
-- when "10000000" => index_i_v <= 7;
-- when others => index_i_v <= 0;
-- end case;
--end process;
 
store_index_value : process(clock,store_index,read_enable_in) --(clock,store_index) --reset_index,store_index)
variable index_i_v_v : integer range 0 to num_of_ports;
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
read_enable_in_v <= read_enable_in;
if(store_index = '1') then
index_i_v_v := find_high_bit(read_enable_in_v);
else
index_i_v_v := index_i_v_v;
end if;
end if;
index_i_v <= index_i_v_v;
end process;
 
--store_index_value : process(clock,store_index,read_enable_in) --(clock,store_index) --reset_index,store_index)
--begin
---- if(clock'event and clock = '1') then
-- if(rising_edge(clock)) then
-- read_enable_in_v <= read_enable_in;
-- if(store_index = '1') then
-- index_i_v <= find_high_bit(read_enable_in_v);
-- else
-- index_i_v <= index_i_v;
-- end if;
-- end if;
--end process;
 
save_port: process(clock,store_port,adr_i,index_i_v,id_i)
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
if(store_port = '1') then
port_i_v <= check_ID(adr_i,index_i_v, id_i).return_port;
else
port_i_v <= port_i_v;
end if;
end if;
end process;
 
assert_error: process(clock,send_error)
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
if(send_error = '1') then
err_o(index_i_v) <= '1';
else
err_o <= "000000000";
end if;
end if;
end process;
 
decode_adr : process(clock,port_i_v,adr_i) --FOR SHARED READS
begin
--if(rising_edge(clock)) then
--if(port_i_v < 7) then
--dummy_vector <= "11110";
case(port_i_v) is
when 0 => BA <= "000"; --11110";
when 1 => BA <= "001"; --11110";
when 2 => BA <= "010"; --11110";
when 3 => BA <= "011"; --11110";
when 4 => BA <= "100"; --11110";
when 5 => BA <= "101"; --11110";
when 6 => BA <= "110"; --11110";
when 7 => BA <= "111"; --11110";
when others => BA <= "000";
end case;
--else
--dummy_vector <= "11110";
-- case (adr_i(8)(18 downto 16)) is
-- when "000" => BA <= "000" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "001" => BA <= "001" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "010" => BA <= "010" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "011" => BA <= "011" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "100" => BA <= "100" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "101" => BA <= "101" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "110" => BA <= "110" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when "111" => BA <= "111" ;--& decoded_addresses(num_of_ports)(15 downto 0);
-- when others => BA <= "000";
-- end case;
--end if;
end process;
 
decode_adr_0 : process(clock,read_enable_in) --FOR LOCAL READS
begin
if(rising_edge(clock)) then
--if(port_i_v < 7) then
--dummy_vector <= "11110";
case(read_enable_in) is
when "000000001" => BA_0 <= "000"; --11110";
when "000000010" => BA_0 <= "001"; --11110";
when "000000100" => BA_0 <= "010"; --11110";
when "000001000" => BA_0 <= "011"; --11110";
when "000010000" => BA_0 <= "100"; --11110";
when "000100000" => BA_0 <= "101"; --11110";
when "001000000" => BA_0 <= "110"; --11110";
when "010000000" => BA_0 <= "111"; --11110";
when others => BA_0 <= BA_0;
end case;
end if;
END PROCESS;
 
 
 
 
read_acces_process: process(CurrentState,read_enable_in,adr_i,index_i_v,id_i,BA,BA_0)--,Memory_access_in)
 
begin
case (CurrentState) is
when reset_state =>
NextState <= idle_0;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when idle_0 =>
if(read_enable_in = "00000000") then
NextState <= idle_0;
else
NextState <= read_requested;
end if;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when read_requested =>
NextState <= check_type;
read_enable_out <= '0';
store_index <= '1';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when check_availability =>
NextState <= check_availability_1;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when check_availability_1 =>
if(check_ID(adr_i,index_i_v, id_i).id_avail) then
NextState <= shared_read;
else
NextState <= error_state;
end if;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when check_type =>
if(adr_i(index_i_v)(21) = '0') then
NextState <= local_read;
else
NextState <= check_availability;
end if;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when local_read =>
NextState <= find_port_0;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when find_port =>
NextState <= send_read;
read_enable_out <= '0';
store_index <= '0';
store_port <= '1';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when find_port_0 =>
NextState <= send_read_0;
read_enable_out <= '0';
store_index <= '0';
store_port <= '1';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
-- when decode_address
-- NextState <= idle_0;
--
-- read_enable_out <= '0';
-- store_index <= '0';
-- store_port <= '0';
when send_read =>
NextState <= idle_0;
read_enable_out <= '1';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= BA & "11011" & adr_i(index_i_v) (15 downto 0);
read_index <= index_i_v;
send_error <= '0';
when send_read_0 =>
NextState <= idle_0;
read_enable_out <= '1';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= BA_0 & adr_i(index_i_v)(20 downto 0) ;
read_index <= index_i_v;
send_error <= '0';
when shared_read =>
NextState <= find_port;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
when error_state =>
NextState <= reset_state;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '1';
when others =>
NextState <= reset_state;
read_enable_out <= '0';
store_index <= '0';
store_port <= '0';
decoded_read_address_out <= (others => '0');
read_index <= 0;
send_error <= '0';
end case;
end process read_acces_process;
nextstatelogic: process
begin
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
if (Reset = '1') then
CurrentState <= reset_state;
else
CurrentState <= NextState;
end if;
end process nextstatelogic;
 
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/write_read_FIFO.vhd
0,0 → 1,220
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Write_read_FIFO - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for read and write access.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity write_read_FIFO is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
DAT_I : in v_data_i;
SEL_I : in v_sel_i;
Read_Enable : in STD_LOGIC;
Write_Enable : in std_logic_vector(num_of_ports downto 0);
decoded_write_address : in std_logic_vector(physical_address_width -1 downto 0);
decoded_read_address : in std_logic_vector(physical_address_width -1 downto 0);
Acknowledge_in : in STD_LOGIC;
Write_data_out : out std_logic_vector(data_width -1 downto 0);
address_out : out std_logic_vector(physical_address_width -1 downto 0);
write_enable_out : out STD_LOGIC;
read_enable_out : out STD_LOGIC;
FIFO_empty : out STD_LOGIC;
FIFO_full : out STD_LOGIC);
end write_read_FIFO;
 
architecture Behavioral of write_read_FIFO is
type Data_Array is
array (0 to stack_depth -1) of std_logic_vector(WR_FIFO_witdh -1 downto 0);
signal full_s,empty_s : std_logic;
signal count_v_s : std_logic_vector(2 downto 0);
signal decoded_write_address_s : std_logic_vector(physical_address_width -1 downto 0);
begin
counter : process(clock,decoded_write_address) --(clock,store_index) --reset_index,store_index)
--variable index_i_v_v : integer range 0 to num_of_ports;
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
begin
-- if(clock'event and clock = '1') then
if(rising_edge(clock)) then
decoded_write_address_s <= decoded_write_address;
end if;
end process;
 
 
 
store_WR_data : process(clock,reset,read_enable,write_enable,acknowledge_in)
variable Data_array_v : data_array;
variable var_a, var_b : integer range 0 to stack_depth -1;
--variable read_ack_v : STD_LOGIC_VECTOR(7 downto 0);
variable count_v : std_logic_vector(2 downto 0);
begin
if clock='1' and clock'event then
-------------------Works------------------------
if reset='1' then
var_a := 0;
var_b := 0;
count_v := "000";
for i in 0 to (stack_depth -1) loop
data_array_v(i) := (others => '0');
end loop;
else
if(read_enable = '1' AND acknowledge_in = '1') then -- AND full_s = '0') then
Data_array_v(var_a) := decoded_read_address & dummy_data & read_cmd;
-- read_ack_v(index_array(var_b)) := '1';
count_v := count_v;
if(var_a = stack_depth -1) then
var_a := 0;
else
var_a := var_a +1;
end if;
if(var_b = stack_depth -1) then
var_b := 0;
else
var_b := var_b +1;
end if;
elsif(read_enable = '1') then -- AND full_s = '0') then
if(full_s = '0') then
Data_array_v(var_a) := decoded_read_address & dummy_data & read_cmd;
count_v := count_v +1;
if(var_a = stack_depth -1) then
var_a := 0;
else
var_a := var_a +1;
end if;
end if;
 
----------------------------------------------------------------------
elsif(write_enable > "000000000" AND acknowledge_in = '1') then -- AND full_s = '0') then
case(write_enable) is
when "000000001" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(0) & write_cmd;
when "000000010" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(1) & write_cmd;
when "000000100" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(2) & write_cmd;
when "000001000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(3) & write_cmd;
when "000010000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(4) & write_cmd;
when "000100000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(5) & write_cmd;
when "001000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(6) & write_cmd;
when "010000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(7) & write_cmd;
when "100000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(8) & write_cmd;
when others =>
Data_array_v(var_a) := decoded_write_address_s & dummy_data & "00";
end case;
count_v := count_v;
if(var_a = stack_depth -1) then
var_a := 0;
else
var_a := var_a +1;
end if;
if(var_b = stack_depth -1) then
var_b := 0;
else
var_b := var_b +1;
end if;
elsif(write_enable > "000000000") then
if(full_s = '0') then
count_v := count_v +1;
case(write_enable) is
when "000000001" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(0) & write_cmd;
when "000000010" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(1) & write_cmd;
when "000000100" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(2) & write_cmd;
when "000001000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(3) & write_cmd;
when "000010000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(4) & write_cmd;
when "000100000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(5) & write_cmd;
when "001000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(6) & write_cmd;
when "010000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(7) & write_cmd;
when "100000000" =>
Data_array_v(var_a) := decoded_write_address_s & dat_i(8) & write_cmd;
when others =>
Data_array_v(var_a) := decoded_write_address_s & dummy_data & "00";
end case;
if(var_a = stack_depth -1) then
var_a := 0;
else
var_a := var_a +1;
end if;
end if;
elsif(acknowledge_in = '1') then -- AND empty_s = '0') then
if(empty_s = '0') then
count_v := count_v -1;
if(var_b = stack_depth -1) then
var_b := 0;
else
var_b := var_b +1;
end if;
end if;
else
count_v := count_v;
var_a := var_a;
var_b := var_b;
end if;
end if;
end if;
count_v_s <= count_v;
Write_data_out <= Data_array_v(var_b)(data_delimiter downto read_write_delimiter);
address_out <= Data_array_v(var_b)(address_delimiter downto data_delimiter +1);
--Write_data_out <= Data_array_v(var_b)(33 downto 2);
--address_out <= Data_array_v(var_b)(57 downto 34);
write_enable_out <= Data_array_v(var_b)(1);
read_enable_out <= Data_array_v(var_b)(0);
 
end process store_WR_data;
 
FULL_s <= '1'when (conv_integer(count_v_s) = stack_depth) else '0';
EMPTY_s <= '1'when (conv_integer(count_v_s) = 0) else '0';
 
fifo_full <= full_s;
fifo_empty <= empty_s;
 
end Behavioral;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/Top_Level_MAC.vhd
0,0 → 1,409
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Top_Level_MAC - Structural
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Top-level structural description for Memory Access Controller (MAC).
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Top_Level_MAC is
Port ( clock : in STD_LOGIC;
device_clock : in STD_LOGIC;
reset : in STD_LOGIC;
Memory_Access_in : in Memory_Access_Port_in;
Memory_Access_out : out Memory_Access_Port_out;
MAC_in : in Preprocessor_Interface_Port_in;
MAC_out : out Preprocessor_Interface_Port_out
);
end Top_Level_MAC;
 
architecture Structural of Top_Level_MAC is
 
component Arbitration_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
FIFO_full : in STD_LOGIC;
FIFO_empty : in std_logic;
read_request : in std_logic_vector(num_of_ports downto 0);
write_request : in std_logic_vector(num_of_ports downto 0);
-- Memory_Access_in : in Memory_Access_Port_in;
priority_signals : in priority_type;
read_acknowledge : in std_logic_vector(num_of_ports downto 0);
read_enable_in : out std_logic_vector(num_of_ports downto 0);
write_enable_in : out std_logic_vector(num_of_ports downto 0)
);
end component;
 
component write_read_FIFO is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
DAT_I : in v_data_i;
SEL_I : in v_sel_i;
Read_Enable : in STD_LOGIC;
Write_Enable : in std_logic_vector(num_of_ports downto 0);
decoded_write_address : in std_logic_vector(physical_address_width -1 downto 0);
decoded_read_address : in std_logic_vector(physical_address_width -1 downto 0);
Acknowledge_in : in STD_LOGIC;
Write_data_out : out std_logic_vector(data_width -1 downto 0);
address_out : out std_logic_vector(physical_address_width -1 downto 0);
write_enable_out : out STD_LOGIC;
read_enable_out : out STD_LOGIC;
FIFO_empty : out STD_LOGIC;
FIFO_full : out STD_LOGIC);
end component;
 
component write_address_decoder is
Port ( clock : std_logic;
ports_in : memory_access_port_in;
write_enable_in : in STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
decoded_write_address : out STD_LOGIC_VECTOR (physical_address_width -1 downto 0);
write_enable_out : out STD_LOGIC_VECTOR (num_of_ports -1 downto 0));
end component;
 
signal read_enable_in_s, write_enable_in_s, write_enable_out_s,burst_write_enable_s,
read_request_s,write_request_s, acknowledge_s : std_logic_vector(num_of_ports downto 0);
signal read_enable_out_s,FIFO_full_s,FIFO_empty_s: std_logic;
signal decoded_read_address_out_s : std_logic_vector(physical_address_width -1 downto 0);
signal Decoded_write_address_out_s : std_logic_vector(physical_address_width -1 downto 0);
signal Read_Acknowledge_out_s,Read_Acknowledge_out_s_1,read_err_o_s,write_err_o_s,pop_burst_data_s : std_logic_vector(num_of_ports downto 0);
--signal Memory_Access_out_s : Memory_Access_Port_out;
signal burst_data_s : v_data_i;
signal burst_full_s, burst_empty_s,reset_buffer_s, acknowledge_read_data_s,reset_pop_count_s : std_logic_vector(num_of_ports downto 0);
signal address_vectors,burst_addresses_s : v_adr_i;
signal data_out_s : Data_out_Array;
signal pop_index_s, store_data_s : std_logic;
signal read_data_out_s,read_data_reg_s : std_logic_vector(data_width -1 downto 0);
signal read_index_s : integer range 0 to num_of_ports;
signal read_buffer_enable_s, pop_dummy_s, buffer_full_dummy_s, buffer_empty_dummy_s,pop_read_data_s : std_logic_vector(num_of_ports downto 0);
signal data_out_dummy_s : read_data_array;
 
component Address_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
read_enable_in : in std_logic_vector(num_of_ports downto 0);
write_enable_in : in std_logic_vector(num_of_ports downto 0);
Memory_Access_in : in Memory_Access_Port_in;
burst_addresses : in v_adr_i;
read_address : in v_adr_i;
acknowledge_read_data_in : in STD_LOGIC;
read_index : out integer range 0 to num_of_ports;
read_err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
write_err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
Decoded_write_address_out : out std_logic_vector(physical_address_width -1 downto 0);
Write_enable_out : out STD_LOGIC_VECTOR (num_of_ports downto 0);
Decoded_Read_address_out : out std_logic_vector(physical_address_width -1 downto 0);
read_enable_out : out STD_LOGIC;
Read_Acknowledge_out : out STD_LOGIC_VECTOR(num_of_ports downto 0)
);
end component;
 
component burst_data_fetch is
Port ( reset : in std_logic;
clock : in STD_LOGIC;
buffer_empty : in STD_LOGIC_VECTOR (num_of_ports downto 0);
write_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
pop_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
burst_write_enable : out STD_LOGIC_VECTOR (num_of_ports downto 0);
reset_pop_count : out STD_LOGIC_VECTOR (num_of_ports downto 0)
);
end component;
 
component Burst_data_Buffer is
Port (clock : in STD_LOGIC;
device_clock : in STD_LOGIC;
reset : in std_logic;
we_i : in std_logic;
data_in : in std_logic_vector(data_width -1 downto 0);
address_in : in std_logic_vector(virtual_address_width -1 downto 0);
data_out : out std_logic_vector((data_width + virtual_address_width)-1 downto 0);
read_address : out std_logic_vector(virtual_address_width -1 downto 0);
pop : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
lock_i : in std_logic;
read_err_i : in std_logic;
write_err_i : in std_logic;
err_o : out std_logic;
read_buffer_full : in std_logic;
read_serviced : in std_logic;
reset_pop_count_in : in std_logic;
read_acknowledge : in std_logic;
buffer_full : out std_logic;
buffer_empty : out std_logic;
write_enable_out : out std_logic;
read_enable_out : out std_logic;
acknowledge : out std_logic;
reset_buffer : out std_logic;
acknowledge_read_data : out std_logic
);
end component;
 
component burst_read_data_fetcher is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
acknowledge_read_data_in : in STD_LOGIC;
data_in : in std_logic_vector(data_width -1 downto 0);
data_out : out std_logic_vector(data_width -1 downto 0);
pop_index : out STD_LOGIC;
store_data : out STD_LOGIC
);
end component;
 
component read_data_buffer is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
clear_buffer : in std_logic;
push : in STD_LOGIC;
pop : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(data_width -1 downto 0);
data_out : out STD_LOGIC_VECTOR(data_width -1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic
);
end component;
 
begin
--process(Read_Acknowledge_out_s,Memory_Access_out_s)
--begin
----if clock='1' and clock'event then
-- for i in 0 to num_of_ports loop
-- if(Memory_Access_out_s.ack_o(i) = '1') then
-- Memory_Access_out.ack_o(i) <= '1';
-- elsif(Read_Acknowledge_out_s(i) = '1') then
-- Memory_Access_out.ack_o(i) <= '1';
-- else
-- Memory_Access_out.ack_o(i) <= '0';
-- end if;
-- end loop;
----end if;
--end process;
 
--process(clock,read_err_o_s,write_err_o_s)
--begin
--if clock='1' and clock'event then
-- for i in 0 to num_of_ports loop
-- if(read_err_o_s(i) = '1') then
-- Memory_Access_out.err_o(i) <= '1';
-- elsif(write_err_o_s(i) = '1') then
-- Memory_Access_out.err_o(i) <= '1';
-- else
-- Memory_Access_out.err_o(i) <= '0';
-- end if;
-- end loop;
--end if;
--end process;
 
register_read_data : process(clock,reset,MAC_in.Acknowledge_read_data_in)
begin
if(clock ='1' AND clock'event) then
if(reset = '1') then
read_data_reg_s <= (others => '0');
elsif(MAC_in.Acknowledge_read_data_in = '1') then
read_data_reg_s <= MAC_in.read_data_in;
else
read_data_reg_s <= read_data_reg_s;
end if;
end if;
end process;
 
multiplex_read_data : process(clock,reset,read_index_s,store_data_s)
begin
if(clock ='1' AND clock'event) then -- May not need to use clock enable for this signal
if(store_data_s = '1') then
read_buffer_enable_s(read_index_s) <= '1';
else
read_buffer_enable_s <= (others => '0');
end if;
end if;
end process;
 
process(data_out_s)
begin
for i in 0 to num_of_ports loop
burst_data_s(i) <= data_out_s(i)(53 downto 22);
burst_addresses_s(i) <= data_out_s(i)(21 downto 0);
end loop;
--end if;
end process;
 
 
 
A0 : Address_Path
Port Map( clock => clock,
reset => reset,
read_enable_in => read_enable_in_s,
write_enable_in => write_enable_in_s,
Memory_Access_in => Memory_Access_in,
burst_addresses => burst_addresses_s,
read_address => address_vectors,
acknowledge_read_data_in => pop_index_s,
read_index => read_index_s,
read_err_o => read_err_o_s,
write_err_o => write_err_o_s,
Decoded_write_address_out => Decoded_write_address_out_s,
Write_enable_out => write_enable_out_s,
Decoded_Read_address_out => Decoded_Read_address_out_s,
read_enable_out => read_enable_out_s,
Read_Acknowledge_out => Read_Acknowledge_out_s
);
 
A1 : Arbitration_Path
Port Map( clock => clock,
reset => reset,
FIFO_full => FIFO_full_s,
FIFO_empty => FIFO_empty_s,
read_request => read_request_s,
write_request => write_request_s,
priority_signals => Memory_Access_in.priority_i,
read_acknowledge => Read_Acknowledge_out_s,
read_enable_in => read_enable_in_s,
write_enable_in => write_enable_in_s
);
A2 : write_read_FIFO
Port MAP( clock => clock,
reset => reset,
DAT_I => burst_data_s,
SEL_I => Memory_Access_in.sel_i,
Read_Enable => read_enable_out_s,
Write_Enable => burst_write_enable_s,
decoded_write_address => Decoded_write_address_out_s,
decoded_read_address => Decoded_Read_address_out_s,
Acknowledge_in => MAC_in.ack_access_in,
Write_data_out => MAC_out.Write_data_out,
address_out => MAC_out.address_out,
write_enable_out => MAC_out.write_enable_out,
read_enable_out => MAC_out.read_enable_out,
FIFO_empty => FIFO_empty_s,
FIFO_full => FIFO_full_s
);
Burts_write_data_fetcher : burst_data_fetch
Port Map( reset => reset,
clock => clock,
buffer_empty => burst_empty_s,
write_enable_in => write_enable_out_s,
pop_o => pop_burst_data_s,
burst_write_enable => burst_write_enable_s,
reset_pop_count => reset_pop_count_s
);
 
Make_Buffers: for i in 0 to num_of_ports generate
begin
Buffer_FIFO : Burst_data_Buffer
Port Map( clock => clock,
device_clock => device_clock,
reset => reset,
we_i => Memory_Access_in.we_i(i),
data_in => Memory_Access_in.dat_i(i),
address_in => Memory_Access_in.adr_i(i),
read_address => address_vectors(i),
pop => pop_burst_data_s(i),
data_out => data_out_s(i),
cyc_i => Memory_Access_in.cyc_i(i),
stb_i => Memory_Access_in.stb_i(i),
lock_i => Memory_Access_in.lock_i(i),
read_err_i => read_err_o_s(i),
write_err_i => write_err_o_s(i),
err_o => Memory_Access_out.err_o(i),
read_buffer_full => buffer_full_dummy_s(i),
read_serviced => read_enable_in_s(i),
reset_pop_count_in => reset_pop_count_s(i),
read_acknowledge => pop_burst_data_s(i),
buffer_full => burst_full_s(i),
buffer_empty => burst_empty_s(i),
write_enable_out => write_request_s(i),
read_enable_out => read_request_s(i),
reset_buffer => reset_buffer_s(i),
acknowledge => Read_Acknowledge_out_s_1(i),
acknowledge_read_data => acknowledge_read_data_s(i)
);
end generate;
 
read_data_fetcher : burst_read_data_fetcher
Port Map( clock => clock,
reset => reset,
acknowledge_read_data_in => MAC_in.Acknowledge_read_data_in,
data_in => MAC_in.Read_data_in,
data_out => read_data_out_s,
pop_index => pop_index_s,
store_data => store_data_s
);
 
Make_Read_Buffers : for i in 0 to num_of_ports generate
begin
read_buffers : read_data_buffer
Port Map( clock => clock,
reset => reset,
clear_buffer => reset_buffer_s(i),
push => read_buffer_enable_s(i),
pop => pop_read_data_s(i),
-- pop => acknowledge_read_data_s(i),
-- pop => pop_read_data_s(i),
data_in => read_data_reg_s,
data_out => Memory_Access_Out.dat_o(i),
buffer_full => buffer_full_dummy_s(i),
buffer_empty => buffer_empty_dummy_s(i)
);
end generate;
 
 
MAC_out.FIFO_empty_out <= FIFO_empty_s;
Memory_Access_out.burst_full <= burst_full_s;
Memory_Access_out.burst_empty <= burst_empty_s;
 
process(Read_Acknowledge_out_s_1,buffer_full_dummy_s,clock,acknowledge_read_data_s)
begin
if(rising_Edge(clock)) then
for i in 0 to (num_of_ports) loop
if(acknowledge_read_data_s(i) = '1') then
Memory_Access_out.ack_o(i) <= '1';
pop_read_data_s(i) <= '1';
elsif(Read_Acknowledge_out_s_1(i) = '1') then
Memory_Access_out.ack_o(i) <= '1';
pop_read_data_s(i) <= '0';
else
Memory_Access_out.ack_o(i) <= '0';
pop_read_data_s(i) <= '0';
end if;
end loop;
end if;
end process;
 
end Structural;
 
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/Arbitration_Path.vhd
0,0 → 1,635
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Arbitration_Path - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for memory access arbitration scheme.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Arbitration_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
FIFO_full : in STD_LOGIC;
FIFO_empty : in std_logic;
-- burst_full : in std_logic_vector(num_of_ports downto 0);
read_request : in std_logic_vector(num_of_ports downto 0);
write_request : in std_logic_vector(num_of_ports downto 0);
-- burst_empty : in std_logic_vector(num_of_ports downto 0);
priority_signals : in priority_type;
-- Memory_Access_out : out Memory_Access_Port_out;
read_acknowledge : in std_logic_vector(num_of_ports downto 0);
read_enable_in : out std_logic_vector(num_of_ports downto 0);
write_enable_in : out std_logic_vector(num_of_ports downto 0)
);
end Arbitration_Path;
 
architecture Behavioral of Arbitration_Path is
 
 
type StateType is (reset_state, idle_0, idle_1, idle_2, idle_3,
access_requested, access_requested_check,
inc_counter, increment_index_i, check_request_vector,
increment_index_j,check_priority, check_access_type,
check_access_type_1,check_access_type_2,check_access_type_3,
grant_write_access_1,
pre_inc_index_j, check_request_vector_0,
grant_write_access, grant_read_access,
check_index_j, pre_clear_index_j,
increment_index_i_0, increment_access_count, check_i_j,
clear_j, increment_req_index_i
);
signal CurrentState,NextState: StateType;
signal request, read_flag_a : std_logic_vector(num_of_ports downto 0);
signal access_count : std_logic_vector(7 downto 0);
signal index_i : integer range 0 to 7;
signal index_j : integer range 0 to num_of_ports;
signal read_access_out,write_access_out : std_logic_vector(num_of_ports downto 0);
signal inc_count, inc_index_i, inc_index_j, read_enable,write_enable,
clear_index_i,clear_index_j : std_logic;
begin
 
Generate_Access_Signals : process(clock,write_request,read_request)--,read_flag_a)
--variable : integer range (0 to num_of_ports-1);
begin
for i in 0 to (num_of_ports) loop
request(i) <= write_request(i) OR (read_request(i));-- AND ( read_flag_a(i)) );
end loop;
end process;
 
--toggle_read : process(clock,reset)
--variable flag : std_logic;
--begin
-- if clock='1' and clock'event then
-- if reset='1' then
-- read_flag_a <= "111111111";
-- else
-- for i in 0 to (num_of_ports) loop
-- flag := read_acknowledge(i) XOR read_access_out(i);
-- if(flag = '1') then
-- read_flag_a(i) <= not read_flag_a(i);
-- else
-- read_flag_a(i) <= read_flag_a(i);
-- end if;
-- end loop;
-- end if;
-- end if;
--end process;
 
 
access_counter : process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
access_count <= (others => '0');
elsif inc_count = '1' then
access_count <= access_count + 1;
end if;
end if;
end process;
 
Index_i_counter : process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
index_i <= 0;
elsif inc_index_i = '1' then
index_i <= index_i + 1;
elsif clear_index_i = '1' then
index_i <= 0;
end if;
end if;
end process;
 
Index_j_counter : process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
index_j <= 0;
elsif inc_index_j = '1' then
index_j <= index_j + 1;
elsif clear_index_j = '1' then
index_j <= 0;
end if;
end if;
end process;
 
set_access_outputs : process (clock,reset,read_enable,write_enable,read_access_out,write_access_out)
--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);
begin
if clock='1' and clock'event then
if reset='1' then
read_access_out <= "000000000";
write_access_out <= "000000000";
elsif read_enable = '1' then
read_access_out(index_j) <= '1';
write_access_out <= "000000000";
elsif write_enable = '1' then
write_access_out(index_j) <= '1';
read_access_out <= "000000000";
else
read_access_out <= "000000000";
write_access_out <= "000000000";
end if;
end if;
read_enable_in <= read_access_out;
write_enable_in <= write_access_out;
end process;
 
--set_access_outputs : process (clock,reset,read_enable,write_enable)
--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);
--begin
-- if clock='1' and clock'event then
-- if reset='1' then
-- read_access_out := "00000000";
-- write_access_out := "00000000";
-- elsif read_enable = '1' then
-- read_access_out(index_j) := '1';
-- write_access_out := "00000000";
-- elsif write_enable = '1' then
-- write_access_out(index_j) := '1';
-- read_access_out := "00000000";
-- else
-- read_access_out := "00000000";
-- write_access_out := "00000000";
-- end if;
-- end if;
-- read_enable_in <= read_access_out;
-- write_enable_in <= write_access_out;
--end process;
 
--set_write_acknowledge_outputs : process (clock,reset,write_enable)
--variable ack_write_out : std_logic_vector(num_of_ports downto 0);
--begin
-- if clock='1' and clock'event then
-- if reset='1' then
-- ack_write_out := "000000000";
-- elsif write_enable = '1' then
-- ack_write_out(index_j) := '1';
-- else
-- ack_write_out := "000000000";
-- end if;
-- end if;
-- Memory_Access_out.ack_o <= ack_write_out;
--end process;
 
 
--access_vector : process (clock)
----variable cnt : std_logic_vector(5 downto 0);
--begin
-- if reset='1' then
-- access_count <= (others => '0');
-- elsif inc_count = '1' then
-- access_count <= access_count + 1;
-- end if;
-- end if;
--end process;
 
 
arbitration_algorithm: process(CurrentState,request,index_j,index_i,access_count,FIFO_full,FIFO_empty,read_request,write_request,priority_signals)--,Memory_access_in)
 
begin
case (CurrentState) is
when reset_state =>
NextState <= idle_0;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when idle_0 =>
NextState <= idle_1;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when idle_1 =>
NextState <= idle_2;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when idle_2 =>
NextState <= idle_3;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when idle_3 =>
if(request = "00000000") then
NextState <= inc_counter;
else
NextState <= access_requested;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when inc_counter =>
NextState <= idle_0;
inc_count <= '1';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
------------------------------------------------------------------------------------
-- Access Counter Loop
when access_requested =>
NextState <= access_requested_check;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when access_requested_check =>
if(access_count(index_i) = '0') then
NextState <= increment_index_i;
else
NextState <= check_request_vector;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when increment_index_i =>
if(index_i = 7) then
NextState <= increment_access_count;
else
NextState <= increment_index_i_0;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when increment_index_i_0 =>
NextState <= access_requested_check;
inc_count <= '0';
inc_index_i <= '1';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
 
-------------------------------------------------------------------------------------
-- Request Vector Loop
when check_request_vector =>
-- if(index_j = 7 AND index_i = 7) then
-- NextState <= increment_access_count;
-- elsif(index_j = 7) then
-- NextState <= pre_clear_index_j;
-- else
NextState <= check_request_vector_0;
-- end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when pre_clear_index_j =>
NextState <= access_requested;
inc_count <= '0';
inc_index_i <= '1';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '1';
read_enable <= '0';
write_enable <= '0';
when check_request_vector_0 =>
if((request(index_j) = '0') AND (index_j = num_of_ports)) then
NextState <= increment_access_count;
elsif(request(index_j) = '0') then
NextState <= increment_index_j;
else
NextState <= check_priority;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when increment_index_j =>
NextState <= check_request_vector;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '1';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
-------------------------------------------------------------------------------------
-- Check Priority
 
when check_priority =>
if(priority_signals(index_j)(index_i) = '1') then
NextState <= check_access_type;
else
NextState <= check_index_j;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when check_index_j =>
if(index_j = num_of_ports AND index_i = 7) then
NextState <= increment_access_count;
elsif(index_j = num_of_ports) then
NextState <= pre_clear_index_j;
else
NextState <= pre_inc_index_j;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when pre_inc_index_j =>
NextState <= check_request_vector;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '1';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
 
----------------------------------------------------------------------------------------
-- Check Access Type
when check_access_type =>
NextState <= check_access_type_1;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when check_access_type_1 =>
NextState <= check_access_type_2;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when check_access_type_2 =>
NextState <= check_access_type_3;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when check_access_type_3 =>
if(FIFO_full = '1') then
NextState <= check_access_type_3;
elsif(write_request(index_j) = '1') then
NextState <= grant_write_access;
else
NextState <= grant_read_access;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
 
----------------------------------------------------------------------------------------
-- Grant Access
-- when grant_write_access =>
-- if(FIFO_empty = '1' AND burst_full(index_j) = '1') then
-- NextState <= grant_write_access_1;
-- else
-- NextState <= grant_write_access;
-- end if;
-- inc_count <= '0';
-- inc_index_i <= '0';
-- inc_index_j <= '0';
-- clear_index_i <= '0';
-- clear_index_j <= '0';
-- read_enable <= '0';
-- write_enable <= '0';
when grant_write_access =>
if(FIFO_empty = '1') then
NextState <= grant_write_access_1;
else
NextState <= grant_write_access;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when grant_write_access_1 =>
NextState <= check_i_j;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '1';
when grant_read_access =>
NextState <= check_i_j;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '1';
write_enable <= '0';
when check_i_j =>
if(index_i = 7 AND index_j = num_of_ports) then
NextState <= increment_access_count;
elsif(index_j = num_of_ports) then
NextState <= clear_j;
else
NextState <= increment_req_index_i;
end if;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when increment_req_index_i =>
NextState <= access_requested;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '1';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
when clear_j =>
NextState <= access_requested;
inc_count <= '0';
inc_index_i <= '1';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '1';
read_enable <= '0';
write_enable <= '0';
 
when increment_access_count =>
NextState <= reset_state;
inc_count <= '1';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '1';
clear_index_j <= '1';
read_enable <= '0';
write_enable <= '0';
when others =>
NextState <= reset_state;
inc_count <= '0';
inc_index_i <= '0';
inc_index_j <= '0';
clear_index_i <= '0';
clear_index_j <= '0';
read_enable <= '0';
write_enable <= '0';
end case;
end process Arbitration_algorithm;
nextstatelogic: process
begin
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
-- INITIALIZATION
if (Reset = '1') then
CurrentState <= reset_state;
else
CurrentState <= NextState;
end if;
end process nextstatelogic;
end Behavioral;
 
 
 
-- when access_requested_check =>
-- if((request(index_i) = '1') AND Memory_Access_in.priority_i(index_j)(index_k) = access_count(index_i)) then
-- NextState <= idle_0;
-- else
-- NextState <= idle_0;
-- end if;
--
-- inc_count <= '1';
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/MAC_constants.vhd
0,0 → 1,196
-- Package Filea Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use work.mem_interface_top_parameters_0.all;
 
package MAC_Constants is
 
constant max_burst_length : integer := 8;
constant burst_length : integer := 4;
--constant burst_data_width integer :=
constant num_of_ports : integer := 8;
constant virtual_address_width : integer := 22;
constant physical_address_width : integer := 24;
constant data_width : integer := 32;
constant data_resolution : integer := 4;
constant ID_width : integer := 5;
constant priority_width : integer := 8;
constant stack_depth : integer := 4;
constant cmd_width : integer := 2;
constant WR_FIFO_witdh : integer := (physical_address_width + data_width + cmd_width);
constant dummy_data : std_logic_vector(data_width -1 downto 0) := (others => '0');
constant read_cmd : std_logic_vector(1 downto 0) := "01";
constant write_cmd : std_logic_vector(1 downto 0) := "10";
constant data_delimiter : integer := data_width + 1;
constant address_delimiter : integer := data_width + physical_address_width + 1;
constant read_write_delimiter : integer := 2;
 
 
type ID_type is
array (0 to num_of_ports -1) of std_logic_vector(ID_width -1 downto 0);
 
type priority_type is
array (0 to num_of_ports) of std_logic_vector(priority_width -1 downto 0);
type v_adr_i is
array (0 to num_of_ports) of std_logic_vector(virtual_address_width -1 downto 0);
 
--type v_adr_i_0 is
-- array (0 to num_of_ports -1) of std_logic_vector(virtual_address_width -2 downto 0);
 
type v_data_i is
array (0 to num_of_ports) of std_logic_vector(data_width -1 downto 0);
 
type burst_data_o is
array (0 to burst_length -1) of std_logic_vector(data_width -1 downto 0);
type v_sel_i is
array (0 to num_of_ports -1) of std_logic_vector(data_resolution -1 downto 0);
type Burst_Data_Array is
array (0 to burst_length -1) of std_logic_vector((data_width + virtual_address_width) -1 downto 0);
 
type Data_out_Array is
array (0 to num_of_ports) of std_logic_vector((data_width + virtual_address_width) -1 downto 0);
 
type burst_read_data_array is
array (0 to burst_length -1) of std_logic_vector(data_width -1 downto 0);
 
type read_data_array is
array (0 to num_of_ports) of std_logic_vector(data_width -1 downto 0);
 
 
type Memory_Access_Port_in is
record
adr_i : v_adr_i;
dat_i : v_data_i;
we_i : std_logic_vector(num_of_ports downto 0);
sel_i : v_sel_i;
stb_i : std_logic_vector(num_of_ports downto 0);
cyc_i : std_logic_vector(num_of_ports downto 0);
ID_i : ID_type;
priority_i : priority_type;
push_i : std_logic_vector(num_of_ports downto 0);
lock_i : std_logic_vector(num_of_ports downto 0);
end record;
type port_avail is
record
id_avail : boolean;
return_port : integer range 0 to num_of_ports -1;
end record;
type Memory_Access_Port_out is
record
err_o : std_logic_vector(num_of_ports downto 0);
ack_o : std_logic_vector(num_of_ports downto 0);
burst_full : std_logic_vector(num_of_ports downto 0);
burst_empty : std_logic_vector(num_of_ports downto 0);
dat_o : v_data_i;
end record;
 
type Preprocessor_Interface_Port_out is
record
write_data_out : std_logic_vector(data_width -1 downto 0);
address_out : std_logic_vector(physical_address_width -1 downto 0);
write_enable_out : std_logic;
read_enable_out : std_logic;
FIFO_empty_out : std_logic;
end record;
 
type Preprocessor_Interface_Port_in is
record
Acknowledge_read_data_in : std_logic;
ack_access_in : std_logic;
Read_data_in : std_logic_vector(data_width -1 downto 0);
end record;
 
function find_high_bit (signal l : in STD_LOGIC_VECTOR (num_of_ports downto 0)) return integer;
function check_ID (signal l : in v_adr_i; signal n : in integer range 0 to num_of_ports; signal m : in ID_type) return port_avail;
end MAC_Constants;
 
 
package body MAC_Constants is
 
function find_high_bit (signal l : in STD_LOGIC_VECTOR (num_of_ports downto 0)) return integer is
variable return_v : integer range 0 to num_of_ports;
begin
for i in 0 to num_of_ports loop
if(l(i) = '1') then
return_v := i ;
exit;
end if;
end loop;
return return_v;
end find_high_bit;
function check_ID (signal l : in v_adr_i; signal n : in integer range 0 to num_of_ports; signal m : in ID_type) return port_avail is
variable return_v : port_avail;
-- variable return_v : boolean;
-- variable return_port : integer range 0 to num_of_ports -1;
begin
for i in 0 to num_of_ports -1 loop
if(l(n)(20 downto 16) = m(i)) then
return_v.id_avail := true;
return_v.return_port := i;
exit;
else
return_v.id_avail := false;
return_v.return_port := 0;
end if;
end loop;
return return_v;
end check_ID;
--function decode_a (signal l : in v_adr_i; signal n : in integer range 0 to num_of_ports -1; signal m : in ID_type) return port_avail is
-- variable return_v : port_avail;
---- variable return_v : boolean;
---- variable return_port : integer range 0 to num_of_ports -1;
-- begin
-- for i in 0 to num_of_ports -1 loop
-- if(l(n)(20 downto 16) = m(i)) then
-- return_v.id_avail := true;
-- return_v.return_port := i;
-- exit;
-- else
-- return_v.id_avail := false;
-- return_v.return_port := 0;
-- end if;
-- end loop;
-- return return_v;
-- end check_ID;
 
--function translate_ID (signal l : in integer; signal n : in integer range 0 to num_of_ports -1; signal m : in ID_type) return boolean is
-- variable return_v : boolean;
-- begin
-- for i in 0 to num_of_ports -1 loop
-- if(l(n)(20 downto 16) = m(i)) then
-- return_v := true;
-- exit;
-- else
-- return_v := false;
-- end if;
-- end loop;
-- return return_v;
-- end check_ID;
-- if(check_ID(adr_i,index_i_v, id_i) then
--function decode (signal l : in std_logic_vector; signal m : in ID_type) return boolean is
-- variable return_v : boolean;
-- begin
-- for i in 0 to num_of_ports -1 loop
-- if(m(i) = l) then
-- return_v := true;
-- exit;
-- end if;
-- end loop;
-- return return_v;
-- end check_ID;
end MAC_Constants;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/decode_top_of_FIFO.vhd
0,0 → 1,126
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Acknowledge_Path - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for memory access acknowledgement (read and write).
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Acknowledge_Path is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
read_index : in integer range 0 to num_of_ports;
read_index_out : out integer range 0 to num_of_ports;
read_enable : in STD_LOGIC;
acknowledge_read_data_in : in STD_LOGIC;
read_acknowledge : out STD_LOGIC_VECTOR (num_of_ports downto 0));
end Acknowledge_Path;
 
architecture Behavioral of Acknowledge_Path is
type read_array is
array (0 to num_of_ports) of integer range 0 to num_of_ports;
signal full_s,empty_s : std_logic;
--signal read_enable_s, acknowledge_read_data_in_s : std_logic;
signal read_ack_v_s : STD_LOGIC_VECTOR(8 downto 0);
signal count_v_s : std_logic_vector(2 downto 0);
 
begin
store_index_values : process(clock,reset,read_enable,acknowledge_read_data_in)
variable index_array : read_array;
variable var_a, var_b : integer range 0 to num_of_ports;
variable read_ack_v : STD_LOGIC_VECTOR(8 downto 0);
variable count_v : std_logic_vector(2 downto 0);
begin
if clock='1' and clock'event then
-------------------Works------------------------
if reset='1' then
var_a := 0;
var_b := 0;
count_v := "000";
read_ack_v := "000000000";
else
if(read_enable = '1' AND acknowledge_read_data_in = '1') then -- AND full_s = '0') then
index_array(var_a) := read_index;
read_ack_v(index_array(var_b)) := '1';
count_v := count_v;
if(var_a = num_of_ports) then
var_a := 0;
else
var_a := var_a +1;
end if;
if(var_b = num_of_ports) then
var_b := 0;
else
var_b := var_b +1;
end if;
elsif(read_enable = '1') then -- AND full_s = '0') then
if(full_s = '0') then
index_array(var_a) := read_index;
count_v := count_v +1;
if(var_a = num_of_ports) then
var_a := 0;
else
var_a := var_a +1;
end if;
end if;
elsif(acknowledge_read_data_in = '1') then -- AND empty_s = '0') then
if(empty_s = '0') then
read_ack_v(index_array(var_b)) := '1';
count_v := count_v -1;
if(var_b = num_of_ports) then
var_b := 0;
else
var_b := var_b +1;
end if;
end if;
else
read_ack_v := "000000000";
count_v := count_v;
var_a := var_a;
var_b := var_b;
end if;
end if;
end if;
read_ack_v_s <= read_ack_v;
count_v_s <= count_v;
read_index_out <= index_array(var_b);
end process store_index_values;
 
FULL_s <= '1'when (conv_integer(count_v_s) = num_of_ports) else '0';
EMPTY_s <= '1'when (conv_integer(count_v_s) = 0) else '0';
 
read_acknowledge <= read_ack_v_s;
end Behavioral;
/the_wizardry_project/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/RDIC/read_data_buffer.vhd
0,0 → 1,118
----------------------------------------------------------------------------------
--
-- This file is a part of Technica Corporation Wizardry Project
--
-- Copyright (C) 2004-2009, Technica Corporation
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: read_data_buffer - Behavioral
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for read data buffer.
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity read_data_buffer is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
clear_buffer : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(data_width -1 downto 0);
data_out : out STD_LOGIC_VECTOR(data_width -1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic
);
end read_data_buffer;
 
architecture Behavioral of read_data_buffer is
signal data_array_v : burst_read_data_array;
signal var_a, var_b : integer range 0 to burst_length -1;
signal count_v : std_logic_vector(2 downto 0);
signal empty_s, full_s : std_logic;
signal count_v_s : std_logic_vector(2 downto 0);
 
begin
read_burst_data : process(clock,reset,pop,push,count_v,data_array_v,clear_buffer)
begin
if clock='1' and clock'event then
 
if (reset='1' OR clear_buffer = '1') then
var_a <= 0;
var_b <= 0;
count_v <= "000";
for i in 0 to (burst_length -1) loop
data_array_v(i) <= (others => '0');
end loop;
else
if(push = '1') then -- AND full_s = '0') then
if(count_v < "100") then
Data_array_v(var_a) <= data_in;
count_v <= count_v +1;
if(var_a = burst_length -1) then
var_a <= 0;
else
var_a <= var_a +1;
end if;
end if;
elsif(pop = '1') then -- AND empty_s = '0') then
if(empty_s = '0') then
count_v <= count_v -1;
if(var_b = burst_length -1) then
var_b <= 0;
else
var_b <= var_b +1;
end if;
end if;
else
count_v <= count_v;
var_a <= var_a;
var_b <= var_b;
end if;
end if;
end if;
 
 
 
count_v_s <= count_v;
data_out <= Data_array_v(var_b);
 
end process read_burst_data;
 
--FULL_s <= '1' when (conv_integer(count_v_s) = stack_depth) else '0';
FULL_s <= '1' when (conv_integer(count_v_s) = 1) else '0';
EMPTY_s <= '1' when (conv_integer(count_v_s) = 0) else '0';
 
buffer_full <= full_s;
buffer_empty <= empty_s;
 
end Behavioral;
 

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