OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

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Rev 20 → Rev 21

/uart_block/trunk/hdl/iseProject/isim.log
1,19 → 1,20
ISim log file
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_wishbone_slave.vhd:stim_proc
INFO: Simulator is stopped.
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_control.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
/uart_block/trunk/hdl/iseProject/fuseRelaunch.cmd
1,19 → 1,20
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave"
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj" "work.testUart_control"
/uart_block/trunk/hdl/iseProject/testUart_control.vhd
53,7 → 53,7
signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
 
-- Clock period definitions
constant clk_period : time := 2 ns; -- 2ns (50Mhz)
constant clk_period : time := 20 ns; -- 20ns (50Mhz)
BEGIN
/uart_block/trunk/hdl/iseProject/fuse.log
1,37 → 1,28
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
Compiling architecture behavior of entity testuart_wishbone_slave
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 21 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
Fuse Memory Usage: 37372 KB
Fuse CPU Usage: 420 ms
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj work.testUart_control
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36628 KB
Fuse CPU Usage: 1100 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling architecture behavior of entity testuart_control
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 10 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
Fuse Memory Usage: 85692 KB
Fuse CPU Usage: 1180 ms
GCC CPU Usage: 400 ms
/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
25,6 → 25,7
STB_I : IN std_logic;
ACK_O : OUT std_logic;
serial_in : IN std_logic;
data_Avaible : out std_logic; -- Indicate that the receiver module got something
serial_out : OUT std_logic
);
END COMPONENT;
43,6 → 44,7
signal DAT_O0 : std_logic_vector(31 downto 0);
signal ACK_O : std_logic;
signal serial_out : std_logic;
signal data_Avaible : std_logic;
 
-- Clock period definitions (1.8432MHz)
constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
60,6 → 62,7
STB_I => STB_I,
ACK_O => ACK_O,
serial_in => serial_in,
data_Avaible => data_Avaible,
serial_out => serial_out
);
 
/uart_block/trunk/hdl/iseProject/uart_wishbone_slave.vhd
15,6 → 15,7
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
serial_in : in std_logic;
data_Avaible : out std_logic; -- Indicate that the receiver module got something
serial_out : out std_logic
);
end uart_wishbone_slave;
34,7 → 35,7
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
tx_start : out std_logic; -- Signal to start sending serial data...
rst_comm_blocks : out std_logic; -- Reset Communication blocks
rst_comm_blocks : out std_logic; -- Reset Communication blocks
rx_data_ready : in std_logic);
end component;
 
90,6 → 91,8
serial_in => serial_in,
start_tx => tx_start
);
data_Avaible <= rx_data_ready;
 
end Behavioral;
 
/uart_block/trunk/hdl/iseProject/webtalk_pn.xml
1,46 → 1,47
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed May 02 01:22:50 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s500e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="15" type="source"/>
</section>
</application>
</document>
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed May 2 08:01:19 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/laraujo/work/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s500e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="15" type="source"/>
</section>
</application>
</document>
/uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
1,36 → 1,15
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/baud_generator.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/divisor.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/pkgDefinitions.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/serial_receiver.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/serial_transmitter.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/uart_control.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
1,324 → 1,114
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">53</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
</msg>
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">53</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
</msg>
 
<msg type="info" file="Xst" num="1561" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">84</arg>: Mux is complete : default of case is discarded
</msg>
<msg type="info" file="Xst" num="1561" delta="old" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">84</arg>: Mux is complete : default of case is discarded
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_23&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_6&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_18&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_19&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_14&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_1&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_28&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_2&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_26&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_22&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_7&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_4&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_17&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_13&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_27&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_25&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; &lt;half_cycle0_0&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_21&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_16&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_30&gt; &lt;half_cycle_31&gt; &lt;half_cycle0_31&gt; &lt;half_cycle0_30&gt; &lt;half_cycle0_29&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_12&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_8&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_5&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_10&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_24&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_20&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_15&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_1&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_11&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_9&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_3&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uBaudGen</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
</messages>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_23&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_6&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_18&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_19&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_14&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_28&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_26&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_22&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_7&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_4&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_17&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_13&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_27&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_25&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; &lt;half_cycle0_0&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_21&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_16&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_12&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_8&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_5&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_10&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_24&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_20&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_15&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_11&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_9&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_3&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">serial_receiver</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;data_ready&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/uart_block/trunk/hdl/iseProject/fuse.xmsgs
1,12 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
</messages>
 
</messages>
 
/uart_block/trunk/hdl/iseProject/xilinxsim.ini
1,12 → 1,9
work=isim/work
work=isim/work
/uart_block/trunk/hdl/iseProject/isim.cmd
1,3 → 1,3
onerror {resume}
wave add /
run 1000 ms;
onerror {resume}
wave add /
run 1000 ms;
/uart_block/trunk/hdl/iseProject/iseProject.xise
16,8 → 16,8
 
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
30,8 → 30,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
40,8 → 40,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
50,8 → 50,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
60,8 → 60,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
70,21 → 70,21
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/>
115,7 → 115,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
194,9 → 194,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_wishbone_slave|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_wishbone_slave.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_control|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_control.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave/uUartControl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
254,7 → 254,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
266,10 → 266,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_control_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_control_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_control_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_control_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
289,7 → 289,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
313,8 → 313,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_control" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_control" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
330,7 → 330,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
379,7 → 379,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_control|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/uart_block/trunk/hdl/iseProject/xst/work/hdpdeps.ref
1,63 → 1,70
V3 39
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.13:49:58 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/01.14:32:36 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd
EN work/baud_generator 1335914573 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1335914572
AR work/baud_generator/Behavioral 1335914574 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1335914573
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd
EN work/divisor 1335914579 FL E:/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1335914572
AR work/divisor/Behavioral 1335914580 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335914579
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.23:44:07 O.87xd
PH work/pkgDefinitions 1335914571 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335914572 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1335914571
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd
EN work/serial_receiver 1335914577 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1335914572
AR work/serial_receiver/Behavioral 1335914578 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335914577
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1335914575 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335914572
AR work/serial_transmitter/Behavioral 1335914576 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335914575
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd
EN work/uart_communication_blocks 1335914583 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335914572
AR work/uart_communication_blocks/Behavioral 1335914584 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1335914583 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.01:14:06 O.87xd
EN work/uart_control 1335914581 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335914572
AR work/uart_control/Behavioral 1335914582 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1335914581 \
CP divisor
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.23:14:46 O.87xd
EN work/uart_wishbone_slave 1335914585 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335914572
AR work/uart_wishbone_slave/Behavioral 1335914586 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1335914585 CP uart_control \
CP uart_communication_blocks
V3 39
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd
EN work/baud_generator 1335938431 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \
PB work/pkgDefinitions 1335938484
AR work/baud_generator/Behavioral 1335938432 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
EN work/baud_generator 1335938431
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd
EN work/divisor 1335938485 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1335938484
AR work/divisor/Behavioral 1335938486 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335938485
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/02.07:33:56 O.87xd
PH work/pkgDefinitions 1335938483 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335938484 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PH work/pkgDefinitions 1335938483
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd
EN work/serial_receiver 1335938435 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484
AR work/serial_receiver/Behavioral 1335938436 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
EN work/serial_receiver 1335938435
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd
EN work/serial_transmitter 1335938433 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484
AR work/serial_transmitter/Behavioral 1335938434 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335938433
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd
EN work/uart_communication_blocks 1335938441 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484
AR work/uart_communication_blocks/Behavioral 1335938442 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1335938441 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.07:33:56 O.87xd
EN work/uart_control 1335938487 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484
AR work/uart_control/Behavioral 1335938488 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1335938487 CP divisor
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd
EN work/uart_wishbone_slave 1335938443 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484
AR work/uart_wishbone_slave/Behavioral 1335938444 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1335938443 CP uart_control \
CP uart_communication_blocks
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.23:44:07 O.87xd
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.01:14:06 O.87xd
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.23:14:46 O.87xd
/uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
1,16 → 1,16
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335914584
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335914582
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335914572
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335914577
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335914586
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335914576
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335914583
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335914579
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335914580
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335914574
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335914581
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335914575
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335914571
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335914585
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335914573
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335914578
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335938487
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335938434
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335938443
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335938432
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335938435
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335938485
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335938486
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335938433
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335938442
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335938444
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335938436
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335938441
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335938484
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335938488
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335938431
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335938483
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl00.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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