URL
https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk
Subversion Repositories vg_z80_sbc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/trunk/rtl/rotary.v
9,62 → 9,46
input reset, |
input [2:0] rot, |
// |
output reg rot_btn, |
output rot_btn, |
output reg rot_event, |
output reg rot_left |
); |
|
assign rot_btn = 0; |
|
|
//---------------------------------------------------------------------------- |
// decode rotary encoder |
//---------------------------------------------------------------------------- |
reg [1:0] rot_q; |
parameter counter_init = 10000000; |
reg [31:0] counter; |
|
always @(posedge clk) |
begin |
case (rot[1:0]) |
2'b00: rot_q <= { rot_q[1], 1'b0 }; |
2'b01: rot_q <= { 1'b0, rot_q[0] }; |
2'b10: rot_q <= { 1'b1, rot_q[0] }; |
2'b11: rot_q <= { rot_q[1], 1'b1 }; |
endcase |
end |
reg rot_event2; |
reg rot_left2; |
|
reg [1:0] rot_q_delayed; |
|
always @(posedge clk) |
begin |
rot_q_delayed <= rot_q; |
if (reset) |
counter <= counter_init; |
else begin |
rot_event <= rot_event2; |
rot_left <= rot_left2; |
|
if (rot_q[0] && ~rot_q_delayed[0]) begin |
rot_event <= 1; |
rot_left <= rot_q[1]; |
end else |
rot_event <= 0; |
end |
rot_event2 <= 0; |
rot_left2 <= 0; |
|
//---------------------------------------------------------------------------- |
// debounce push button (rot[2]) |
//---------------------------------------------------------------------------- |
reg [2:0] rot_d; |
reg [15:0] dead_count; |
if (counter == 0) begin |
counter <= counter_init; |
|
always @(posedge clk) |
begin |
if (reset) begin |
rot_btn <= 0; |
dead_count <= 0; |
end else begin |
rot_btn <= 1'b0; |
rot_d <= { rot_d[1:0], rot[2] }; |
if (rot[0] | rot[1]) |
rot_event2 <= 1; |
|
if (dead_count == 0) begin |
if ( rot_d[2:1] == 2'b01 ) begin |
rot_btn <= 1'b1; |
dead_count <= dead_count - 1; |
end |
if (rot[0]) |
rot_left2 <= 1; |
end else |
dead_count <= dead_count - 1; |
counter <= counter - 1; |
end |
end |
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endmodule |
/trunk/rtl/dpram.v
1,3 → 1,4
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//---------------------------------------------------------------------------- |
// Wishbone DDR Controller |
// |