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Rev 201 → Rev 202

/aemb/trunk/rtl/verilog/aeMB2_exec.v
32,6 → 32,7
module aeMB2_exec (/*AUTOARG*/
// Outputs
sfr_mx, mul_mx, msr_ex, mem_ex, bsf_mx, bpc_ex, alu_mx, alu_ex,
exc_ill,
// Inputs
rd_of, ra_of, opd_of, opc_of, opb_of, opa_of, imm_of, grst, gpha,
gclk, dena
41,7 → 42,7
parameter AEMB_MUL = 1;
parameter AEMB_BSF = 1;
parameter AEMB_HTX = 1;
 
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] alu_ex; // From intu0 of aeMB2_intu.v
69,6 → 70,27
// End of automatics
/*AUTOWIRE*/
 
output exc_ill;
 
reg exc_ill; // illegal instruction exception
 
//TODO: OPTIMISE!
wire wILL =
//(opc_of == 6'o23) | (opc_of == 6'o24) | (opc_of == 6'o25) | (opc_of == 6'o26) | opc_of == 6'o27) |
//(opc_of == 6'o32) | (opc_of == 6'o34) | (opc_of == 6'o35) | (opc_of == 6'o36) | opc_of == 6'o37) |
(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
exc_ill <= 1'h0;
// End of automatics
end else if (dena) begin
exc_ill <= #1 wILL;
end
aeMB2_bsft
#(/*AUTOINSTPARAM*/
// Parameters
85,7 → 107,7
.gclk (gclk),
.grst (grst),
.dena (dena),
.gpha (gpha));
.gpha (gpha));
aeMB2_mult
#(/*AUTOINSTPARAM*/
102,7 → 124,7
.gclk (gclk),
.grst (grst),
.dena (dena),
.gpha (gpha));
.gpha (gpha));
 
aeMB2_intu
#(/*AUTOINSTPARAM*/
130,18 → 152,6
.gclk (gclk),
.grst (grst),
.dena (dena),
.gpha (gpha));
.gpha (gpha));
endmodule // aeMB2_exec
 
/*
$Log: not supported by cvs2svn $
Revision 1.3 2008/04/26 01:11:30 sybreon
Fixed minor typos.
 
Revision 1.2 2008/04/26 01:09:06 sybreon
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
Revision 1.1 2008/04/18 00:21:52 sybreon
Initial import.
*/
/aemb/trunk/rtl/verilog/aeMB2_dwbif.v
30,10 → 30,10
module aeMB2_dwbif (/*AUTOARG*/
// Outputs
dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
dwb_dat_o, dwb_fb, sel_mx, dwb_mx,
dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
// Inputs
dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of,
msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
dwb_dat_i, dwb_ack_i, dwb_err_i, imm_of, opd_of, opc_of, opa_of,
opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
);
parameter AEMB_DWB = 32; ///< data bus address width
 
47,6 → 47,7
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
input dwb_ack_i;
input dwb_err_i; // for bus error exception
// INTERNAL
output dwb_fb;
60,7 → 61,10
input [7:0] msr_ex;
input [AEMB_DWB-1:2] mem_ex;
input [7:5] sfr_mx;
// EXC signals
output [1:0] exc_dwb; // 1: unaligned; 0: bus error
// SYS signals
input gclk,
grst,
68,25 → 72,20
gpha;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg dwb_cyc_o;
reg [31:0] dwb_dat_o;
reg [31:0] dwb_mx;
reg [3:0] dwb_sel_o;
reg dwb_stb_o;
reg dwb_wre_o;
reg [3:0] sel_mx;
// End of automatics
reg [3:0] dwb_sel_o;
reg dwb_stb_o, dwb_cyc_o, dwb_wre_o;
reg [31:0] dwb_dat_o;
reg [3:0] sel_mx;
reg [31:0] dwb_mx;
reg dwb_exc;
wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
wire [3:0] wSEL = {opc_of[1:0], wOFF};
wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
// ENABLE FEEDBACK
assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i);
 
// DATA bus
assign dwb_adr_o = mem_ex; // passthru
 
assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i); // feedback
assign dwb_adr_o = mem_ex; // data-bus passthru
assign exc_dwb = {dwb_exc, dwb_err_i}; // exception signal
// STORE SIZER
// TODO: Move the right words to the right place
// TODO: Make this work with dwb_mx to for partial word loads.
115,6 → 114,7
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_exc <= 1'h0;
dwb_mx <= 32'h0;
dwb_sel_o <= 4'h0;
dwb_wre_o <= 1'h0;
151,9 → 151,17
// TODO: ILLEGAL
default: dwb_sel_o <= #1 4'hX;
endcase // case (wSEL)
 
// exception checking
case (opc_of[1:0])
2'o2: dwb_exc <= #1 |wOFF[1:0];
2'o1: dwb_exc <= #1 wOFF[0];
default: dwb_exc <= #1 1'b0;
endcase // case (opc_of[1:0])
end // if (dena)
 
// Independent on pipeline
// Independent of pipeline
always @(posedge gclk)
if (grst) begin
161,7 → 169,7
// Beginning of autoreset for uninitialized flops
dwb_lat <= 32'h0;
// End of automatics
end else if (dwb_ack_i) begin
end else if (dwb_ack_i) begin // if (grst)
// LATCH READS
dwb_lat <= #1 dwb_dat_i;
end
174,7 → 182,7
dwb_stb_o <= 1'h0;
// End of automatics
//end else if (dwb_fb) begin
end else if (dwb_fb) begin
end else if (dwb_fb) begin // if (grst)
dwb_stb_o <= #1
(dena) ? &opc_of[5:4] : // LXX/SSS
(dwb_stb_o & !dwb_ack_i); // LXX/SSS
185,25 → 193,4
 
assign dwb_tag_o = msr_ex[7]; // MSR_DCE
endmodule // aeMB2_dwbif
 
/*
$Log: not supported by cvs2svn $
Revision 1.6 2008/04/26 17:57:43 sybreon
Minor performance improvements.
 
Revision 1.5 2008/04/26 01:09:05 sybreon
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
Revision 1.4 2008/04/23 14:18:52 sybreon
Fixed pipelined latching of data bug.
 
Revision 1.3 2008/04/21 12:11:38 sybreon
Passes arithmetic tests with single thread.
 
Revision 1.2 2008/04/20 16:34:32 sybreon
Basic version with some features left out.
 
Revision 1.1 2008/04/18 00:21:52 sybreon
Initial import.
*/
endmodule // unmatched end(function|task|module|primitive|interface|package|class|clocking)
/aemb/trunk/rtl/verilog/aeMB2_iwbif.v
31,10 → 31,10
module aeMB2_iwbif (/*AUTOARG*/
// Outputs
iwb_adr_o, iwb_stb_o, iwb_sel_o, iwb_wre_o, iwb_cyc_o, iwb_tag_o,
ich_adr, fet_fb, rpc_if, rpc_mx,
ich_adr, fet_fb, rpc_if, rpc_mx, exc_iwb,
// Inputs
iwb_ack_i, iwb_dat_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd, bra_ex,
bpc_ex, gclk, grst, dena, iena, gpha
iwb_ack_i, iwb_dat_i, iwb_err_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd,
bra_ex, bpc_ex, gclk, grst, dena, iena, gpha
);
parameter AEMB_IWB = 32;
parameter AEMB_HTX = 1;
48,6 → 48,7
output iwb_tag_o;
input iwb_ack_i;
input [31:0] iwb_dat_i;
input iwb_err_i; // bus error exception
// Cache
output [AEMB_IWB-1:2] ich_adr;
65,6 → 66,8
input [1:0] bra_ex;
input [31:2] bpc_ex;
 
output exc_iwb;
// SYS signals
input gclk,
152,20 → 155,8
assign iwb_tag_o = msr_ex[5];
assign fet_fb = iwb_stb_o ~^ iwb_ack_i; // no WB cycle
 
assign exc_iwb = iwb_err_i; // exception pass-thru
endmodule // aeMB2_iwbif
 
/*
$Log: not supported by cvs2svn $
Revision 1.4 2008/04/26 01:09:06 sybreon
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
Revision 1.3 2008/04/21 12:11:38 sybreon
Passes arithmetic tests with single thread.
 
Revision 1.2 2008/04/20 16:34:32 sybreon
Basic version with some features left out.
 
Revision 1.1 2008/04/18 00:21:52 sybreon
Initial import.
*/

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