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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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    from Rev 202 to Rev 203
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Rev 202 → Rev 203

/open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd
80,8 → 80,7
 
signal RX_LatchEn_SR : std_logic_vector(Clock_Offset downto 0) := (others => '0');
alias RX_LatchEn_M is RX_LatchEn_SR(Clock_Offset);
 
signal RX_LatchEn_S : std_logic;
alias RX_LatchEn_S is BClk_RE;
signal RX_LatchEn : std_logic;
 
signal RX_Serial_SR : std_logic_vector(1 downto 0) := (others => '0');
123,10 → 122,8
Input_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
RX_LatchEn_S <= '0';
RX_Serial_SR <= (others => '0');
elsif( rising_edge(Clock) )then
RX_LatchEn_S <= BClk_RE;
RX_Serial_SR <= RX_Serial_SR(0) & Serial_In;
end if;
end process;

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