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- from Rev 202 to Rev 203
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Rev 202 → Rev 203
/trunk/or1200/rtl/verilog/pic.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module pic( |
177,13 → 182,13
case (spr_addr[`PICOFS_BITS]) // synopsys full_case parallel_case |
`ifdef PIC_READREGS |
`PIC_OFS_PICMR: begin |
spr_dat_o[`PIC_INTS-1:2] <= {picmr, 2'b0}; |
spr_dat_o[`PIC_INTS-1:0] <= {picmr, 2'b0}; |
`ifdef PIC_UNUSED_ZERO |
spr_dat_o[31:`PIC_INTS] <= 32-`PIC_INTS'b0; |
`endif |
end |
`PIC_OFS_PICPR: begin |
spr_dat_o[`PIC_INTS-1:2] <= {picpr, 2'b0}; |
spr_dat_o[`PIC_INTS-1:0] <= {picpr, 2'b0}; |
`ifdef PIC_UNUSED_ZERO |
spr_dat_o[31:`PIC_INTS] <= 32-`PIC_INTS'b0; |
`endif |
/trunk/or1200/rtl/verilog/pm.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module pm( |
/trunk/or1200/rtl/verilog/frz_logic.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
`define NO_FREEZE 3'd0 |
66,7 → 71,7
clk, rst, |
|
// Internal i/f |
multicycle, except_flushpipe, lsu_stall, ic_stall, branch_stall, pipeline_freeze |
multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch, pipeline_freeze |
); |
|
// |
77,8 → 82,10
input [`MULTICYCLE_WIDTH-1:0] multicycle; |
input except_flushpipe; |
input lsu_stall; |
input ic_stall; |
input if_stall; |
input dclsu_unstall; |
input branch_stall; |
input force_dslot_fetch; |
output pipeline_freeze; |
|
// |
93,7 → 100,7
// |
// Pipeline freeze |
// |
assign pipeline_freeze = (lsu_stall | (ic_stall) | multicycle_freeze) & ~except_flushpipe; |
assign pipeline_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe; |
|
// |
// Freeze FSM1 |
147,7 → 154,7
state2 <= #1 `WAIT_LSU_TO_FINISH; |
multicycle_freeze <= #1 1'b0; |
end |
else if (ic_stall) begin |
else if (if_stall) begin |
state2 <= #1 `NO_FREEZE; |
done_once <= #1 1'b1; |
multicycle_freeze <= #1 1'b0; |
/trunk/or1200/rtl/verilog/generic_tpram_32x32.v
61,12 → 61,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_tpram_32x32( |
// Generic synchronous two-port RAM interface |
112,7 → 118,7
// |
// Artisan Synchronous Double-Port RAM (ra2sh) |
// |
art_hsdp_32x32 #(dw, 2<<aw, aw) artisan_sdp( |
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp( |
.qa(do_a), |
.clka(clk_a), |
.cena(~ce_a), |
198,7 → 204,7
.DIA(di_a[15:0]), |
.ENA(ce_a), |
.WEA(we_a), |
.DOA(do_a[15:0]) |
.DOA(do_a[15:0]), |
|
.CLKB(clk_), |
.RSTB(rst_b), |
219,7 → 225,7
.DIA(di_a[31:16]), |
.ENA(ce_a), |
.WEA(we_a), |
.DOA(do_a[31:16]) |
.DOA(do_a[31:16]), |
|
.CLKB(clk_), |
.RSTB(rst_b), |
239,7 → 245,7
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg_a; // RAM data output register |
reg [dw-1:0] do_reg_b; // RAM data output register |
|
/trunk/or1200/rtl/verilog/cfgr.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module cfgr( |
81,89 → 86,94
`endif |
case(spr_addr[3:0]) |
`SPRGRP_SYS_VR: begin |
spr_dat_o[`VR_REV_BITS] <= `VR_REV; |
spr_dat_o[`VR_RES1_BITS] <= `VR_RES1; |
spr_dat_o[`VR_CFG_BITS] <= `VR_CFG; |
spr_dat_o[`VR_VER_BITS] <= `VR_VER; |
spr_dat_o[`VR_REV_BITS] = `VR_REV; |
spr_dat_o[`VR_RES1_BITS] = `VR_RES1; |
spr_dat_o[`VR_CFG_BITS] = `VR_CFG; |
spr_dat_o[`VR_VER_BITS] = `VR_VER; |
end |
`SPRGRP_SYS_UPR: begin |
spr_dat_o[`UPR_UP_BITS] <= `UPR_UP; |
spr_dat_o[`UPR_DCP_BITS] <= `UPR_DCP; |
spr_dat_o[`UPR_ICP_BITS] <= `UPR_ICP; |
spr_dat_o[`UPR_DMP_BITS] <= `UPR_DMP; |
spr_dat_o[`UPR_IMP_BITS] <= `UPR_IMP; |
spr_dat_o[`UPR_MP_BITS] <= `UPR_MP; |
spr_dat_o[`UPR_DUP_BITS] <= `UPR_DUP; |
spr_dat_o[`UPR_PCUP_BITS] <= `UPR_PCUP; |
spr_dat_o[`UPR_PMP_BITS] <= `UPR_PMP; |
spr_dat_o[`UPR_PICP_BITS] <= `UPR_PICP; |
spr_dat_o[`UPR_TTP_BITS] <= `UPR_TTP; |
spr_dat_o[`UPR_RES1_BITS] <= `UPR_RES1; |
spr_dat_o[`UPR_CUP_BITS] <= `UPR_CUP; |
spr_dat_o[`UPR_UP_BITS] = `UPR_UP; |
spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP; |
spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP; |
spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP; |
spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP; |
spr_dat_o[`UPR_MP_BITS] = `UPR_MP; |
spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP; |
spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP; |
spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP; |
spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP; |
spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP; |
spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1; |
spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP; |
end |
`SPRGRP_SYS_CPUCFGR: begin |
spr_dat_o[`CPUCFGR_NSGF_BITS] <= `CPUCFGR_NSGF; |
spr_dat_o[`CPUCFGR_HGF_BITS] <= `CPUCFGR_HGF; |
spr_dat_o[`CPUCFGR_OB32S_BITS] <= `CPUCFGR_OB32S; |
spr_dat_o[`CPUCFGR_OB64S_BITS] <= `CPUCFGR_OB64S; |
spr_dat_o[`CPUCFGR_OF32S_BITS] <= `CPUCFGR_OF32S; |
spr_dat_o[`CPUCFGR_OF64S_BITS] <= `CPUCFGR_OF64S; |
spr_dat_o[`CPUCFGR_OV64S_BITS] <= `CPUCFGR_OV64S; |
spr_dat_o[`CPUCFGR_RES1_BITS] <= `CPUCFGR_RES1; |
spr_dat_o[`CPUCFGR_NSGF_BITS] = `CPUCFGR_NSGF; |
spr_dat_o[`CPUCFGR_HGF_BITS] = `CPUCFGR_HGF; |
spr_dat_o[`CPUCFGR_OB32S_BITS] = `CPUCFGR_OB32S; |
spr_dat_o[`CPUCFGR_OB64S_BITS] = `CPUCFGR_OB64S; |
spr_dat_o[`CPUCFGR_OF32S_BITS] = `CPUCFGR_OF32S; |
spr_dat_o[`CPUCFGR_OF64S_BITS] = `CPUCFGR_OF64S; |
spr_dat_o[`CPUCFGR_OV64S_BITS] = `CPUCFGR_OV64S; |
spr_dat_o[`CPUCFGR_RES1_BITS] = `CPUCFGR_RES1; |
end |
`SPRGRP_SYS_DMMUCFGR: begin |
spr_dat_o[`DMMUCFGR_NTW_BITS] <= `DMMUCFGR_NTW; |
spr_dat_o[`DMMUCFGR_NTS_BITS] <= `DMMUCFGR_NTS; |
spr_dat_o[`DMMUCFGR_NAE_BITS] <= `DMMUCFGR_NAE; |
spr_dat_o[`DMMUCFGR_CRI_BITS] <= `DMMUCFGR_CRI; |
spr_dat_o[`DMMUCFGR_PRI_BITS] <= `DMMUCFGR_PRI; |
spr_dat_o[`DMMUCFGR_TEIRI_BITS] <= `DMMUCFGR_TEIRI; |
spr_dat_o[`DMMUCFGR_HTR_BITS] <= `DMMUCFGR_HTR; |
spr_dat_o[`DMMUCFGR_RES1_BITS] <= `DMMUCFGR_RES1; |
spr_dat_o[`DMMUCFGR_NTW_BITS] = `DMMUCFGR_NTW; |
spr_dat_o[`DMMUCFGR_NTS_BITS] = `DMMUCFGR_NTS; |
spr_dat_o[`DMMUCFGR_NAE_BITS] = `DMMUCFGR_NAE; |
spr_dat_o[`DMMUCFGR_CRI_BITS] = `DMMUCFGR_CRI; |
spr_dat_o[`DMMUCFGR_PRI_BITS] = `DMMUCFGR_PRI; |
spr_dat_o[`DMMUCFGR_TEIRI_BITS] = `DMMUCFGR_TEIRI; |
spr_dat_o[`DMMUCFGR_HTR_BITS] = `DMMUCFGR_HTR; |
spr_dat_o[`DMMUCFGR_RES1_BITS] = `DMMUCFGR_RES1; |
end |
`SPRGRP_SYS_IMMUCFGR: begin |
spr_dat_o[`IMMUCFGR_NTW_BITS] <= `IMMUCFGR_NTW; |
spr_dat_o[`IMMUCFGR_NTS_BITS] <= `IMMUCFGR_NTS; |
spr_dat_o[`IMMUCFGR_NAE_BITS] <= `IMMUCFGR_NAE; |
spr_dat_o[`IMMUCFGR_CRI_BITS] <= `IMMUCFGR_CRI; |
spr_dat_o[`IMMUCFGR_PRI_BITS] <= `IMMUCFGR_PRI; |
spr_dat_o[`IMMUCFGR_TEIRI_BITS] <= `IMMUCFGR_TEIRI; |
spr_dat_o[`IMMUCFGR_HTR_BITS] <= `IMMUCFGR_HTR; |
spr_dat_o[`IMMUCFGR_RES1_BITS] <= `IMMUCFGR_RES1; |
spr_dat_o[`IMMUCFGR_NTW_BITS] = `IMMUCFGR_NTW; |
spr_dat_o[`IMMUCFGR_NTS_BITS] = `IMMUCFGR_NTS; |
spr_dat_o[`IMMUCFGR_NAE_BITS] = `IMMUCFGR_NAE; |
spr_dat_o[`IMMUCFGR_CRI_BITS] = `IMMUCFGR_CRI; |
spr_dat_o[`IMMUCFGR_PRI_BITS] = `IMMUCFGR_PRI; |
spr_dat_o[`IMMUCFGR_TEIRI_BITS] = `IMMUCFGR_TEIRI; |
spr_dat_o[`IMMUCFGR_HTR_BITS] = `IMMUCFGR_HTR; |
spr_dat_o[`IMMUCFGR_RES1_BITS] = `IMMUCFGR_RES1; |
end |
`SPRGRP_SYS_DCCFGR: begin |
spr_dat_o[`DCCFGR_NCW_BITS] <= `DCCFGR_NCW; |
spr_dat_o[`DCCFGR_NCS_BITS] <= `DCCFGR_NCS; |
spr_dat_o[`DCCFGR_CBS_BITS] <= `DCCFGR_CBS; |
spr_dat_o[`DCCFGR_CWS_BITS] <= `DCCFGR_CWS; |
spr_dat_o[`DCCFGR_CCRI_BITS] <= `DCCFGR_CCRI; |
spr_dat_o[`DCCFGR_CBIRI_BITS] <= `DCCFGR_CBIRI; |
spr_dat_o[`DCCFGR_CBPRI_BITS] <= `DCCFGR_CBPRI; |
spr_dat_o[`DCCFGR_CBLRI_BITS] <= `DCCFGR_CBLRI; |
spr_dat_o[`DCCFGR_CBFRI_BITS] <= `DCCFGR_CBFRI; |
spr_dat_o[`DCCFGR_CBWBRI_BITS] <= `DCCFGR_CBWBRI; |
spr_dat_o[`DCCFGR_RES1_BITS] <= `DCCFGR_RES1; |
spr_dat_o[`DCCFGR_NCW_BITS] = `DCCFGR_NCW; |
spr_dat_o[`DCCFGR_NCS_BITS] = `DCCFGR_NCS; |
spr_dat_o[`DCCFGR_CBS_BITS] = `DCCFGR_CBS; |
spr_dat_o[`DCCFGR_CWS_BITS] = `DCCFGR_CWS; |
spr_dat_o[`DCCFGR_CCRI_BITS] = `DCCFGR_CCRI; |
spr_dat_o[`DCCFGR_CBIRI_BITS] = `DCCFGR_CBIRI; |
spr_dat_o[`DCCFGR_CBPRI_BITS] = `DCCFGR_CBPRI; |
spr_dat_o[`DCCFGR_CBLRI_BITS] = `DCCFGR_CBLRI; |
spr_dat_o[`DCCFGR_CBFRI_BITS] = `DCCFGR_CBFRI; |
spr_dat_o[`DCCFGR_CBWBRI_BITS] = `DCCFGR_CBWBRI; |
spr_dat_o[`DCCFGR_RES1_BITS] = `DCCFGR_RES1; |
end |
`SPRGRP_SYS_ICCFGR: begin |
spr_dat_o[`ICCFGR_NCW_BITS] <= `ICCFGR_NCW; |
spr_dat_o[`ICCFGR_NCS_BITS] <= `ICCFGR_NCS; |
spr_dat_o[`ICCFGR_CBS_BITS] <= `ICCFGR_CBS; |
spr_dat_o[`ICCFGR_CWS_BITS] <= `ICCFGR_CWS; |
spr_dat_o[`ICCFGR_CCRI_BITS] <= `ICCFGR_CCRI; |
spr_dat_o[`ICCFGR_CBIRI_BITS] <= `ICCFGR_CBIRI; |
spr_dat_o[`ICCFGR_CBPRI_BITS] <= `ICCFGR_CBPRI; |
spr_dat_o[`ICCFGR_CBLRI_BITS] <= `ICCFGR_CBLRI; |
spr_dat_o[`ICCFGR_CBFRI_BITS] <= `ICCFGR_CBFRI; |
spr_dat_o[`ICCFGR_CBWBRI_BITS] <= `ICCFGR_CBWBRI; |
spr_dat_o[`ICCFGR_RES1_BITS] <= `ICCFGR_RES1; |
spr_dat_o[`ICCFGR_NCW_BITS] = `ICCFGR_NCW; |
spr_dat_o[`ICCFGR_NCS_BITS] = `ICCFGR_NCS; |
spr_dat_o[`ICCFGR_CBS_BITS] = `ICCFGR_CBS; |
spr_dat_o[`ICCFGR_CWS_BITS] = `ICCFGR_CWS; |
spr_dat_o[`ICCFGR_CCRI_BITS] = `ICCFGR_CCRI; |
spr_dat_o[`ICCFGR_CBIRI_BITS] = `ICCFGR_CBIRI; |
spr_dat_o[`ICCFGR_CBPRI_BITS] = `ICCFGR_CBPRI; |
spr_dat_o[`ICCFGR_CBLRI_BITS] = `ICCFGR_CBLRI; |
spr_dat_o[`ICCFGR_CBFRI_BITS] = `ICCFGR_CBFRI; |
spr_dat_o[`ICCFGR_CBWBRI_BITS] = `ICCFGR_CBWBRI; |
spr_dat_o[`ICCFGR_RES1_BITS] = `ICCFGR_RES1; |
end |
`SPRGRP_SYS_DCFGR: begin |
spr_dat_o[`DCFGR_NDP_BITS] <= `DCFGR_NDP; |
spr_dat_o[`DCFGR_WPCI_BITS] <= `DCFGR_WPCI; |
spr_dat_o[`DCFGR_RES1_BITS] <= `DCFGR_RES1; |
spr_dat_o[`DCFGR_NDP_BITS] = `DCFGR_NDP; |
spr_dat_o[`DCFGR_WPCI_BITS] = `DCFGR_WPCI; |
spr_dat_o[`DCFGR_RES1_BITS] = `DCFGR_RES1; |
end |
default: spr_dat_o <= 32'b0; |
default: spr_dat_o = 32'h0000_0000; |
endcase |
`ifdef SYS_FULL_DECODE |
else |
spr_dat_o = 32'h0000_0000; |
`endif |
|
`else |
|
// |
176,28 → 186,32
`endif |
case(spr_addr[3:0]) |
`SPRGRP_SYS_VR: begin |
spr_dat_o[`VR_REV_BITS] <= `VR_REV; |
spr_dat_o[`VR_RES1_BITS] <= `VR_RES1; |
spr_dat_o[`VR_CFG_BITS] <= `VR_CFG; |
spr_dat_o[`VR_VER_BITS] <= `VR_VER; |
spr_dat_o[`VR_REV_BITS] = `VR_REV; |
spr_dat_o[`VR_RES1_BITS] = `VR_RES1; |
spr_dat_o[`VR_CFG_BITS] = `VR_CFG; |
spr_dat_o[`VR_VER_BITS] = `VR_VER; |
end |
`SPRGRP_SYS_UPR: begin |
spr_dat_o[`UPR_UP_BITS] <= `UPR_UP; |
spr_dat_o[`UPR_DCP_BITS] <= `UPR_DCP; |
spr_dat_o[`UPR_ICP_BITS] <= `UPR_ICP; |
spr_dat_o[`UPR_DMP_BITS] <= `UPR_DMP; |
spr_dat_o[`UPR_IMP_BITS] <= `UPR_IMP; |
spr_dat_o[`UPR_MP_BITS] <= `UPR_MP; |
spr_dat_o[`UPR_DUP_BITS] <= `UPR_DUP; |
spr_dat_o[`UPR_PCUP_BITS] <= `UPR_PCUP; |
spr_dat_o[`UPR_PMP_BITS] <= `UPR_PMP; |
spr_dat_o[`UPR_PICP_BITS] <= `UPR_PICP; |
spr_dat_o[`UPR_TTP_BITS] <= `UPR_TTP; |
spr_dat_o[`UPR_RES1_BITS] <= `UPR_RES1; |
spr_dat_o[`UPR_CUP_BITS] <= `UPR_CUP; |
spr_dat_o[`UPR_UP_BITS] = `UPR_UP; |
spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP; |
spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP; |
spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP; |
spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP; |
spr_dat_o[`UPR_MP_BITS] = `UPR_MP; |
spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP; |
spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP; |
spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP; |
spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP; |
spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP; |
spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1; |
spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP; |
end |
default: spr_dat_o <= 32'b0; |
default: spr_dat_o = 32'h0000_0000; |
endcase |
`ifdef SYS_FULL_DECODE |
else |
spr_dat_o = 32'h0000_0000; |
`endif |
|
`endif |
|
/trunk/or1200/rtl/verilog/dc_tag.v
44,14 → 44,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
`define NO_UTI |
|
module dc_tag( |
// Clock and reset |
58,7 → 62,7
clk, rst, |
|
// Internal i/f |
addr, we, datain, dataout |
addr, en, we, datain, dataout |
); |
|
parameter dw = 19; |
70,17 → 74,27
input clk; |
input rst; |
input [aw-1:0] addr; |
input en; |
input we; |
input [dw-1:0] datain; |
output [dw-1:0] dataout; |
|
`ifdef OR1200_NO_DC |
|
// |
// Data cache not implemented |
// |
assign dataout = {dw{1'b0}}; |
|
`else |
|
// |
// Instantiation of TAG RAM block |
// |
generic_spram_512x19 dc_tag0( |
.clk(clk), |
.rst(rst), |
.ce(1'b1), |
.ce(en), |
.we(we), |
.oe(1'b1), |
.addr(addr), |
88,4 → 102,6
.do(dataout) |
); |
|
`endif |
|
endmodule |
/trunk/or1200/rtl/verilog/or1200.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.3 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
55,7 → 58,9
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module or1200( |
168,6 → 173,7
// |
// CPU's SPR access to various RISC units (shared wires) |
// |
wire supv; |
wire [aw-1:0] spr_addr; |
wire [dw-1:0] spr_dat_cpu; |
wire [31:0] spr_cs; |
174,9 → 180,23
wire spr_we; |
|
// |
// DMMU and CPU |
// |
wire dmmu_en; |
wire dmmuexcept_miss; |
wire dmmuexcept_fault; |
wire [31:0] spr_dat_dmmu; |
|
// |
// DMMU and DC |
// |
wire [aw-1:0] dcdmmu_paddr; |
|
// |
// DC and CPU's LSU |
// |
wire dclsu_stall; |
wire dclsu_unstall; |
wire [aw-1:0] dclsu_addr; |
wire [aw-1:0] dclsu_from_dc; |
wire [aw-1:0] dclsu_to_dc; |
184,14 → 204,28
wire dc_en; |
|
// |
// IMMU and CPU |
// |
wire immu_en; |
wire immuexcept_miss; |
wire immuexcept_fault; |
wire [31:0] spr_dat_immu; |
|
// |
// IC and CPU's ifetch |
// |
wire icfetch_stall; |
wire [aw-1:0] icfetch_addr; |
wire [dw-1:0] icfetch_dataout; |
wire [`FETCHOP_WIDTH-1:0] icfetch_op; |
wire ic_en; |
|
// |
// IMMU and IC |
// |
wire [aw-1:0] icimmu_paddr; |
|
// |
// Connection between CPU and PIC |
// |
wire [dw-1:0] spr_dat_pic; |
287,6 → 321,36
); |
|
// |
// Instantiation of IMMU |
// |
immu immu( |
// Rst and clk |
.clk(clk), |
.rst(rst), |
|
// Fetch i/f |
.immu_en(immu_en), |
.supv(supv), |
.immufetch_vaddr(icfetch_addr), |
.immufetch_op(icfetch_op), |
.immufetch_stall(), |
|
// Except I/F |
.immuexcept_miss(immuexcept_miss), |
.immuexcept_fault(immuexcept_fault), |
|
// SPR access |
.spr_cs(spr_cs[`SPR_GROUP_IMMU]), |
.spr_write(spr_we), |
.spr_addr(spr_addr), |
.spr_dat_i(spr_dat_cpu), |
.spr_dat_o(spr_dat_immu), |
|
// IC i/f |
.icimmu_paddr(icimmu_paddr) |
); |
|
// |
// Instantiation of Instruction Cache |
// |
ic ic( |
295,8 → 359,8
.clkdiv_by_2(clkdiv_by_2), |
|
// These connect IC to CPU's ifetch |
.icfetch_addr(icfetch_addr), |
.icfetch_op(`FETCHOP_LW), |
.icfetch_addr(icimmu_paddr), |
.icfetch_op(icfetch_op), |
.icfetch_dataout(icfetch_dataout), |
.icfetch_stall(icfetch_stall), |
.ic_en(ic_en), |
319,20 → 383,32
.clk(clk), |
.rst(rst), |
|
// These connect IC and IFETCHER inside CPU |
// Connection IC and IFETCHER inside CPU |
.ic_insn(icfetch_dataout), |
.ic_pcaddr(icfetch_addr), |
.ic_addr(icfetch_addr), |
.ic_stall(icfetch_stall), |
.ic_fetchop(icfetch_op), |
.ic_en(ic_en), |
|
// These connect CPU to external Trace port |
// Connection CPU to external Trace port |
.tp_dir_in(tp_dir_in), |
.tp_sel(tp_sel), |
.tp_in(tp_in), |
.tp_out(tp_out), |
|
// These connect DC and CPU's LSU |
// Connection IMMU and CPU internally |
.immu_en(immu_en), |
.immuexcept_miss(immuexcept_miss), |
.immuexcept_fault(immuexcept_fault), |
|
// Connection DMMU and CPU internally |
.dmmu_en(dmmu_en), |
.dmmuexcept_miss(dmmuexcept_miss), |
.dmmuexcept_fault(dmmuexcept_fault), |
|
// Connection DC and CPU's LSU |
.dclsu_stall(dclsu_stall), |
.dclsu_unstall(dclsu_unstall), |
.dclsu_addr(dclsu_addr), |
.dclsu_datain(dclsu_from_dc), |
.dclsu_dataout(dclsu_to_dc), |
339,16 → 415,18
.dclsu_lsuop(dclsu_lsuop), |
.dc_en(dc_en), |
|
// These connect PIC and CPU's EXCEPT |
// Connection PIC and CPU's EXCEPT |
.int_high(int_high_tt), |
.int_low(int_low), |
|
// SPRs |
.supv(supv), |
.spr_addr(spr_addr), |
.spr_dataout(spr_dat_cpu), |
.spr_dat_pic(spr_dat_pic), |
.spr_dat_tt(spr_dat_tt), |
.spr_dat_pm(spr_dat_pm), |
.spr_dat_dmmu(spr_dat_dmmu), |
.spr_cs(spr_cs), |
.spr_we(spr_we), |
|
358,6 → 436,36
); |
|
// |
// Instantiation of DMMU |
// |
dmmu dmmu( |
// Rst and clk |
.clk(clk), |
.rst(rst), |
|
// LSU i/f |
.dmmu_en(dmmu_en), |
.supv(supv), |
.dmmulsu_vaddr(dclsu_addr), |
.dmmulsu_lsuop(dclsu_lsuop), |
.dmmulsu_stall(), |
|
// Except I/F |
.dmmuexcept_miss(dmmuexcept_miss), |
.dmmuexcept_fault(dmmuexcept_fault), |
|
// SPR access |
.spr_cs(spr_cs[`SPR_GROUP_DMMU]), |
.spr_write(spr_we), |
.spr_addr(spr_addr), |
.spr_dat_i(spr_dat_cpu), |
.spr_dat_o(spr_dat_dmmu), |
|
// DC i/f |
.dcdmmu_paddr(dcdmmu_paddr) |
); |
|
// |
// Instantiation of Data Cache |
// |
dc dc( |
366,11 → 474,12
.clkdiv_by_2(clkdiv_by_2), |
|
// These connect DC to CPU's LSU |
.dclsu_addr(dclsu_addr), |
.dclsu_addr(dcdmmu_paddr), |
.dclsu_lsuop(dclsu_lsuop), |
.dclsu_datain(dclsu_to_dc), |
.dclsu_dataout(dclsu_from_dc), |
.dclsu_stall(dclsu_stall), |
.dclsu_unstall(dclsu_unstall), |
.dc_en(dc_en), |
|
// These connect DC to BIU |
/trunk/or1200/rtl/verilog/multp2_32x32.v
44,159 → 44,20
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// 32x32 multiplier, no input/output registers |
// Registers inside Wallace trees every 8 full adder levels, |
// with first pipeline after level 4 |
|
module multp2_32x32 ( X, Y, CLK, P ); |
input [31:0] X; |
input [31:0] Y; |
input CLK; |
output [63:0] P; |
wire [0:32] A; |
wire [0:31] B; |
wire [0:63] Q; |
MULTIPLIER_33_32 U1 (A , B , CLK , CLK , Q ); |
assign A[0] = X[0]; |
assign A[1] = X[1]; |
assign A[2] = X[2]; |
assign A[3] = X[3]; |
assign A[4] = X[4]; |
assign A[5] = X[5]; |
assign A[6] = X[6]; |
assign A[7] = X[7]; |
assign A[8] = X[8]; |
assign A[9] = X[9]; |
assign A[10] = X[10]; |
assign A[11] = X[11]; |
assign A[12] = X[12]; |
assign A[13] = X[13]; |
assign A[14] = X[14]; |
assign A[15] = X[15]; |
assign A[16] = X[16]; |
assign A[17] = X[17]; |
assign A[18] = X[18]; |
assign A[19] = X[19]; |
assign A[20] = X[20]; |
assign A[21] = X[21]; |
assign A[22] = X[22]; |
assign A[23] = X[23]; |
assign A[24] = X[24]; |
assign A[25] = X[25]; |
assign A[26] = X[26]; |
assign A[27] = X[27]; |
assign A[28] = X[28]; |
assign A[29] = X[29]; |
assign A[30] = X[30]; |
assign A[31] = X[31]; |
assign A[32] = X[31]; |
assign B[0] = Y[0]; |
assign B[1] = Y[1]; |
assign B[2] = Y[2]; |
assign B[3] = Y[3]; |
assign B[4] = Y[4]; |
assign B[5] = Y[5]; |
assign B[6] = Y[6]; |
assign B[7] = Y[7]; |
assign B[8] = Y[8]; |
assign B[9] = Y[9]; |
assign B[10] = Y[10]; |
assign B[11] = Y[11]; |
assign B[12] = Y[12]; |
assign B[13] = Y[13]; |
assign B[14] = Y[14]; |
assign B[15] = Y[15]; |
assign B[16] = Y[16]; |
assign B[17] = Y[17]; |
assign B[18] = Y[18]; |
assign B[19] = Y[19]; |
assign B[20] = Y[20]; |
assign B[21] = Y[21]; |
assign B[22] = Y[22]; |
assign B[23] = Y[23]; |
assign B[24] = Y[24]; |
assign B[25] = Y[25]; |
assign B[26] = Y[26]; |
assign B[27] = Y[27]; |
assign B[28] = Y[28]; |
assign B[29] = Y[29]; |
assign B[30] = Y[30]; |
assign B[31] = Y[31]; |
assign P[0] = Q[0]; |
assign P[1] = Q[1]; |
assign P[2] = Q[2]; |
assign P[3] = Q[3]; |
assign P[4] = Q[4]; |
assign P[5] = Q[5]; |
assign P[6] = Q[6]; |
assign P[7] = Q[7]; |
assign P[8] = Q[8]; |
assign P[9] = Q[9]; |
assign P[10] = Q[10]; |
assign P[11] = Q[11]; |
assign P[12] = Q[12]; |
assign P[13] = Q[13]; |
assign P[14] = Q[14]; |
assign P[15] = Q[15]; |
assign P[16] = Q[16]; |
assign P[17] = Q[17]; |
assign P[18] = Q[18]; |
assign P[19] = Q[19]; |
assign P[20] = Q[20]; |
assign P[21] = Q[21]; |
assign P[22] = Q[22]; |
assign P[23] = Q[23]; |
assign P[24] = Q[24]; |
assign P[25] = Q[25]; |
assign P[26] = Q[26]; |
assign P[27] = Q[27]; |
assign P[28] = Q[28]; |
assign P[29] = Q[29]; |
assign P[30] = Q[30]; |
assign P[31] = Q[31]; |
assign P[32] = Q[32]; |
assign P[33] = Q[33]; |
assign P[34] = Q[34]; |
assign P[35] = Q[35]; |
assign P[36] = Q[36]; |
assign P[37] = Q[37]; |
assign P[38] = Q[38]; |
assign P[39] = Q[39]; |
assign P[40] = Q[40]; |
assign P[41] = Q[41]; |
assign P[42] = Q[42]; |
assign P[43] = Q[43]; |
assign P[44] = Q[44]; |
assign P[45] = Q[45]; |
assign P[46] = Q[46]; |
assign P[47] = Q[47]; |
assign P[48] = Q[48]; |
assign P[49] = Q[49]; |
assign P[50] = Q[50]; |
assign P[51] = Q[51]; |
assign P[52] = Q[52]; |
assign P[53] = Q[53]; |
assign P[54] = Q[54]; |
assign P[55] = Q[55]; |
assign P[56] = Q[56]; |
assign P[57] = Q[57]; |
assign P[58] = Q[58]; |
assign P[59] = Q[59]; |
assign P[60] = Q[60]; |
assign P[61] = Q[61]; |
assign P[62] = Q[62]; |
assign P[63] = Q[63]; |
endmodule |
|
|
module PP_LOW ( ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT ); |
input ONEPOS; |
input ONENEG; |
918,20 → 779,25
endmodule |
|
|
module FLIPFLOP ( DIN, CLK, DOUT ); |
module FLIPFLOP ( DIN, RST, CLK, DOUT ); |
input DIN; |
input RST; |
input CLK; |
output DOUT; |
reg DOUT_reg; |
always @ ( posedge CLK ) begin |
DOUT_reg = DIN; |
always @ ( posedge RST or posedge CLK ) begin |
if (RST) |
DOUT_reg <= DIN; |
else |
DOUT_reg <= #1 DIN; |
end |
assign DOUT = DOUT_reg; |
endmodule |
|
|
module WALLACE_33_32 ( SUMMAND, CLK, CARRY, SUM ); |
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM ); |
input [0:575] SUMMAND; |
input RST; |
input CLK; |
output [0:62] CARRY; |
output [0:63] SUM; |
939,51 → 805,51
wire [0:523] INT_CARRY; |
wire [0:669] INT_SUM; |
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SAVE (INT_SUM[0]) , .CARRY (INT_CARRY[0]) ); |
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .CLK (CLK) , .DOUT (SUM[0]) ); |
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .CLK (CLK) , .DOUT (CARRY[0]) ); |
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[0]) ); |
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[0]) ); |
assign INT_SUM[1] = SUMMAND[2]; |
assign CARRY[1] = 0; |
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .CLK (CLK) , .DOUT (SUM[1]) ); |
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[1]) ); |
FULL_ADDER FA_0 (.DATA_A (SUMMAND[3]) , .DATA_B (SUMMAND[4]) , .DATA_C (SUMMAND[5]) , .SAVE (INT_SUM[2]) , .CARRY (INT_CARRY[1]) ); |
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .CLK (CLK) , .DOUT (SUM[2]) ); |
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .CLK (CLK) , .DOUT (CARRY[2]) ); |
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[2]) ); |
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[2]) ); |
HALF_ADDER HA_1 (.DATA_A (SUMMAND[6]) , .DATA_B (SUMMAND[7]) , .SAVE (INT_SUM[3]) , .CARRY (INT_CARRY[2]) ); |
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .CLK (CLK) , .DOUT (SUM[3]) ); |
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .CLK (CLK) , .DOUT (CARRY[3]) ); |
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[3]) ); |
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[3]) ); |
FULL_ADDER FA_1 (.DATA_A (SUMMAND[8]) , .DATA_B (SUMMAND[9]) , .DATA_C (SUMMAND[10]) , .SAVE (INT_SUM[4]) , .CARRY (INT_CARRY[4]) ); |
assign INT_SUM[5] = SUMMAND[11]; |
HALF_ADDER HA_2 (.DATA_A (INT_SUM[4]) , .DATA_B (INT_SUM[5]) , .SAVE (INT_SUM[6]) , .CARRY (INT_CARRY[3]) ); |
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .CLK (CLK) , .DOUT (SUM[4]) ); |
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .CLK (CLK) , .DOUT (CARRY[4]) ); |
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[4]) ); |
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[4]) ); |
FULL_ADDER FA_2 (.DATA_A (SUMMAND[12]) , .DATA_B (SUMMAND[13]) , .DATA_C (SUMMAND[14]) , .SAVE (INT_SUM[7]) , .CARRY (INT_CARRY[6]) ); |
HALF_ADDER HA_3 (.DATA_A (INT_SUM[7]) , .DATA_B (INT_CARRY[4]) , .SAVE (INT_SUM[8]) , .CARRY (INT_CARRY[5]) ); |
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .CLK (CLK) , .DOUT (SUM[5]) ); |
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .CLK (CLK) , .DOUT (CARRY[5]) ); |
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[5]) ); |
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[5]) ); |
FULL_ADDER FA_3 (.DATA_A (SUMMAND[15]) , .DATA_B (SUMMAND[16]) , .DATA_C (SUMMAND[17]) , .SAVE (INT_SUM[9]) , .CARRY (INT_CARRY[8]) ); |
HALF_ADDER HA_4 (.DATA_A (SUMMAND[18]) , .DATA_B (SUMMAND[19]) , .SAVE (INT_SUM[10]) , .CARRY (INT_CARRY[9]) ); |
FULL_ADDER FA_4 (.DATA_A (INT_SUM[9]) , .DATA_B (INT_SUM[10]) , .DATA_C (INT_CARRY[6]) , .SAVE (INT_SUM[11]) , .CARRY (INT_CARRY[7]) ); |
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .CLK (CLK) , .DOUT (SUM[6]) ); |
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .CLK (CLK) , .DOUT (CARRY[6]) ); |
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[6]) ); |
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[6]) ); |
FULL_ADDER FA_5 (.DATA_A (SUMMAND[20]) , .DATA_B (SUMMAND[21]) , .DATA_C (SUMMAND[22]) , .SAVE (INT_SUM[12]) , .CARRY (INT_CARRY[11]) ); |
assign INT_SUM[13] = SUMMAND[23]; |
FULL_ADDER FA_6 (.DATA_A (INT_SUM[12]) , .DATA_B (INT_SUM[13]) , .DATA_C (INT_CARRY[8]) , .SAVE (INT_SUM[14]) , .CARRY (INT_CARRY[12]) ); |
assign INT_SUM[15] = INT_CARRY[9]; |
HALF_ADDER HA_5 (.DATA_A (INT_SUM[14]) , .DATA_B (INT_SUM[15]) , .SAVE (INT_SUM[16]) , .CARRY (INT_CARRY[10]) ); |
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .CLK (CLK) , .DOUT (SUM[7]) ); |
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .CLK (CLK) , .DOUT (CARRY[7]) ); |
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[7]) ); |
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[7]) ); |
FULL_ADDER FA_7 (.DATA_A (SUMMAND[24]) , .DATA_B (SUMMAND[25]) , .DATA_C (SUMMAND[26]) , .SAVE (INT_SUM[17]) , .CARRY (INT_CARRY[14]) ); |
FULL_ADDER FA_8 (.DATA_A (SUMMAND[27]) , .DATA_B (SUMMAND[28]) , .DATA_C (SUMMAND[29]) , .SAVE (INT_SUM[18]) , .CARRY (INT_CARRY[15]) ); |
FULL_ADDER FA_9 (.DATA_A (INT_SUM[17]) , .DATA_B (INT_SUM[18]) , .DATA_C (INT_CARRY[11]) , .SAVE (INT_SUM[19]) , .CARRY (INT_CARRY[16]) ); |
HALF_ADDER HA_6 (.DATA_A (INT_SUM[19]) , .DATA_B (INT_CARRY[12]) , .SAVE (INT_SUM[20]) , .CARRY (INT_CARRY[13]) ); |
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .CLK (CLK) , .DOUT (SUM[8]) ); |
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .CLK (CLK) , .DOUT (CARRY[8]) ); |
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[8]) ); |
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[8]) ); |
FULL_ADDER FA_10 (.DATA_A (SUMMAND[30]) , .DATA_B (SUMMAND[31]) , .DATA_C (SUMMAND[32]) , .SAVE (INT_SUM[21]) , .CARRY (INT_CARRY[18]) ); |
HALF_ADDER HA_7 (.DATA_A (SUMMAND[33]) , .DATA_B (SUMMAND[34]) , .SAVE (INT_SUM[22]) , .CARRY (INT_CARRY[19]) ); |
FULL_ADDER FA_11 (.DATA_A (INT_SUM[21]) , .DATA_B (INT_SUM[22]) , .DATA_C (INT_CARRY[14]) , .SAVE (INT_SUM[23]) , .CARRY (INT_CARRY[20]) ); |
assign INT_SUM[24] = INT_CARRY[15]; |
FULL_ADDER FA_12 (.DATA_A (INT_SUM[23]) , .DATA_B (INT_SUM[24]) , .DATA_C (INT_CARRY[16]) , .SAVE (INT_SUM[25]) , .CARRY (INT_CARRY[17]) ); |
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .CLK (CLK) , .DOUT (SUM[9]) ); |
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .CLK (CLK) , .DOUT (CARRY[9]) ); |
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[9]) ); |
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[9]) ); |
FULL_ADDER FA_13 (.DATA_A (SUMMAND[35]) , .DATA_B (SUMMAND[36]) , .DATA_C (SUMMAND[37]) , .SAVE (INT_SUM[26]) , .CARRY (INT_CARRY[22]) ); |
FULL_ADDER FA_14 (.DATA_A (SUMMAND[38]) , .DATA_B (SUMMAND[39]) , .DATA_C (SUMMAND[40]) , .SAVE (INT_SUM[27]) , .CARRY (INT_CARRY[23]) ); |
assign INT_SUM[28] = SUMMAND[41]; |
990,8 → 856,8
FULL_ADDER FA_15 (.DATA_A (INT_SUM[26]) , .DATA_B (INT_SUM[27]) , .DATA_C (INT_SUM[28]) , .SAVE (INT_SUM[29]) , .CARRY (INT_CARRY[24]) ); |
HALF_ADDER HA_8 (.DATA_A (INT_CARRY[18]) , .DATA_B (INT_CARRY[19]) , .SAVE (INT_SUM[30]) , .CARRY (INT_CARRY[25]) ); |
FULL_ADDER FA_16 (.DATA_A (INT_SUM[29]) , .DATA_B (INT_SUM[30]) , .DATA_C (INT_CARRY[20]) , .SAVE (INT_SUM[31]) , .CARRY (INT_CARRY[21]) ); |
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .CLK (CLK) , .DOUT (SUM[10]) ); |
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .CLK (CLK) , .DOUT (CARRY[10]) ); |
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[10]) ); |
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[10]) ); |
FULL_ADDER FA_17 (.DATA_A (SUMMAND[42]) , .DATA_B (SUMMAND[43]) , .DATA_C (SUMMAND[44]) , .SAVE (INT_SUM[32]) , .CARRY (INT_CARRY[27]) ); |
FULL_ADDER FA_18 (.DATA_A (SUMMAND[45]) , .DATA_B (SUMMAND[46]) , .DATA_C (SUMMAND[47]) , .SAVE (INT_SUM[33]) , .CARRY (INT_CARRY[28]) ); |
FULL_ADDER FA_19 (.DATA_A (INT_SUM[32]) , .DATA_B (INT_SUM[33]) , .DATA_C (INT_CARRY[22]) , .SAVE (INT_SUM[34]) , .CARRY (INT_CARRY[29]) ); |
999,8 → 865,8
FULL_ADDER FA_20 (.DATA_A (INT_SUM[34]) , .DATA_B (INT_SUM[35]) , .DATA_C (INT_CARRY[24]) , .SAVE (INT_SUM[36]) , .CARRY (INT_CARRY[30]) ); |
assign INT_SUM[37] = INT_CARRY[25]; |
HALF_ADDER HA_9 (.DATA_A (INT_SUM[36]) , .DATA_B (INT_SUM[37]) , .SAVE (INT_SUM[38]) , .CARRY (INT_CARRY[26]) ); |
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .CLK (CLK) , .DOUT (SUM[11]) ); |
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .CLK (CLK) , .DOUT (CARRY[11]) ); |
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[11]) ); |
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[11]) ); |
FULL_ADDER FA_21 (.DATA_A (SUMMAND[48]) , .DATA_B (SUMMAND[49]) , .DATA_C (SUMMAND[50]) , .SAVE (INT_SUM[39]) , .CARRY (INT_CARRY[32]) ); |
FULL_ADDER FA_22 (.DATA_A (SUMMAND[51]) , .DATA_B (SUMMAND[52]) , .DATA_C (SUMMAND[53]) , .SAVE (INT_SUM[40]) , .CARRY (INT_CARRY[33]) ); |
assign INT_SUM[41] = SUMMAND[54]; |
1009,8 → 875,8
FULL_ADDER FA_24 (.DATA_A (INT_SUM[42]) , .DATA_B (INT_CARRY[27]) , .DATA_C (INT_CARRY[28]) , .SAVE (INT_SUM[44]) , .CARRY (INT_CARRY[35]) ); |
FULL_ADDER FA_25 (.DATA_A (INT_SUM[43]) , .DATA_B (INT_SUM[44]) , .DATA_C (INT_CARRY[29]) , .SAVE (INT_SUM[45]) , .CARRY (INT_CARRY[36]) ); |
HALF_ADDER HA_10 (.DATA_A (INT_SUM[45]) , .DATA_B (INT_CARRY[30]) , .SAVE (INT_SUM[46]) , .CARRY (INT_CARRY[31]) ); |
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .CLK (CLK) , .DOUT (SUM[12]) ); |
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .CLK (CLK) , .DOUT (CARRY[12]) ); |
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[12]) ); |
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[12]) ); |
FULL_ADDER FA_26 (.DATA_A (SUMMAND[56]) , .DATA_B (SUMMAND[57]) , .DATA_C (SUMMAND[58]) , .SAVE (INT_SUM[47]) , .CARRY (INT_CARRY[38]) ); |
FULL_ADDER FA_27 (.DATA_A (SUMMAND[59]) , .DATA_B (SUMMAND[60]) , .DATA_C (SUMMAND[61]) , .SAVE (INT_SUM[48]) , .CARRY (INT_CARRY[39]) ); |
assign INT_SUM[49] = SUMMAND[62]; |
1019,8 → 885,8
FULL_ADDER FA_29 (.DATA_A (INT_SUM[50]) , .DATA_B (INT_SUM[51]) , .DATA_C (INT_CARRY[34]) , .SAVE (INT_SUM[52]) , .CARRY (INT_CARRY[42]) ); |
assign INT_SUM[53] = INT_CARRY[35]; |
FULL_ADDER FA_30 (.DATA_A (INT_SUM[52]) , .DATA_B (INT_SUM[53]) , .DATA_C (INT_CARRY[36]) , .SAVE (INT_SUM[54]) , .CARRY (INT_CARRY[37]) ); |
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .CLK (CLK) , .DOUT (SUM[13]) ); |
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .CLK (CLK) , .DOUT (CARRY[13]) ); |
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[13]) ); |
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[13]) ); |
FULL_ADDER FA_31 (.DATA_A (SUMMAND[63]) , .DATA_B (SUMMAND[64]) , .DATA_C (SUMMAND[65]) , .SAVE (INT_SUM[55]) , .CARRY (INT_CARRY[44]) ); |
FULL_ADDER FA_32 (.DATA_A (SUMMAND[66]) , .DATA_B (SUMMAND[67]) , .DATA_C (SUMMAND[68]) , .SAVE (INT_SUM[56]) , .CARRY (INT_CARRY[45]) ); |
FULL_ADDER FA_33 (.DATA_A (SUMMAND[69]) , .DATA_B (SUMMAND[70]) , .DATA_C (SUMMAND[71]) , .SAVE (INT_SUM[57]) , .CARRY (INT_CARRY[46]) ); |
1029,8 → 895,8
FULL_ADDER FA_35 (.DATA_A (INT_SUM[58]) , .DATA_B (INT_SUM[59]) , .DATA_C (INT_CARRY[40]) , .SAVE (INT_SUM[60]) , .CARRY (INT_CARRY[49]) ); |
assign INT_SUM[61] = INT_CARRY[41]; |
FULL_ADDER FA_36 (.DATA_A (INT_SUM[60]) , .DATA_B (INT_SUM[61]) , .DATA_C (INT_CARRY[42]) , .SAVE (INT_SUM[62]) , .CARRY (INT_CARRY[43]) ); |
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .CLK (CLK) , .DOUT (SUM[14]) ); |
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .CLK (CLK) , .DOUT (CARRY[14]) ); |
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[14]) ); |
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[14]) ); |
FULL_ADDER FA_37 (.DATA_A (SUMMAND[72]) , .DATA_B (SUMMAND[73]) , .DATA_C (SUMMAND[74]) , .SAVE (INT_SUM[63]) , .CARRY (INT_CARRY[51]) ); |
FULL_ADDER FA_38 (.DATA_A (SUMMAND[75]) , .DATA_B (SUMMAND[76]) , .DATA_C (SUMMAND[77]) , .SAVE (INT_SUM[64]) , .CARRY (INT_CARRY[52]) ); |
HALF_ADDER HA_13 (.DATA_A (SUMMAND[78]) , .DATA_B (SUMMAND[79]) , .SAVE (INT_SUM[65]) , .CARRY (INT_CARRY[53]) ); |
1039,8 → 905,8
FULL_ADDER FA_41 (.DATA_A (INT_SUM[66]) , .DATA_B (INT_SUM[67]) , .DATA_C (INT_CARRY[47]) , .SAVE (INT_SUM[68]) , .CARRY (INT_CARRY[56]) ); |
assign INT_SUM[69] = INT_CARRY[48]; |
FULL_ADDER FA_42 (.DATA_A (INT_SUM[68]) , .DATA_B (INT_SUM[69]) , .DATA_C (INT_CARRY[49]) , .SAVE (INT_SUM[70]) , .CARRY (INT_CARRY[50]) ); |
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .CLK (CLK) , .DOUT (SUM[15]) ); |
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .CLK (CLK) , .DOUT (CARRY[15]) ); |
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[15]) ); |
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[15]) ); |
FULL_ADDER FA_43 (.DATA_A (SUMMAND[80]) , .DATA_B (SUMMAND[81]) , .DATA_C (SUMMAND[82]) , .SAVE (INT_SUM[71]) , .CARRY (INT_CARRY[58]) ); |
FULL_ADDER FA_44 (.DATA_A (SUMMAND[83]) , .DATA_B (SUMMAND[84]) , .DATA_C (SUMMAND[85]) , .SAVE (INT_SUM[72]) , .CARRY (INT_CARRY[59]) ); |
FULL_ADDER FA_45 (.DATA_A (SUMMAND[86]) , .DATA_B (SUMMAND[87]) , .DATA_C (SUMMAND[88]) , .SAVE (INT_SUM[73]) , .CARRY (INT_CARRY[60]) ); |
1051,8 → 917,8
FULL_ADDER FA_48 (.DATA_A (INT_SUM[75]) , .DATA_B (INT_SUM[76]) , .DATA_C (INT_SUM[77]) , .SAVE (INT_SUM[78]) , .CARRY (INT_CARRY[63]) ); |
HALF_ADDER HA_14 (.DATA_A (INT_CARRY[54]) , .DATA_B (INT_CARRY[55]) , .SAVE (INT_SUM[79]) , .CARRY (INT_CARRY[64]) ); |
FULL_ADDER FA_49 (.DATA_A (INT_SUM[78]) , .DATA_B (INT_SUM[79]) , .DATA_C (INT_CARRY[56]) , .SAVE (INT_SUM[80]) , .CARRY (INT_CARRY[57]) ); |
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .CLK (CLK) , .DOUT (SUM[16]) ); |
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .CLK (CLK) , .DOUT (CARRY[16]) ); |
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[16]) ); |
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[16]) ); |
FULL_ADDER FA_50 (.DATA_A (SUMMAND[90]) , .DATA_B (SUMMAND[91]) , .DATA_C (SUMMAND[92]) , .SAVE (INT_SUM[81]) , .CARRY (INT_CARRY[65]) ); |
FULL_ADDER FA_51 (.DATA_A (SUMMAND[93]) , .DATA_B (SUMMAND[94]) , .DATA_C (SUMMAND[95]) , .SAVE (INT_SUM[82]) , .CARRY (INT_CARRY[66]) ); |
FULL_ADDER FA_52 (.DATA_A (SUMMAND[96]) , .DATA_B (SUMMAND[97]) , .DATA_C (SUMMAND[98]) , .SAVE (INT_SUM[83]) , .CARRY (INT_CARRY[67]) ); |
1062,8 → 928,8
assign INT_SUM[87] = INT_CARRY[62]; |
FULL_ADDER FA_56 (.DATA_A (INT_SUM[86]) , .DATA_B (INT_SUM[87]) , .DATA_C (INT_CARRY[63]) , .SAVE (INT_SUM[88]) , .CARRY (INT_CARRY[71]) ); |
assign INT_SUM[90] = INT_CARRY[64]; |
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .CLK (CLK) , .DOUT (INT_SUM[89]) ); |
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .CLK (CLK) , .DOUT (INT_SUM[91]) ); |
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[89]) ); |
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[91]) ); |
HALF_ADDER HA_15 (.DATA_A (INT_SUM[89]) , .DATA_B (INT_SUM[91]) , .SAVE (SUM[17]) , .CARRY (CARRY[17]) ); |
FULL_ADDER FA_57 (.DATA_A (SUMMAND[99]) , .DATA_B (SUMMAND[100]) , .DATA_C (SUMMAND[101]) , .SAVE (INT_SUM[92]) , .CARRY (INT_CARRY[73]) ); |
FULL_ADDER FA_58 (.DATA_A (SUMMAND[102]) , .DATA_B (SUMMAND[103]) , .DATA_C (SUMMAND[104]) , .SAVE (INT_SUM[93]) , .CARRY (INT_CARRY[74]) ); |
1077,8 → 943,8
FULL_ADDER FA_62 (.DATA_A (INT_SUM[97]) , .DATA_B (INT_SUM[98]) , .DATA_C (INT_SUM[99]) , .SAVE (INT_SUM[101]) , .CARRY (INT_CARRY[78]) ); |
FULL_ADDER FA_63 (.DATA_A (INT_SUM[100]) , .DATA_B (INT_CARRY[68]) , .DATA_C (INT_CARRY[69]) , .SAVE (INT_SUM[102]) , .CARRY (INT_CARRY[79]) ); |
FULL_ADDER FA_64 (.DATA_A (INT_SUM[101]) , .DATA_B (INT_SUM[102]) , .DATA_C (INT_CARRY[70]) , .SAVE (INT_SUM[103]) , .CARRY (INT_CARRY[80]) ); |
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .CLK (CLK) , .DOUT (INT_SUM[104]) ); |
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .CLK (CLK) , .DOUT (INT_CARRY[72]) ); |
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[104]) ); |
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[72]) ); |
HALF_ADDER HA_16 (.DATA_A (INT_SUM[104]) , .DATA_B (INT_CARRY[72]) , .SAVE (SUM[18]) , .CARRY (CARRY[18]) ); |
FULL_ADDER FA_65 (.DATA_A (SUMMAND[110]) , .DATA_B (SUMMAND[111]) , .DATA_C (SUMMAND[112]) , .SAVE (INT_SUM[105]) , .CARRY (INT_CARRY[82]) ); |
FULL_ADDER FA_66 (.DATA_A (SUMMAND[113]) , .DATA_B (SUMMAND[114]) , .DATA_C (SUMMAND[115]) , .SAVE (INT_SUM[106]) , .CARRY (INT_CARRY[83]) ); |
1091,9 → 957,9
HALF_ADDER HA_17 (.DATA_A (INT_CARRY[76]) , .DATA_B (INT_CARRY[77]) , .SAVE (INT_SUM[113]) , .CARRY (INT_CARRY[88]) ); |
FULL_ADDER FA_71 (.DATA_A (INT_SUM[112]) , .DATA_B (INT_SUM[113]) , .DATA_C (INT_CARRY[78]) , .SAVE (INT_SUM[114]) , .CARRY (INT_CARRY[89]) ); |
assign INT_SUM[116] = INT_CARRY[79]; |
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .CLK (CLK) , .DOUT (INT_SUM[115]) ); |
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .CLK (CLK) , .DOUT (INT_SUM[117]) ); |
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .CLK (CLK) , .DOUT (INT_CARRY[81]) ); |
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[115]) ); |
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[117]) ); |
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[81]) ); |
FULL_ADDER FA_72 (.DATA_A (INT_SUM[115]) , .DATA_B (INT_SUM[117]) , .DATA_C (INT_CARRY[81]) , .SAVE (SUM[19]) , .CARRY (CARRY[19]) ); |
FULL_ADDER FA_73 (.DATA_A (SUMMAND[120]) , .DATA_B (SUMMAND[121]) , .DATA_C (SUMMAND[122]) , .SAVE (INT_SUM[118]) , .CARRY (INT_CARRY[91]) ); |
FULL_ADDER FA_74 (.DATA_A (SUMMAND[123]) , .DATA_B (SUMMAND[124]) , .DATA_C (SUMMAND[125]) , .SAVE (INT_SUM[119]) , .CARRY (INT_CARRY[92]) ); |
1106,9 → 972,9
HALF_ADDER HA_18 (.DATA_A (INT_CARRY[85]) , .DATA_B (INT_CARRY[86]) , .SAVE (INT_SUM[126]) , .CARRY (INT_CARRY[98]) ); |
FULL_ADDER FA_80 (.DATA_A (INT_SUM[125]) , .DATA_B (INT_SUM[126]) , .DATA_C (INT_CARRY[87]) , .SAVE (INT_SUM[127]) , .CARRY (INT_CARRY[99]) ); |
assign INT_SUM[129] = INT_CARRY[88]; |
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .CLK (CLK) , .DOUT (INT_SUM[128]) ); |
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .CLK (CLK) , .DOUT (INT_SUM[130]) ); |
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .CLK (CLK) , .DOUT (INT_CARRY[90]) ); |
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[128]) ); |
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[130]) ); |
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[90]) ); |
FULL_ADDER FA_81 (.DATA_A (INT_SUM[128]) , .DATA_B (INT_SUM[130]) , .DATA_C (INT_CARRY[90]) , .SAVE (SUM[20]) , .CARRY (CARRY[20]) ); |
FULL_ADDER FA_82 (.DATA_A (SUMMAND[132]) , .DATA_B (SUMMAND[133]) , .DATA_C (SUMMAND[134]) , .SAVE (INT_SUM[131]) , .CARRY (INT_CARRY[101]) ); |
FULL_ADDER FA_83 (.DATA_A (SUMMAND[135]) , .DATA_B (SUMMAND[136]) , .DATA_C (SUMMAND[137]) , .SAVE (INT_SUM[132]) , .CARRY (INT_CARRY[102]) ); |
1122,9 → 988,9
HALF_ADDER HA_19 (.DATA_A (INT_CARRY[95]) , .DATA_B (INT_CARRY[96]) , .SAVE (INT_SUM[140]) , .CARRY (INT_CARRY[108]) ); |
FULL_ADDER FA_89 (.DATA_A (INT_SUM[139]) , .DATA_B (INT_SUM[140]) , .DATA_C (INT_CARRY[97]) , .SAVE (INT_SUM[141]) , .CARRY (INT_CARRY[109]) ); |
assign INT_SUM[143] = INT_CARRY[98]; |
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .CLK (CLK) , .DOUT (INT_SUM[142]) ); |
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .CLK (CLK) , .DOUT (INT_SUM[144]) ); |
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .CLK (CLK) , .DOUT (INT_CARRY[100]) ); |
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[142]) ); |
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[144]) ); |
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[100]) ); |
FULL_ADDER FA_90 (.DATA_A (INT_SUM[142]) , .DATA_B (INT_SUM[144]) , .DATA_C (INT_CARRY[100]) , .SAVE (SUM[21]) , .CARRY (CARRY[21]) ); |
FULL_ADDER FA_91 (.DATA_A (SUMMAND[143]) , .DATA_B (SUMMAND[144]) , .DATA_C (SUMMAND[145]) , .SAVE (INT_SUM[145]) , .CARRY (INT_CARRY[111]) ); |
FULL_ADDER FA_92 (.DATA_A (SUMMAND[146]) , .DATA_B (SUMMAND[147]) , .DATA_C (SUMMAND[148]) , .SAVE (INT_SUM[146]) , .CARRY (INT_CARRY[112]) ); |
1138,9 → 1004,9
FULL_ADDER FA_98 (.DATA_A (INT_CARRY[104]) , .DATA_B (INT_CARRY[105]) , .DATA_C (INT_CARRY[106]) , .SAVE (INT_SUM[154]) , .CARRY (INT_CARRY[119]) ); |
FULL_ADDER FA_99 (.DATA_A (INT_SUM[153]) , .DATA_B (INT_SUM[154]) , .DATA_C (INT_CARRY[107]) , .SAVE (INT_SUM[155]) , .CARRY (INT_CARRY[120]) ); |
assign INT_SUM[157] = INT_CARRY[108]; |
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .CLK (CLK) , .DOUT (INT_SUM[156]) ); |
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .CLK (CLK) , .DOUT (INT_SUM[158]) ); |
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .CLK (CLK) , .DOUT (INT_CARRY[110]) ); |
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[156]) ); |
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[158]) ); |
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[110]) ); |
FULL_ADDER FA_100 (.DATA_A (INT_SUM[156]) , .DATA_B (INT_SUM[158]) , .DATA_C (INT_CARRY[110]) , .SAVE (SUM[22]) , .CARRY (CARRY[22]) ); |
FULL_ADDER FA_101 (.DATA_A (SUMMAND[156]) , .DATA_B (SUMMAND[157]) , .DATA_C (SUMMAND[158]) , .SAVE (INT_SUM[159]) , .CARRY (INT_CARRY[122]) ); |
FULL_ADDER FA_102 (.DATA_A (SUMMAND[159]) , .DATA_B (SUMMAND[160]) , .DATA_C (SUMMAND[161]) , .SAVE (INT_SUM[160]) , .CARRY (INT_CARRY[123]) ); |
1153,9 → 1019,9
FULL_ADDER FA_108 (.DATA_A (INT_CARRY[115]) , .DATA_B (INT_CARRY[116]) , .DATA_C (INT_CARRY[117]) , .SAVE (INT_SUM[167]) , .CARRY (INT_CARRY[130]) ); |
FULL_ADDER FA_109 (.DATA_A (INT_SUM[166]) , .DATA_B (INT_SUM[167]) , .DATA_C (INT_CARRY[118]) , .SAVE (INT_SUM[168]) , .CARRY (INT_CARRY[131]) ); |
assign INT_SUM[170] = INT_CARRY[119]; |
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .CLK (CLK) , .DOUT (INT_SUM[169]) ); |
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .CLK (CLK) , .DOUT (INT_SUM[171]) ); |
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .CLK (CLK) , .DOUT (INT_CARRY[121]) ); |
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[169]) ); |
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[171]) ); |
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[121]) ); |
FULL_ADDER FA_110 (.DATA_A (INT_SUM[169]) , .DATA_B (INT_SUM[171]) , .DATA_C (INT_CARRY[121]) , .SAVE (SUM[23]) , .CARRY (CARRY[23]) ); |
FULL_ADDER FA_111 (.DATA_A (SUMMAND[168]) , .DATA_B (SUMMAND[169]) , .DATA_C (SUMMAND[170]) , .SAVE (INT_SUM[172]) , .CARRY (INT_CARRY[133]) ); |
FULL_ADDER FA_112 (.DATA_A (SUMMAND[171]) , .DATA_B (SUMMAND[172]) , .DATA_C (SUMMAND[173]) , .SAVE (INT_SUM[173]) , .CARRY (INT_CARRY[134]) ); |
1169,9 → 1035,9
FULL_ADDER FA_119 (.DATA_A (INT_CARRY[126]) , .DATA_B (INT_CARRY[127]) , .DATA_C (INT_CARRY[128]) , .SAVE (INT_SUM[181]) , .CARRY (INT_CARRY[142]) ); |
FULL_ADDER FA_120 (.DATA_A (INT_SUM[180]) , .DATA_B (INT_SUM[181]) , .DATA_C (INT_CARRY[129]) , .SAVE (INT_SUM[182]) , .CARRY (INT_CARRY[143]) ); |
assign INT_SUM[184] = INT_CARRY[130]; |
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .CLK (CLK) , .DOUT (INT_SUM[183]) ); |
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .CLK (CLK) , .DOUT (INT_SUM[185]) ); |
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .CLK (CLK) , .DOUT (INT_CARRY[132]) ); |
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[183]) ); |
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[185]) ); |
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[132]) ); |
FULL_ADDER FA_121 (.DATA_A (INT_SUM[183]) , .DATA_B (INT_SUM[185]) , .DATA_C (INT_CARRY[132]) , .SAVE (SUM[24]) , .CARRY (CARRY[24]) ); |
FULL_ADDER FA_122 (.DATA_A (SUMMAND[182]) , .DATA_B (SUMMAND[183]) , .DATA_C (SUMMAND[184]) , .SAVE (INT_SUM[186]) , .CARRY (INT_CARRY[145]) ); |
FULL_ADDER FA_123 (.DATA_A (SUMMAND[185]) , .DATA_B (SUMMAND[186]) , .DATA_C (SUMMAND[187]) , .SAVE (INT_SUM[187]) , .CARRY (INT_CARRY[146]) ); |
1187,9 → 1053,9
assign INT_SUM[197] = INT_CARRY[140]; |
FULL_ADDER FA_131 (.DATA_A (INT_SUM[195]) , .DATA_B (INT_SUM[196]) , .DATA_C (INT_SUM[197]) , .SAVE (INT_SUM[198]) , .CARRY (INT_CARRY[154]) ); |
HALF_ADDER HA_23 (.DATA_A (INT_CARRY[141]) , .DATA_B (INT_CARRY[142]) , .SAVE (INT_SUM[200]) , .CARRY (INT_CARRY[156]) ); |
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .CLK (CLK) , .DOUT (INT_SUM[199]) ); |
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .CLK (CLK) , .DOUT (INT_SUM[201]) ); |
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .CLK (CLK) , .DOUT (INT_CARRY[144]) ); |
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[199]) ); |
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[201]) ); |
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[144]) ); |
FULL_ADDER FA_132 (.DATA_A (INT_SUM[199]) , .DATA_B (INT_SUM[201]) , .DATA_C (INT_CARRY[144]) , .SAVE (SUM[25]) , .CARRY (CARRY[25]) ); |
FULL_ADDER FA_133 (.DATA_A (SUMMAND[195]) , .DATA_B (SUMMAND[196]) , .DATA_C (SUMMAND[197]) , .SAVE (INT_SUM[202]) , .CARRY (INT_CARRY[158]) ); |
FULL_ADDER FA_134 (.DATA_A (SUMMAND[198]) , .DATA_B (SUMMAND[199]) , .DATA_C (SUMMAND[200]) , .SAVE (INT_SUM[203]) , .CARRY (INT_CARRY[159]) ); |
1203,11 → 1069,11
FULL_ADDER FA_142 (.DATA_A (INT_CARRY[149]) , .DATA_B (INT_CARRY[150]) , .DATA_C (INT_CARRY[151]) , .SAVE (INT_SUM[211]) , .CARRY (INT_CARRY[167]) ); |
FULL_ADDER FA_143 (.DATA_A (INT_SUM[210]) , .DATA_B (INT_SUM[211]) , .DATA_C (INT_CARRY[152]) , .SAVE (INT_SUM[212]) , .CARRY (INT_CARRY[168]) ); |
assign INT_SUM[214] = INT_CARRY[153]; |
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .CLK (CLK) , .DOUT (INT_SUM[213]) ); |
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .CLK (CLK) , .DOUT (INT_SUM[215]) ); |
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .CLK (CLK) , .DOUT (INT_CARRY[155]) ); |
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[213]) ); |
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[215]) ); |
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[155]) ); |
FULL_ADDER FA_144 (.DATA_A (INT_SUM[213]) , .DATA_B (INT_SUM[215]) , .DATA_C (INT_CARRY[155]) , .SAVE (INT_SUM[216]) , .CARRY (INT_CARRY[170]) ); |
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .CLK (CLK) , .DOUT (INT_CARRY[157]) ); |
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[157]) ); |
assign INT_SUM[217] = INT_CARRY[157]; |
HALF_ADDER HA_24 (.DATA_A (INT_SUM[216]) , .DATA_B (INT_SUM[217]) , .SAVE (SUM[26]) , .CARRY (CARRY[26]) ); |
FULL_ADDER FA_145 (.DATA_A (SUMMAND[210]) , .DATA_B (SUMMAND[211]) , .DATA_C (SUMMAND[212]) , .SAVE (INT_SUM[218]) , .CARRY (INT_CARRY[171]) ); |
1225,11 → 1091,11
FULL_ADDER FA_154 (.DATA_A (INT_SUM[227]) , .DATA_B (INT_SUM[228]) , .DATA_C (INT_SUM[229]) , .SAVE (INT_SUM[230]) , .CARRY (INT_CARRY[181]) ); |
assign INT_SUM[232] = INT_CARRY[166]; |
assign INT_SUM[234] = INT_CARRY[167]; |
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .CLK (CLK) , .DOUT (INT_SUM[231]) ); |
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .CLK (CLK) , .DOUT (INT_SUM[233]) ); |
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .CLK (CLK) , .DOUT (INT_SUM[235]) ); |
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[231]) ); |
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[233]) ); |
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[235]) ); |
FULL_ADDER FA_155 (.DATA_A (INT_SUM[231]) , .DATA_B (INT_SUM[233]) , .DATA_C (INT_SUM[235]) , .SAVE (INT_SUM[236]) , .CARRY (INT_CARRY[183]) ); |
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .CLK (CLK) , .DOUT (INT_CARRY[169]) ); |
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[169]) ); |
assign INT_SUM[237] = INT_CARRY[169]; |
FULL_ADDER FA_156 (.DATA_A (INT_SUM[236]) , .DATA_B (INT_SUM[237]) , .DATA_C (INT_CARRY[170]) , .SAVE (SUM[27]) , .CARRY (CARRY[27]) ); |
FULL_ADDER FA_157 (.DATA_A (SUMMAND[224]) , .DATA_B (SUMMAND[225]) , .DATA_C (SUMMAND[226]) , .SAVE (INT_SUM[238]) , .CARRY (INT_CARRY[184]) ); |
1249,9 → 1115,9
assign INT_SUM[252] = INT_CARRY[178]; |
FULL_ADDER FA_167 (.DATA_A (INT_SUM[249]) , .DATA_B (INT_SUM[250]) , .DATA_C (INT_SUM[251]) , .SAVE (INT_SUM[253]) , .CARRY (INT_CARRY[194]) ); |
FULL_ADDER FA_168 (.DATA_A (INT_SUM[252]) , .DATA_B (INT_CARRY[179]) , .DATA_C (INT_CARRY[180]) , .SAVE (INT_SUM[255]) , .CARRY (INT_CARRY[196]) ); |
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .CLK (CLK) , .DOUT (INT_SUM[254]) ); |
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .CLK (CLK) , .DOUT (INT_SUM[256]) ); |
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .CLK (CLK) , .DOUT (INT_CARRY[182]) ); |
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[254]) ); |
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[256]) ); |
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[182]) ); |
FULL_ADDER FA_169 (.DATA_A (INT_SUM[254]) , .DATA_B (INT_SUM[256]) , .DATA_C (INT_CARRY[182]) , .SAVE (INT_SUM[257]) , .CARRY (INT_CARRY[198]) ); |
HALF_ADDER HA_26 (.DATA_A (INT_SUM[257]) , .DATA_B (INT_CARRY[183]) , .SAVE (SUM[28]) , .CARRY (CARRY[28]) ); |
FULL_ADDER FA_170 (.DATA_A (SUMMAND[240]) , .DATA_B (SUMMAND[241]) , .DATA_C (SUMMAND[242]) , .SAVE (INT_SUM[258]) , .CARRY (INT_CARRY[199]) ); |
1268,11 → 1134,11
assign INT_SUM[269] = INT_CARRY[191]; |
FULL_ADDER FA_180 (.DATA_A (INT_SUM[267]) , .DATA_B (INT_SUM[268]) , .DATA_C (INT_SUM[269]) , .SAVE (INT_SUM[270]) , .CARRY (INT_CARRY[209]) ); |
HALF_ADDER HA_27 (.DATA_A (INT_CARRY[192]) , .DATA_B (INT_CARRY[193]) , .SAVE (INT_SUM[272]) , .CARRY (INT_CARRY[211]) ); |
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .CLK (CLK) , .DOUT (INT_SUM[271]) ); |
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .CLK (CLK) , .DOUT (INT_SUM[273]) ); |
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .CLK (CLK) , .DOUT (INT_CARRY[195]) ); |
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[271]) ); |
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[273]) ); |
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[195]) ); |
FULL_ADDER FA_181 (.DATA_A (INT_SUM[271]) , .DATA_B (INT_SUM[273]) , .DATA_C (INT_CARRY[195]) , .SAVE (INT_SUM[274]) , .CARRY (INT_CARRY[213]) ); |
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .CLK (CLK) , .DOUT (INT_CARRY[197]) ); |
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[197]) ); |
assign INT_SUM[275] = INT_CARRY[197]; |
FULL_ADDER FA_182 (.DATA_A (INT_SUM[274]) , .DATA_B (INT_SUM[275]) , .DATA_C (INT_CARRY[198]) , .SAVE (SUM[29]) , .CARRY (CARRY[29]) ); |
FULL_ADDER FA_183 (.DATA_A (SUMMAND[255]) , .DATA_B (SUMMAND[256]) , .DATA_C (SUMMAND[257]) , .SAVE (INT_SUM[276]) , .CARRY (INT_CARRY[214]) ); |
1291,11 → 1157,11
assign INT_SUM[289] = INT_CARRY[206]; |
FULL_ADDER FA_194 (.DATA_A (INT_SUM[287]) , .DATA_B (INT_SUM[288]) , .DATA_C (INT_SUM[289]) , .SAVE (INT_SUM[290]) , .CARRY (INT_CARRY[225]) ); |
HALF_ADDER HA_28 (.DATA_A (INT_CARRY[207]) , .DATA_B (INT_CARRY[208]) , .SAVE (INT_SUM[292]) , .CARRY (INT_CARRY[227]) ); |
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .CLK (CLK) , .DOUT (INT_SUM[291]) ); |
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .CLK (CLK) , .DOUT (INT_SUM[293]) ); |
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .CLK (CLK) , .DOUT (INT_CARRY[210]) ); |
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[291]) ); |
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[293]) ); |
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[210]) ); |
FULL_ADDER FA_195 (.DATA_A (INT_SUM[291]) , .DATA_B (INT_SUM[293]) , .DATA_C (INT_CARRY[210]) , .SAVE (INT_SUM[294]) , .CARRY (INT_CARRY[229]) ); |
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .CLK (CLK) , .DOUT (INT_CARRY[212]) ); |
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[212]) ); |
assign INT_SUM[295] = INT_CARRY[212]; |
FULL_ADDER FA_196 (.DATA_A (INT_SUM[294]) , .DATA_B (INT_SUM[295]) , .DATA_C (INT_CARRY[213]) , .SAVE (SUM[30]) , .CARRY (CARRY[30]) ); |
FULL_ADDER FA_197 (.DATA_A (SUMMAND[272]) , .DATA_B (SUMMAND[273]) , .DATA_C (SUMMAND[274]) , .SAVE (INT_SUM[296]) , .CARRY (INT_CARRY[230]) ); |
1314,11 → 1180,11
FULL_ADDER FA_207 (.DATA_A (INT_CARRY[220]) , .DATA_B (INT_CARRY[221]) , .DATA_C (INT_CARRY[222]) , .SAVE (INT_SUM[309]) , .CARRY (INT_CARRY[240]) ); |
FULL_ADDER FA_208 (.DATA_A (INT_SUM[307]) , .DATA_B (INT_SUM[308]) , .DATA_C (INT_SUM[309]) , .SAVE (INT_SUM[310]) , .CARRY (INT_CARRY[241]) ); |
HALF_ADDER HA_29 (.DATA_A (INT_CARRY[223]) , .DATA_B (INT_CARRY[224]) , .SAVE (INT_SUM[312]) , .CARRY (INT_CARRY[243]) ); |
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .CLK (CLK) , .DOUT (INT_SUM[311]) ); |
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .CLK (CLK) , .DOUT (INT_SUM[313]) ); |
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .CLK (CLK) , .DOUT (INT_CARRY[226]) ); |
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[311]) ); |
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[313]) ); |
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[226]) ); |
FULL_ADDER FA_209 (.DATA_A (INT_SUM[311]) , .DATA_B (INT_SUM[313]) , .DATA_C (INT_CARRY[226]) , .SAVE (INT_SUM[314]) , .CARRY (INT_CARRY[245]) ); |
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .CLK (CLK) , .DOUT (INT_CARRY[228]) ); |
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[228]) ); |
assign INT_SUM[315] = INT_CARRY[228]; |
FULL_ADDER FA_210 (.DATA_A (INT_SUM[314]) , .DATA_B (INT_SUM[315]) , .DATA_C (INT_CARRY[229]) , .SAVE (SUM[31]) , .CARRY (CARRY[31]) ); |
FULL_ADDER FA_211 (.DATA_A (SUMMAND[288]) , .DATA_B (SUMMAND[289]) , .DATA_C (SUMMAND[290]) , .SAVE (INT_SUM[316]) , .CARRY (INT_CARRY[246]) ); |
1336,11 → 1202,11
assign INT_SUM[328] = INT_CARRY[237]; |
FULL_ADDER FA_221 (.DATA_A (INT_SUM[326]) , .DATA_B (INT_SUM[327]) , .DATA_C (INT_SUM[328]) , .SAVE (INT_SUM[329]) , .CARRY (INT_CARRY[257]) ); |
FULL_ADDER FA_222 (.DATA_A (INT_CARRY[238]) , .DATA_B (INT_CARRY[239]) , .DATA_C (INT_CARRY[240]) , .SAVE (INT_SUM[331]) , .CARRY (INT_CARRY[259]) ); |
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .CLK (CLK) , .DOUT (INT_SUM[330]) ); |
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .CLK (CLK) , .DOUT (INT_SUM[332]) ); |
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .CLK (CLK) , .DOUT (INT_CARRY[242]) ); |
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[330]) ); |
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[332]) ); |
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[242]) ); |
FULL_ADDER FA_223 (.DATA_A (INT_SUM[330]) , .DATA_B (INT_SUM[332]) , .DATA_C (INT_CARRY[242]) , .SAVE (INT_SUM[333]) , .CARRY (INT_CARRY[261]) ); |
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .CLK (CLK) , .DOUT (INT_CARRY[244]) ); |
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[244]) ); |
assign INT_SUM[334] = INT_CARRY[244]; |
FULL_ADDER FA_224 (.DATA_A (INT_SUM[333]) , .DATA_B (INT_SUM[334]) , .DATA_C (INT_CARRY[245]) , .SAVE (SUM[32]) , .CARRY (CARRY[32]) ); |
FULL_ADDER FA_225 (.DATA_A (SUMMAND[304]) , .DATA_B (SUMMAND[305]) , .DATA_C (SUMMAND[306]) , .SAVE (INT_SUM[335]) , .CARRY (INT_CARRY[262]) ); |
1360,11 → 1226,11
assign INT_SUM[349] = INT_CARRY[254]; |
FULL_ADDER FA_236 (.DATA_A (INT_SUM[346]) , .DATA_B (INT_SUM[347]) , .DATA_C (INT_SUM[348]) , .SAVE (INT_SUM[350]) , .CARRY (INT_CARRY[273]) ); |
FULL_ADDER FA_237 (.DATA_A (INT_SUM[349]) , .DATA_B (INT_CARRY[255]) , .DATA_C (INT_CARRY[256]) , .SAVE (INT_SUM[352]) , .CARRY (INT_CARRY[275]) ); |
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .CLK (CLK) , .DOUT (INT_SUM[351]) ); |
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .CLK (CLK) , .DOUT (INT_SUM[353]) ); |
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .CLK (CLK) , .DOUT (INT_CARRY[258]) ); |
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[351]) ); |
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[353]) ); |
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[258]) ); |
FULL_ADDER FA_238 (.DATA_A (INT_SUM[351]) , .DATA_B (INT_SUM[353]) , .DATA_C (INT_CARRY[258]) , .SAVE (INT_SUM[354]) , .CARRY (INT_CARRY[277]) ); |
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .CLK (CLK) , .DOUT (INT_CARRY[260]) ); |
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[260]) ); |
assign INT_SUM[355] = INT_CARRY[260]; |
FULL_ADDER FA_239 (.DATA_A (INT_SUM[354]) , .DATA_B (INT_SUM[355]) , .DATA_C (INT_CARRY[261]) , .SAVE (SUM[33]) , .CARRY (CARRY[33]) ); |
FULL_ADDER FA_240 (.DATA_A (SUMMAND[321]) , .DATA_B (SUMMAND[322]) , .DATA_C (SUMMAND[323]) , .SAVE (INT_SUM[356]) , .CARRY (INT_CARRY[278]) ); |
1383,11 → 1249,11
FULL_ADDER FA_250 (.DATA_A (INT_CARRY[268]) , .DATA_B (INT_CARRY[269]) , .DATA_C (INT_CARRY[270]) , .SAVE (INT_SUM[369]) , .CARRY (INT_CARRY[288]) ); |
FULL_ADDER FA_251 (.DATA_A (INT_SUM[367]) , .DATA_B (INT_SUM[368]) , .DATA_C (INT_SUM[369]) , .SAVE (INT_SUM[370]) , .CARRY (INT_CARRY[289]) ); |
HALF_ADDER HA_31 (.DATA_A (INT_CARRY[271]) , .DATA_B (INT_CARRY[272]) , .SAVE (INT_SUM[372]) , .CARRY (INT_CARRY[291]) ); |
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .CLK (CLK) , .DOUT (INT_SUM[371]) ); |
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .CLK (CLK) , .DOUT (INT_SUM[373]) ); |
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .CLK (CLK) , .DOUT (INT_CARRY[274]) ); |
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[371]) ); |
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[373]) ); |
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[274]) ); |
FULL_ADDER FA_252 (.DATA_A (INT_SUM[371]) , .DATA_B (INT_SUM[373]) , .DATA_C (INT_CARRY[274]) , .SAVE (INT_SUM[374]) , .CARRY (INT_CARRY[293]) ); |
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .CLK (CLK) , .DOUT (INT_CARRY[276]) ); |
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[276]) ); |
assign INT_SUM[375] = INT_CARRY[276]; |
FULL_ADDER FA_253 (.DATA_A (INT_SUM[374]) , .DATA_B (INT_SUM[375]) , .DATA_C (INT_CARRY[277]) , .SAVE (SUM[34]) , .CARRY (CARRY[34]) ); |
FULL_ADDER FA_254 (.DATA_A (SUMMAND[337]) , .DATA_B (SUMMAND[338]) , .DATA_C (SUMMAND[339]) , .SAVE (INT_SUM[376]) , .CARRY (INT_CARRY[294]) ); |
1404,11 → 1270,11
assign INT_SUM[387] = INT_CARRY[285]; |
FULL_ADDER FA_264 (.DATA_A (INT_SUM[385]) , .DATA_B (INT_SUM[386]) , .DATA_C (INT_SUM[387]) , .SAVE (INT_SUM[388]) , .CARRY (INT_CARRY[304]) ); |
FULL_ADDER FA_265 (.DATA_A (INT_CARRY[286]) , .DATA_B (INT_CARRY[287]) , .DATA_C (INT_CARRY[288]) , .SAVE (INT_SUM[390]) , .CARRY (INT_CARRY[306]) ); |
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .CLK (CLK) , .DOUT (INT_SUM[389]) ); |
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .CLK (CLK) , .DOUT (INT_SUM[391]) ); |
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .CLK (CLK) , .DOUT (INT_CARRY[290]) ); |
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[389]) ); |
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[391]) ); |
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[290]) ); |
FULL_ADDER FA_266 (.DATA_A (INT_SUM[389]) , .DATA_B (INT_SUM[391]) , .DATA_C (INT_CARRY[290]) , .SAVE (INT_SUM[392]) , .CARRY (INT_CARRY[308]) ); |
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .CLK (CLK) , .DOUT (INT_CARRY[292]) ); |
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[292]) ); |
assign INT_SUM[393] = INT_CARRY[292]; |
FULL_ADDER FA_267 (.DATA_A (INT_SUM[392]) , .DATA_B (INT_SUM[393]) , .DATA_C (INT_CARRY[293]) , .SAVE (SUM[35]) , .CARRY (CARRY[35]) ); |
FULL_ADDER FA_268 (.DATA_A (SUMMAND[352]) , .DATA_B (SUMMAND[353]) , .DATA_C (SUMMAND[354]) , .SAVE (INT_SUM[394]) , .CARRY (INT_CARRY[309]) ); |
1425,11 → 1291,11
assign INT_SUM[405] = INT_CARRY[301]; |
FULL_ADDER FA_278 (.DATA_A (INT_SUM[403]) , .DATA_B (INT_SUM[404]) , .DATA_C (INT_SUM[405]) , .SAVE (INT_SUM[406]) , .CARRY (INT_CARRY[319]) ); |
HALF_ADDER HA_32 (.DATA_A (INT_CARRY[302]) , .DATA_B (INT_CARRY[303]) , .SAVE (INT_SUM[408]) , .CARRY (INT_CARRY[321]) ); |
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .CLK (CLK) , .DOUT (INT_SUM[407]) ); |
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .CLK (CLK) , .DOUT (INT_SUM[409]) ); |
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .CLK (CLK) , .DOUT (INT_CARRY[305]) ); |
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[407]) ); |
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[409]) ); |
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[305]) ); |
FULL_ADDER FA_279 (.DATA_A (INT_SUM[407]) , .DATA_B (INT_SUM[409]) , .DATA_C (INT_CARRY[305]) , .SAVE (INT_SUM[410]) , .CARRY (INT_CARRY[323]) ); |
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .CLK (CLK) , .DOUT (INT_CARRY[307]) ); |
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[307]) ); |
assign INT_SUM[411] = INT_CARRY[307]; |
FULL_ADDER FA_280 (.DATA_A (INT_SUM[410]) , .DATA_B (INT_SUM[411]) , .DATA_C (INT_CARRY[308]) , .SAVE (SUM[36]) , .CARRY (CARRY[36]) ); |
FULL_ADDER FA_281 (.DATA_A (SUMMAND[367]) , .DATA_B (SUMMAND[368]) , .DATA_C (SUMMAND[369]) , .SAVE (INT_SUM[412]) , .CARRY (INT_CARRY[324]) ); |
1446,11 → 1312,11
assign INT_SUM[423] = INT_CARRY[316]; |
FULL_ADDER FA_290 (.DATA_A (INT_SUM[421]) , .DATA_B (INT_SUM[422]) , .DATA_C (INT_SUM[423]) , .SAVE (INT_SUM[424]) , .CARRY (INT_CARRY[334]) ); |
HALF_ADDER HA_34 (.DATA_A (INT_CARRY[317]) , .DATA_B (INT_CARRY[318]) , .SAVE (INT_SUM[426]) , .CARRY (INT_CARRY[336]) ); |
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .CLK (CLK) , .DOUT (INT_SUM[425]) ); |
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .CLK (CLK) , .DOUT (INT_SUM[427]) ); |
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .CLK (CLK) , .DOUT (INT_CARRY[320]) ); |
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[425]) ); |
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[427]) ); |
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[320]) ); |
FULL_ADDER FA_291 (.DATA_A (INT_SUM[425]) , .DATA_B (INT_SUM[427]) , .DATA_C (INT_CARRY[320]) , .SAVE (INT_SUM[428]) , .CARRY (INT_CARRY[338]) ); |
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .CLK (CLK) , .DOUT (INT_CARRY[322]) ); |
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[322]) ); |
assign INT_SUM[429] = INT_CARRY[322]; |
FULL_ADDER FA_292 (.DATA_A (INT_SUM[428]) , .DATA_B (INT_SUM[429]) , .DATA_C (INT_CARRY[323]) , .SAVE (SUM[37]) , .CARRY (CARRY[37]) ); |
FULL_ADDER FA_293 (.DATA_A (SUMMAND[381]) , .DATA_B (SUMMAND[382]) , .DATA_C (SUMMAND[383]) , .SAVE (INT_SUM[430]) , .CARRY (INT_CARRY[339]) ); |
1467,11 → 1333,11
assign INT_SUM[441] = INT_CARRY[331]; |
FULL_ADDER FA_302 (.DATA_A (INT_SUM[439]) , .DATA_B (INT_SUM[440]) , .DATA_C (INT_SUM[441]) , .SAVE (INT_SUM[442]) , .CARRY (INT_CARRY[349]) ); |
HALF_ADDER HA_36 (.DATA_A (INT_CARRY[332]) , .DATA_B (INT_CARRY[333]) , .SAVE (INT_SUM[444]) , .CARRY (INT_CARRY[351]) ); |
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .CLK (CLK) , .DOUT (INT_SUM[443]) ); |
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .CLK (CLK) , .DOUT (INT_SUM[445]) ); |
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .CLK (CLK) , .DOUT (INT_CARRY[335]) ); |
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[443]) ); |
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[445]) ); |
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[335]) ); |
FULL_ADDER FA_303 (.DATA_A (INT_SUM[443]) , .DATA_B (INT_SUM[445]) , .DATA_C (INT_CARRY[335]) , .SAVE (INT_SUM[446]) , .CARRY (INT_CARRY[353]) ); |
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .CLK (CLK) , .DOUT (INT_CARRY[337]) ); |
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[337]) ); |
assign INT_SUM[447] = INT_CARRY[337]; |
FULL_ADDER FA_304 (.DATA_A (INT_SUM[446]) , .DATA_B (INT_SUM[447]) , .DATA_C (INT_CARRY[338]) , .SAVE (SUM[38]) , .CARRY (CARRY[38]) ); |
FULL_ADDER FA_305 (.DATA_A (SUMMAND[395]) , .DATA_B (SUMMAND[396]) , .DATA_C (SUMMAND[397]) , .SAVE (INT_SUM[448]) , .CARRY (INT_CARRY[354]) ); |
1488,11 → 1354,11
assign INT_SUM[459] = INT_CARRY[346]; |
FULL_ADDER FA_314 (.DATA_A (INT_SUM[457]) , .DATA_B (INT_SUM[458]) , .DATA_C (INT_SUM[459]) , .SAVE (INT_SUM[460]) , .CARRY (INT_CARRY[363]) ); |
HALF_ADDER HA_37 (.DATA_A (INT_CARRY[347]) , .DATA_B (INT_CARRY[348]) , .SAVE (INT_SUM[462]) , .CARRY (INT_CARRY[365]) ); |
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .CLK (CLK) , .DOUT (INT_SUM[461]) ); |
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .CLK (CLK) , .DOUT (INT_SUM[463]) ); |
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .CLK (CLK) , .DOUT (INT_CARRY[350]) ); |
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[461]) ); |
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[463]) ); |
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[350]) ); |
FULL_ADDER FA_315 (.DATA_A (INT_SUM[461]) , .DATA_B (INT_SUM[463]) , .DATA_C (INT_CARRY[350]) , .SAVE (INT_SUM[464]) , .CARRY (INT_CARRY[367]) ); |
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .CLK (CLK) , .DOUT (INT_CARRY[352]) ); |
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[352]) ); |
assign INT_SUM[465] = INT_CARRY[352]; |
FULL_ADDER FA_316 (.DATA_A (INT_SUM[464]) , .DATA_B (INT_SUM[465]) , .DATA_C (INT_CARRY[353]) , .SAVE (SUM[39]) , .CARRY (CARRY[39]) ); |
FULL_ADDER FA_317 (.DATA_A (SUMMAND[408]) , .DATA_B (SUMMAND[409]) , .DATA_C (SUMMAND[410]) , .SAVE (INT_SUM[466]) , .CARRY (INT_CARRY[368]) ); |
1508,11 → 1374,11
assign INT_SUM[476] = INT_CARRY[360]; |
FULL_ADDER FA_325 (.DATA_A (INT_SUM[473]) , .DATA_B (INT_SUM[474]) , .DATA_C (INT_SUM[475]) , .SAVE (INT_SUM[477]) , .CARRY (INT_CARRY[376]) ); |
FULL_ADDER FA_326 (.DATA_A (INT_SUM[476]) , .DATA_B (INT_CARRY[361]) , .DATA_C (INT_CARRY[362]) , .SAVE (INT_SUM[479]) , .CARRY (INT_CARRY[378]) ); |
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .CLK (CLK) , .DOUT (INT_SUM[478]) ); |
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .CLK (CLK) , .DOUT (INT_SUM[480]) ); |
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .CLK (CLK) , .DOUT (INT_CARRY[364]) ); |
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[478]) ); |
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[480]) ); |
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[364]) ); |
FULL_ADDER FA_327 (.DATA_A (INT_SUM[478]) , .DATA_B (INT_SUM[480]) , .DATA_C (INT_CARRY[364]) , .SAVE (INT_SUM[481]) , .CARRY (INT_CARRY[380]) ); |
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .CLK (CLK) , .DOUT (INT_CARRY[366]) ); |
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[366]) ); |
assign INT_SUM[482] = INT_CARRY[366]; |
FULL_ADDER FA_328 (.DATA_A (INT_SUM[481]) , .DATA_B (INT_SUM[482]) , .DATA_C (INT_CARRY[367]) , .SAVE (SUM[40]) , .CARRY (CARRY[40]) ); |
FULL_ADDER FA_329 (.DATA_A (SUMMAND[421]) , .DATA_B (SUMMAND[422]) , .DATA_C (SUMMAND[423]) , .SAVE (INT_SUM[483]) , .CARRY (INT_CARRY[381]) ); |
1524,11 → 1390,11
FULL_ADDER FA_335 (.DATA_A (INT_CARRY[370]) , .DATA_B (INT_CARRY[371]) , .DATA_C (INT_CARRY[372]) , .SAVE (INT_SUM[489]) , .CARRY (INT_CARRY[387]) ); |
FULL_ADDER FA_336 (.DATA_A (INT_SUM[487]) , .DATA_B (INT_SUM[488]) , .DATA_C (INT_SUM[489]) , .SAVE (INT_SUM[490]) , .CARRY (INT_CARRY[388]) ); |
FULL_ADDER FA_337 (.DATA_A (INT_CARRY[373]) , .DATA_B (INT_CARRY[374]) , .DATA_C (INT_CARRY[375]) , .SAVE (INT_SUM[492]) , .CARRY (INT_CARRY[390]) ); |
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .CLK (CLK) , .DOUT (INT_SUM[491]) ); |
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .CLK (CLK) , .DOUT (INT_SUM[493]) ); |
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .CLK (CLK) , .DOUT (INT_CARRY[377]) ); |
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[491]) ); |
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[493]) ); |
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[377]) ); |
FULL_ADDER FA_338 (.DATA_A (INT_SUM[491]) , .DATA_B (INT_SUM[493]) , .DATA_C (INT_CARRY[377]) , .SAVE (INT_SUM[494]) , .CARRY (INT_CARRY[392]) ); |
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .CLK (CLK) , .DOUT (INT_CARRY[379]) ); |
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[379]) ); |
assign INT_SUM[495] = INT_CARRY[379]; |
FULL_ADDER FA_339 (.DATA_A (INT_SUM[494]) , .DATA_B (INT_SUM[495]) , .DATA_C (INT_CARRY[380]) , .SAVE (SUM[41]) , .CARRY (CARRY[41]) ); |
FULL_ADDER FA_340 (.DATA_A (SUMMAND[433]) , .DATA_B (SUMMAND[434]) , .DATA_C (SUMMAND[435]) , .SAVE (INT_SUM[496]) , .CARRY (INT_CARRY[393]) ); |
1540,11 → 1406,11
HALF_ADDER HA_38 (.DATA_A (INT_CARRY[383]) , .DATA_B (INT_CARRY[384]) , .SAVE (INT_SUM[502]) , .CARRY (INT_CARRY[399]) ); |
FULL_ADDER FA_346 (.DATA_A (INT_SUM[500]) , .DATA_B (INT_SUM[501]) , .DATA_C (INT_SUM[502]) , .SAVE (INT_SUM[503]) , .CARRY (INT_CARRY[400]) ); |
FULL_ADDER FA_347 (.DATA_A (INT_CARRY[385]) , .DATA_B (INT_CARRY[386]) , .DATA_C (INT_CARRY[387]) , .SAVE (INT_SUM[505]) , .CARRY (INT_CARRY[402]) ); |
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .CLK (CLK) , .DOUT (INT_SUM[504]) ); |
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .CLK (CLK) , .DOUT (INT_SUM[506]) ); |
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .CLK (CLK) , .DOUT (INT_CARRY[389]) ); |
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[504]) ); |
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[506]) ); |
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[389]) ); |
FULL_ADDER FA_348 (.DATA_A (INT_SUM[504]) , .DATA_B (INT_SUM[506]) , .DATA_C (INT_CARRY[389]) , .SAVE (INT_SUM[507]) , .CARRY (INT_CARRY[404]) ); |
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .CLK (CLK) , .DOUT (INT_CARRY[391]) ); |
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[391]) ); |
assign INT_SUM[508] = INT_CARRY[391]; |
FULL_ADDER FA_349 (.DATA_A (INT_SUM[507]) , .DATA_B (INT_SUM[508]) , .DATA_C (INT_CARRY[392]) , .SAVE (SUM[42]) , .CARRY (CARRY[42]) ); |
FULL_ADDER FA_350 (.DATA_A (SUMMAND[445]) , .DATA_B (SUMMAND[446]) , .DATA_C (SUMMAND[447]) , .SAVE (INT_SUM[509]) , .CARRY (INT_CARRY[405]) ); |
1557,11 → 1423,11
FULL_ADDER FA_355 (.DATA_A (INT_CARRY[394]) , .DATA_B (INT_CARRY[395]) , .DATA_C (INT_CARRY[396]) , .SAVE (INT_SUM[516]) , .CARRY (INT_CARRY[410]) ); |
FULL_ADDER FA_356 (.DATA_A (INT_SUM[514]) , .DATA_B (INT_SUM[515]) , .DATA_C (INT_SUM[516]) , .SAVE (INT_SUM[517]) , .CARRY (INT_CARRY[411]) ); |
FULL_ADDER FA_357 (.DATA_A (INT_CARRY[397]) , .DATA_B (INT_CARRY[398]) , .DATA_C (INT_CARRY[399]) , .SAVE (INT_SUM[519]) , .CARRY (INT_CARRY[413]) ); |
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .CLK (CLK) , .DOUT (INT_SUM[518]) ); |
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .CLK (CLK) , .DOUT (INT_SUM[520]) ); |
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .CLK (CLK) , .DOUT (INT_CARRY[401]) ); |
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[518]) ); |
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[520]) ); |
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[401]) ); |
FULL_ADDER FA_358 (.DATA_A (INT_SUM[518]) , .DATA_B (INT_SUM[520]) , .DATA_C (INT_CARRY[401]) , .SAVE (INT_SUM[521]) , .CARRY (INT_CARRY[415]) ); |
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .CLK (CLK) , .DOUT (INT_CARRY[403]) ); |
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[403]) ); |
assign INT_SUM[522] = INT_CARRY[403]; |
FULL_ADDER FA_359 (.DATA_A (INT_SUM[521]) , .DATA_B (INT_SUM[522]) , .DATA_C (INT_CARRY[404]) , .SAVE (SUM[43]) , .CARRY (CARRY[43]) ); |
FULL_ADDER FA_360 (.DATA_A (SUMMAND[456]) , .DATA_B (SUMMAND[457]) , .DATA_C (SUMMAND[458]) , .SAVE (INT_SUM[523]) , .CARRY (INT_CARRY[416]) ); |
1573,11 → 1439,11
assign INT_SUM[529] = INT_CARRY[407]; |
FULL_ADDER FA_365 (.DATA_A (INT_SUM[527]) , .DATA_B (INT_SUM[528]) , .DATA_C (INT_SUM[529]) , .SAVE (INT_SUM[530]) , .CARRY (INT_CARRY[422]) ); |
FULL_ADDER FA_366 (.DATA_A (INT_CARRY[408]) , .DATA_B (INT_CARRY[409]) , .DATA_C (INT_CARRY[410]) , .SAVE (INT_SUM[532]) , .CARRY (INT_CARRY[424]) ); |
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .CLK (CLK) , .DOUT (INT_SUM[531]) ); |
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .CLK (CLK) , .DOUT (INT_SUM[533]) ); |
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .CLK (CLK) , .DOUT (INT_CARRY[412]) ); |
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[531]) ); |
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[533]) ); |
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[412]) ); |
FULL_ADDER FA_367 (.DATA_A (INT_SUM[531]) , .DATA_B (INT_SUM[533]) , .DATA_C (INT_CARRY[412]) , .SAVE (INT_SUM[534]) , .CARRY (INT_CARRY[426]) ); |
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .CLK (CLK) , .DOUT (INT_CARRY[414]) ); |
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[414]) ); |
assign INT_SUM[535] = INT_CARRY[414]; |
FULL_ADDER FA_368 (.DATA_A (INT_SUM[534]) , .DATA_B (INT_SUM[535]) , .DATA_C (INT_CARRY[415]) , .SAVE (SUM[44]) , .CARRY (CARRY[44]) ); |
FULL_ADDER FA_369 (.DATA_A (SUMMAND[467]) , .DATA_B (SUMMAND[468]) , .DATA_C (SUMMAND[469]) , .SAVE (INT_SUM[536]) , .CARRY (INT_CARRY[427]) ); |
1590,11 → 1456,11
assign INT_SUM[543] = INT_CARRY[419]; |
FULL_ADDER FA_374 (.DATA_A (INT_SUM[540]) , .DATA_B (INT_SUM[541]) , .DATA_C (INT_SUM[542]) , .SAVE (INT_SUM[544]) , .CARRY (INT_CARRY[432]) ); |
FULL_ADDER FA_375 (.DATA_A (INT_SUM[543]) , .DATA_B (INT_CARRY[420]) , .DATA_C (INT_CARRY[421]) , .SAVE (INT_SUM[546]) , .CARRY (INT_CARRY[434]) ); |
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .CLK (CLK) , .DOUT (INT_SUM[545]) ); |
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .CLK (CLK) , .DOUT (INT_SUM[547]) ); |
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .CLK (CLK) , .DOUT (INT_CARRY[423]) ); |
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[545]) ); |
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[547]) ); |
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[423]) ); |
FULL_ADDER FA_376 (.DATA_A (INT_SUM[545]) , .DATA_B (INT_SUM[547]) , .DATA_C (INT_CARRY[423]) , .SAVE (INT_SUM[548]) , .CARRY (INT_CARRY[436]) ); |
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .CLK (CLK) , .DOUT (INT_CARRY[425]) ); |
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[425]) ); |
assign INT_SUM[549] = INT_CARRY[425]; |
FULL_ADDER FA_377 (.DATA_A (INT_SUM[548]) , .DATA_B (INT_SUM[549]) , .DATA_C (INT_CARRY[426]) , .SAVE (SUM[45]) , .CARRY (CARRY[45]) ); |
FULL_ADDER FA_378 (.DATA_A (SUMMAND[477]) , .DATA_B (SUMMAND[478]) , .DATA_C (SUMMAND[479]) , .SAVE (INT_SUM[550]) , .CARRY (INT_CARRY[437]) ); |
1606,11 → 1472,11
assign INT_SUM[556] = INT_CARRY[429]; |
FULL_ADDER FA_383 (.DATA_A (INT_SUM[554]) , .DATA_B (INT_SUM[555]) , .DATA_C (INT_SUM[556]) , .SAVE (INT_SUM[557]) , .CARRY (INT_CARRY[442]) ); |
HALF_ADDER HA_40 (.DATA_A (INT_CARRY[430]) , .DATA_B (INT_CARRY[431]) , .SAVE (INT_SUM[559]) , .CARRY (INT_CARRY[444]) ); |
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .CLK (CLK) , .DOUT (INT_SUM[558]) ); |
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .CLK (CLK) , .DOUT (INT_SUM[560]) ); |
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .CLK (CLK) , .DOUT (INT_CARRY[433]) ); |
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[558]) ); |
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[560]) ); |
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[433]) ); |
FULL_ADDER FA_384 (.DATA_A (INT_SUM[558]) , .DATA_B (INT_SUM[560]) , .DATA_C (INT_CARRY[433]) , .SAVE (INT_SUM[561]) , .CARRY (INT_CARRY[446]) ); |
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .CLK (CLK) , .DOUT (INT_CARRY[435]) ); |
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[435]) ); |
assign INT_SUM[562] = INT_CARRY[435]; |
FULL_ADDER FA_385 (.DATA_A (INT_SUM[561]) , .DATA_B (INT_SUM[562]) , .DATA_C (INT_CARRY[436]) , .SAVE (SUM[46]) , .CARRY (CARRY[46]) ); |
FULL_ADDER FA_386 (.DATA_A (SUMMAND[487]) , .DATA_B (SUMMAND[488]) , .DATA_C (SUMMAND[489]) , .SAVE (INT_SUM[563]) , .CARRY (INT_CARRY[447]) ); |
1620,11 → 1486,11
FULL_ADDER FA_390 (.DATA_A (INT_CARRY[437]) , .DATA_B (INT_CARRY[438]) , .DATA_C (INT_CARRY[439]) , .SAVE (INT_SUM[567]) , .CARRY (INT_CARRY[451]) ); |
FULL_ADDER FA_391 (.DATA_A (INT_SUM[566]) , .DATA_B (INT_SUM[567]) , .DATA_C (INT_CARRY[440]) , .SAVE (INT_SUM[568]) , .CARRY (INT_CARRY[452]) ); |
assign INT_SUM[570] = INT_CARRY[441]; |
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .CLK (CLK) , .DOUT (INT_SUM[569]) ); |
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .CLK (CLK) , .DOUT (INT_SUM[571]) ); |
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .CLK (CLK) , .DOUT (INT_CARRY[443]) ); |
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[569]) ); |
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[571]) ); |
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[443]) ); |
FULL_ADDER FA_392 (.DATA_A (INT_SUM[569]) , .DATA_B (INT_SUM[571]) , .DATA_C (INT_CARRY[443]) , .SAVE (INT_SUM[572]) , .CARRY (INT_CARRY[454]) ); |
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .CLK (CLK) , .DOUT (INT_CARRY[445]) ); |
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[445]) ); |
assign INT_SUM[573] = INT_CARRY[445]; |
FULL_ADDER FA_393 (.DATA_A (INT_SUM[572]) , .DATA_B (INT_SUM[573]) , .DATA_C (INT_CARRY[446]) , .SAVE (SUM[47]) , .CARRY (CARRY[47]) ); |
FULL_ADDER FA_394 (.DATA_A (SUMMAND[496]) , .DATA_B (SUMMAND[497]) , .DATA_C (SUMMAND[498]) , .SAVE (INT_SUM[574]) , .CARRY (INT_CARRY[455]) ); |
1634,9 → 1500,9
FULL_ADDER FA_398 (.DATA_A (INT_CARRY[447]) , .DATA_B (INT_CARRY[448]) , .DATA_C (INT_CARRY[449]) , .SAVE (INT_SUM[578]) , .CARRY (INT_CARRY[459]) ); |
FULL_ADDER FA_399 (.DATA_A (INT_SUM[577]) , .DATA_B (INT_SUM[578]) , .DATA_C (INT_CARRY[450]) , .SAVE (INT_SUM[579]) , .CARRY (INT_CARRY[460]) ); |
assign INT_SUM[581] = INT_CARRY[451]; |
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .CLK (CLK) , .DOUT (INT_SUM[580]) ); |
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .CLK (CLK) , .DOUT (INT_SUM[582]) ); |
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .CLK (CLK) , .DOUT (INT_CARRY[453]) ); |
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[580]) ); |
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[582]) ); |
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[453]) ); |
FULL_ADDER FA_400 (.DATA_A (INT_SUM[580]) , .DATA_B (INT_SUM[582]) , .DATA_C (INT_CARRY[453]) , .SAVE (INT_SUM[583]) , .CARRY (INT_CARRY[462]) ); |
HALF_ADDER HA_41 (.DATA_A (INT_SUM[583]) , .DATA_B (INT_CARRY[454]) , .SAVE (SUM[48]) , .CARRY (CARRY[48]) ); |
FULL_ADDER FA_401 (.DATA_A (SUMMAND[505]) , .DATA_B (SUMMAND[506]) , .DATA_C (SUMMAND[507]) , .SAVE (INT_SUM[584]) , .CARRY (INT_CARRY[463]) ); |
1645,9 → 1511,9
HALF_ADDER HA_42 (.DATA_A (INT_CARRY[456]) , .DATA_B (INT_CARRY[457]) , .SAVE (INT_SUM[587]) , .CARRY (INT_CARRY[466]) ); |
FULL_ADDER FA_404 (.DATA_A (INT_SUM[584]) , .DATA_B (INT_SUM[585]) , .DATA_C (INT_SUM[586]) , .SAVE (INT_SUM[588]) , .CARRY (INT_CARRY[467]) ); |
FULL_ADDER FA_405 (.DATA_A (INT_SUM[587]) , .DATA_B (INT_CARRY[458]) , .DATA_C (INT_CARRY[459]) , .SAVE (INT_SUM[590]) , .CARRY (INT_CARRY[469]) ); |
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .CLK (CLK) , .DOUT (INT_SUM[589]) ); |
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .CLK (CLK) , .DOUT (INT_SUM[591]) ); |
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .CLK (CLK) , .DOUT (INT_CARRY[461]) ); |
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[589]) ); |
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[591]) ); |
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[461]) ); |
FULL_ADDER FA_406 (.DATA_A (INT_SUM[589]) , .DATA_B (INT_SUM[591]) , .DATA_C (INT_CARRY[461]) , .SAVE (INT_SUM[592]) , .CARRY (INT_CARRY[471]) ); |
HALF_ADDER HA_43 (.DATA_A (INT_SUM[592]) , .DATA_B (INT_CARRY[462]) , .SAVE (SUM[49]) , .CARRY (CARRY[49]) ); |
FULL_ADDER FA_407 (.DATA_A (SUMMAND[513]) , .DATA_B (SUMMAND[514]) , .DATA_C (SUMMAND[515]) , .SAVE (INT_SUM[593]) , .CARRY (INT_CARRY[472]) ); |
1658,11 → 1524,11
assign INT_SUM[598] = INT_SUM[596]; |
FULL_ADDER FA_410 (.DATA_A (INT_SUM[597]) , .DATA_B (INT_SUM[598]) , .DATA_C (INT_CARRY[463]) , .SAVE (INT_SUM[599]) , .CARRY (INT_CARRY[475]) ); |
FULL_ADDER FA_411 (.DATA_A (INT_CARRY[464]) , .DATA_B (INT_CARRY[465]) , .DATA_C (INT_CARRY[466]) , .SAVE (INT_SUM[601]) , .CARRY (INT_CARRY[477]) ); |
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .CLK (CLK) , .DOUT (INT_SUM[600]) ); |
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .CLK (CLK) , .DOUT (INT_SUM[602]) ); |
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .CLK (CLK) , .DOUT (INT_CARRY[468]) ); |
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[600]) ); |
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[602]) ); |
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[468]) ); |
FULL_ADDER FA_412 (.DATA_A (INT_SUM[600]) , .DATA_B (INT_SUM[602]) , .DATA_C (INT_CARRY[468]) , .SAVE (INT_SUM[603]) , .CARRY (INT_CARRY[479]) ); |
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .CLK (CLK) , .DOUT (INT_CARRY[470]) ); |
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[470]) ); |
assign INT_SUM[604] = INT_CARRY[470]; |
FULL_ADDER FA_413 (.DATA_A (INT_SUM[603]) , .DATA_B (INT_SUM[604]) , .DATA_C (INT_CARRY[471]) , .SAVE (SUM[50]) , .CARRY (CARRY[50]) ); |
FULL_ADDER FA_414 (.DATA_A (SUMMAND[521]) , .DATA_B (SUMMAND[522]) , .DATA_C (SUMMAND[523]) , .SAVE (INT_SUM[605]) , .CARRY (INT_CARRY[480]) ); |
1670,11 → 1536,11
FULL_ADDER FA_416 (.DATA_A (SUMMAND[527]) , .DATA_B (INT_CARRY[472]) , .DATA_C (INT_CARRY[473]) , .SAVE (INT_SUM[607]) , .CARRY (INT_CARRY[482]) ); |
FULL_ADDER FA_417 (.DATA_A (INT_SUM[605]) , .DATA_B (INT_SUM[606]) , .DATA_C (INT_SUM[607]) , .SAVE (INT_SUM[608]) , .CARRY (INT_CARRY[483]) ); |
assign INT_SUM[610] = INT_CARRY[474]; |
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .CLK (CLK) , .DOUT (INT_SUM[609]) ); |
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .CLK (CLK) , .DOUT (INT_SUM[611]) ); |
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .CLK (CLK) , .DOUT (INT_CARRY[476]) ); |
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[609]) ); |
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[611]) ); |
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[476]) ); |
FULL_ADDER FA_418 (.DATA_A (INT_SUM[609]) , .DATA_B (INT_SUM[611]) , .DATA_C (INT_CARRY[476]) , .SAVE (INT_SUM[612]) , .CARRY (INT_CARRY[485]) ); |
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .CLK (CLK) , .DOUT (INT_CARRY[478]) ); |
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[478]) ); |
assign INT_SUM[613] = INT_CARRY[478]; |
FULL_ADDER FA_419 (.DATA_A (INT_SUM[612]) , .DATA_B (INT_SUM[613]) , .DATA_C (INT_CARRY[479]) , .SAVE (SUM[51]) , .CARRY (CARRY[51]) ); |
FULL_ADDER FA_420 (.DATA_A (SUMMAND[528]) , .DATA_B (SUMMAND[529]) , .DATA_C (SUMMAND[530]) , .SAVE (INT_SUM[614]) , .CARRY (INT_CARRY[486]) ); |
1682,9 → 1548,9
assign INT_SUM[616] = SUMMAND[534]; |
FULL_ADDER FA_422 (.DATA_A (INT_SUM[614]) , .DATA_B (INT_SUM[615]) , .DATA_C (INT_SUM[616]) , .SAVE (INT_SUM[617]) , .CARRY (INT_CARRY[488]) ); |
FULL_ADDER FA_423 (.DATA_A (INT_CARRY[480]) , .DATA_B (INT_CARRY[481]) , .DATA_C (INT_CARRY[482]) , .SAVE (INT_SUM[619]) , .CARRY (INT_CARRY[490]) ); |
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .CLK (CLK) , .DOUT (INT_SUM[618]) ); |
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .CLK (CLK) , .DOUT (INT_SUM[620]) ); |
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .CLK (CLK) , .DOUT (INT_CARRY[484]) ); |
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[618]) ); |
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[620]) ); |
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[484]) ); |
FULL_ADDER FA_424 (.DATA_A (INT_SUM[618]) , .DATA_B (INT_SUM[620]) , .DATA_C (INT_CARRY[484]) , .SAVE (INT_SUM[621]) , .CARRY (INT_CARRY[492]) ); |
HALF_ADDER HA_44 (.DATA_A (INT_SUM[621]) , .DATA_B (INT_CARRY[485]) , .SAVE (SUM[52]) , .CARRY (CARRY[52]) ); |
FULL_ADDER FA_425 (.DATA_A (SUMMAND[535]) , .DATA_B (SUMMAND[536]) , .DATA_C (SUMMAND[537]) , .SAVE (INT_SUM[622]) , .CARRY (INT_CARRY[493]) ); |
1691,11 → 1557,11
FULL_ADDER FA_426 (.DATA_A (SUMMAND[538]) , .DATA_B (SUMMAND[539]) , .DATA_C (SUMMAND[540]) , .SAVE (INT_SUM[623]) , .CARRY (INT_CARRY[494]) ); |
FULL_ADDER FA_427 (.DATA_A (INT_SUM[622]) , .DATA_B (INT_SUM[623]) , .DATA_C (INT_CARRY[486]) , .SAVE (INT_SUM[624]) , .CARRY (INT_CARRY[495]) ); |
assign INT_SUM[626] = INT_CARRY[487]; |
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .CLK (CLK) , .DOUT (INT_SUM[625]) ); |
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .CLK (CLK) , .DOUT (INT_SUM[627]) ); |
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .CLK (CLK) , .DOUT (INT_CARRY[489]) ); |
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[625]) ); |
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[627]) ); |
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[489]) ); |
FULL_ADDER FA_428 (.DATA_A (INT_SUM[625]) , .DATA_B (INT_SUM[627]) , .DATA_C (INT_CARRY[489]) , .SAVE (INT_SUM[628]) , .CARRY (INT_CARRY[497]) ); |
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .CLK (CLK) , .DOUT (INT_CARRY[491]) ); |
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[491]) ); |
assign INT_SUM[629] = INT_CARRY[491]; |
FULL_ADDER FA_429 (.DATA_A (INT_SUM[628]) , .DATA_B (INT_SUM[629]) , .DATA_C (INT_CARRY[492]) , .SAVE (SUM[53]) , .CARRY (CARRY[53]) ); |
FULL_ADDER FA_430 (.DATA_A (SUMMAND[541]) , .DATA_B (SUMMAND[542]) , .DATA_C (SUMMAND[543]) , .SAVE (INT_SUM[630]) , .CARRY (INT_CARRY[498]) ); |
1702,9 → 1568,9
FULL_ADDER FA_431 (.DATA_A (SUMMAND[544]) , .DATA_B (SUMMAND[545]) , .DATA_C (SUMMAND[546]) , .SAVE (INT_SUM[631]) , .CARRY (INT_CARRY[499]) ); |
FULL_ADDER FA_432 (.DATA_A (INT_SUM[630]) , .DATA_B (INT_SUM[631]) , .DATA_C (INT_CARRY[493]) , .SAVE (INT_SUM[632]) , .CARRY (INT_CARRY[500]) ); |
assign INT_SUM[634] = INT_CARRY[494]; |
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .CLK (CLK) , .DOUT (INT_SUM[633]) ); |
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .CLK (CLK) , .DOUT (INT_SUM[635]) ); |
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .CLK (CLK) , .DOUT (INT_CARRY[496]) ); |
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[633]) ); |
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[635]) ); |
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[496]) ); |
FULL_ADDER FA_433 (.DATA_A (INT_SUM[633]) , .DATA_B (INT_SUM[635]) , .DATA_C (INT_CARRY[496]) , .SAVE (INT_SUM[636]) , .CARRY (INT_CARRY[502]) ); |
HALF_ADDER HA_45 (.DATA_A (INT_SUM[636]) , .DATA_B (INT_CARRY[497]) , .SAVE (SUM[54]) , .CARRY (CARRY[54]) ); |
FULL_ADDER FA_434 (.DATA_A (SUMMAND[547]) , .DATA_B (SUMMAND[548]) , .DATA_C (SUMMAND[549]) , .SAVE (INT_SUM[637]) , .CARRY (INT_CARRY[503]) ); |
1711,9 → 1577,9
HALF_ADDER HA_46 (.DATA_A (SUMMAND[550]) , .DATA_B (SUMMAND[551]) , .SAVE (INT_SUM[638]) , .CARRY (INT_CARRY[504]) ); |
FULL_ADDER FA_435 (.DATA_A (INT_SUM[637]) , .DATA_B (INT_SUM[638]) , .DATA_C (INT_CARRY[498]) , .SAVE (INT_SUM[639]) , .CARRY (INT_CARRY[505]) ); |
assign INT_SUM[641] = INT_CARRY[499]; |
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .CLK (CLK) , .DOUT (INT_SUM[640]) ); |
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .CLK (CLK) , .DOUT (INT_SUM[642]) ); |
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .CLK (CLK) , .DOUT (INT_CARRY[501]) ); |
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[640]) ); |
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[642]) ); |
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[501]) ); |
FULL_ADDER FA_436 (.DATA_A (INT_SUM[640]) , .DATA_B (INT_SUM[642]) , .DATA_C (INT_CARRY[501]) , .SAVE (INT_SUM[643]) , .CARRY (INT_CARRY[507]) ); |
HALF_ADDER HA_47 (.DATA_A (INT_SUM[643]) , .DATA_B (INT_CARRY[502]) , .SAVE (SUM[55]) , .CARRY (CARRY[55]) ); |
FULL_ADDER FA_437 (.DATA_A (SUMMAND[552]) , .DATA_B (SUMMAND[553]) , .DATA_C (SUMMAND[554]) , .SAVE (INT_SUM[644]) , .CARRY (INT_CARRY[508]) ); |
1720,49 → 1586,49
HALF_ADDER HA_48 (.DATA_A (SUMMAND[555]) , .DATA_B (SUMMAND[556]) , .SAVE (INT_SUM[645]) , .CARRY (INT_CARRY[509]) ); |
FULL_ADDER FA_438 (.DATA_A (INT_SUM[644]) , .DATA_B (INT_SUM[645]) , .DATA_C (INT_CARRY[503]) , .SAVE (INT_SUM[646]) , .CARRY (INT_CARRY[510]) ); |
assign INT_SUM[648] = INT_CARRY[504]; |
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .CLK (CLK) , .DOUT (INT_SUM[647]) ); |
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .CLK (CLK) , .DOUT (INT_SUM[649]) ); |
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .CLK (CLK) , .DOUT (INT_CARRY[506]) ); |
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[647]) ); |
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[649]) ); |
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[506]) ); |
FULL_ADDER FA_439 (.DATA_A (INT_SUM[647]) , .DATA_B (INT_SUM[649]) , .DATA_C (INT_CARRY[506]) , .SAVE (INT_SUM[650]) , .CARRY (INT_CARRY[512]) ); |
HALF_ADDER HA_49 (.DATA_A (INT_SUM[650]) , .DATA_B (INT_CARRY[507]) , .SAVE (SUM[56]) , .CARRY (CARRY[56]) ); |
FULL_ADDER FA_440 (.DATA_A (SUMMAND[557]) , .DATA_B (SUMMAND[558]) , .DATA_C (SUMMAND[559]) , .SAVE (INT_SUM[651]) , .CARRY (INT_CARRY[513]) ); |
FULL_ADDER FA_441 (.DATA_A (SUMMAND[560]) , .DATA_B (INT_CARRY[508]) , .DATA_C (INT_CARRY[509]) , .SAVE (INT_SUM[653]) , .CARRY (INT_CARRY[515]) ); |
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .CLK (CLK) , .DOUT (INT_SUM[652]) ); |
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .CLK (CLK) , .DOUT (INT_SUM[654]) ); |
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .CLK (CLK) , .DOUT (INT_CARRY[511]) ); |
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[652]) ); |
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[654]) ); |
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[511]) ); |
FULL_ADDER FA_442 (.DATA_A (INT_SUM[652]) , .DATA_B (INT_SUM[654]) , .DATA_C (INT_CARRY[511]) , .SAVE (INT_SUM[655]) , .CARRY (INT_CARRY[517]) ); |
HALF_ADDER HA_50 (.DATA_A (INT_SUM[655]) , .DATA_B (INT_CARRY[512]) , .SAVE (SUM[57]) , .CARRY (CARRY[57]) ); |
FULL_ADDER FA_443 (.DATA_A (SUMMAND[561]) , .DATA_B (SUMMAND[562]) , .DATA_C (SUMMAND[563]) , .SAVE (INT_SUM[656]) , .CARRY (INT_CARRY[518]) ); |
assign INT_SUM[658] = SUMMAND[564]; |
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .CLK (CLK) , .DOUT (INT_SUM[657]) ); |
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .CLK (CLK) , .DOUT (INT_SUM[659]) ); |
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .CLK (CLK) , .DOUT (INT_CARRY[514]) ); |
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[657]) ); |
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[659]) ); |
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[514]) ); |
FULL_ADDER FA_444 (.DATA_A (INT_SUM[657]) , .DATA_B (INT_SUM[659]) , .DATA_C (INT_CARRY[514]) , .SAVE (INT_SUM[660]) , .CARRY (INT_CARRY[520]) ); |
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .CLK (CLK) , .DOUT (INT_CARRY[516]) ); |
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[516]) ); |
assign INT_SUM[661] = INT_CARRY[516]; |
FULL_ADDER FA_445 (.DATA_A (INT_SUM[660]) , .DATA_B (INT_SUM[661]) , .DATA_C (INT_CARRY[517]) , .SAVE (SUM[58]) , .CARRY (CARRY[58]) ); |
FULL_ADDER FA_446 (.DATA_A (SUMMAND[565]) , .DATA_B (SUMMAND[566]) , .DATA_C (SUMMAND[567]) , .SAVE (INT_SUM[662]) , .CARRY (INT_CARRY[521]) ); |
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .CLK (CLK) , .DOUT (INT_SUM[663]) ); |
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[663]) ); |
assign INT_SUM[664] = INT_SUM[663]; |
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .CLK (CLK) , .DOUT (INT_CARRY[519]) ); |
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[519]) ); |
assign INT_SUM[665] = INT_CARRY[519]; |
FULL_ADDER FA_447 (.DATA_A (INT_SUM[664]) , .DATA_B (INT_SUM[665]) , .DATA_C (INT_CARRY[520]) , .SAVE (SUM[59]) , .CARRY (CARRY[59]) ); |
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .CLK (CLK) , .DOUT (LATCHED_PP[0]) ); |
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .CLK (CLK) , .DOUT (LATCHED_PP[1]) ); |
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .CLK (CLK) , .DOUT (LATCHED_PP[2]) ); |
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[0]) ); |
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[1]) ); |
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[2]) ); |
FULL_ADDER FA_448 (.DATA_A (LATCHED_PP[0]) , .DATA_B (LATCHED_PP[1]) , .DATA_C (LATCHED_PP[2]) , .SAVE (INT_SUM[666]) , .CARRY (INT_CARRY[523]) ); |
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .CLK (CLK) , .DOUT (INT_CARRY[522]) ); |
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[522]) ); |
assign INT_SUM[667] = INT_CARRY[522]; |
HALF_ADDER HA_51 (.DATA_A (INT_SUM[666]) , .DATA_B (INT_SUM[667]) , .SAVE (SUM[60]) , .CARRY (CARRY[60]) ); |
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .CLK (CLK) , .DOUT (LATCHED_PP[3]) ); |
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[3]) ); |
assign INT_SUM[668] = LATCHED_PP[3]; |
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .CLK (CLK) , .DOUT (LATCHED_PP[4]) ); |
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[4]) ); |
assign INT_SUM[669] = LATCHED_PP[4]; |
FULL_ADDER FA_449 (.DATA_A (INT_SUM[668]) , .DATA_B (INT_SUM[669]) , .DATA_C (INT_CARRY[523]) , .SAVE (SUM[61]) , .CARRY (CARRY[61]) ); |
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .CLK (CLK) , .DOUT (LATCHED_PP[5]) ); |
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .CLK (CLK) , .DOUT (LATCHED_PP[6]) ); |
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[5]) ); |
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[6]) ); |
HALF_ADDER HA_52 (.DATA_A (LATCHED_PP[5]) , .DATA_B (LATCHED_PP[6]) , .SAVE (SUM[62]) , .CARRY (CARRY[62]) ); |
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .CLK (CLK) , .DOUT (LATCHED_PP[7]) ); |
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[7]) ); |
assign SUM[63] = LATCHED_PP[7]; |
endmodule |
|
2479,9 → 2345,10
endmodule |
|
|
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, CLK, PHI, RESULT ); |
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, RST, CLK, PHI, RESULT ); |
input [0:32] MULTIPLICAND; |
input [0:31] MULTIPLIER; |
input RST; |
input CLK; |
input PHI; |
output [0:63] RESULT; |
2491,9 → 2358,154
wire LOGIC_ZERO; |
assign LOGIC_ZERO = 0; |
BOOTHCODER_33_32 B (.OPA(MULTIPLICAND[0:32]) , .OPB(MULTIPLIER[0:31]) , .SUMMAND(PPBIT[0:575]) ); |
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) ); |
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) ); |
assign INT_CARRY[0] = LOGIC_ZERO; |
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(RESULT[0:63]), .COUT() ); |
endmodule |
|
|
// 32x32 multiplier, no input/output registers |
// Registers inside Wallace trees every 8 full adder levels, |
// with first pipeline after level 4 |
|
module multp2_32x32 ( X, Y, RST, CLK, P ); |
input [31:0] X; |
input [31:0] Y; |
input RST; |
input CLK; |
output [63:0] P; |
wire [0:32] A; |
wire [0:31] B; |
wire [0:63] Q; |
assign A[0] = X[0]; |
assign A[1] = X[1]; |
assign A[2] = X[2]; |
assign A[3] = X[3]; |
assign A[4] = X[4]; |
assign A[5] = X[5]; |
assign A[6] = X[6]; |
assign A[7] = X[7]; |
assign A[8] = X[8]; |
assign A[9] = X[9]; |
assign A[10] = X[10]; |
assign A[11] = X[11]; |
assign A[12] = X[12]; |
assign A[13] = X[13]; |
assign A[14] = X[14]; |
assign A[15] = X[15]; |
assign A[16] = X[16]; |
assign A[17] = X[17]; |
assign A[18] = X[18]; |
assign A[19] = X[19]; |
assign A[20] = X[20]; |
assign A[21] = X[21]; |
assign A[22] = X[22]; |
assign A[23] = X[23]; |
assign A[24] = X[24]; |
assign A[25] = X[25]; |
assign A[26] = X[26]; |
assign A[27] = X[27]; |
assign A[28] = X[28]; |
assign A[29] = X[29]; |
assign A[30] = X[30]; |
assign A[31] = X[31]; |
assign A[32] = X[31]; |
assign B[0] = Y[0]; |
assign B[1] = Y[1]; |
assign B[2] = Y[2]; |
assign B[3] = Y[3]; |
assign B[4] = Y[4]; |
assign B[5] = Y[5]; |
assign B[6] = Y[6]; |
assign B[7] = Y[7]; |
assign B[8] = Y[8]; |
assign B[9] = Y[9]; |
assign B[10] = Y[10]; |
assign B[11] = Y[11]; |
assign B[12] = Y[12]; |
assign B[13] = Y[13]; |
assign B[14] = Y[14]; |
assign B[15] = Y[15]; |
assign B[16] = Y[16]; |
assign B[17] = Y[17]; |
assign B[18] = Y[18]; |
assign B[19] = Y[19]; |
assign B[20] = Y[20]; |
assign B[21] = Y[21]; |
assign B[22] = Y[22]; |
assign B[23] = Y[23]; |
assign B[24] = Y[24]; |
assign B[25] = Y[25]; |
assign B[26] = Y[26]; |
assign B[27] = Y[27]; |
assign B[28] = Y[28]; |
assign B[29] = Y[29]; |
assign B[30] = Y[30]; |
assign B[31] = Y[31]; |
assign P[0] = Q[0]; |
assign P[1] = Q[1]; |
assign P[2] = Q[2]; |
assign P[3] = Q[3]; |
assign P[4] = Q[4]; |
assign P[5] = Q[5]; |
assign P[6] = Q[6]; |
assign P[7] = Q[7]; |
assign P[8] = Q[8]; |
assign P[9] = Q[9]; |
assign P[10] = Q[10]; |
assign P[11] = Q[11]; |
assign P[12] = Q[12]; |
assign P[13] = Q[13]; |
assign P[14] = Q[14]; |
assign P[15] = Q[15]; |
assign P[16] = Q[16]; |
assign P[17] = Q[17]; |
assign P[18] = Q[18]; |
assign P[19] = Q[19]; |
assign P[20] = Q[20]; |
assign P[21] = Q[21]; |
assign P[22] = Q[22]; |
assign P[23] = Q[23]; |
assign P[24] = Q[24]; |
assign P[25] = Q[25]; |
assign P[26] = Q[26]; |
assign P[27] = Q[27]; |
assign P[28] = Q[28]; |
assign P[29] = Q[29]; |
assign P[30] = Q[30]; |
assign P[31] = Q[31]; |
assign P[32] = Q[32]; |
assign P[33] = Q[33]; |
assign P[34] = Q[34]; |
assign P[35] = Q[35]; |
assign P[36] = Q[36]; |
assign P[37] = Q[37]; |
assign P[38] = Q[38]; |
assign P[39] = Q[39]; |
assign P[40] = Q[40]; |
assign P[41] = Q[41]; |
assign P[42] = Q[42]; |
assign P[43] = Q[43]; |
assign P[44] = Q[44]; |
assign P[45] = Q[45]; |
assign P[46] = Q[46]; |
assign P[47] = Q[47]; |
assign P[48] = Q[48]; |
assign P[49] = Q[49]; |
assign P[50] = Q[50]; |
assign P[51] = Q[51]; |
assign P[52] = Q[52]; |
assign P[53] = Q[53]; |
assign P[54] = Q[54]; |
assign P[55] = Q[55]; |
assign P[56] = Q[56]; |
assign P[57] = Q[57]; |
assign P[58] = Q[58]; |
assign P[59] = Q[59]; |
assign P[60] = Q[60]; |
assign P[61] = Q[61]; |
assign P[62] = Q[62]; |
assign P[63] = Q[63]; |
MULTIPLIER_33_32 U1 (.MULTIPLICAND(A) , .MULTIPLIER(B) , .RST(RST), .CLK(CLK) , .PHI(1'b0) , .RESULT(Q) ); |
endmodule |
|
/trunk/or1200/rtl/verilog/generic_spram_64x14.v
0,0 → 1,237
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// - Artisan Single-Port Sync RAM //// |
//// - Avant! Two-Port Sync RAM (*) //// |
//// - Virage Single-Port Sync RAM //// |
//// - Virtual Silicon Single-Port Sync RAM //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// //// |
//// To Do: //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs (Altera etc) //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_64x14( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 6; |
parameter dw = 14; |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
|
|
`ifdef ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
); |
|
`else |
|
`ifdef AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
avant_atp avant_atp( |
.web(~we), |
.reb(), |
.oeb(~oe), |
.rcsb(), |
.wcsb(), |
.ra(addr), |
.wa(addr), |
.di(di), |
.do(do) |
); |
|
`else |
|
`ifdef VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
virage_ssp virage_ssp( |
.clk(clk), |
.adr(addr), |
.d(di), |
.we(we), |
.oe(oe), |
.me(ce), |
.q(do) |
); |
|
`else |
|
`ifdef VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
.WEN(~we), |
.CEN(~ce), |
.OEN(~oe), |
.DOUT(do) |
); |
|
`else |
|
`ifdef XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S16 ramb4_s16_0( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[13:0]), |
.EN(ce), |
.WE(we), |
.DO(do[13:0]) |
); |
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !XILINX_RAMB4_S16 |
`endif // !VIRTUALSILICON_SSP |
`endif // !VIRAGE_SSP |
`endif // !AVANT_ATP |
`endif // !ARTISAN_SSP |
|
endmodule |
trunk/or1200/rtl/verilog/generic_spram_64x14.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/dc_ram.v
===================================================================
--- trunk/or1200/rtl/verilog/dc_ram.v (revision 202)
+++ trunk/or1200/rtl/verilog/dc_ram.v (revision 203)
@@ -44,12 +44,17 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
module dc_ram(
@@ -57,7 +62,7 @@
clk, rst,
// Internal i/f
- addr, we, datain, dataout
+ addr, en, we, datain, dataout
);
parameter dw = `OPERAND_WIDTH;
@@ -69,17 +74,28 @@
input clk;
input rst;
input [aw-1:0] addr;
+input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
+`ifdef OR1200_NO_DC
+
//
+// Data cache not implemented
+//
+
+assign dataout = {dw{1'b0}};
+
+`else
+
+//
// Instantiation of RAM block 0
//
generic_spram_2048x8 dc_ram0(
.clk(clk),
.rst(rst),
- .ce(1'b1),
+ .ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
@@ -93,7 +109,7 @@
generic_spram_2048x8 dc_ram1(
.clk(clk),
.rst(rst),
- .ce(1'b1),
+ .ce(en),
.we(we[1]),
.oe(1'b1),
.addr(addr),
@@ -107,7 +123,7 @@
generic_spram_2048x8 dc_ram2(
.clk(clk),
.rst(rst),
- .ce(1'b1),
+ .ce(en),
.we(we[2]),
.oe(1'b1),
.addr(addr),
@@ -121,7 +137,7 @@
generic_spram_2048x8 dc_ram3(
.clk(clk),
.rst(rst),
- .ce(1'b1),
+ .ce(en),
.we(we[3]),
.oe(1'b1),
.addr(addr),
@@ -129,4 +145,6 @@
.do(dataout[31:24])
);
+`endif
+
endmodule
/trunk/or1200/rtl/verilog/dtlb.v
0,0 → 1,218
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1200's Data TLB //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// Instantiation of DTLB. //// |
//// //// |
//// To Do: //// |
//// - make it smaller and faster //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// |
// Data TLB |
// |
|
module dtlb( |
// Rst and clk |
clk, rst, |
|
// I/F for translation |
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, |
|
// SPR access |
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o |
); |
|
parameter dw = `OPERAND_WIDTH; |
parameter aw = `OPERAND_WIDTH; |
|
// |
// I/O |
// |
|
// |
// Clock and reset |
// |
input clk; |
input rst; |
|
// |
// I/F for translation |
// |
input tlb_en; |
input [aw-1:0] vaddr; |
output hit; |
output [31:13] ppn; |
output uwe; |
output ure; |
output swe; |
output sre; |
|
// |
// SPR access |
// |
input spr_cs; |
input spr_write; |
input [31:0] spr_addr; |
input [31:0] spr_dat_i; |
output [31:0] spr_dat_o; |
|
// |
// Internal wires and regs |
// |
wire [31:19] vpn; |
wire v; |
wire [5:0] tlb_index; |
wire tlb_mr_en; |
wire tlb_mr_we; |
wire [13:0] tlb_mr_ram_in; |
wire [13:0] tlb_mr_ram_out; |
wire tlb_tr_en; |
wire tlb_tr_we; |
wire [22:0] tlb_tr_ram_in; |
wire [22:0] tlb_tr_ram_out; |
|
// |
// Implemented bits inside match and translate registers |
// |
// dtlbwYmrX: vpn 31-19 v 0 |
// dtlbwYtrX: ppn 31-13 uwe 9 ure 8 swe 7 sre 6 |
// |
// dtlb memory width: |
// 19 bits for ppn |
// 13 bits for vpn |
// 1 bit for valid |
// 4 bits for protection |
|
// |
// Enable for Match registers |
// |
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[9]); |
|
// |
// Write enable for Match registers |
// |
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9]; |
|
// |
// Enable for Translate registers |
// |
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[9]); |
|
// |
// Write enable for Translate registers |
// |
assign tlb_tr_we = spr_cs & spr_write & spr_addr[9]; |
|
// |
// Output to SPRS unit |
// |
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ? |
{vpn, {18{1'b1}}, v} : |
(spr_cs & !spr_write & spr_addr[9]) ? |
{ppn, 3'b000, uwe, ure, swe, sre, {6{1'b1}}} : |
32'h00000000; |
|
// |
// Assign outputs from Match registers |
// |
assign {vpn, v} = tlb_mr_ram_out; |
|
// |
// Assign to Match registers inputs |
// |
assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]}; |
|
// |
// Assign outputs from Translate registers |
// |
assign {ppn, uwe, ure, swe, sre} = tlb_tr_ram_out; |
|
// |
// Assign to Translate registers inputs |
// |
assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[9:6]}; |
|
// |
// Generate hit |
// |
assign hit = (vpn == vaddr[31:19]) & v; |
|
// |
// TLB index is normally vaddr[18:13]. If it is SPR access then index is |
// spr_addr[5:0]. |
// |
assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13]; |
|
// |
// Instantiation of DTLB Match Registers |
// |
generic_spram_64x14 dtlb_mr_ram( |
.clk(clk), |
.rst(rst), |
.ce(tlb_mr_en), |
.we(tlb_mr_we), |
.oe(1'b1), |
.addr(tlb_index), |
.di(tlb_mr_ram_in), |
.do(tlb_mr_ram_out) |
); |
|
// |
// Instantiation of DTLB Translate Registers |
// |
generic_spram_64x23 dtlb_tr_ram( |
.clk(clk), |
.rst(rst), |
.ce(tlb_tr_en), |
.we(tlb_tr_we), |
.oe(1'b1), |
.addr(tlb_index), |
.di(tlb_tr_ram_in), |
.do(tlb_tr_ram_out) |
); |
|
endmodule |
/trunk/or1200/rtl/verilog/sprs.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
63,7 → 66,7
flag, addrbase, addrofs, dat_i, alu_op, branch_op, |
epcr, eear, esr, except_start, except_started, |
to_wbmux, epcr_we, eear_we, esr_we, sr, |
spr_dat_cfgr, |
spr_dat_cfgr, spr_dat_dmmu, |
|
// From/to other RISC units |
spr_dat_pic, spr_dat_tt, spr_dat_pm, |
105,6 → 108,7
input [31:0] spr_dat_pic; // Data from PIC |
input [31:0] spr_dat_tt; // Data from TT |
input [31:0] spr_dat_pm; // Data from PM |
input [31:0] spr_dat_dmmu; // Data from DMMU |
output [31:0] spr_addr; // SPR Address |
output [31:0] spr_dataout; // Data to unit |
output [31:0] spr_cs; // Unit select |
147,37 → 151,38
// |
always @(spr_addr) |
case (spr_addr[`SPR_GROUP_BITS]) // synopsys parallel_case |
`SPR_GROUP_WIDTH'd00: spr_cs <= 32'b00000000_00000000_00000000_00000001; |
`SPR_GROUP_WIDTH'd01: spr_cs <= 32'b00000000_00000000_00000000_00000010; |
`SPR_GROUP_WIDTH'd02: spr_cs <= 32'b00000000_00000000_00000000_00000100; |
`SPR_GROUP_WIDTH'd03: spr_cs <= 32'b00000000_00000000_00000000_00001000; |
`SPR_GROUP_WIDTH'd04: spr_cs <= 32'b00000000_00000000_00000000_00010000; |
`SPR_GROUP_WIDTH'd05: spr_cs <= 32'b00000000_00000000_00000000_00100000; |
`SPR_GROUP_WIDTH'd06: spr_cs <= 32'b00000000_00000000_00000000_01000000; |
`SPR_GROUP_WIDTH'd07: spr_cs <= 32'b00000000_00000000_00000000_10000000; |
`SPR_GROUP_WIDTH'd08: spr_cs <= 32'b00000000_00000000_00000001_00000000; |
`SPR_GROUP_WIDTH'd09: spr_cs <= 32'b00000000_00000000_00000010_00000000; |
`SPR_GROUP_WIDTH'd10: spr_cs <= 32'b00000000_00000000_00000100_00000000; |
`SPR_GROUP_WIDTH'd11: spr_cs <= 32'b00000000_00000000_00001000_00000000; |
`SPR_GROUP_WIDTH'd12: spr_cs <= 32'b00000000_00000000_00010000_00000000; |
`SPR_GROUP_WIDTH'd13: spr_cs <= 32'b00000000_00000000_00100000_00000000; |
`SPR_GROUP_WIDTH'd14: spr_cs <= 32'b00000000_00000000_01000000_00000000; |
`SPR_GROUP_WIDTH'd15: spr_cs <= 32'b00000000_00000000_10000000_00000000; |
`SPR_GROUP_WIDTH'd16: spr_cs <= 32'b00000000_00000001_00000000_00000000; |
`SPR_GROUP_WIDTH'd17: spr_cs <= 32'b00000000_00000010_00000000_00000000; |
`SPR_GROUP_WIDTH'd18: spr_cs <= 32'b00000000_00000100_00000000_00000000; |
`SPR_GROUP_WIDTH'd19: spr_cs <= 32'b00000000_00001000_00000000_00000000; |
`SPR_GROUP_WIDTH'd20: spr_cs <= 32'b00000000_00010000_00000000_00000000; |
`SPR_GROUP_WIDTH'd21: spr_cs <= 32'b00000000_00100000_00000000_00000000; |
`SPR_GROUP_WIDTH'd22: spr_cs <= 32'b00000000_01000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd23: spr_cs <= 32'b00000000_10000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd24: spr_cs <= 32'b00000001_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd25: spr_cs <= 32'b00000010_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd26: spr_cs <= 32'b00000100_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd27: spr_cs <= 32'b00001000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd28: spr_cs <= 32'b00010000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd29: spr_cs <= 32'b00100000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd30: spr_cs <= 32'b01000000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd00: spr_cs = 32'b00000000_00000000_00000000_00000001; |
`SPR_GROUP_WIDTH'd01: spr_cs = 32'b00000000_00000000_00000000_00000010; |
`SPR_GROUP_WIDTH'd02: spr_cs = 32'b00000000_00000000_00000000_00000100; |
`SPR_GROUP_WIDTH'd03: spr_cs = 32'b00000000_00000000_00000000_00001000; |
`SPR_GROUP_WIDTH'd04: spr_cs = 32'b00000000_00000000_00000000_00010000; |
`SPR_GROUP_WIDTH'd05: spr_cs = 32'b00000000_00000000_00000000_00100000; |
`SPR_GROUP_WIDTH'd06: spr_cs = 32'b00000000_00000000_00000000_01000000; |
`SPR_GROUP_WIDTH'd07: spr_cs = 32'b00000000_00000000_00000000_10000000; |
`SPR_GROUP_WIDTH'd08: spr_cs = 32'b00000000_00000000_00000001_00000000; |
`SPR_GROUP_WIDTH'd09: spr_cs = 32'b00000000_00000000_00000010_00000000; |
`SPR_GROUP_WIDTH'd10: spr_cs = 32'b00000000_00000000_00000100_00000000; |
`SPR_GROUP_WIDTH'd11: spr_cs = 32'b00000000_00000000_00001000_00000000; |
`SPR_GROUP_WIDTH'd12: spr_cs = 32'b00000000_00000000_00010000_00000000; |
`SPR_GROUP_WIDTH'd13: spr_cs = 32'b00000000_00000000_00100000_00000000; |
`SPR_GROUP_WIDTH'd14: spr_cs = 32'b00000000_00000000_01000000_00000000; |
`SPR_GROUP_WIDTH'd15: spr_cs = 32'b00000000_00000000_10000000_00000000; |
`SPR_GROUP_WIDTH'd16: spr_cs = 32'b00000000_00000001_00000000_00000000; |
`SPR_GROUP_WIDTH'd17: spr_cs = 32'b00000000_00000010_00000000_00000000; |
`SPR_GROUP_WIDTH'd18: spr_cs = 32'b00000000_00000100_00000000_00000000; |
`SPR_GROUP_WIDTH'd19: spr_cs = 32'b00000000_00001000_00000000_00000000; |
`SPR_GROUP_WIDTH'd20: spr_cs = 32'b00000000_00010000_00000000_00000000; |
`SPR_GROUP_WIDTH'd21: spr_cs = 32'b00000000_00100000_00000000_00000000; |
`SPR_GROUP_WIDTH'd22: spr_cs = 32'b00000000_01000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd23: spr_cs = 32'b00000000_10000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd24: spr_cs = 32'b00000001_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd25: spr_cs = 32'b00000010_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd26: spr_cs = 32'b00000100_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd27: spr_cs = 32'b00001000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd28: spr_cs = 32'b00010000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd29: spr_cs = 32'b00100000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd30: spr_cs = 32'b01000000_00000000_00000000_00000000; |
`SPR_GROUP_WIDTH'd31: spr_cs = 32'b10000000_00000000_00000000_00000000; |
endcase |
|
// |
222,12 → 227,20
if (rst) |
sr <= #1 `SR_WIDTH'b011; |
else if (except_started) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared."); |
// synopsys translate_on |
`endif |
sr[`SR_SUPV] <= #1 1'b1; |
sr[`SR_EXR] <= #1 1'b0; |
end |
else if (sr_we) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: writing into SR register: %h", dat_i); |
// synopsys translate_on |
`endif |
sr <= #1 to_sr; |
end |
|
234,34 → 247,40
// |
// MTSPR/MFSPR interface |
// |
always @(alu_op or spr_addr or dat_i or sys_data or spr_dat_pic or spr_dat_pm or spr_dat_tt) begin |
always @(alu_op or spr_addr or dat_i or sys_data or spr_dat_pic or spr_dat_pm or spr_dat_dmmu or spr_dat_tt) begin |
case (alu_op) // synopsys full_case parallel_case |
`ALUOP_MTSR : begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, dat_i); |
write_spr <= #1 1'b1; |
read_spr <= #1 1'b0; |
to_wbmux <= #1 32'b0; |
// synopsys translate_on |
`endif |
write_spr = 1'b1; |
read_spr = 1'b0; |
to_wbmux = 32'b0; |
end |
`ALUOP_MFSR : begin |
casex (spr_addr[`SPR_GROUP_BITS]) |
`SPR_GROUP_TT: |
to_wbmux <= #1 spr_dat_tt; |
to_wbmux = spr_dat_tt; |
`SPR_GROUP_PIC: |
to_wbmux <= #1 spr_dat_pic; |
to_wbmux = spr_dat_pic; |
`SPR_GROUP_PM: |
to_wbmux <= #1 spr_dat_pm; |
to_wbmux = spr_dat_pm; |
`SPR_GROUP_DMMU: |
to_wbmux = spr_dat_dmmu; |
`SPR_GROUP_SYS: |
to_wbmux <= #1 sys_data; |
to_wbmux = sys_data; |
default: |
to_wbmux <= #1 32'b0; |
to_wbmux = 32'b0; |
endcase |
write_spr <= #1 1'b0; |
read_spr <= #1 1'b1; |
write_spr = 1'b0; |
read_spr = 1'b1; |
end |
default : begin |
write_spr <= #1 1'b0; |
read_spr <= #1 1'b0; |
to_wbmux <= #1 32'b0; |
write_spr = 1'b0; |
read_spr = 1'b0; |
to_wbmux = 32'b0; |
end |
endcase |
end |
/trunk/or1200/rtl/verilog/tt.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:23 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module tt( |
/trunk/or1200/rtl/verilog/generic_spram_64x37.v
0,0 → 1,263
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// - Artisan Single-Port Sync RAM //// |
//// - Avant! Two-Port Sync RAM (*) //// |
//// - Virage Single-Port Sync RAM //// |
//// - Virtual Silicon Single-Port Sync RAM //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// //// |
//// To Do: //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs (Altera etc) //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_64x37( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 6; |
parameter dw = 37; |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
|
|
`ifdef ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_64x37 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
); |
|
`else |
|
`ifdef AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
avant_atp avant_atp( |
.web(~we), |
.reb(), |
.oeb(~oe), |
.rcsb(), |
.wcsb(), |
.ra(addr), |
.wa(addr), |
.di(di), |
.do(do) |
); |
|
`else |
|
`ifdef VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
virage_ssp virage_ssp( |
.clk(clk), |
.adr(addr), |
.d(di), |
.we(we), |
.oe(oe), |
.me(ce), |
.q(do) |
); |
|
`else |
|
`ifdef VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
.WEN(~we), |
.CEN(~ce), |
.OEN(~oe), |
.DOUT(do) |
); |
|
`else |
|
`ifdef XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S16 ramb4_s16_0( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[15:0]), |
.EN(ce), |
.WE(we), |
.DO(do[15:0]) |
); |
|
// |
// Block 1 |
// |
RAMB4_S16 ramb4_s16_1( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[31:16]), |
.EN(ce), |
.WE(we), |
.DO(do[31:16]) |
); |
|
// |
// Block 2 |
// |
RAMB4_S16 ramb4_s16_2( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[36:32]), |
.EN(ce), |
.WE(we), |
.DO(do[36:32]) |
); |
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !XILINX_RAMB4_S16 |
`endif // !VIRTUALSILICON_SSP |
`endif // !VIRAGE_SSP |
`endif // !AVANT_ATP |
`endif // !ARTISAN_SSP |
|
endmodule |
trunk/or1200/rtl/verilog/generic_spram_64x37.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/dc_fsm.v
===================================================================
--- trunk/or1200/rtl/verilog/dc_fsm.v (revision 202)
+++ trunk/or1200/rtl/verilog/dc_fsm.v (revision 203)
@@ -44,20 +44,25 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
-`define DCFSM_IDLE 'd0
-`define DCFSM_DOLOAD 'd1
-`define DCFSM_LREFILL3 'd2
-`define DCFSM_DOSTORE 'd3
-`define DCFSM_SREFILL3 'd4
-`define DCFSM_SMEMWR 'd5
+`define DCFSM_IDLE 3'd0
+`define DCFSM_DOLOAD 3'd1
+`define DCFSM_LREFILL3 3'd2
+`define DCFSM_DOSTORE 3'd3
+`define DCFSM_SREFILL3 3'd4
+`define DCFSM_SMEMWR 3'd5
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
@@ -135,7 +140,7 @@
always @(posedge clk or posedge rst) begin
if (rst) begin
refill <= #1 1'b0;
- state <= #1 3`DCFSM_IDLE;
+ state <= #1 `DCFSM_IDLE;
biu_read <= #1 1'b0;
biu_write <= #1 1'b0;
saved_addr <= #1 32'b0;
@@ -148,8 +153,12 @@
`DCFSM_IDLE :
casex(lsu_op)
`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);
- state <= #1 3`DCFSM_DOLOAD;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_DOLOAD;
refill <= #1 1'b0;
saved_addr <= #1 start_addr;
refill_first <= #1 1'b0;
@@ -160,8 +169,12 @@
cntrbusy <= #1 1'b0;
end
`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);
- state <= #1 3`DCFSM_DOSTORE;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_DOSTORE;
refill <= #1 1'b0;
saved_addr <= #1 start_addr;
refill_first <= #1 1'b0;
@@ -172,7 +185,7 @@
cntrbusy <= #1 1'b0;
end
default: begin
- state <= #1 3`DCFSM_IDLE;
+ state <= #1 `DCFSM_IDLE;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
refill_prepare <= #1 1'b0;
@@ -184,8 +197,12 @@
endcase
`DCFSM_DOLOAD:
if (dcache_off) begin
-// $display("%t: DC_FSM DCache off", $time);
- state <= #1 3`DCFSM_DOLOAD;
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
+ $display("%t: DC_FSM DCache off", $time);
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_DOLOAD;
refill <= #1 1'b1;
refill_first <= #1 1'b1;
refill_prepare <= #1 1'b0;
@@ -192,7 +209,7 @@
refill_rest <= #1 1'b0;
biu_read <= #1 1'b1;
if (biudata_valid) begin
- state <= #1 3`DCFSM_IDLE;
+ state <= #1 `DCFSM_IDLE;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
biu_read <= #1 1'b0;
@@ -200,8 +217,12 @@
end
end else
if (miss) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Load miss", $time);
- state <= #1 3`DCFSM_LREFILL3;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_LREFILL3;
refill <= #1 1'b1;
refill_first <= #1 1'b1;
refill_prepare <= #1 1'b0;
@@ -209,8 +230,12 @@
biu_read <= #1 1'b1;
end
else begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Load hit", $time);
- state <= #1 3`DCFSM_IDLE;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_IDLE;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
refill_prepare <= #1 1'b0;
@@ -218,14 +243,22 @@
end
`DCFSM_LREFILL3 : begin
if (biudata_valid && cnt) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Load refill %d", $time, cnt);
+// synopsys translate_on
+`endif
cnt <= #1 cnt - 'd1;
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
refill_first <= #1 1'b0;
end
else if (biudata_valid) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Load refill end", $time, cnt);
- state <= #1 3`DCFSM_IDLE;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_IDLE;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
biu_read <= #1 1'b0;
@@ -235,8 +268,12 @@
end
`DCFSM_DOSTORE:
if (miss) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store miss", $time);
- state <= #1 3`DCFSM_SREFILL3;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_SREFILL3;
refill <= #1 1'b1;
refill_first <= #1 1'b1;
refill_prepare <= #1 1'b0;
@@ -244,8 +281,12 @@
biu_read <= #1 1'b1;
end
else begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store hit", $time);
- state <= #1 3`DCFSM_SMEMWR;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_SMEMWR;
refill <= #1 1'b1;
refill_first <= #1 1'b0;
refill_prepare <= #1 1'b0;
@@ -254,14 +295,22 @@
end
`DCFSM_SREFILL3 : begin
if (biudata_valid && cnt) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store refill %d", $time, cnt);
+// synopsys translate_on
+`endif
cnt <= #1 cnt - 'd1;
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
refill_first <= #1 1'b0;
end
else if (biudata_valid) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store refill almost done", $time);
- state <= #1 3`DCFSM_SMEMWR;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_SMEMWR;
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
biu_write <= #1 1'b1;
biu_read <= #1 1'b0;
@@ -270,8 +319,12 @@
end
`DCFSM_SMEMWR :
if (biudata_valid) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
- state <= #1 3`DCFSM_IDLE;
+// synopsys translate_on
+`endif
+ state <= #1 `DCFSM_IDLE;
refill <= #1 1'b0;
biu_write <= #1 1'b0;
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
/trunk/or1200/rtl/verilog/ic.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/08/17 08:01:19 lampret |
// IC enable/disable. |
// |
// Revision 1.3 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
55,7 → 58,9
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module ic( |
160,7 → 165,8
// IC fetch stall |
// |
//assign icfetch_stall = (ic_en & (refill | ~hit)) | (~ic_en & bypass_wait[1] & ~icbiu_valid); |
assign icfetch_stall = (ic_en & (refill | ~hit)) | (~ic_en & bypass_wait[1] & ~icbiu_rdy); |
//assign icfetch_stall = (ic_en & (refill | ~hit)) | (~ic_en & bypass_wait[1] & ~icbiu_rdy); |
assign icfetch_stall = (ic_en & (refill | ~hit)) | (~ic_en & icbiu_read & ~icbiu_rdy); |
|
// |
// Select between claddr generated by IC FSM and addr[3:2] generated by IFETCH |
236,6 → 242,7
.clk(clk), |
.rst(rst), |
.addr(ic_addr[`ICINDXH:2]), |
.en(ic_en), |
.we(icram_we), |
.datain(to_icram), |
.dataout(from_icram) |
248,6 → 255,7
.clk(clk), |
.rst(rst), |
.addr(ic_addr[`ICINDXH:4]), |
.en(ic_en), |
.we(ictag_we), |
.datain(ic_addr[31:`ICTAGL]), |
.dataout(tag) |
/trunk/or1200/rtl/verilog/id.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
60,7 → 63,8
pipeline_freeze, except_flushpipe, if_insn, branch_op, |
rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op, |
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op, |
multicycle, branch_stall, spr_addrimm, wbforw_valid, sig_syscall |
multicycle, spr_addrimm, wbforw_valid, sig_syscall, |
force_dslot_fetch |
); |
|
// |
87,10 → 91,10
output [`LSUOP_WIDTH-1:0] lsu_op; |
output [`COMPOP_WIDTH-1:0] comp_op; |
output [`MULTICYCLE_WIDTH-1:0] multicycle; |
output branch_stall; |
output [15:0] spr_addrimm; |
input wbforw_valid; |
output sig_syscall; |
output force_dslot_fetch; |
|
// |
// Internal wires and regs |
124,6 → 128,12
assign rf_addrb = if_insn[15:11]; |
|
// |
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store |
// instructions |
// |
assign force_dslot_fetch = (pre_branch_op && lsu_op); |
|
// |
// Sign/Zero extension of immediates |
// |
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]}; |
134,11 → 144,6
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]}; |
|
// |
// Assert branch_stall if pre_branch_op is a branch operation |
// |
assign branch_stall = pre_branch_op ? 1'b1 : 1'b0; |
|
// |
// Async reset for most of pipeline flops |
// |
assign rst_or_except_flushpipe = rst | except_flushpipe; |
323,7 → 328,11
end |
else if (!pipeline_freeze) begin |
id_insn <= #1 if_insn; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: id_insn <= %h", $time, if_insn); |
// synopsys translate_on |
`endif |
end |
end |
|
337,7 → 346,11
end |
else if (!pipeline_freeze) begin |
ex_insn <= #1 id_insn; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: ex_insn <= %h", $time, id_insn); |
// synopsys translate_on |
`endif |
end |
end |
|
558,7 → 571,11
// Illegal and OR1200 unsupported instructions |
default: begin |
alu_op <= #1 `ALUOP_NOP; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: Illegal insn.... insn %h", $time, id_insn); |
// synopsys translate_on |
`endif |
end |
|
endcase |
790,10 → 807,12
if (rst) |
sig_syscall <= #1 1'b0; |
else if (!pipeline_freeze) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00}) |
$display("Generating sig_syscall"); |
// synopsys translate_on |
`endif |
// sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00}); |
end |
end |
/trunk/or1200/rtl/verilog/reg2mem.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module reg2mem(addr, lsu_op, regdata, memdata); |
74,9 → 79,9
// |
always @(lsu_op or addr or regdata) begin |
casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case |
{`LSUOP_SB, 2'b00} : memdata[31:24] <= #1 regdata[7:0]; |
{`LSUOP_SH, 2'b00} : memdata[31:24] <= #1 regdata[15:8]; |
default : memdata[31:24] <= #1 regdata[31:24]; |
{`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0]; |
{`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8]; |
default : memdata[31:24] = regdata[31:24]; |
endcase |
end |
|
85,8 → 90,8
// |
always @(lsu_op or addr or regdata) begin |
casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case |
{`LSUOP_SW, 2'b00} : memdata[23:16] <= #1 regdata[23:16]; |
default : memdata[23:16] <= #1 regdata[7:0]; |
{`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16]; |
default : memdata[23:16] = regdata[7:0]; |
endcase |
end |
|
95,8 → 100,8
// |
always @(lsu_op or addr or regdata) begin |
casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case |
{`LSUOP_SB, 2'b10} : memdata[15:8] <= #1 regdata[7:0]; |
default : memdata[15:8] <= #1 regdata[15:8]; |
{`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0]; |
default : memdata[15:8] = regdata[15:8]; |
endcase |
end |
|
104,6 → 109,6
// Mux to memdata[7:0] |
// |
always @(regdata) |
memdata[7:0] <= #1 regdata[7:0]; |
memdata[7:0] = regdata[7:0]; |
|
endmodule |
/trunk/or1200/rtl/verilog/mem2reg.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module mem2reg(addr, lsu_op, memdata, regdata); |
86,19 → 91,19
always @(addr or lsu_op) begin |
casex({lsu_op[2:0], addr}) |
{3'b01x, 2'b00}: |
sel_byte0 <= #1 `SEL_11; |
sel_byte0 = `SEL_11; |
{3'b01x, 2'b01}: |
sel_byte0 <= #1 `SEL_10; |
sel_byte0 = `SEL_10; |
{3'b01x, 2'b10}: |
sel_byte0 <= #1 `SEL_01; |
sel_byte0 = `SEL_01; |
{3'b01x, 2'b11}: |
sel_byte0 <= #1 `SEL_00; |
sel_byte0 = `SEL_00; |
{3'b10x, 2'b00}: |
sel_byte0 <= #1 `SEL_10; |
sel_byte0 = `SEL_10; |
{3'b10x, 2'b10}: |
sel_byte0 <= #1 `SEL_00; |
sel_byte0 = `SEL_00; |
default: |
sel_byte0 <= #1 `SEL_00; |
sel_byte0 = `SEL_00; |
endcase |
end |
|
108,13 → 113,13
always @(addr or lsu_op) begin |
casex({lsu_op[2:0], addr}) |
{3'b010, 2'bxx}: |
sel_byte1 <= #1 `SEL_00; // zero extend |
sel_byte1 = `SEL_00; // zero extend |
{3'b011, 2'bxx}: |
sel_byte1 <= #1 `SEL_10; // sign extend byte |
sel_byte1 = `SEL_10; // sign extend byte |
{3'b10x, 2'b00}: |
sel_byte1 <= #1 `SEL_11; |
sel_byte1 = `SEL_11; |
default: |
sel_byte1 <= #1 `SEL_01; |
sel_byte1 = `SEL_01; |
endcase |
end |
|
125,13 → 130,13
casex({lsu_op[2:0], addr}) |
{3'b010, 2'bxx}, |
{3'b100, 2'bxx}: |
sel_byte2 <= #1 `SEL_00; // zero extend |
sel_byte2 = `SEL_00; // zero extend |
{3'b011, 2'bxx}: |
sel_byte2 <= #1 `SEL_01; // sign extend byte |
sel_byte2 = `SEL_01; // sign extend byte |
{3'b101, 2'bxx}: |
sel_byte2 <= #1 `SEL_11; // sign extend halfword |
sel_byte2 = `SEL_11; // sign extend halfword |
default: |
sel_byte2 <= #1 `SEL_10; |
sel_byte2 = `SEL_10; |
endcase |
end |
|
142,13 → 147,13
casex({lsu_op[2:0], addr}) |
{3'b010, 2'bxx}, |
{3'b100, 2'bxx}: |
sel_byte3 <= #1 `SEL_00; // zero extend |
sel_byte3 = `SEL_00; // zero extend |
{3'b011, 2'bxx}: |
sel_byte3 <= #1 `SEL_01; // sign extend byte |
sel_byte3 = `SEL_01; // sign extend byte |
{3'b101, 2'bxx}: |
sel_byte3 <= #1 `SEL_10; // sign extend halfword |
sel_byte3 = `SEL_10; // sign extend halfword |
default: |
sel_byte3 <= #1 `SEL_11; |
sel_byte3 = `SEL_11; |
endcase |
end |
|
158,16 → 163,16
always @(sel_byte0 or memdata) begin |
case(sel_byte0) // synopsys full_case parallel_case infer_mux |
`SEL_00: begin |
regdata[7:0] <= #1 memdata[7:0]; |
regdata[7:0] = memdata[7:0]; |
end |
`SEL_01: begin |
regdata[7:0] <= #1 memdata[15:8]; |
regdata[7:0] = memdata[15:8]; |
end |
`SEL_10: begin |
regdata[7:0] <= #1 memdata[23:16]; |
regdata[7:0] = memdata[23:16]; |
end |
`SEL_11: begin |
regdata[7:0] <= #1 memdata[31:24]; |
regdata[7:0] = memdata[31:24]; |
end |
endcase |
end |
178,16 → 183,16
always @(sel_byte1 or memdata) begin |
case(sel_byte1) // synopsys full_case parallel_case infer_mux |
`SEL_00: begin |
regdata[15:8] <= #1 8'b0; |
regdata[15:8] = 8'b0; |
end |
`SEL_01: begin |
regdata[15:8] <= #1 memdata[15:8]; |
regdata[15:8] = memdata[15:8]; |
end |
`SEL_10: begin |
regdata[15:8] <= #1 {8{memdata[7]}}; |
regdata[15:8] = {8{memdata[7]}}; |
end |
`SEL_11: begin |
regdata[15:8] <= #1 memdata[31:24]; |
regdata[15:8] = memdata[31:24]; |
end |
endcase |
end |
198,16 → 203,16
always @(sel_byte2 or memdata) begin |
case(sel_byte2) // synopsys full_case parallel_case infer_mux |
`SEL_00: begin |
regdata[23:16] <= #1 8'b0; |
regdata[23:16] = 8'b0; |
end |
`SEL_01: begin |
regdata[23:16] <= #1 {8{memdata[7]}}; |
regdata[23:16] = {8{memdata[7]}}; |
end |
`SEL_10: begin |
regdata[23:16] <= #1 memdata[23:16]; |
regdata[23:16] = memdata[23:16]; |
end |
`SEL_11: begin |
regdata[23:16] <= #1 {8{memdata[15]}}; |
regdata[23:16] = {8{memdata[15]}}; |
end |
endcase |
end |
218,16 → 223,16
always @(sel_byte3 or memdata) begin |
case(sel_byte3) // synopsys full_case parallel_case infer_mux |
`SEL_00: begin |
regdata[31:24] <= #1 8'b0; |
regdata[31:24] = 8'b0; |
end |
`SEL_01: begin |
regdata[31:24] <= #1 {8{memdata[7]}}; |
regdata[31:24] = {8{memdata[7]}}; |
end |
`SEL_10: begin |
regdata[31:24] <= #1 {8{memdata[15]}}; |
regdata[31:24] = {8{memdata[15]}}; |
end |
`SEL_11: begin |
regdata[31:24] <= #1 memdata[31:24]; |
regdata[31:24] = memdata[31:24]; |
end |
endcase |
end |
247,13 → 252,13
always @(addr or memdata) begin |
case(addr) // synopsys infer_mux |
2'b00: |
aligned <= #1 memdata; |
aligned = memdata; |
2'b01: |
aligned <= #1 {memdata[23:0], 8'b0}; |
aligned = {memdata[23:0], 8'b0}; |
2'b10: |
aligned <= #1 {memdata[15:0], 16'b0}; |
aligned = {memdata[15:0], 16'b0}; |
2'b11: |
aligned <= #1 {memdata[7:0], 24'b0}; |
aligned = {memdata[7:0], 24'b0}; |
endcase |
end |
|
263,23 → 268,23
always @(lsu_op or aligned) begin |
case(lsu_op) // synopsys infer_mux |
`LSUOP_LBZ: begin |
regdata[7:0] <= #1 aligned[31:24]; |
regdata[31:8] <= #1 24'b0; |
regdata[7:0] = aligned[31:24]; |
regdata[31:8] = 24'b0; |
end |
`LSUOP_LBS: begin |
regdata[7:0] <= #1 aligned[31:24]; |
regdata[31:8] <= #1 {24{aligned[31]}}; |
regdata[7:0] = aligned[31:24]; |
regdata[31:8] = {24{aligned[31]}}; |
end |
`LSUOP_LHZ: begin |
regdata[15:0] <= #1 aligned[31:16]; |
regdata[31:16] <= #1 16'b0; |
regdata[15:0] = aligned[31:16]; |
regdata[31:16] = 16'b0; |
end |
`LSUOP_LHS: begin |
regdata[15:0] <= #1 aligned[31:16]; |
regdata[31:16] <= #1 {16{aligned[31]}}; |
regdata[15:0] = aligned[31:16]; |
regdata[31:16] = {16{aligned[31]}}; |
end |
default: |
regdata <= #1 aligned; |
regdata = aligned; |
endcase |
end |
|
/trunk/or1200/rtl/verilog/lsu.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module lsu( |
/trunk/or1200/rtl/verilog/generic_spram_512x19.v
62,12 → 62,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_512x19( |
// Generic synchronous single-port RAM interface |
104,7 → 110,7
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_512x19 #(dw, 2<<aw, aw) artisan_ssp( |
art_hssp_512x19 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
163,7 → 169,7
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp( |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
222,6 → 228,8
.DO(do[11:8]) |
); |
|
wire x; |
|
// |
// Block 3 |
// |
242,10 → 250,10
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[19:16]), |
.DI({1'b0, di[18:16]}), |
.EN(ce), |
.WE(we), |
.DO(do[19:16]) |
.DO({x, do[18:16]}) |
); |
|
`else |
257,7 → 265,7
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
/trunk/or1200/rtl/verilog/immu.v
0,0 → 1,228
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1200's Insn MMU top level //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// Instantiation of all IMMU blocks. //// |
//// //// |
//// To Do: //// |
//// - make it smaller and faster //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/17 08:03:35 lampret |
// *** empty log message *** |
// |
// Revision 1.2 2001/07/22 03:31:53 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// |
// Insn MMU |
// |
|
module immu( |
// Rst and clk |
clk, rst, |
|
// Fetch i/f |
immu_en, supv, immufetch_vaddr, immufetch_op, immufetch_stall, |
|
// Except I/F |
immuexcept_miss, immuexcept_fault, |
|
// SPR access |
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, |
|
// IC i/f |
icimmu_paddr |
); |
|
parameter dw = `OPERAND_WIDTH; |
parameter aw = `OPERAND_WIDTH; |
|
// |
// I/O |
// |
|
// |
// Clock and reset |
// |
input clk; |
input rst; |
|
// |
// FETCH I/F |
// |
input immu_en; |
input supv; |
input [aw-1:0] immufetch_vaddr; |
input immufetch_op; |
output immufetch_stall; |
|
// |
// Exception I/F |
// |
output immuexcept_miss; |
output immuexcept_fault; |
|
// |
// SPR access |
// |
input spr_cs; |
input spr_write; |
input [aw-1:0] spr_addr; |
input [31:0] spr_dat_i; |
output [31:0] spr_dat_o; |
|
// |
// IC I/F |
// |
output [aw-1:0] icimmu_paddr; |
|
// |
// Internal wires and regs |
// |
wire itlb_spr_access; |
wire [31:13] itlb_ppn; |
wire itlb_hit; |
wire itlb_uxe; |
wire itlb_sxe; |
wire [31:0] itlb_dat_o; |
|
// |
// Implemented bits inside match and translate registers |
// |
// itlbwYmrX: vpn 31-10 v 0 |
// itlbwYtrX: ppn 31-10 uxe 7 sxe 6 |
// |
// itlb memory width: |
// 19 bits for ppn |
// 13 bits for vpn |
// 1 bit for valid |
// 2 bits for protection |
|
`ifdef OR1200_NO_IMMU |
|
// |
// Put all outputs in inactive state |
// |
assign immufetch_stall = 1'b0; |
assign immuexcept_miss = 1'b0; |
assign immuexcept_miss = 1'b1; |
output spr_dat_o = 32'h00000000; |
output icimmu_paddr = immfetch_vaddr; |
|
`else |
|
// |
// ITLB SPR access |
// |
// 1400 - 1600 itlbmr w0-3 |
// 1400 - 1480 itlbmr w0 |
// 1400 - 1440 itlbmr w0 [63:0] |
// |
// 1600 - 1800 itlbtr w0-3 |
// 1600 - 1680 itlbtr w0 |
// 1600 - 1640 itlbtr w0 [63:0] |
// |
assign itlb_spr_access = spr_cs & spr_addr[10]; |
|
// |
// Physical address is either translated virtual address or |
// simply equal when IMMU is disabled |
// |
assign icimmu_paddr = immu_en ? {itlb_ppn, immufetch_vaddr[12:0]} : immufetch_vaddr; |
|
// |
// Output to SPRS unit |
// |
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000; |
|
// |
// IMMU stall |
// |
assign immufetch_stall = 1'b0; |
|
// |
// Page fault exception logic |
// |
assign immuexcept_fault = immu_en && |
( (immufetch_op & !supv & !itlb_uxe) // Fetch in user mode not enabled |
|| (immufetch_op & supv & !itlb_sxe) ); // Fetch in supv mode not enabled |
|
// |
// TLB Miss exception logic |
// |
assign immuexcept_miss = immufetch_op && immu_en && !itlb_hit; |
|
// |
// Instantiation of ITLB |
// |
itlb itlb( |
// Rst and clk |
.clk(clk), |
.rst(rst), |
|
// I/F for translation |
.tlb_en(immu_en), |
.vaddr(immufetch_vaddr), |
.hit(itlb_hit), |
.ppn(itlb_ppn), |
.uxe(itlb_uxe), |
.sxe(itlb_sxe), |
|
// SPR access |
.spr_cs(itlb_spr_access), |
.spr_write(spr_write), |
.spr_addr(spr_addr), |
.spr_dat_i(spr_dat_i), |
.spr_dat_o(itlb_dat_o) |
); |
|
`endif |
|
endmodule |
trunk/or1200/rtl/verilog/immu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/operandmuxes.v
===================================================================
--- trunk/or1200/rtl/verilog/operandmuxes.v (revision 202)
+++ trunk/or1200/rtl/verilog/operandmuxes.v (revision 203)
@@ -44,12 +44,17 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
// Revision 1.1 2001/07/20 00:46:05 lampret
// Development version of RTL. Libraries are missing.
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
module operandmuxes(
@@ -114,11 +119,11 @@
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
casex (sel_a) // synopsys full_case parallel_case infer_mux
`SEL_EX_FORW:
- muxed_a <= #1 ex_forw;
+ muxed_a = ex_forw;
`SEL_WB_FORW:
- muxed_a <= #1 wb_forw;
+ muxed_a = wb_forw;
default:
- muxed_a <= #1 rf_dataa;
+ muxed_a = rf_dataa;
endcase
end
@@ -128,13 +133,13 @@
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
casex (sel_b) // synopsys full_case parallel_case infer_mux
`SEL_IMM:
- muxed_b <= #1 simm;
+ muxed_b = simm;
`SEL_EX_FORW:
- muxed_b <= #1 ex_forw;
+ muxed_b = ex_forw;
`SEL_WB_FORW:
- muxed_b <= #1 wb_forw;
+ muxed_b = wb_forw;
default:
- muxed_b <= #1 rf_datab;
+ muxed_b = rf_datab;
endcase
end
/trunk/or1200/rtl/verilog/generic_spram_2048x8.v
62,12 → 62,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_2048x8( |
// Generic synchronous single-port RAM interface |
104,7 → 110,7
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_2048x8 #(dw, 2<<aw, aw) artisan_ssp( |
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
163,7 → 169,7
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp( |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
244,7 → 250,7
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
/trunk/or1200/rtl/verilog/defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/08/17 08:01:19 lampret |
// IC enable/disable. |
// |
// Revision 1.2 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
58,7 → 61,10
// |
// |
|
`define ARTISAN_SSP |
`define XILINX_RAMB4 |
`define XILINX_RAM32X1D |
//`define ARTISAN_SSP |
//`define ARTISAN_SDP |
//`define ARTISAN_STP |
|
// Dump VCD |
65,6 → 71,21
//`define VCD_DUMP |
|
// |
// Data cache not implemented |
// |
`define OR1200_NO_DC |
|
// |
// Insn cache not implemented |
// |
`define OR1200_NO_IC |
|
// |
// Register OR1200 outputs |
// |
//`define OR1200_REGISTERED_OUTPUTS |
|
// |
// Implement rotate in the ALU |
// |
`define IMPL_ALU_ROTATE |
203,8 → 224,6
`define SIGNED_COMPARE 'd3 |
`define COMPOP_WIDTH 4 |
|
`define LSUOP_WIDTH 4 |
|
`define PAGEINDX_WIDTH 13 |
`define ITLBADDR_WIDTH 7 |
|
396,10 → 415,10
`define SPR_GROUP_PM 5'd8 |
`define SPR_GROUP_PIC 5'd9 |
`define SPR_GROUP_TT 5'd10 |
`define SPR_GROUP_ITLB 5'd28 |
`define SPR_GROUP_IMMU 5'd28 |
`define SPR_GROUP_MODA 5'd29 |
`define SPR_GROUP_MODD 5'd30 |
`define SPR_GROUP_DTLB 5'd31 |
`define SPR_GROUP_DMMU 5'd31 |
|
`define SPR_CFGR 3'd0 |
`define SPR_SR 7'd16 |
/trunk/or1200/rtl/verilog/alu.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module alu(clk, rst, a, b, alu_op, shrot_op, comp_op, result, flag); |
101,6 → 106,7
// |
// Simulation check for bad ALU behavior |
// |
`ifdef OR1200_WARNINGS |
// synopsys translate_off |
always @(result) begin |
if (result === 32'bx) |
107,6 → 113,7
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time); |
end |
// synopsys translate_on |
`endif |
|
// |
// Central part of the ALU |
114,41 → 121,45
always @(alu_op or a or b or shifted_rotated or mul_prod) begin |
casex (alu_op) // synopsys parallel_case full_case |
`ALUOP_SHROT : begin |
result <= #1 shifted_rotated; |
flag_we <= #1 1'b0; |
result = shifted_rotated; |
flag_we = 1'b0; |
end |
`ALUOP_ADD : begin |
result <= #1 a + b; |
flag_we <= #1 1'b0; |
result = a + b; |
flag_we = 1'b0; |
end |
`ALUOP_SUB : begin |
result <= #1 a - b; |
flag_we <= #1 1'b0; |
result = a - b; |
flag_we = 1'b0; |
end |
`ALUOP_XOR : begin |
result <= #1 a ^ b; |
flag_we <= #1 1'b0; |
result = a ^ b; |
flag_we = 1'b0; |
end |
`ALUOP_OR : begin |
result <= #1 a | b; |
flag_we <= #1 1'b0; |
result = a | b; |
flag_we = 1'b0; |
end |
`ALUOP_AND : begin |
result <= #1 a & b; |
flag_we <= #1 1'b0; |
result = a & b; |
flag_we = 1'b0; |
end |
`ALUOP_IMM : begin |
result <= #1 b; |
flag_we <= #1 1'b0; |
result = b; |
flag_we = 1'b0; |
end |
`ALUOP_MOVHI : begin |
result <= #1 b << 16; |
flag_we <= #1 1'b0; |
result = b << 16; |
flag_we = 1'b0; |
end |
`ALUOP_MUL : begin |
result <= #1 mul_prod; |
result = mul_prod; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: MUL operation: %h * %h = %h", $time, a, b, mul_prod); |
flag_we <= #1 1'b0; |
// synopsys translate_on |
`endif |
flag_we = 1'b0; |
end |
// synopsys translate_off |
`ifdef SIM_ALU_DIV |
156,20 → 167,26
d1 = a; |
d2 = b; |
$display("DIV operation: %d / %d = %d", d1, d2, d1/d2); |
result <= #1 d1 / d2; |
flag_we <= #1 1'b0; |
if (d2) |
result = d1 / d2; |
else |
result = 32'h00000000; |
flag_we = 1'b0; |
end |
`endif |
`ifdef SIM_ALU_DIVU |
`ALUOP_DIVU : begin |
result <= #1 a / b; |
flag_we <= #1 1'b0; |
if (b) |
result = a / b; |
else |
result = 32'h00000000; |
flag_we = 1'b0; |
end |
`endif |
// synopsys translate_on |
`ALUOP_COMP: begin |
flag_we <= #1 1'b1; |
result <= #1 32'd0; |
flag_we = 1'b1; |
result = 32'd0; |
end |
endcase |
end |
180,15 → 197,15
always @(shrot_op or a or b) begin |
case (shrot_op) // synopsys parallel_case full_case |
`SHROTOP_SLL : |
shifted_rotated <= #1 (a << b[4:0]); |
shifted_rotated = (a << b[4:0]); |
`SHROTOP_SRL : |
shifted_rotated <= #1 (a >> b[4:0]); |
shifted_rotated = (a >> b[4:0]); |
`ifdef IMPL_ALU_ROTATE |
`SHROTOP_ROR : |
shifted_rotated <= #1 (a << (5'd32-b[4:0])) | (a >> b[4:0]); |
shifted_rotated = (a << (6'd32-b[4:0])) | (a >> b[4:0]); |
`endif |
default: |
shifted_rotated <= #1 ({32{a[31]}} << (5'd32-b[4:0])) | a >> b[4:0]; |
shifted_rotated = ({32{a[31]}} << (6'd32-b[4:0])) | a >> b[4:0]; |
endcase |
end |
|
199,20 → 216,20
always @(comp_op or a_eq_b or a_lt_b) begin |
case(comp_op[2:0]) // synopsys parallel_case full_case |
`COP_SFEQ: |
flagforw <= #1 a_eq_b; |
flagforw = a_eq_b; |
`COP_SFNE: |
flagforw <= #1 ~a_eq_b; |
flagforw = ~a_eq_b; |
`COP_SFGT: |
flagforw <= #1 ~(a_eq_b | a_lt_b); |
flagforw = ~(a_eq_b | a_lt_b); |
`COP_SFGE: |
flagforw <= #1 ~a_lt_b; |
flagforw = ~a_lt_b; |
`COP_SFLT: |
flagforw <= #1 a_lt_b; |
flagforw = a_lt_b; |
`COP_SFLE: |
flagforw <= #1 a_eq_b | a_lt_b; |
flagforw = a_eq_b | a_lt_b; |
// synopsys translate_off |
default: |
flagforw <= #1 1'bx; |
flagforw = 1'bx; |
// synopsys translate_on |
endcase |
end |
225,20 → 242,20
always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin |
case(comp_op[2:0]) // synopsys parallel_case full_case |
`COP_SFEQ: |
flagforw <= #1 (comp_a == comp_b); |
flagforw = (comp_a == comp_b); |
`COP_SFNE: |
flagforw <= #1 (comp_a != comp_b); |
flagforw = (comp_a != comp_b); |
`COP_SFGT: |
flagforw <= #1 (comp_a > comp_b); |
flagforw = (comp_a > comp_b); |
`COP_SFGE: |
flagforw <= #1 (comp_a >= comp_b); |
flagforw = (comp_a >= comp_b); |
`COP_SFLT: |
flagforw <= #1 (comp_a < comp_b); |
flagforw = (comp_a < comp_b); |
`COP_SFLE: |
flagforw <= #1 (comp_a <= comp_b); |
flagforw = (comp_a <= comp_b); |
// synopsys translate_off |
default: |
flagforw <= #1 1'bx; |
flagforw = 1'bx; |
// synopsys translate_on |
endcase |
end |
251,7 → 268,11
if (rst) |
flag <= #1 1'b0; |
else if (flag_we) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b); |
// synopsys translate_on |
`endif |
flag <= #1 flagforw; |
end |
end |
262,6 → 283,7
multp2_32x32 multp2_32x32( |
.X(mul_a), |
.Y(mul_b), |
.RST(rst), |
.CLK(clk), |
.P(tmp_prod) |
); |
/trunk/or1200/rtl/verilog/generic_spram_64x21.v
0,0 → 1,250
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// - Artisan Single-Port Sync RAM //// |
//// - Avant! Two-Port Sync RAM (*) //// |
//// - Virage Single-Port Sync RAM //// |
//// - Virtual Silicon Single-Port Sync RAM //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// //// |
//// To Do: //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs (Altera etc) //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_64x21( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 6; |
parameter dw = 21; |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
|
|
`ifdef ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_64x21 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
); |
|
`else |
|
`ifdef AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
avant_atp avant_atp( |
.web(~we), |
.reb(), |
.oeb(~oe), |
.rcsb(), |
.wcsb(), |
.ra(addr), |
.wa(addr), |
.di(di), |
.do(do) |
); |
|
`else |
|
`ifdef VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
virage_ssp virage_ssp( |
.clk(clk), |
.adr(addr), |
.d(di), |
.we(we), |
.oe(oe), |
.me(ce), |
.q(do) |
); |
|
`else |
|
`ifdef VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
.WEN(~we), |
.CEN(~ce), |
.OEN(~oe), |
.DOUT(do) |
); |
|
`else |
|
`ifdef XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S16 ramb4_s16_0( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[15:0]), |
.EN(ce), |
.WE(we), |
.DO(do[15:0]) |
); |
|
// |
// Block 1 |
// |
RAMB4_S16 ramb4_s16_1( |
.CLK(clk), |
.RST(rst), |
.ADDR({2'b00, addr}), |
.DI(di[20:16]), |
.EN(ce), |
.WE(we), |
.DO(do[20:16]) |
); |
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !XILINX_RAMB4_S16 |
`endif // !VIRTUALSILICON_SSP |
`endif // !VIRAGE_SSP |
`endif // !AVANT_ATP |
`endif // !ARTISAN_SSP |
|
endmodule |
trunk/or1200/rtl/verilog/generic_spram_64x21.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/generic_spram_64x23.v
===================================================================
--- trunk/or1200/rtl/verilog/generic_spram_64x23.v (nonexistent)
+++ trunk/or1200/rtl/verilog/generic_spram_64x23.v (revision 203)
@@ -0,0 +1,250 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Generic Single-Port Synchronous RAM ////
+//// ////
+//// This file is part of memory library available from ////
+//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
+//// ////
+//// Description ////
+//// This block is a wrapper with common single-port ////
+//// synchronous memory interface for different ////
+//// types of ASIC and FPGA RAMs. Beside universal memory ////
+//// interface it also provides behavioral model of generic ////
+//// single-port synchronous RAM. ////
+//// It should be used in all OPENCORES designs that want to be ////
+//// portable accross different target technologies and ////
+//// independent of target memory. ////
+//// ////
+//// Supported ASIC RAMs are: ////
+//// - Artisan Single-Port Sync RAM ////
+//// - Avant! Two-Port Sync RAM (*) ////
+//// - Virage Single-Port Sync RAM ////
+//// - Virtual Silicon Single-Port Sync RAM ////
+//// ////
+//// Supported FPGA RAMs are: ////
+//// - Xilinx Virtex RAMB4_S16 ////
+//// ////
+//// To Do: ////
+//// - xilinx rams need external tri-state logic ////
+//// - fix avant! two-port ram ////
+//// - add additional RAMs (Altera etc) ////
+//// ////
+//// Author(s): ////
+//// - Damjan Lampret, lampret@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
+// Revision 1.2 2001/07/30 05:38:02 lampret
+// Adding empty directories required by HDL coding guidelines
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "defines.v"
+
+module generic_spram_64x23(
+ // Generic synchronous single-port RAM interface
+ clk, rst, ce, we, oe, addr, di, do
+);
+
+//
+// Default address and data buses width
+//
+parameter aw = 6;
+parameter dw = 23;
+
+//
+// Generic synchronous single-port RAM interface
+//
+input clk; // Clock
+input rst; // Reset
+input ce; // Chip enable input
+input we; // Write enable input
+input oe; // Output enable input
+input [aw-1:0] addr; // address bus inputs
+input [dw-1:0] di; // input data bus
+output [dw-1:0] do; // output data bus
+
+//
+// Internal wires and registers
+//
+
+
+`ifdef ARTISAN_SSP
+
+//
+// Instantiation of ASIC memory:
+//
+// Artisan Synchronous Single-Port RAM (ra1sh)
+//
+art_hssp_64x23 #(dw, 1<
trunk/or1200/rtl/verilog/generic_spram_64x23.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/ic_tag.v
===================================================================
--- trunk/or1200/rtl/verilog/ic_tag.v (revision 202)
+++ trunk/or1200/rtl/verilog/ic_tag.v (revision 203)
@@ -44,12 +44,17 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
module ic_tag(
@@ -57,7 +62,7 @@
clk, rst,
// Internal i/f
- addr, we, datain, dataout
+ addr, en, we, datain, dataout
);
parameter dw = 19;
@@ -77,17 +82,27 @@
// Internal i/f
//
input [aw-1:0] addr;
+input en;
input we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
+`ifdef OR1200_NO_IC
+
//
+// Insn cache not implemented
+//
+assign dataout = {dw{1'b0}};
+
+`else
+
+//
// Instantiation of TAG RAM block
//
generic_spram_512x19 ic_tag0(
.clk(clk),
.rst(rst),
- .ce(1'b1),
+ .ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
@@ -95,4 +110,6 @@
.do(dataout)
);
+`endif
+
endmodule
/trunk/or1200/rtl/verilog/dc.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.3 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
55,7 → 58,9
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// |
70,7 → 75,7
dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel, |
|
// Internal i/f |
dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, |
dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, dclsu_unstall, |
|
// Trace |
tp2w |
109,6 → 114,7
output [dw-1:0] dclsu_dataout; |
output [dw-1:0] dcbiu_dataout; |
output dclsu_stall; |
output dclsu_unstall; |
|
// |
// Trace |
149,6 → 155,7
// |
assign dcbiu_addr = dc_addr; |
assign dctag_we = refill; |
assign dclsu_unstall = dcbiu_rdy; |
|
// |
// Data to BIU is from DCRAM when DC is enabled or from LSU when |
205,7 → 212,8
// |
// DC/LSU stall |
// |
assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid); |
//assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid); |
assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & (dcbiu_read | dcbiu_write) & ~dcbiu_rdy); |
|
// |
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU |
292,6 → 300,7
.clk(clk), |
.rst(rst), |
.addr(dc_addr[12:2]), |
.en(dc_en), |
.we(dcram_we), |
.datain(to_dcram), |
.dataout(from_dcram) |
304,6 → 313,7
.clk(clk), |
.rst(rst), |
.addr(dc_addr[12:4]), |
.en(dc_en), |
.we(dctag_we), |
.datain(dc_addr[31:13]), |
.dataout(tag) |
/trunk/or1200/rtl/verilog/cpu.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/08/17 08:01:19 lampret |
// IC enable/disable. |
// |
// Revision 1.3 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
56,7 → 59,9
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module cpu( |
64,19 → 69,21
clk, rst, |
|
// Insn interface |
ic_insn, ic_pcaddr, ic_stall, ic_en, |
ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en, |
immu_en, immuexcept_miss, immuexcept_fault, |
|
// Trace port |
tp_dir_in, tp_sel, tp_in, tp_out, |
|
// Data interface |
dclsu_stall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en, |
dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en, |
dmmu_en, dmmuexcept_miss, dmmuexcept_fault, |
|
// Interrupt exceptions |
int_high, int_low, |
|
// SPR interface |
spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_cs, spr_we, |
supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_dat_dmmu, spr_cs, spr_we, |
|
// Trace port |
tp2w, tp3w |
99,11 → 106,19
// Insn (IC) interface |
// |
input [31:0] ic_insn; |
output [31:0] ic_pcaddr; |
output [31:0] ic_addr; |
input ic_stall; |
output [`FETCHOP_WIDTH-1:0] ic_fetchop; |
output ic_en; |
|
// |
// Insn (IMMU) interface |
// |
input immuexcept_miss; |
input immuexcept_fault; |
output immu_en; |
|
// |
// Trace |
// |
input tp_dir_in; |
117,6 → 132,7
// Data (DC) interface |
// |
input dclsu_stall; |
input dclsu_unstall; |
output [31:0] dclsu_addr; |
input [31:0] dclsu_datain; |
output [31:0] dclsu_dataout; |
124,11 → 140,20
output dc_en; |
|
// |
// Data (DMMU) interface |
// |
input dmmuexcept_miss; |
input dmmuexcept_fault; |
output dmmu_en; |
|
// |
// SPR interface |
// |
input supv; |
input [dw-1:0] spr_dat_pic; |
input [dw-1:0] spr_dat_tt; |
input [dw-1:0] spr_dat_pm; |
input [dw-1:0] spr_dat_dmmu; |
output [dw-1:0] spr_addr; |
output [dw-1:0] spr_dataout; |
output [31:0] spr_cs; |
195,6 → 220,8
wire [15:0] spr_addrimm; |
wire sig_syscall; |
wire [31:0] spr_dat_cfgr; |
wire force_dslot_fetch; |
wire if_stall; |
|
// |
// Trace port |
213,24 → 240,40
// |
// Instruction cache enable |
// |
//assign ic_en = 1'b1; |
assign ic_en = sr[`SR_ICE]; |
|
// |
// DMMU enable |
// |
assign dmmu_en = sr[`SR_DME]; |
|
// |
// IMMU enable |
// |
assign immu_en = sr[`SR_IME]; |
|
// |
// SUPV bit |
// |
assign supv = sr[`SR_SUPV]; |
|
// |
// Instantiation of exception block |
// |
except except( |
.clk(clk), |
.rst(rst), |
.sig_dtlbmiss(1'b0), |
.sig_dmmufault(1'b0), |
.sig_dtlbmiss(dmmuexcept_miss), |
.sig_dmmufault(dmmuexcept_fault), |
.sig_inthigh(int_high), |
.sig_syscall(sig_syscall), |
.sig_itlbmiss(1'b0), |
.sig_immufault(1'b0), |
.sig_itlbmiss(immuexcept_miss), |
.sig_immufault(immuexcept_fault), |
.sig_intlow(int_low), |
.branch_taken(branch_taken), |
.pipeline_freeze(pipeline_freeze), |
.ic_stall(ic_stall), |
.if_stall(if_stall), |
.if_pc(if_pc), |
.lr_sav(lr_sav), |
.except_flushpipe(except_flushpipe), |
258,8 → 301,9
.clk(clk), |
.rst(rst), |
.ic_insn(ic_insn), |
.ic_pcaddr(ic_pcaddr), |
.ic_addr(ic_addr), |
.ic_stall(ic_stall), |
.ic_fetchop(ic_fetchop), |
.tp_insn(tp_insn), |
.tp_wr_insn(tp_wr_insn), |
.pipeline_freeze(pipeline_freeze), |
273,7 → 317,10
.flag(flag), |
.taken(branch_taken), |
.binsn_addr(lr_sav), |
.epcr(epcr) |
.epcr(epcr), |
.force_dslot_fetch(force_dslot_fetch), |
.if_stall(if_stall), |
.branch_stall(branch_stall) |
); |
|
// |
301,10 → 348,10
.sel_b(sel_b), |
.lsu_op(lsu_op), |
.multicycle(multicycle), |
.branch_stall(branch_stall), |
.spr_addrimm(spr_addrimm), |
.wbforw_valid(wbforw_valid), |
.sig_syscall(sig_syscall) |
.sig_syscall(sig_syscall), |
.force_dslot_fetch(force_dslot_fetch) |
); |
|
// |
396,6 → 443,8
.spr_dat_pic(spr_dat_pic), |
.spr_dat_tt(spr_dat_tt), |
.spr_dat_pm(spr_dat_pm), |
.spr_dat_cfgr(spr_dat_cfgr), |
.spr_dat_dmmu(spr_dat_dmmu), |
.spr_dataout(spr_dataout), |
.spr_cs(spr_cs), |
.spr_we(spr_we), |
441,8 → 490,10
.multicycle(multicycle), |
.except_flushpipe(except_flushpipe), |
.lsu_stall(lsu_stall), |
.ic_stall(ic_stall), |
.if_stall(if_stall), |
.dclsu_unstall(dclsu_unstall), |
.branch_stall(branch_stall), |
.force_dslot_fetch(force_dslot_fetch), |
.pipeline_freeze(pipeline_freeze) |
); |
|
481,7 → 532,9
.insn(tp_insn), |
.tp1w(tp1w), |
.tp2w(tp2w), |
.tp3w(tp3w) |
.tp3w(tp3w), |
.tp4w(), |
.tpdw() |
); |
|
endmodule |
/trunk/or1200/rtl/verilog/except.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
`define EXCEPTFSM_WIDTH 2 |
68,7 → 73,7
|
// Internal i/f |
sig_dtlbmiss, sig_dmmufault, sig_inthigh, sig_syscall, sig_itlbmiss, |
sig_immufault, sig_intlow, branch_taken, pipeline_freeze, ic_stall, |
sig_immufault, sig_intlow, branch_taken, pipeline_freeze, if_stall, |
if_pc, lr_sav, except_flushpipe, except_type, except_start, |
except_started, wb_pc, datain, epcr_we, eear_we, esr_we, epcr, eear, |
esr, sr, lsu_addr |
88,7 → 93,7
input sig_intlow; |
input branch_taken; |
input pipeline_freeze; |
input ic_stall; |
input if_stall; |
input [31:0] if_pc; |
output [31:2] lr_sav; |
input [31:0] datain; |
147,8 → 152,12
delayed2_ex_dslot <= #1 1'b0; |
end |
else if (!pipeline_freeze) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: id_pc <= %h", $time, if_pc); |
$display("%t: ex_pc <= %h", $time, id_pc); |
// synopsys translate_on |
`endif |
ex_dslot <= #1 branch_taken; |
id_pc <= #1 if_pc; |
ex_pc <= #1 id_pc; |
190,19 → 199,35
state <= #1 `EXCEPTFSM_FLU1; |
extend_flush <= #1 1'b1; |
if (ex_dslot) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: Exception during first delay slot instruction."); |
// synopsys translate_on |
`endif |
epcr <= #1 wb_pc; |
end |
else if (delayed1_ex_dslot) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: Exception during second (NOP) delay slot instruction."); |
// synopsys translate_on |
`endif |
epcr <= #1 id_pc; |
end |
else if (delayed2_ex_dslot) begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN)."); |
// synopsys translate_on |
`endif |
epcr <= #1 id_pc; |
end |
else begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: Exception during normal (no delay slot) instruction."); |
// synopsys translate_on |
`endif |
epcr <= #1 ex_pc; |
end |
esr <= #1 sr; |
235,9 → 260,13
esr <= #1 datain; |
end |
`EXCEPTFSM_FLU1: |
if (!ic_stall && !pipeline_freeze) |
if (!if_stall && !pipeline_freeze) |
begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr); |
// synopsys translate_on |
`endif |
state <= #1 `EXCEPTFSM_FLU2; |
except_type <= #1 `EXCEPT_NONE; |
end |
244,7 → 273,11
`EXCEPTFSM_FLU2: |
state <= #1 `EXCEPTFSM_FLU3; |
`EXCEPTFSM_FLU3: begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" INFO: Exception just finished flushing pipeline."); |
// synopsys translate_on |
`endif |
state <= #1 `EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
end |
/trunk/or1200/rtl/verilog/generic_spram_2048x32.v
62,12 → 62,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_2048x32( |
// Generic synchronous single-port RAM interface |
104,7 → 110,7
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hdsp_2048x32 #(dw, 2<<aw, aw) artisan_ssp( |
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
163,7 → 169,7
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp( |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
400,7 → 406,7
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
/trunk/or1200/rtl/verilog/xcv_ram32x8d.v
44,8 → 44,16
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
`ifdef XILINX_RAM32X1D |
|
module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE); |
/trunk/or1200/rtl/verilog/ic_ram.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/22 03:31:54 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
52,7 → 55,9
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module ic_ram( |
60,7 → 65,7
clk, rst, |
|
// Internal i/f |
addr, we, datain, dataout |
addr, en, we, datain, dataout |
); |
|
parameter dw = `OPERAND_WIDTH; |
72,17 → 77,27
input clk; |
input rst; |
input [aw-1:0] addr; |
input en; |
input [3:0] we; |
input [dw-1:0] datain; |
output [dw-1:0] dataout; |
|
`ifdef OR1200_NO_IC |
|
// |
// Insn cache not implemented |
// |
assign dataout = {dw{1'b0}}; |
|
`else |
|
// |
// Instantiation of 2048x32 RAM block |
// |
generic_spram_2048x32 ic_ram0( |
.clk(clk), |
.rst(rst), |
.ce(1'b1), |
.ce(en), |
.we(we[0]), |
.oe(1'b1), |
.addr(addr), |
90,5 → 105,7
.do(dataout) |
); |
|
`endif |
|
endmodule |
|
/trunk/or1200/rtl/verilog/itlb.v
0,0 → 1,216
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1200's Insn TLB //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// Instantiation of ITLB. //// |
//// //// |
//// To Do: //// |
//// - make it smaller and faster //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// |
// Insn TLB |
// |
|
module itlb( |
// Rst and clk |
clk, rst, |
|
// I/F for translation |
tlb_en, vaddr, hit, ppn, uxe, sxe, |
|
// SPR access |
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o |
); |
|
parameter dw = `OPERAND_WIDTH; |
parameter aw = `OPERAND_WIDTH; |
|
// |
// I/O |
// |
|
// |
// Clock and reset |
// |
input clk; |
input rst; |
|
// |
// I/F for translation |
// |
input tlb_en; |
input [aw-1:0] vaddr; |
output hit; |
output [31:13] ppn; |
output uxe; |
output sxe; |
|
// |
// SPR access |
// |
input spr_cs; |
input spr_write; |
input [31:0] spr_addr; |
input [31:0] spr_dat_i; |
output [31:0] spr_dat_o; |
|
// |
// Internal wires and regs |
// |
wire [31:19] vpn; |
wire v; |
wire [5:0] tlb_index; |
wire tlb_mr_en; |
wire tlb_mr_we; |
wire [13:0] tlb_mr_ram_in; |
wire [13:0] tlb_mr_ram_out; |
wire tlb_tr_en; |
wire tlb_tr_we; |
wire [20:0] tlb_tr_ram_in; |
wire [20:0] tlb_tr_ram_out; |
|
// |
// Implemented bits inside match and translate registers |
// |
// itlbwYmrX: vpn 31-19 v 0 |
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6 |
// |
// itlb memory width: |
// 19 bits for ppn |
// 13 bits for vpn |
// 1 bit for valid |
// 2 bits for protection |
|
// |
// Enable for Match registers |
// |
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[9]); |
|
// |
// Write enable for Match registers |
// |
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9]; |
|
// |
// Enable for Translate registers |
// |
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[9]); |
|
// |
// Write enable for Translate registers |
// |
assign tlb_tr_we = spr_cs & spr_write & spr_addr[9]; |
|
// |
// Output to SPRS unit |
// |
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ? |
{vpn, {18{1'b1}}, v} : |
(spr_cs & !spr_write & spr_addr[9]) ? |
{ppn, 5'b00000, uxe, sxe, {6{1'b1}}} : |
32'h00000000; |
|
// |
// Assign outputs from Match registers |
// |
assign {vpn, v} = tlb_mr_ram_out; |
|
// |
// Assign to Match registers inputs |
// |
assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]}; |
|
// |
// Assign outputs from Translate registers |
// |
assign {ppn, uxe, sxe} = tlb_tr_ram_out; |
|
// |
// Assign to Translate registers inputs |
// |
assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[9:6]}; |
|
// |
// Generate hit |
// |
assign hit = (vpn == vaddr[31:19]) & v; |
|
// |
// TLB index is normally vaddr[18:13]. If it is SPR access then index is |
// spr_addr[5:0]. |
// |
assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13]; |
|
// |
// Instantiation of ITLB Match Registers |
// |
generic_spram_64x14 itlb_mr_ram( |
.clk(clk), |
.rst(rst), |
.ce(tlb_mr_en), |
.we(tlb_mr_we), |
.oe(1'b1), |
.addr(tlb_index), |
.di(tlb_mr_ram_in), |
.do(tlb_mr_ram_out) |
); |
|
// |
// Instantiation of ITLB Translate Registers |
// |
generic_spram_64x21 itlb_tr_ram( |
.clk(clk), |
.rst(rst), |
.ce(tlb_tr_en), |
.we(tlb_tr_we), |
.oe(1'b1), |
.addr(tlb_index), |
.di(tlb_tr_ram_in), |
.do(tlb_tr_ram_out) |
); |
|
endmodule |
/trunk/or1200/rtl/verilog/generic_spram_512x20.v
0,0 → 1,289
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// - Artisan Single-Port Sync RAM //// |
//// - Avant! Two-Port Sync RAM (*) //// |
//// - Virage Single-Port Sync RAM //// |
//// - Virtual Silicon Single-Port Sync RAM //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// //// |
//// To Do: //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs (Altera etc) //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_spram_512x20( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 9; |
parameter dw = 20; |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
|
|
`ifdef ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp( |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
); |
|
`else |
|
`ifdef AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
avant_atp avant_atp( |
.web(~we), |
.reb(), |
.oeb(~oe), |
.rcsb(), |
.wcsb(), |
.ra(addr), |
.wa(addr), |
.di(di), |
.do(do) |
); |
|
`else |
|
`ifdef VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
virage_ssp virage_ssp( |
.clk(clk), |
.adr(addr), |
.d(di), |
.we(we), |
.oe(oe), |
.me(ce), |
.q(do) |
); |
|
`else |
|
`ifdef VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
.CK(clk), |
.ADR(addr), |
.DI(di), |
.WEN(~we), |
.CEN(~ce), |
.OEN(~oe), |
.DOUT(do) |
); |
|
`else |
|
`ifdef XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S4 ramb4_s4_0( |
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[3:0]), |
.EN(ce), |
.WE(we), |
.DO(do[3:0]) |
); |
|
// |
// Block 1 |
// |
RAMB4_S4 ramb4_s4_1( |
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[7:4]), |
.EN(ce), |
.WE(we), |
.DO(do[7:4]) |
); |
|
// |
// Block 2 |
// |
RAMB4_S4 ramb4_s4_2( |
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[11:8]), |
.EN(ce), |
.WE(we), |
.DO(do[11:8]) |
); |
|
// |
// Block 3 |
// |
RAMB4_S4 ramb4_s4_3( |
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[15:12]), |
.EN(ce), |
.WE(we), |
.DO(do[15:12]) |
); |
|
// |
// Block 4 |
// |
RAMB4_S4 ramb4_s4_4( |
.CLK(clk), |
.RST(rst), |
.ADDR(addr), |
.DI(di[19:16]), |
.EN(ce), |
.WE(we), |
.DO(do[19:16]) |
); |
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !XILINX_RAMB4_S16 |
`endif // !VIRTUALSILICON_SSP |
`endif // !VIRAGE_SSP |
`endif // !AVANT_ATP |
`endif // !ARTISAN_SSP |
|
endmodule |
trunk/or1200/rtl/verilog/generic_spram_512x20.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/ic_fsm.v
===================================================================
--- trunk/or1200/rtl/verilog/ic_fsm.v (revision 202)
+++ trunk/or1200/rtl/verilog/ic_fsm.v (revision 203)
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.3 2001/08/17 08:01:19 lampret
+// IC enable/disable.
+//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
@@ -52,12 +55,14 @@
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
-`define ICFSM_IDLE 'd0
-`define ICFSM_DOLOAD 'd1
-`define ICFSM_LREFILL3 'd2
+`define ICFSM_IDLE 3'd0
+`define ICFSM_DOLOAD 3'd1
+`define ICFSM_LREFILL3 3'd2
//
// Insn cache FSM for cache line of 16 bytes (4x singleword)
@@ -124,7 +129,7 @@
always @(posedge clk or posedge rst) begin
if (rst) begin
refill <= #1 1'b0;
- state <= #1 3`ICFSM_IDLE;
+ state <= #1 `ICFSM_IDLE;
biu_read <= #1 1'b0;
saved_addr <= #1 32'b0;
refill_first <= #1 1'b0;
@@ -138,8 +143,12 @@
`ICFSM_IDLE :
case(fetch_op)
`FETCHOP_LW: begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: IC_FSM Load op %h start_addr %h", $time, fetch_op, start_addr);
- state <= #1 3`ICFSM_DOLOAD;
+// synopsys translate_on
+`endif
+ state <= #1 `ICFSM_DOLOAD;
refill <= #1 1'b0;
saved_addr <= #1 start_addr;
refill_first <= #1 1'b0;
@@ -149,7 +158,7 @@
cntrbusy <= #1 1'b0;
end
default: begin
- state <= #1 3`ICFSM_IDLE;
+ state <= #1 `ICFSM_IDLE;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
refill_prepare <= #1 1'b0;
@@ -160,8 +169,12 @@
endcase
`ICFSM_DOLOAD:
if (icache_off) begin
-// $display("%t: IC_FSM ICache off", $time);
- state <= #1 3`ICFSM_DOLOAD;
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
+ $display("%t: IC_FSM ICache off", $time);
+// synopsys translate_on
+`endif
+ state <= #1 `ICFSM_DOLOAD;
refill <= #1 1'b1;
refill_first <= #1 1'b1;
refill_prepare <= #1 1'b0;
@@ -175,8 +188,12 @@
end
end else
if (miss) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: IC_FSM Load miss", $time);
- state <= #1 3`ICFSM_LREFILL3;
+// synopsys translate_on
+`endif
+ state <= #1 `ICFSM_LREFILL3;
refill <= #1 1'b1;
refill_first <= #1 1'b1;
refill_prepare <= #1 1'b0;
@@ -185,8 +202,12 @@
biu_read <= #1 1'b1;
end
else begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: IC_FSM Load hit", $time);
- state <= #1 3`ICFSM_DOLOAD;
+// synopsys translate_on
+`endif
+ state <= #1 `ICFSM_DOLOAD;
saved_addr <= #1 start_addr;
refill <= #1 1'b0;
refill_first <= #1 1'b0;
@@ -196,14 +217,22 @@
end
`ICFSM_LREFILL3 : begin
if (biudata_valid && cnt) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: IC_FSM Load refill %d", $time, cnt);
+// synopsys translate_on
+`endif
cnt <= #1 cnt - 'd1;
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
refill_first <= #1 1'b0;
end
else if (biudata_valid) begin
+`ifdef OR1200_VERBOSE
+// synopsys translate_off
$display("%t: IC_FSM Load refill end", $time, cnt);
- state <= #1 3`ICFSM_DOLOAD;
+// synopsys translate_on
+`endif
+ state <= #1 `ICFSM_DOLOAD;
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
refill <= #1 1'b1;
refill_first <= #1 1'b0;
/trunk/or1200/rtl/verilog/generic_dpram_32x32.v
61,12 → 61,18
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module generic_dpram_32x32( |
// Generic synchronous double-port RAM interface |
107,7 → 113,7
// |
// Artisan Synchronous Double-Port RAM (ra2sh) |
// |
art_hsdp_32x32 #(dw, 2<<aw, aw) artisan_sdp( |
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp( |
.qa(do_a), |
.clka(clk_a), |
.cena(~ce_a), |
297,7 → 303,7
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
/trunk/or1200/rtl/verilog/ifetch.v
44,9 → 44,14
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module ifetch( |
54,12 → 59,12
clk, rst, |
|
// External i/f to IC |
ic_insn, ic_pcaddr, ic_stall, tp_insn, tp_wr_insn, |
ic_insn, ic_addr, ic_stall, ic_fetchop, tp_insn, tp_wr_insn, |
|
// Internal i/f |
pipeline_freeze, if_insn, if_pc, branch_op, except_type, |
branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start, |
epcr |
epcr, force_dslot_fetch, if_stall, branch_stall |
); |
|
// |
76,7 → 81,8
// External i/f to IC |
// |
input [31:0] ic_insn; |
output [31:0] ic_pcaddr; |
output [31:0] ic_addr; |
output [`FETCHOP_WIDTH-1:0] ic_fetchop; |
input ic_stall; |
input [31:0] tp_insn; |
input tp_wr_insn; |
96,13 → 102,18
output taken; |
input except_start; |
input [31:0] epcr; |
input force_dslot_fetch; |
output if_stall; |
output branch_stall; |
|
// |
// Internal wires and regs |
// |
reg [31:2] pcreg; |
reg [32:2] dslot_pc; |
reg [32:0] if_saved; |
reg [31:0] ic_pcaddr; |
reg [31:0] pcaddr; |
reg [31:0] pc_saved; |
reg taken; /* Set to in case of jump or taken branch */ |
|
// Selection between insn from IC or Trace port |
111,14 → 122,35
// |
// Current registered PC (corresponds to fetched instruction) |
// |
assign if_pc = {pcreg[31:2], 2'b0}; |
//assign if_pc = {pcreg[31:2], 2'b00}; |
assign if_pc = (if_saved[32]) ? pc_saved : ic_addr; |
assign ic_addr = dslot_pc[32] ? {dslot_pc[31:2], 2'b00} : pcaddr; |
assign branch_stall = dslot_pc[32] & taken; |
//assign if_stall = ic_stall | (~branch_stall & taken); |
assign if_stall = ic_stall; |
|
// |
// Control access to IC subsystem |
// |
assign ic_fetchop = (if_saved[32] & !if_stall) ? `FETCHOP_NOP : `FETCHOP_LW; |
|
// |
// Just fetched instruction |
// |
assign if_insn = (if_saved[32]) ? if_saved[31:0] : ((taken || ic_stall) ? 32'h1500FFFF : ic_tp_insn); |
assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall) ? 32'h1500FFFF : ic_tp_insn; |
|
// |
// Delay slot PC saved |
// |
always @(posedge clk or posedge rst) |
if (rst) |
dslot_pc <= #1 31'h00000000; |
// else if (force_dslot_fetch) |
// dslot_pc <= #1 {1'b1, pcaddr[31:2]}; |
else if (!ic_stall) |
dslot_pc <= #1 31'h00000000; |
|
// |
// Async calculation of new PC value. This value is used for addressing the IC. |
// |
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type |
125,57 → 157,91
or except_start or lr_restor or epcr) begin |
casex ({except_start, branch_op}) // synopsys parallel_case |
{1'b0, `BRANCHOP_NOP}: begin |
ic_pcaddr <= #1 {pcreg + 'd1, 2'b0}; |
taken <= #1 1'b0; |
pcaddr = {pcreg + 'd1, 2'b0}; |
taken = 1'b0; |
end |
{1'b0, `BRANCHOP_J}: begin |
$display("%t: BRANCHOP_J: ic_pcaddr <= branch_addrofs %h", $time, branch_addrofs); |
ic_pcaddr <= #1 {branch_addrofs, 2'b0}; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_J: pcaddr <= branch_addrofs %h", $time, branch_addrofs); |
// synopsys translate_on |
`endif |
pcaddr = {branch_addrofs, 2'b0}; |
taken = 1'b1; |
end |
{1'b0, `BRANCHOP_JR}: begin |
$display("%t: BRANCHOP_JR: ic_pcaddr <= lr_restor %h", $time, lr_restor); |
ic_pcaddr <= #1 lr_restor; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_JR: pcaddr <= lr_restor %h", $time, lr_restor); |
// synopsys translate_on |
`endif |
pcaddr = lr_restor; |
taken = 1'b1; |
end |
{1'b0, `BRANCHOP_BAL}: begin |
$display("%t: BRANCHOP_BAL: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0}; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_BAL: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
// synopsys translate_on |
`endif |
pcaddr = {binsn_addr + branch_addrofs, 2'b0}; |
taken = 1'b1; |
end |
{1'b0, `BRANCHOP_BF}: |
if (flag) begin |
$display("%t: BRANCHOP_BF: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0}; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_BF: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
// synopsys translate_on |
`endif |
pcaddr = {binsn_addr + branch_addrofs, 2'b0}; |
taken = 1'b1; |
end |
else begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_BF: not taken", $time); |
ic_pcaddr <= #1 {pcreg + 'd1, 2'b0}; |
taken <= #1 1'b0; |
// synopsys translate_on |
`endif |
pcaddr = {pcreg + 'd1, 2'b0}; |
taken = 1'b0; |
end |
{1'b0, `BRANCHOP_BNF}: |
if (flag) begin |
ic_pcaddr <= #1 {pcreg + 'd1, 2'b0}; |
pcaddr = {pcreg + 'd1, 2'b0}; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_BNF: not taken", $time); |
taken <= #1 1'b0; |
// synopsys translate_on |
`endif |
taken = 1'b0; |
end |
else begin |
$display("%t: BRANCHOP_BNF: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0}; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_BNF: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); |
// synopsys translate_on |
`endif |
pcaddr = {binsn_addr + branch_addrofs, 2'b0}; |
taken = 1'b1; |
end |
{1'b0, `BRANCHOP_RFE}: begin |
$display("%t: BRANCHOP_RFE: ic_pcaddr <= epcr %h", $time, epcr); |
ic_pcaddr <= #1 epcr; |
taken <= #1 1'b1; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: BRANCHOP_RFE: pcaddr <= epcr %h", $time, epcr); |
// synopsys translate_on |
`endif |
pcaddr = epcr; |
taken = 1'b1; |
end |
default: begin |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("Starting exception: %h.", except_type); |
// synopsys translate_on |
ic_pcaddr <= #1 { 21'h0, except_type, 8'h00}; |
taken <= #1 1'b1; |
`endif |
pcaddr = { 21'h0, except_type, 8'h00}; |
taken = 1'b1; |
end |
endcase |
end |
187,8 → 253,12
if (rst) |
pcreg <= #1 30'd64; |
else if (!pipeline_freeze && !ic_stall) begin |
pcreg <= #1 ic_pcaddr[31:2]; |
$display("%t: pcreg incremented to %h", $time, {ic_pcaddr[31:2], 2'b0}); |
pcreg <= #1 ic_addr[31:2]; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: pcreg incremented to %h", $time, {ic_addr[31:2], 2'b0}); |
// synopsys translate_on |
`endif |
end |
end |
|
199,14 → 269,36
if (rst) begin |
if_saved <= #1 33'b0; |
end |
else if (pipeline_freeze && !if_saved[32] && !ic_stall && !taken) begin |
else if (pipeline_freeze && !if_saved[32] && !ic_stall) begin // && !taken |
if_saved <= #1 {1'b1, ic_tp_insn}; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: if_saved <= %h", $time, {1'b1, ic_tp_insn}); |
// synopsys translate_on |
`endif |
end |
else if (!pipeline_freeze) begin |
if_saved[32] <= #1 1'b0; |
if_saved[31:0] <= #1 32'h1500eeee; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display("%t: if_saved[32] <= 0", $time); |
// synopsys translate_on |
`endif |
end |
|
// |
// Stores PC when pipeline is frozen |
// |
always @(posedge clk or posedge rst) |
if (rst) begin |
pc_saved <= #1 32'b0; |
end |
else if (pipeline_freeze && !if_saved[32] && !ic_stall) begin // && !taken |
pc_saved <= #1 ic_addr; |
end |
else if (!pipeline_freeze) begin |
pc_saved <= #1 32'h00000000; |
end |
|
endmodule |
/trunk/or1200/rtl/verilog/wbmux.v
44,12 → 44,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:23 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
module wbmux( |
113,18 → 118,30
// |
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin |
case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux |
'b00: muxout <= #1 muxin_a; |
'b00: muxout = muxin_a; |
'b01: begin |
muxout <= #1 muxin_b; |
muxout = muxin_b; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" WBMUX: muxin_b %h", muxin_b); |
// translate_on |
`endif |
end |
'b10: begin |
muxout <= #1 muxin_c; |
muxout = muxin_c; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" WBMUX: muxin_c %h", muxin_c); |
// translate_on |
`endif |
end |
'b11: begin |
muxout <= #1 muxin_d + 4'h8; |
muxout = muxin_d + 4'h8; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" WBMUX: muxin_d %h", muxin_d + 4'h8); |
// translate_on |
`endif |
end |
endcase |
end |
/trunk/or1200/rtl/verilog/dmmu.v
0,0 → 1,234
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1200's Data MMU top level //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// Instantiation of all DMMU blocks. //// |
//// //// |
//// To Do: //// |
//// - make it smaller and faster //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/17 08:03:35 lampret |
// *** empty log message *** |
// |
// Revision 1.2 2001/07/22 03:31:53 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
|
// |
// Data MMU |
// |
|
module dmmu( |
// Rst and clk |
clk, rst, |
|
// LSU i/f |
dmmu_en, supv, dmmulsu_vaddr, dmmulsu_lsuop, dmmulsu_stall, |
|
// Except I/F |
dmmuexcept_miss, dmmuexcept_fault, |
|
// SPR access |
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, |
|
// DC i/f |
dcdmmu_paddr |
); |
|
parameter dw = `OPERAND_WIDTH; |
parameter aw = `OPERAND_WIDTH; |
|
// |
// I/O |
// |
|
// |
// Clock and reset |
// |
input clk; |
input rst; |
|
// |
// LSU I/F |
// |
input dmmu_en; |
input supv; |
input [aw-1:0] dmmulsu_vaddr; |
input [`LSUOP_WIDTH-1:0] dmmulsu_lsuop; |
output dmmulsu_stall; |
|
// |
// Exception I/F |
// |
output dmmuexcept_miss; |
output dmmuexcept_fault; |
|
// |
// SPR access |
// |
input spr_cs; |
input spr_write; |
input [aw-1:0] spr_addr; |
input [31:0] spr_dat_i; |
output [31:0] spr_dat_o; |
|
// |
// DC I/F |
// |
output [aw-1:0] dcdmmu_paddr; |
|
// |
// Internal wires and regs |
// |
wire dtlb_spr_access; |
wire [31:13] dtlb_ppn; |
wire dtlb_hit; |
wire dtlb_uwe; |
wire dtlb_ure; |
wire dtlb_swe; |
wire dtlb_sre; |
wire [31:0] dtlb_dat_o; |
|
// |
// Implemented bits inside match and translate registers |
// |
// dtlbwYmrX: vpn 31-10 v 0 |
// dtlbwYtrX: ppn 31-10 uwe 9 ure 8 swe 7 sre 6 |
// |
// dtlb memory width: |
// 19 bits for ppn |
// 13 bits for vpn |
// 1 bit for valid |
// 4 bits for protection |
|
`ifdef OR1200_NO_DMMU |
|
// |
// Put all outputs in inactive state |
// |
assign dmmulsu_stall = 1'b0; |
assign dmmuexcept_miss = 1'b0; |
assign dmmuexcept_miss = 1'b1; |
output spr_dat_o = 32'h00000000; |
output dcdmmu_paddr = dmmlsu_vaddr; |
|
`else |
|
// |
// DTLB SPR access |
// |
// 0C00 - 0E00 dtlbmr w0-3 |
// 0C00 - 0C80 dtlbmr w0 |
// 0C00 - 0C40 dtlbmr w0 [63:0] |
// |
// 0E00 - 1000 dtlbtr w0-3 |
// 0E00 - 0E80 dtlbtr w0 |
// 0E00 - 0E40 dtlbtr w0 [63:0] |
// |
assign dtlb_spr_access = spr_cs & spr_addr[10]; |
|
// |
// Physical address is either translated virtual address or |
// simply equal when DMMU is disabled |
// |
assign dcdmmu_paddr = dmmu_en ? {dtlb_ppn, dmmulsu_vaddr[12:0]} : dmmulsu_vaddr; |
|
// |
// Output to SPRS unit |
// |
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000; |
|
// |
// DMMU stall |
// |
assign dmmulsu_stall = 1'b0; |
|
// |
// Page fault exception logic |
// |
assign dmmuexcept_fault = dmmulsu_lsuop && dmmu_en && |
( (!dmmulsu_lsuop[3] & !supv & !dtlb_ure) // Load in user mode not enabled |
|| (!dmmulsu_lsuop[3] & supv & !dtlb_sre) // Load in supv mode not enabled |
|| (dmmulsu_lsuop[3] & !supv & !dtlb_uwe) // Store in user mode not enabled |
|| (dmmulsu_lsuop[3] & supv & !dtlb_swe) ); // Store in supv mode not enabled |
|
// |
// TLB Miss exception logic |
// |
assign dmmuexcept_miss = dmmulsu_lsuop && dmmu_en && !dtlb_hit; |
|
// |
// Instantiation of DTLB |
// |
dtlb dtlb( |
// Rst and clk |
.clk(clk), |
.rst(rst), |
|
// I/F for translation |
.tlb_en(dmmu_en), |
.vaddr(dmmulsu_vaddr), |
.hit(dtlb_hit), |
.ppn(dtlb_ppn), |
.uwe(dtlb_uwe), |
.ure(dtlb_ure), |
.swe(dtlb_swe), |
.sre(dtlb_sre), |
|
// SPR access |
.spr_cs(dtlb_spr_access), |
.spr_write(spr_write), |
.spr_addr(spr_addr), |
.spr_dat_i(spr_dat_i), |
.spr_dat_o(dtlb_dat_o) |
); |
|
`endif |
|
endmodule |
trunk/or1200/rtl/verilog/dmmu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/or1200/rtl/verilog/rf.v
===================================================================
--- trunk/or1200/rtl/verilog/rf.v (revision 202)
+++ trunk/or1200/rtl/verilog/rf.v (revision 203)
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: not supported by cvs2svn $
+// Revision 1.3 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
@@ -52,7 +55,9 @@
//
//
+// synopsys translate_off
`include "timescale.v"
+// synopsys translate_on
`include "defines.v"
module rf(
@@ -164,15 +169,17 @@
datab_saved[32] <= #1 1'b0;
//
-// Instantiation of register file dual-port RAM A
+// Instantiation of register file two-port RAM A
//
-generic_dpram_32x32 rf_a(
+generic_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
+ .we_a(1'b0),
.oe_a(1'b1),
.addr_a(addra),
+ .di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
@@ -180,20 +187,24 @@
.rst_b(rst),
.ce_b(we),
.we_b(we),
+ .oe_b(1'b0),
.addr_b(addrw),
- .di_b(dataw)
+ .di_b(dataw),
+ .do_b()
);
//
-// Instantiation of register file dual-port RAM B
+// Instantiation of register file two-port RAM B
//
-generic_dpram_32x32 rf_b(
+generic_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
+ .we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
+ .di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
@@ -201,8 +212,10 @@
.rst_b(rst),
.ce_b(we),
.we_b(we),
+ .oe_b(1'b0),
.addr_b(addrw),
- .di_b(dataw)
+ .di_b(dataw),
+ .do_b()
);
endmodule
/trunk/or1200/rtl/verilog/wb_biu.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/22 03:31:54 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
52,7 → 55,9
// |
// |
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// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "defines.v" |
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module wb_biu( |
70,31 → 75,42
// |
// WISHBONE interface |
// |
input wb_clk_i; // clock input |
input wb_rst_i; // reset input |
input wb_ack_i; // normal termination |
input wb_err_i; // termination w/ error |
input wb_rty_i; // termination w/ retry |
input [dw-1:0] wb_dat_i; // input data bus |
output wb_cyc_o; // cycle valid output |
output [aw-1:0] wb_adr_o; // address bus outputs |
output wb_stb_o; // strobe output |
output wb_we_o; // indicates write transfer |
output [3:0] wb_sel_o; // byte select outputs |
output [dw-1:0] wb_dat_o; // output data bus |
input wb_clk_i; // clock input |
input wb_rst_i; // reset input |
input wb_ack_i; // normal termination |
input wb_err_i; // termination w/ error |
input wb_rty_i; // termination w/ retry |
input [dw-1:0] wb_dat_i; // input data bus |
output wb_cyc_o; // cycle valid output |
output [aw-1:0] wb_adr_o; // address bus outputs |
output wb_stb_o; // strobe output |
output wb_we_o; // indicates write transfer |
output [3:0] wb_sel_o; // byte select outputs |
output [dw-1:0] wb_dat_o; // output data bus |
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// |
// Internal RISC interface |
// |
input [dw-1:0] biu_to_biu; // input data bus |
input [aw-1:0] biu_addr; // address bus |
input biu_read; // read request |
input biu_write; // write request |
output biu_rdy; // data valid |
output [dw-1:0] biu_from_biu; // output data bus |
input [3:0] biu_sel; // byte select inputs |
input [dw-1:0] biu_to_biu; // input data bus |
input [aw-1:0] biu_addr; // address bus |
input biu_read; // read request |
input biu_write; // write request |
output biu_rdy; // data valid |
output [dw-1:0] biu_from_biu; // output data bus |
input [3:0] biu_sel; // byte select inputs |
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// |
// Registers |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
reg [aw-1:0] wb_adr_o; // address bus outputs |
reg wb_stb_o; // strobe output |
reg wb_we_o; // indicates write transfer |
reg [3:0] wb_sel_o; // byte select outputs |
reg [dw-1:0] wb_dat_o; // output data bus |
`endif |
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// |
// WISHBONE I/F <-> Internal RISC I/F conversion |
// |
|
101,7 → 117,15
// |
// Address bus |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_adr_o <= #1 {aw{1'b0}}; |
else |
wb_adr_o <= #1 biu_addr; |
`else |
assign wb_adr_o = biu_addr; |
`endif |
|
// |
// Input data bus |
111,7 → 135,15
// |
// Output data bus |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_dat_o <= #1 {dw{1'b0}}; |
else |
wb_dat_o <= #1 biu_to_biu; |
`else |
assign wb_dat_o = biu_to_biu; |
`endif |
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// |
// Acknowledgment of the data to the RISC |
126,16 → 158,40
// |
// WB stb_o |
// |
assign wb_stb_o = biu_read | biu_write; |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_stb_o <= #1 1'b0; |
else |
wb_stb_o <= #1 (biu_read | biu_write); |
`else |
assign wb_stb_o = (biu_read | biu_write); |
`endif |
|
// |
// WB we_o |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_we_o <= #1 1'b0; |
else |
wb_we_o <= #1 biu_write; |
`else |
assign wb_we_o = biu_write; |
`endif |
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// |
// WB sel_o |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_sel_o <= #1 4'b0000; |
else |
wb_sel_o <= #1 biu_sel; |
`else |
assign wb_sel_o = biu_sel; |
`endif |
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endmodule |