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Rev 21 → Rev 22

/trunk/rtl/verilog/ocidec-1/ud_cnt.v
1,10 → 1,50
/////////////////////////////////////////////////////////////////////
//// ////
//// Generic Up/Down counter ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// file: ud_cnt.v (universal up/down counter)
// $Id: ud_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
//
// Author: Richard Herveille
// Rev. 1.0 June 27th, 2001. Initial Verilog release
// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list.
// $Date: 2002-02-16 10:42:17 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
 
/////////////////////////////
13,9 → 53,11
 
`include "timescale.v"
 
module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, resd, rci, rco);
module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco);
// parameter declaration
parameter SIZE = 8;
parameter RESD = {SIZE{1'b0}}; // data after reset
 
// inputs & outputs
input clk; // master clock
input nReset; // asynchronous active low reset
25,7 → 67,6
input nld; // synchronous active low load
input [SIZE-1:0] d; // load counter value
output [SIZE-1:0] q; // current counter value
input [SIZE-1:0] resd; // initial data after/during reset
input rci; // carry input
output rco; // carry output
 
42,9 → 83,9
always@(posedge clk or negedge nReset)
begin
if (~nReset)
Qi <= #1 resd;
Qi <= #1 RESD;
else if (rst)
Qi <= #1 resd;
Qi <= #1 RESD;
else if (~nld)
Qi <= #1 d;
else if (cnt_en)
55,3 → 96,5
assign q = Qi;
assign rco = val[SIZE];
endmodule
 
 
/trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v
1,17 → 1,57
//
// file: pio_tctrl.v
// description: PIO mode timing controller for ATA controller
// author : Richard Herveille
// Rev. 1.0 June 27th, 2001. Initial Verilog release
// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues.
// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation.
/////////////////////////////////////////////////////////////////////
//// ////
//// OCIDEC-1 ATA Controller ////
//// PIO Mode timing controller ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
///////////////////////////
// PIO Timing controller //
///////////////////////////
// $Id: atahost_pio_tctrl.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
//
// $Date: 2002-02-16 10:42:17 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// Rev. 1.0 June 27th, 2001. Initial Verilog release
// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues.
// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation.
//
// $Log: not supported by cvs2svn $
//
 
 
//
// Timing PIO mode transfers
//--------------------------------------------
126,7 → 166,17
assign igo = (go | hold_go) & !busy;
 
// 1) hookup T1 counter
ro_cnt #(TWIDTH) t1_cnt(.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(1'b1), .go(igo), .d(T1), .id(T1_m0), .done(T1done), .q());
ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1)
t1_cnt(
.clk(clk),
.rst(rst),
.nReset(nReset),
.cnt_en(1'b1),
.go(igo),
.d(T1),
.q(),
.done(T1done)
);
 
// 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device
always@(posedge clk or negedge nReset)
150,7 → 200,17
end
 
// 3) hookup T2 counter
ro_cnt #(TWIDTH) t2_cnt(.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(1'b1), .go(T1done), .d(T2), .id(T2_m0), .done(T2done), .q());
ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2)
t2_cnt(
.clk(clk),
.rst(rst),
.nReset(nReset),
.cnt_en(1'b1),
.go(T1done),
.d(T2),
.q(),
.done(T2done)
);
 
// 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
// hold T2done
169,11 → 229,32
dstrb <= IORDY_done;
 
// hookup data hold counter
ro_cnt #(TWIDTH) dhold_cnt(.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(1'b1), .go(IORDY_done), .d(T4), .id(T4_m0), .done(T4done), .q());
ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4)
dhold_cnt(
.clk(clk),
.rst(rst),
.nReset(nReset),
.cnt_en(1'b1),
.go(IORDY_done),
.d(T4),
.q(),
.done(T4done)
);
 
assign done = T4done; // placing done here provides the fastest return possible,
// while still guaranteeing data and address hold-times
 
// 5) hookup end_of_cycle counter
ro_cnt #(TWIDTH) eoc_cnt(.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(1'b1), .go(IORDY_done), .d(Teoc), .id(Teoc_m0), .done(Teoc_done), .q());
ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc)
eoc_cnt(
.clk(clk),
.rst(rst),
.nReset(nReset),
.cnt_en(1'b1),
.go(IORDY_done),
.d(Teoc),
.q(),
.done(Teoc_done)
);
 
endmodule
/trunk/rtl/verilog/ocidec-1/ro_cnt.v
1,11 → 1,52
/////////////////////////////////////////////////////////////////////
//// ////
//// Run-Once counter ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// Counter.v, contains 1) run-once down-counter 2) general purpose up-down riple-carry counter
// $Id: ro_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
//
// Author: Richard Herveille
// Rev. 1.0 June 27th, 2001. Initial Verilog release
// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list.
// $Date: 2002-02-16 10:42:17 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
 
///////////////////////////
// run-once down-counter //
///////////////////////////
14,9 → 55,14
 
`include "timescale.v"
 
module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q, id);
module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q);
 
// parameter declaration
parameter SIZE = 8;
 
parameter UD = 1'b0; // default count down
parameter ID = {SIZE{1'b0}}; // initial data after reset
 
// inputs & outputs
input clk; // master clock
input nReset; // asynchronous active low reset
26,7 → 72,6
output done; // done counting
input [SIZE-1:0] d; // load counter value
output [SIZE-1:0] q; // current counter value
input [SIZE-1:0] id; // initial data after reset
 
// variable declarations
reg rci;
41,15 → 86,21
rci <= #1 1'b0;
else if (rst)
rci <= #1 1'b0;
else if (cnt_en)
rci <= #1 (go | rci) & !rco;
else //if (cnt_en)
rci <= #1 go | (rci & !rco);
 
assign nld = !go;
 
// hookup counter
ud_cnt #(SIZE) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
.ud(1'b0), .nld(nld), .d(d), .q(q), .resd(id), .rci(rci), .rco(rco));
ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
.ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco));
 
 
// assign outputs
 
assign done = rco;
 
endmodule
 
 
 
/trunk/rtl/verilog/ocidec-1/atahost_top.v
1,19 → 1,69
/////////////////////////////////////////////////////////////////////
//// ////
//// OCIDEC-1 ATA/ATAPI-5 Controller ////
//// Main Controller ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// Project: AT Atachement interface
// ATA-3 rev7B compliant
// Author: Richard Herveille
// rev.: 1.0 June 29th, 2001. Initial Verilog release
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
// $Id: atahost_top.v,v 1.6 2002-02-16 10:42:17 rherveille Exp $
//
// $Date: 2002-02-16 10:42:17 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// rev.: 1.0 June 29th, 2001. Initial Verilog release
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
//
// $Log: not supported by cvs2svn $
//
//
//
 
/////////////////////////////////////////////////////////////
//
// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
// Features: PIO Compatible Timing
// DeviceID: 0x01
// RevNo : 0x00
//
 
//
// Host signals:
277,3 → 327,4
 
 
 
 
/trunk/rtl/verilog/ocidec-1/atahost_controller.v
1,16 → 1,58
//
// file: controller.v
// description: OCIDEC1 OpenCores IDE controller type-1
// author : Richard Herveille
// rev.: 1.0 june 28th, 2001. Initial Verilog release
// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section.
// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite.
// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
/////////////////////////////////////////////////////////////////////
//// ////
//// OCIDEC-1 ATA Controller ////
//// Main Controller ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// OCIDEC1 supports:
// -Common Compatible timing access to all connected devices
// CVS Log
//
// $Id: atahost_controller.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
//
// $Date: 2002-02-16 10:42:17 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// rev.: 1.0 june 28th, 2001. Initial Verilog release
// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section.
// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite.
// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
//
// $Log: not supported by cvs2svn $
//
//
 
`include "timescale.v"
 
191,3 → 233,4
PIOack <= PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
 
endmodule
 
/trunk/rtl/verilog/ocidec-1/revision_history.txt
54,7 → 54,7
-----------------------------
 
-----------------------------
Revision: 1.5
Revision: 1.6
Date: September 12th, 2001.
Author: Richard Herveille
- Made asynchronous input programmable (using atahost_define.v)
61,8 → 61,18
-----------------------------
 
-----------------------------
Revision: 1.5
Revision: 1.7
Date: October 16th, 2001.
Author: Richard Herveille
- Changed programmable asynchronous level from define to parameter
-----------------------------
 
-----------------------------
Revision: 1.8
Date: Februar 16th, 2002.
Author: Richard Herveille
- Added disclaimer
- Added CVS information
- Changed core for new counter libraries
- Updated testbench
-----------------------------

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