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/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf
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tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf
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Index: tags/arelease/ieee_1149.1_tap/InputCell.v
===================================================================
--- tags/arelease/ieee_1149.1_tap/InputCell.v (revision 21)
+++ tags/arelease/ieee_1149.1_tap/InputCell.v (nonexistent)
@@ -1,62 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Input Cell: *
-* *
-* InputPin: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR: TAP states *
-* TCK: Test Clock *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
-input InputPin;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-
-endmodule // InputCell
\ No newline at end of file
Index: tags/arelease/ieee_1149.1_tap/OutputCell.v
===================================================================
--- tags/arelease/ieee_1149.1_tap/OutputCell.v (revision 21)
+++ tags/arelease/ieee_1149.1_tap/OutputCell.v (nonexistent)
@@ -1,83 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Output Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* TristatedPin: Signal from core is connected to this output pin via BS *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to TristatedPin comes from core or BS chain. *
-* Tristate control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output TristatedPin;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-endmodule // OutputCell
\ No newline at end of file
Index: tags/arelease/ieee_1149.1_tap/ControlCell.v
===================================================================
--- tags/arelease/ieee_1149.1_tap/ControlCell.v (revision 21)
+++ tags/arelease/ieee_1149.1_tap/ControlCell.v (nonexistent)
@@ -1,77 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* I/O Control Cell: *
-* *
-* OutputControl: Output Control from on-chip logic *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* *
-* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
-* shifting data for the exact number of time *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
-input OutputControl;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-output ToOutputEnable;
-
-reg ToNextBSCell;
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-assign ToOutputEnable = extest? ShiftedControl : OutputControl;
-
-endmodule // ControlCell
\ No newline at end of file
Index: tags/arelease/ieee_1149.1_tap/TAP.v
===================================================================
--- tags/arelease/ieee_1149.1_tap/TAP.v (revision 21)
+++ tags/arelease/ieee_1149.1_tap/TAP.v (nonexistent)
@@ -1,585 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-// Top module
-module TAP(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO,
- TestSignal,
- InputPin,
- Output3Pin,
- Output2Pin,
- BidirectionalPin
- );
-
-`define BSLength 14
-
-supply1 vcc;
-supply0 gnd;
-
-// Instructions specified by the IEEE-1149.1
-parameter EXTEST = 4'b0000;
-parameter SAMPLE_PRELOAD = 4'b0001;
-parameter IDCODE = 4'b0010;
-parameter BYPASS = 4'b1111;
-
-
-input P_TMS, P_TCK;
-input P_TRST, P_TDI;
-
-output P_TDO;
-
-input [1:0] InputPin; // Input pin
-output [1:0] Output3Pin; // Output pin with tristate control
-output [1:0] Output2Pin; // Output pin without tristate control
-inout [1:0] BidirectionalPin; // Input/Output pin (with tristate control)
-
-output [5:0]TestSignal; // Signals for testing purposes (can be deleted)
-
-wire TCK = P_TCK;
-wire TCKn = ~P_TCK;
-wire TMS = P_TMS;
-wire TDI = P_TDI;
-
-wire TRST = P_TRST; // TRST is active high (for easier development). Should be change to active low
-//wire TRST = ~P_TRST; // active low
-
-reg TestLogicReset;
-reg RunTestIdle;
-reg SelectDRScan;
-reg CaptureDR;
-reg ShiftDR;
-reg Exit1DR;
-reg PauseDR;
-reg Exit2DR;
-reg UpdateDR;
-
-reg SelectIRScan;
-reg CaptureIR;
-reg ShiftIR;
-reg Exit1IR;
-reg PauseIR;
-reg Exit2IR;
-reg UpdateIR;
-
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-* P_TRST must toggle at the beginning if PowerONReset signal is not present *
-* in the design. *
-* *
-* *
-* *
-**********************************************************************************/
-//wire RESET = TRST | PowerONReset; // If PowerONReset signal is used in the design
-wire RESET = TRST; // If no PowerONReset signal is used in the design
-
-// TestLogicReset state
-always @ (posedge TCK or posedge RESET)
-begin
- if(RESET)
- TestLogicReset<=1;
- else
- begin
- if(TMS & (TestLogicReset | SelectIRScan))
- TestLogicReset<=1;
- else
- TestLogicReset<=0;
- end
-end
-
-// RunTestIdle state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- RunTestIdle<=0;
- else
- begin
- if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
- RunTestIdle<=1;
- else
- RunTestIdle<=0;
- end
-end
-
-// SelectDRScan state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- SelectDRScan<=0;
- else
- begin
- if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
- SelectDRScan<=1;
- else
- SelectDRScan<=0;
- end
-end
-
-// CaptureDR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- CaptureDR<=0;
- else
- begin
- if(~TMS & SelectDRScan)
- CaptureDR<=1;
- else
- CaptureDR<=0;
- end
-end
-
-// ShiftDR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- ShiftDR<=0;
- else
- begin
- if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
- ShiftDR<=1;
- else
- ShiftDR<=0;
- end
-end
-
-// Exit1DR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- Exit1DR<=0;
- else
- begin
- if(TMS & (CaptureDR | ShiftDR))
- Exit1DR<=1;
- else
- Exit1DR<=0;
- end
-end
-
-// PauseDR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- PauseDR<=0;
- else
- begin
- if(~TMS & (Exit1DR | PauseDR))
- PauseDR<=1;
- else
- PauseDR<=0;
- end
-end
-
-// Exit2DR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- Exit2DR<=0;
- else
- begin
- if(TMS & PauseDR)
- Exit2DR<=1;
- else
- Exit2DR<=0;
- end
-end
-
-// UpdateDR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- UpdateDR<=0;
- else
- begin
- if(TMS & (Exit1DR | Exit2DR))
- UpdateDR<=1;
- else
- UpdateDR<=0;
- end
-end
-
-// SelectIRScan state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- SelectIRScan<=0;
- else
- begin
- if(TMS & SelectDRScan)
- SelectIRScan<=1;
- else
- SelectIRScan<=0;
- end
-end
-
-// CaptureIR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- CaptureIR<=0;
- else
- begin
- if(~TMS & SelectIRScan)
- CaptureIR<=1;
- else
- CaptureIR<=0;
- end
-end
-
-// ShiftIR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- ShiftIR<=0;
- else
- begin
- if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
- ShiftIR<=1;
- else
- ShiftIR<=0;
- end
-end
-
-// Exit1IR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- Exit1IR<=0;
- else
- begin
- if(TMS & (CaptureIR | ShiftIR))
- Exit1IR<=1;
- else
- Exit1IR<=0;
- end
-end
-
-// PauseIR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- PauseIR<=0;
- else
- begin
- if(~TMS & (Exit1IR | PauseIR))
- PauseIR<=1;
- else
- PauseIR<=0;
- end
-end
-
-// Exit2IR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- Exit2IR<=0;
- else
- begin
- if(TMS & PauseIR)
- Exit2IR<=1;
- else
- Exit2IR<=0;
- end
-end
-
-// UpdateIR state
-always @ (posedge TCK or posedge TRST)
-begin
- if(TRST)
- UpdateIR<=0;
- else
- begin
- if(TMS & (Exit1IR | Exit2IR))
- UpdateIR<=1;
- else
- UpdateIR<=0;
- end
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* JTAG_SIR: JTAG Shift Instruction Register: Instruction shifted in, status out *
-* JTAG_IR: JTAG Instruction Register: Updated on UpdateIR or TestLogicReset *
-* *
-* Status is shifted out. *
-* *
-**********************************************************************************/
-wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
-
-reg [3:0]JTAG_SIR; // Register used for shifting in and out
-reg [3:0]JTAG_IR; // Instruction register
-reg TDOInstruction;
-
-always @ (posedge TCK)
-begin
- if(CaptureIR)
- begin
- JTAG_SIR[1:0] <= 2'b01; // This value is fixed for easier fault detection
- JTAG_SIR[3:2] <= Status[1:0]; // Current status of chip
- end
- else
- begin
- if(ShiftIR)
- begin
- JTAG_SIR[3:0] <= JTAG_SIR[3:0] >> 1;
- JTAG_SIR[3] <= TDI;
- end
- end
-end
-
-// Updating JTAG_IR (Instruction Register)
-always @ (posedge TCK or posedge TestLogicReset)
-begin
- if(TestLogicReset)
- JTAG_IR <= IDCODE;
- else
- begin
- if(UpdateIR)
- JTAG_IR <= JTAG_SIR;
- end
-end
-
-//TDO is changing on the falling edge of TCK
-always @ (negedge TCK)
-begin
- if(ShiftIR)
- TDOInstruction <= JTAG_SIR[0];
-end
-
-/**********************************************************************************
-* *
-* End: JTAG_SIR *
-* End: JTAG_IR *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* JTAG_SDR: JTAG Shift Data Register: Data shifted in and out *
-* JTAG_DR: JTAG Data Register: Updated on UpdateDR *
-* *
-* Data that is shifted out can be a chip ID or a requested data (register value,*
-* memory value, etc. *
-* *
-**********************************************************************************/
-wire [32:0] IDCodeValue = 33'b011000011110000111100001111000011; // ID value (constant 0x0c3c3c3c3). IDCODE is 32-bit long, so the MSB is not used
-wire [32:0] DataValue = 33'b101001100011100001111000111001101; // This should be data from the core. For now a constant value 0x14c70f1cd is used
-wire [32:0] RequestedData = (JTAG_IR==IDCODE)? IDCodeValue : DataValue; // This is to be expanded with number of user registers
-
-reg [32:0]JTAG_SDR; // Register used for shifting in and out
-reg [32:0]JTAG_DR; // Data register
-reg TDOData;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR)
- JTAG_SDR <= RequestedData; // DataResponse contains data requested in previous cycle
- else
- begin
- if(ShiftDR)
- begin
- JTAG_SDR <= JTAG_SDR >> 1;
- JTAG_SDR[32] <= TDI;
- end
- end
-end
-
-// Updating JTAG_DR (Data Register)
-always @ (posedge TCK)
-begin
- if(UpdateDR)
- JTAG_DR <= JTAG_SDR;
-end
-
-//TDO is changing on the falling edge of TCK
-always @ (negedge TCK)
-begin
- if(ShiftDR)
- TDOData <= JTAG_SDR[0];
-end
-
-/**********************************************************************************
-* *
-* End: JTAG_SDR *
-* End: JTAG_DR *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg BypassRegister;
-reg TDOBypassed;
-
-always @ (posedge TCK)
-begin
- if(ShiftDR)
- BypassRegister<=TDI;
-end
-
-always @ (negedge TCK)
-begin
- TDOBypassed<=BypassRegister;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Boundary Scan Logic *
-* *
-**********************************************************************************/
-wire [`BSLength-1:0]ExitFromBSCell;
-
-
-wire [3:0]ToOutputEnable;
-wire [1:0]BidirectionalBuffered;
-
-wire [5:0]FromCore = 6'h0; // This are signals that core send to output (or bidirectional) pins. We have no core, so they are all zero.
-wire [3:0]ControlPIN = 4'h0; // Core control signals. Since no core is used, they are fixed to zero.
-
-// buffers
-assign BidirectionalBuffered[1:0] = BidirectionalPin[1:0]; // Inputs of bidirectional signals should be buffered (as seen below)
-//IBUF buffer0 (.I(BidirectionalPin[0]), .O(BidirectionalBuffered[0]));
-//IBUF buffer1 (.I(BidirectionalPin[1]), .O(BidirectionalBuffered[1]));
-
-wire ExtTestEnabled = (JTAG_IR==EXTEST) | (JTAG_IR==SAMPLE_PRELOAD);
-
-
-// BOUNDARY SCAN REGISTER
-// closest to TDO
-InputCell BS0 ( .InputPin(InputPin[0]), .FromPreviousBSCell(ExitFromBSCell[12]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[`BSLength-1]));
-InputCell BS1 ( .InputPin(InputPin[1]), .FromPreviousBSCell(ExitFromBSCell[11]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[12]));
-
-OutputCell BS2 ( .FromCore(FromCore[0]), .FromPreviousBSCell(ExitFromBSCell[10]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[11]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[0]), .TristatedPin(Output3Pin[0]));
-ControlCell BS3 ( .OutputControl(ControlPIN[0]), .FromPreviousBSCell(ExitFromBSCell[9]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[10]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[0]));
-
-OutputCell BS4 ( .FromCore(FromCore[1]), .FromPreviousBSCell(ExitFromBSCell[8]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[9]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[1]), .TristatedPin(Output3Pin[1]));
-ControlCell BS5 ( .OutputControl(ControlPIN[1]), .FromPreviousBSCell(ExitFromBSCell[7]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[8]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[1]));
-
-InputCell BS6 ( .InputPin(BidirectionalBuffered[0]), .FromPreviousBSCell(ExitFromBSCell[6]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[7]));
-OutputCell BS7 ( .FromCore(FromCore[2]), .FromPreviousBSCell(ExitFromBSCell[5]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[6]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[2]), .TristatedPin(BidirectionalPin[0]));
-ControlCell BS8 ( .OutputControl(ControlPIN[2]), .FromPreviousBSCell(ExitFromBSCell[4]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[5]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[2]));
-
-InputCell BS9 ( .InputPin(BidirectionalBuffered[1]), .FromPreviousBSCell(ExitFromBSCell[3]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[4]));
-OutputCell BS10 ( .FromCore(FromCore[3]), .FromPreviousBSCell(ExitFromBSCell[2]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[3]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[3]), .TristatedPin(BidirectionalPin[1]));
-ControlCell BS11 ( .OutputControl(ControlPIN[3]), .FromPreviousBSCell(ExitFromBSCell[1]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[2]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[3]));
-
-OutputCell BS12 ( .FromCore(FromCore[4]), .FromPreviousBSCell(ExitFromBSCell[0]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[1]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc), .TristatedPin(Output2Pin[0]));
-OutputCell BS13 ( .FromCore(FromCore[5]), .FromPreviousBSCell(TDI), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[0]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc), .TristatedPin(Output2Pin[1]));
-// closest to TDI
-
-
-/**********************************************************************************
-* *
-* End: Boundary Scan Logic *
-* *
-**********************************************************************************/
-
-
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO and Tristate control *
-* *
-**********************************************************************************/
-wire TDOShifted;
-assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
-
-reg TDOMuxed;
-
-
-// This multiplexing can be expanded with number of user registers
-always @ (JTAG_IR or TDOShifted or ExitFromBSCell or TDOBypassed)
-begin
- case(JTAG_IR)
- IDCODE: // Reading ID code
- begin
- TDOMuxed<=TDOShifted;
- end
- SAMPLE_PRELOAD: // Sampling/Preloading
- begin
- TDOMuxed<=ExitFromBSCell[`BSLength-1];
- end
- EXTEST: // External test
- begin
- TDOMuxed<=ExitFromBSCell[`BSLength-1];
- end
- default: // BYPASS instruction
- begin
- TDOMuxed<=TDOBypassed;
- end
- endcase
-end
-
-
-
-// Tristate control for P_TDO pin
-assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR)? TDOMuxed : 1'bz;
-
-
-/**********************************************************************************
-* *
-* End: Multiplexing TDO and Tristate control *
-* *
-**********************************************************************************/
-
-
-
-
-
-
-// Test Signals (can be deleted)
-
-assign TestSignal[0] = CaptureDR;
-assign TestSignal[1] = RunTestIdle;
-assign TestSignal[2] = ShiftDR;
-assign TestSignal[3] = UpdateDR;
-
-assign TestSignal[4] = JTAG_IR[0];
-assign TestSignal[5] = JTAG_IR[1];
-
-
-
-endmodule // TAP
Index: tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v
===================================================================
--- tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v (revision 21)
+++ tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v (nonexistent)
@@ -1,66 +0,0 @@
-/**********************************************************************************
-* *
-* BiDirectional Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* ToCore: Value that is read-in from the pin and goes to core *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* BiDirPin: Bidirectional pin connected to this BS cell *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
-* control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output BiDirPin;
-output ToCore;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-//BUF Buffer (.I(BiDirPin), .O(ToCore));
-assign ToCore = BiDirPin;
-
-
-endmodule // TristateCell
\ No newline at end of file
Index: tags/rel_1/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_1/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/rel_1/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,649 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* jtag_dr: JTAG Data Register *
-* *
-**********************************************************************************/
-reg [`DR_LENGTH-1:0] jtag_dr; // Data register
-reg [`DR_LENGTH-1:0] latched_jtag_dr;
-reg data_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
- else
- if(capture_dr)
- jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
- else
- if(shift_dr)
- jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- data_tdo <= #1 jtag_dr[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_dr *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o <=#1 instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/rel_1/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_1/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/rel_1/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/rel_1/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Length of the Data register
-`define DR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/rel_1/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_1/doc/Boundary-Scan_Architecture.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_1/doc/Boundary-Scan_Architecture.pdf
===================================================================
--- tags/rel_1/doc/Boundary-Scan_Architecture.pdf (revision 21)
+++ tags/rel_1/doc/Boundary-Scan_Architecture.pdf (nonexistent)
tags/rel_1/doc/Boundary-Scan_Architecture.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/rel_1/doc/or1k_10.bsd
===================================================================
--- tags/rel_1/doc/or1k_10.bsd (revision 21)
+++ tags/rel_1/doc/or1k_10.bsd (nonexistent)
@@ -1,139 +0,0 @@
---////////////////////////////////////////////////////////////////////
---// ////
---// or1k_10.bsd ////
---// ////
---// This file is part of the IEEE 1149.1 Test Access Port (TAP) ////
---// IP core project ////
---// http://www.opencores.org/cores/jtag/ ////
---// ////
---// Author(s): ////
---// - Igor Mohor (igorM@opencores.org) ////
---// ////
---// ////
---////////////////////////////////////////////////////////////////////
---// ////
---// Copyright (C) 2000, 2001 Authors ////
---// ////
---// This source file may be used and distributed without ////
---// restriction provided that this copyright statement is not ////
---// removed from the file and that any derivative work contains ////
---// the original copyright notice and the associated disclaimer. ////
---// ////
---// This source file is free software; you can redistribute it ////
---// and/or modify it under the terms of the GNU Lesser General ////
---// Public License as published by the Free Software Foundation; ////
---// either version 2.1 of the License, or (at your option) any ////
---// later version. ////
---// ////
---// This source is distributed in the hope that it will be ////
---// useful, but WITHOUT ANY WARRANTY; without even the implied ////
---// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
---// PURPOSE. See the GNU Lesser General Public License for more ////
---// details. ////
---// ////
---// You should have received a copy of the GNU Lesser General ////
---// Public License along with this source; if not, download it ////
---// from http://www.opencores.org/lgpl.shtml ////
---// ////
---////////////////////////////////////////////////////////////////////
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2001/08/01 18:49:42 mohor
--- Reset signal changed. Bsdl file added to the project.
---
---
---
---
---
-
---
--- BSDL File created/edited by Igor Mohor (igorm@opencores.org)
---
---Package: ??
-entity or1k_10 is
-
-generic (PHYSICAL_PIN_MAP : string := "vq44" );
-
-port (
- MyInput0: in bit;
- MyInput1: in bit;
- MyOutput0: out bit;
- MyOutput1: out bit;
- MyBidirectional0: inout bit;
- MyBidirectional1: inout bit;
- TCK: in bit;
- TDI: in bit;
- TDO: out bit;
- TMS: in bit
- );
-
-use STD_1149_1_1994.all;
-
-attribute COMPONENT_CONFORMANCE of or1k_10 : entity is "STD_1149_1_1993";
-attribute PIN_MAP of or1k_10 : entity is PHYSICAL_PIN_MAP;
-
-constant vq44: PIN_MAP_STRING:=
- "TCK:1," &
- "TDI:2," &
- "TDO:3," &
- "TMS:4," &
- "MyInput0:5," &
- "MyInput1:6," &
- "MyOutput0:7," &
- "MyOutput1:8," &
- "MyBidirectional0:9," &
- "MyBidirectional1:10";
-
-attribute TAP_SCAN_IN of TDI : signal is true;
-attribute TAP_SCAN_OUT of TDO : signal is true;
-attribute TAP_SCAN_MODE of TMS : signal is true;
-attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+06, BOTH); --
-attribute INSTRUCTION_LENGTH of or1k_10 : entity is 4;
-
-attribute INSTRUCTION_OPCODE of or1k_10 : entity is --
- "EXTEST ( 0000)," &
- "SAMPLE ( 0001)," &
- "IDCODE ( 0010)," &
- "BYPASS ( 1111)";
-
-attribute INSTRUCTION_CAPTURE of or1k_10: entity is "1001";
-
-attribute IDCODE_REGISTER of or1k_10: entity is --
- "1100" & -- version
- "0011110000111100" & -- part number
- "00111100001" & -- manufacturer's id
- "1"; -- required by standard
-
---attribute USERCODE_REGISTER of or1k_10: entity is
--- "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-
-
--- attribute INSTRUCTION_DISABLE of or1k_10 : entity is "HIGHZ";
-
-attribute REGISTER_ACCESS of or1k_10 : entity is
- "BYPASS (BYPASS)," &
- "DEVICE_ID (IDCODE)," &
- "BOUNDARY (SAMPLE,EXTEST)";
-
-attribute BOUNDARY_LENGTH of or1k_10 : entity is 12;
---attribute BOUNDARY_LENGTH of or1k_10 : entity is 6;
-
-attribute BOUNDARY_REGISTER of or1k_10 : entity is
--- num cell port function safe [ccell disval rslt]
- "0 ( BC_1, MyInput0 ,input , X), " &
- "1 ( BC_1, MyInput1 ,input , X), " &
- "2 ( BC_1, MyOutput0 ,output3 , 0, 3, 0, Z), " &
- "3 ( BC_1, * ,controlr, 1), " &
- "4 ( BC_1, MyOutput1 ,output3 , 0, 5, 0, Z), " &
- "5 ( BC_1, * ,controlr, 1), " &
- "6 ( BC_1, MyBidirectional0 ,input , X), " &
- "7 ( BC_1, MyBidirectional0 ,output3 , 0, 8, 0, Z), " &
- "8 ( BC_1, * ,controlr, 1), " &
- "9 ( BC_1, MyBidirectional1 ,input , X), " &
- "10 ( BC_1, MyBidirectional1 ,output3 , 0, 11, 0, Z), " &
- "11 ( BC_1, * ,controlr, 1) " ;
-end or1k_10;
-
-end or1k_10;
Index: tags/rel_2/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/rel_2/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/rel_2/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Length of the Data register
-`define DR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/rel_2/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_2/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_2/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/rel_2/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,655 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* jtag_dr: JTAG Data Register *
-* *
-**********************************************************************************/
-reg [`DR_LENGTH-1:0] jtag_dr; // Data register
-reg [`DR_LENGTH-1:0] latched_jtag_dr;
-reg data_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
- else
- if(capture_dr)
- jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
- else
- if(shift_dr)
- jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- data_tdo <= #1 jtag_dr[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_dr *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o <=#1 instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/rel_2/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_2/doc/Boundary-Scan_Architecture.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_2/doc/Boundary-Scan_Architecture.pdf
===================================================================
--- tags/rel_2/doc/Boundary-Scan_Architecture.pdf (revision 21)
+++ tags/rel_2/doc/Boundary-Scan_Architecture.pdf (nonexistent)
tags/rel_2/doc/Boundary-Scan_Architecture.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/rel_2/doc/or1k_10.bsd
===================================================================
--- tags/rel_2/doc/or1k_10.bsd (revision 21)
+++ tags/rel_2/doc/or1k_10.bsd (nonexistent)
@@ -1,139 +0,0 @@
---////////////////////////////////////////////////////////////////////
---// ////
---// or1k_10.bsd ////
---// ////
---// This file is part of the IEEE 1149.1 Test Access Port (TAP) ////
---// IP core project ////
---// http://www.opencores.org/cores/jtag/ ////
---// ////
---// Author(s): ////
---// - Igor Mohor (igorM@opencores.org) ////
---// ////
---// ////
---////////////////////////////////////////////////////////////////////
---// ////
---// Copyright (C) 2000, 2001 Authors ////
---// ////
---// This source file may be used and distributed without ////
---// restriction provided that this copyright statement is not ////
---// removed from the file and that any derivative work contains ////
---// the original copyright notice and the associated disclaimer. ////
---// ////
---// This source file is free software; you can redistribute it ////
---// and/or modify it under the terms of the GNU Lesser General ////
---// Public License as published by the Free Software Foundation; ////
---// either version 2.1 of the License, or (at your option) any ////
---// later version. ////
---// ////
---// This source is distributed in the hope that it will be ////
---// useful, but WITHOUT ANY WARRANTY; without even the implied ////
---// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
---// PURPOSE. See the GNU Lesser General Public License for more ////
---// details. ////
---// ////
---// You should have received a copy of the GNU Lesser General ////
---// Public License along with this source; if not, download it ////
---// from http://www.opencores.org/lgpl.shtml ////
---// ////
---////////////////////////////////////////////////////////////////////
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2001/08/01 18:49:42 mohor
--- Reset signal changed. Bsdl file added to the project.
---
---
---
---
---
-
---
--- BSDL File created/edited by Igor Mohor (igorm@opencores.org)
---
---Package: ??
-entity or1k_10 is
-
-generic (PHYSICAL_PIN_MAP : string := "vq44" );
-
-port (
- MyInput0: in bit;
- MyInput1: in bit;
- MyOutput0: out bit;
- MyOutput1: out bit;
- MyBidirectional0: inout bit;
- MyBidirectional1: inout bit;
- TCK: in bit;
- TDI: in bit;
- TDO: out bit;
- TMS: in bit
- );
-
-use STD_1149_1_1994.all;
-
-attribute COMPONENT_CONFORMANCE of or1k_10 : entity is "STD_1149_1_1993";
-attribute PIN_MAP of or1k_10 : entity is PHYSICAL_PIN_MAP;
-
-constant vq44: PIN_MAP_STRING:=
- "TCK:1," &
- "TDI:2," &
- "TDO:3," &
- "TMS:4," &
- "MyInput0:5," &
- "MyInput1:6," &
- "MyOutput0:7," &
- "MyOutput1:8," &
- "MyBidirectional0:9," &
- "MyBidirectional1:10";
-
-attribute TAP_SCAN_IN of TDI : signal is true;
-attribute TAP_SCAN_OUT of TDO : signal is true;
-attribute TAP_SCAN_MODE of TMS : signal is true;
-attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+06, BOTH); --
-attribute INSTRUCTION_LENGTH of or1k_10 : entity is 4;
-
-attribute INSTRUCTION_OPCODE of or1k_10 : entity is --
- "EXTEST ( 0000)," &
- "SAMPLE ( 0001)," &
- "IDCODE ( 0010)," &
- "BYPASS ( 1111)";
-
-attribute INSTRUCTION_CAPTURE of or1k_10: entity is "1001";
-
-attribute IDCODE_REGISTER of or1k_10: entity is --
- "1100" & -- version
- "0011110000111100" & -- part number
- "00111100001" & -- manufacturer's id
- "1"; -- required by standard
-
---attribute USERCODE_REGISTER of or1k_10: entity is
--- "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-
-
--- attribute INSTRUCTION_DISABLE of or1k_10 : entity is "HIGHZ";
-
-attribute REGISTER_ACCESS of or1k_10 : entity is
- "BYPASS (BYPASS)," &
- "DEVICE_ID (IDCODE)," &
- "BOUNDARY (SAMPLE,EXTEST)";
-
-attribute BOUNDARY_LENGTH of or1k_10 : entity is 12;
---attribute BOUNDARY_LENGTH of or1k_10 : entity is 6;
-
-attribute BOUNDARY_REGISTER of or1k_10 : entity is
--- num cell port function safe [ccell disval rslt]
- "0 ( BC_1, MyInput0 ,input , X), " &
- "1 ( BC_1, MyInput1 ,input , X), " &
- "2 ( BC_1, MyOutput0 ,output3 , 0, 3, 0, Z), " &
- "3 ( BC_1, * ,controlr, 1), " &
- "4 ( BC_1, MyOutput1 ,output3 , 0, 5, 0, Z), " &
- "5 ( BC_1, * ,controlr, 1), " &
- "6 ( BC_1, MyBidirectional0 ,input , X), " &
- "7 ( BC_1, MyBidirectional0 ,output3 , 0, 8, 0, Z), " &
- "8 ( BC_1, * ,controlr, 1), " &
- "9 ( BC_1, MyBidirectional1 ,input , X), " &
- "10 ( BC_1, MyBidirectional1 ,output3 , 0, 11, 0, Z), " &
- "11 ( BC_1, * ,controlr, 1) " ;
-end or1k_10;
-
-end or1k_10;
Index: tags/asyst_2/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/asyst_2/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/asyst_2/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/asyst_2/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/asyst_2/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/asyst_2/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/asyst_2/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,630 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2004/01/18 09:27:39 simons
-// Blocking non blocking assignmenst fixed.
-//
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/asyst_2/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_3/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/rel_3/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/rel_3/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Length of the Data register
-`define DR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/rel_3/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_3/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_3/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/rel_3/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,658 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* jtag_dr: JTAG Data Register *
-* *
-**********************************************************************************/
-reg [`DR_LENGTH-1:0] jtag_dr; // Data register
-reg [`DR_LENGTH-1:0] latched_jtag_dr;
-reg data_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
- else
- if(capture_dr)
- jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
- else
- if(shift_dr)
- jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- data_tdo <= #1 jtag_dr[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_dr *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/rel_3/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/asyst_3/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/asyst_3/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/asyst_3/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/asyst_3/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/asyst_3/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/asyst_3/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/asyst_3/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,630 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2004/01/18 09:27:39 simons
-// Blocking non blocking assignmenst fixed.
-//
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/asyst_3/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_4/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/rel_4/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/rel_4/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/rel_4/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_4/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_4/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/rel_4/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,630 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2004/01/18 09:27:39 simons
-// Blocking non blocking assignmenst fixed.
-//
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/rel_4/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_5/tap/rtl/verilog/tap_defines.v
===================================================================
--- tags/rel_5/tap/rtl/verilog/tap_defines.v (revision 21)
+++ tags/rel_5/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,66 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h14951185
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
tags/rel_5/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_5/tap/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_5/tap/rtl/verilog/tap_top.v (revision 21)
+++ tags/rel_5/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,630 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2004/01/18 09:27:39 simons
-// Blocking non blocking assignmenst fixed.
-//
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
tags/rel_5/tap/rtl/verilog/tap_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_5/tap/doc/jtag.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_5/tap/doc/jtag.pdf
===================================================================
--- tags/rel_5/tap/doc/jtag.pdf (revision 21)
+++ tags/rel_5/tap/doc/jtag.pdf (nonexistent)
tags/rel_5/tap/doc/jtag.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/rel_5/tap/doc/src/jtag.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_5/tap/doc/src/jtag.doc
===================================================================
--- tags/rel_5/tap/doc/src/jtag.doc (revision 21)
+++ tags/rel_5/tap/doc/src/jtag.doc (nonexistent)
tags/rel_5/tap/doc/src/jtag.doc
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/rel_5/cells/rtl/verilog/InputCell.v
===================================================================
--- tags/rel_5/cells/rtl/verilog/InputCell.v (revision 21)
+++ tags/rel_5/cells/rtl/verilog/InputCell.v (nonexistent)
@@ -1,62 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Input Cell: *
-* *
-* InputPin: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR: TAP states *
-* TCK: Test Clock *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
-input InputPin;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-
-endmodule // InputCell
\ No newline at end of file
Index: tags/rel_5/cells/rtl/verilog/OutputCell.v
===================================================================
--- tags/rel_5/cells/rtl/verilog/OutputCell.v (revision 21)
+++ tags/rel_5/cells/rtl/verilog/OutputCell.v (nonexistent)
@@ -1,83 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Output Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* TristatedPin: Signal from core is connected to this output pin via BS *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to TristatedPin comes from core or BS chain. *
-* Tristate control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output TristatedPin;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-endmodule // OutputCell
\ No newline at end of file
Index: tags/rel_5/cells/rtl/verilog/ControlCell.v
===================================================================
--- tags/rel_5/cells/rtl/verilog/ControlCell.v (revision 21)
+++ tags/rel_5/cells/rtl/verilog/ControlCell.v (nonexistent)
@@ -1,77 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* I/O Control Cell: *
-* *
-* OutputControl: Output Control from on-chip logic *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* *
-* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
-* shifting data for the exact number of time *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
-input OutputControl;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-output ToOutputEnable;
-
-reg ToNextBSCell;
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-assign ToOutputEnable = extest? ShiftedControl : OutputControl;
-
-endmodule // ControlCell
\ No newline at end of file
Index: tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v
===================================================================
--- tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v (revision 21)
+++ tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v (nonexistent)
@@ -1,66 +0,0 @@
-/**********************************************************************************
-* *
-* BiDirectional Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* ToCore: Value that is read-in from the pin and goes to core *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* BiDirPin: Bidirectional pin connected to this BS cell *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
-* control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output BiDirPin;
-output ToCore;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-//BUF Buffer (.I(BiDirPin), .O(ToCore));
-assign ToCore = BiDirPin;
-
-
-endmodule // TristateCell
\ No newline at end of file
Index: trunk/cells/rtl/verilog/InputCell.v
===================================================================
--- trunk/cells/rtl/verilog/InputCell.v (revision 21)
+++ trunk/cells/rtl/verilog/InputCell.v (nonexistent)
@@ -1,62 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Input Cell: *
-* *
-* InputPin: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR: TAP states *
-* TCK: Test Clock *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
-input InputPin;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-
-endmodule // InputCell
\ No newline at end of file
Index: trunk/cells/rtl/verilog/OutputCell.v
===================================================================
--- trunk/cells/rtl/verilog/OutputCell.v (revision 21)
+++ trunk/cells/rtl/verilog/OutputCell.v (nonexistent)
@@ -1,83 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* Output Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* TristatedPin: Signal from core is connected to this output pin via BS *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to TristatedPin comes from core or BS chain. *
-* Tristate control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output TristatedPin;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-endmodule // OutputCell
\ No newline at end of file
Index: trunk/cells/rtl/verilog/ControlCell.v
===================================================================
--- trunk/cells/rtl/verilog/ControlCell.v (revision 21)
+++ trunk/cells/rtl/verilog/ControlCell.v (nonexistent)
@@ -1,77 +0,0 @@
-/**********************************************************************************
-* *
-* This verilog file is a part of the Boundary Scan Implementation and comes in *
-* a pack with several other files. It is fully IEEE 1149.1 compliant. *
-* For details check www.opencores.org (pdf files, bsdl file, etc.) *
-* *
-* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
-* *
-* This program is free software; you can redistribute it and/or modify *
-* it under the terms of the GNU General Public License as published by *
-* the Free Software Foundation; either version 2 of the License, or *
-* (at your option) any later version. *
-* *
-* See the file COPYING for the full details of the license. *
-* *
-* OPENCORES.ORG is looking for new open source IP cores and developers that *
-* would like to help in our mission. *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* I/O Control Cell: *
-* *
-* OutputControl: Output Control from on-chip logic *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* *
-* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
-* shifting data for the exact number of time *
-* *
-**********************************************************************************/
-
-// This is not a top module
-module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
-input OutputControl;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-
-reg Latch;
-
-output ToNextBSCell;
-output ToOutputEnable;
-
-reg ToNextBSCell;
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-assign ToOutputEnable = extest? ShiftedControl : OutputControl;
-
-endmodule // ControlCell
\ No newline at end of file
Index: trunk/cells/rtl/verilog/BiDirectionalCell.v
===================================================================
--- trunk/cells/rtl/verilog/BiDirectionalCell.v (revision 21)
+++ trunk/cells/rtl/verilog/BiDirectionalCell.v (nonexistent)
@@ -1,66 +0,0 @@
-/**********************************************************************************
-* *
-* BiDirectional Cell: *
-* *
-* FromCore: Value that comes from on-chip logic and goes to pin *
-* ToCore: Value that is read-in from the pin and goes to core *
-* FromPreviousBSCell: Value from previous boundary scan cell *
-* ToNextBSCell: Value for next boundary scan cell *
-* CaptureDR, ShiftDR, UpdateDR: TAP states *
-* extest: Instruction Register Command *
-* TCK: Test Clock *
-* BiDirPin: Bidirectional pin connected to this BS cell *
-* FromOutputEnable: This pin comes from core or ControlCell *
-* *
-* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
-* control is generated in core or BS chain (ControlCell). *
-* *
-**********************************************************************************/
-
-module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
-input FromCore;
-input FromPreviousBSCell;
-input CaptureDR;
-input ShiftDR;
-input UpdateDR;
-input extest;
-input TCK;
-input FromOutputEnable;
-
-reg Latch;
-
-output ToNextBSCell;
-reg ToNextBSCell;
-
-output BiDirPin;
-output ToCore;
-
-reg ShiftedControl;
-
-wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
-
-always @ (posedge TCK)
-begin
- if(CaptureDR | ShiftDR)
- Latch<=SelectedInput;
-end
-
-always @ (negedge TCK)
-begin
- ToNextBSCell<=Latch;
-end
-
-always @ (negedge TCK)
-begin
- if(UpdateDR)
- ShiftedControl<=ToNextBSCell;
-end
-
-wire MuxedSignal = extest? ShiftedControl : FromCore;
-assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
-
-//BUF Buffer (.I(BiDirPin), .O(ToCore));
-assign ToCore = BiDirPin;
-
-
-endmodule // TristateCell
\ No newline at end of file
Index: trunk/tap/rtl/verilog/tap_defines.v
===================================================================
--- trunk/tap/rtl/verilog/tap_defines.v (revision 21)
+++ trunk/tap/rtl/verilog/tap_defines.v (nonexistent)
@@ -1,73 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_defines.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.2 2004/01/27 10:00:33 mohor
-// Unused registers removed.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-//
-//
-
-
-// Define IDCODE Value
-`define IDCODE_VALUE 32'h149511c3
-// 0001 version
-// 0100100101010001 part number (IQ)
-// 00011100001 manufacturer id (flextronics)
-// 1 required by standard
-
-// Length of the Instruction register
-`define IR_LENGTH 4
-
-// Supported Instructions
-`define EXTEST 4'b0000
-`define SAMPLE_PRELOAD 4'b0001
-`define IDCODE 4'b0010
-`define DEBUG 4'b1000
-`define MBIST 4'b1001
-`define BYPASS 4'b1111
-
trunk/tap/rtl/verilog/tap_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tap/rtl/verilog/tap_top.v
===================================================================
--- trunk/tap/rtl/verilog/tap_top.v (revision 21)
+++ trunk/tap/rtl/verilog/tap_top.v (nonexistent)
@@ -1,630 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tap_top.v ////
-//// ////
-//// ////
-//// This file is part of the JTAG Test Access Port (TAP) ////
-//// http://www.opencores.org/projects/jtag/ ////
-//// ////
-//// Author(s): ////
-//// Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// ////
-//// All additional information is avaliable in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 - 2003 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2004/01/18 09:27:39 simons
-// Blocking non blocking assignmenst fixed.
-//
-// Revision 1.4 2004/01/17 17:37:44 mohor
-// capture_dr_o added to ports.
-//
-// Revision 1.3 2004/01/14 13:50:56 mohor
-// 5 consecutive TMS=1 causes reset of TAP.
-//
-// Revision 1.2 2004/01/08 10:29:44 mohor
-// Control signals for tdo_pad_o mux are changed to negedge.
-//
-// Revision 1.1 2003/12/23 14:52:14 mohor
-// Directory structure changed. New version of TAP.
-//
-// Revision 1.10 2003/10/23 18:08:01 mohor
-// MBIST chain connection fixed.
-//
-// Revision 1.9 2003/10/23 16:17:02 mohor
-// CRC logic changed.
-//
-// Revision 1.8 2003/10/21 09:48:31 simons
-// Mbist support added.
-//
-// Revision 1.7 2002/11/06 14:30:10 mohor
-// Trst active high. Inverted on higher layer.
-//
-// Revision 1.6 2002/04/22 12:55:56 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
-//
-// Revision 1.5 2002/03/26 14:23:38 mohor
-// Signal tdo_padoe_o changed back to tdo_padoen_o.
-//
-// Revision 1.4 2002/03/25 13:16:15 mohor
-// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
-// not named correctly.
-//
-// Revision 1.3 2002/03/12 14:30:05 mohor
-// Few outputs for boundary scan chain added.
-//
-// Revision 1.2 2002/03/12 10:31:53 mohor
-// tap_top and dbg_top modules are put into two separate modules. tap_top
-// contains only tap state machine and related logic. dbg_top contains all
-// logic necessery for debugging.
-//
-// Revision 1.1 2002/03/08 15:28:16 mohor
-// Structure changed. Hooks for jtag chain added.
-//
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "tap_defines.v"
-
-// Top module
-module tap_top(
- // JTAG pads
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
-
- // TAP states
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
-
- // Select signals for boundary scan or mbist
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
-
- // TDO signal that is connected to TDI of sub-modules.
- tdo_o,
-
- // TDI signals from sub-modules
- debug_tdi_i, // from debug module
- bs_chain_tdi_i, // from Boundary Scan Chain
- mbist_tdi_i // from Mbist Chain
- );
-
-
-// JTAG pins
-input tms_pad_i; // JTAG test mode select pad
-input tck_pad_i; // JTAG test clock pad
-input trst_pad_i; // JTAG test reset pad
-input tdi_pad_i; // JTAG test data input pad
-output tdo_pad_o; // JTAG test data output pad
-output tdo_padoe_o; // Output enable for JTAG test data output pad
-
-// TAP states
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-
-// Select signals for boundary scan or mbist
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-
-// TDO signal that is connected to TDI of sub-modules.
-output tdo_o;
-
-// TDI signals from sub-modules
-input debug_tdi_i; // from debug module
-input bs_chain_tdi_i; // from Boundary Scan Chain
-input mbist_tdi_i; // from Mbist Chain
-
-// Registers
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-
-
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-
-
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
-
-
-/**********************************************************************************
-* *
-* TAP State Machine: Fully JTAG compliant *
-* *
-**********************************************************************************/
-
-// test_logic_reset state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-
-// run_test_idle state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-
-// select_dr_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-
-// capture_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-
-// shift_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-
-// exit1_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-
-// pause_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-
-// exit2_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-
-// update_dr state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-
-// select_ir_scan state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-
-// capture_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-
-// shift_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-
-// exit1_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-
-// pause_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-
-// exit2_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-
-// update_ir state
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-
-/**********************************************************************************
-* *
-* End: TAP State Machine *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* jtag_ir: JTAG Instruction Register *
-* *
-**********************************************************************************/
-reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
-reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
- else if(shift_ir)
- jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
-end
-
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-/**********************************************************************************
-* *
-* End: jtag_ir *
-* *
-**********************************************************************************/
-
-
-
-/**********************************************************************************
-* *
-* idcode logic *
-* *
-**********************************************************************************/
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 `IDCODE_VALUE;
-end
-
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-/**********************************************************************************
-* *
-* End: idcode logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Bypass logic *
-* *
-**********************************************************************************/
-reg bypassed_tdo;
-reg bypass_reg;
-
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-/**********************************************************************************
-* *
-* End: Bypass logic *
-* *
-**********************************************************************************/
-
-
-/**********************************************************************************
-* *
-* Activating Instructions *
-* *
-**********************************************************************************/
-// Updating jtag_ir (Instruction Register)
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if (tms_reset)
- latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-
-/**********************************************************************************
-* *
-* End: Activating Instructions *
-* *
-**********************************************************************************/
-
-
-// Updating jtag_ir (Instruction Register)
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
-
- case(latched_jtag_ir) /* synthesis parallel_case */
- `EXTEST: extest_select = 1'b1; // External test
- `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
- `IDCODE: idcode_select = 1'b1; // ID Code
- `MBIST: mbist_select = 1'b1; // Mbist test
- `DEBUG: debug_select = 1'b1; // Debug
- `BYPASS: bypass_select = 1'b1; // BYPASS
- default: bypass_select = 1'b1; // BYPASS
- endcase
-end
-
-
-
-/**********************************************************************************
-* *
-* Multiplexing TDO data *
-* *
-**********************************************************************************/
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg) // synthesis parallel_case
- `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
- `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
- `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
- `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
- `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
- default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
- endcase
- end
-end
-
-
-// Tristate control for tdo_pad_o pin
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-/**********************************************************************************
-* *
-* End: Multiplexing TDO data *
-* *
-**********************************************************************************/
-
-
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-
-
-endmodule
trunk/tap/rtl/verilog/tap_top.v
Property changes :
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## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tap/doc/src/jtag.doc
===================================================================
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Index: trunk/tap/doc/src/jtag.doc
===================================================================
--- trunk/tap/doc/src/jtag.doc (revision 21)
+++ trunk/tap/doc/src/jtag.doc (nonexistent)
trunk/tap/doc/src/jtag.doc
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## -1 +0,0 ##
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Index: trunk/tap/doc/jtag.pdf
===================================================================
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Index: trunk/tap/doc/jtag.pdf
===================================================================
--- trunk/tap/doc/jtag.pdf (revision 21)
+++ trunk/tap/doc/jtag.pdf (nonexistent)
trunk/tap/doc/jtag.pdf
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## -1 +0,0 ##
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\ No newline at end of property
Index: jtag/trunk/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/trunk/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/trunk/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2004/01/27 10:00:33 mohor
+// Unused registers removed.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h149511c3
+// 0001 version
+// 0100100101010001 part number (IQ)
+// 00011100001 manufacturer id (flextronics)
+// 1 required by standard
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/trunk/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/trunk/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/trunk/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/trunk/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,630 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/trunk/tap/rtl/verilog/tap_top.v
Property changes :
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+*
\ No newline at end of property
Index: jtag/trunk/tap/doc/src/jtag.doc
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Index: jtag/trunk/tap/doc/src/jtag.doc
===================================================================
--- jtag/trunk/tap/doc/src/jtag.doc (nonexistent)
+++ jtag/trunk/tap/doc/src/jtag.doc (revision 22)
jtag/trunk/tap/doc/src/jtag.doc
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Index: jtag/trunk/tap/doc/jtag.pdf
===================================================================
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Index: jtag/trunk/tap/doc/jtag.pdf
===================================================================
--- jtag/trunk/tap/doc/jtag.pdf (nonexistent)
+++ jtag/trunk/tap/doc/jtag.pdf (revision 22)
jtag/trunk/tap/doc/jtag.pdf
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+application/octet-stream
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Index: jtag/trunk/cells/rtl/verilog/InputCell.v
===================================================================
--- jtag/trunk/cells/rtl/verilog/InputCell.v (nonexistent)
+++ jtag/trunk/cells/rtl/verilog/InputCell.v (revision 22)
@@ -0,0 +1,62 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Input Cell: *
+* *
+* InputPin: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR: TAP states *
+* TCK: Test Clock *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
+input InputPin;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+
+endmodule // InputCell
\ No newline at end of file
Index: jtag/trunk/cells/rtl/verilog/ControlCell.v
===================================================================
--- jtag/trunk/cells/rtl/verilog/ControlCell.v (nonexistent)
+++ jtag/trunk/cells/rtl/verilog/ControlCell.v (revision 22)
@@ -0,0 +1,77 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* I/O Control Cell: *
+* *
+* OutputControl: Output Control from on-chip logic *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* *
+* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
+* shifting data for the exact number of time *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
+input OutputControl;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+output ToOutputEnable;
+
+reg ToNextBSCell;
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+assign ToOutputEnable = extest? ShiftedControl : OutputControl;
+
+endmodule // ControlCell
\ No newline at end of file
Index: jtag/trunk/cells/rtl/verilog/OutputCell.v
===================================================================
--- jtag/trunk/cells/rtl/verilog/OutputCell.v (nonexistent)
+++ jtag/trunk/cells/rtl/verilog/OutputCell.v (revision 22)
@@ -0,0 +1,83 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Output Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* TristatedPin: Signal from core is connected to this output pin via BS *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to TristatedPin comes from core or BS chain. *
+* Tristate control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output TristatedPin;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+endmodule // OutputCell
\ No newline at end of file
Index: jtag/trunk/cells/rtl/verilog/BiDirectionalCell.v
===================================================================
--- jtag/trunk/cells/rtl/verilog/BiDirectionalCell.v (nonexistent)
+++ jtag/trunk/cells/rtl/verilog/BiDirectionalCell.v (revision 22)
@@ -0,0 +1,66 @@
+/**********************************************************************************
+* *
+* BiDirectional Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* ToCore: Value that is read-in from the pin and goes to core *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* BiDirPin: Bidirectional pin connected to this BS cell *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
+* control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output BiDirPin;
+output ToCore;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+//BUF Buffer (.I(BiDirPin), .O(ToCore));
+assign ToCore = BiDirPin;
+
+
+endmodule // TristateCell
\ No newline at end of file
Index: jtag/trunk
===================================================================
--- jtag/trunk (nonexistent)
+++ jtag/trunk (revision 22)
jtag/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: jtag/web_uploads
===================================================================
--- jtag/web_uploads (nonexistent)
+++ jtag/web_uploads (revision 22)
jtag/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: jtag/branches
===================================================================
--- jtag/branches (nonexistent)
+++ jtag/branches (revision 22)
jtag/branches
Property changes :
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## -0,0 +0,0 ##
Index: jtag/tags/rel_5/tap/doc/src/jtag.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: jtag/tags/rel_5/tap/doc/src/jtag.doc
===================================================================
--- jtag/tags/rel_5/tap/doc/src/jtag.doc (nonexistent)
+++ jtag/tags/rel_5/tap/doc/src/jtag.doc (revision 22)
jtag/tags/rel_5/tap/doc/src/jtag.doc
Property changes :
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## -0,0 +1 ##
+application/octet-stream
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Index: jtag/tags/rel_5/tap/doc/jtag.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: jtag/tags/rel_5/tap/doc/jtag.pdf
===================================================================
--- jtag/tags/rel_5/tap/doc/jtag.pdf (nonexistent)
+++ jtag/tags/rel_5/tap/doc/jtag.pdf (revision 22)
jtag/tags/rel_5/tap/doc/jtag.pdf
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+application/octet-stream
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Index: jtag/tags/rel_5/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/rel_5/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/rel_5/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/rel_5/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_5/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/rel_5/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/rel_5/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,630 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/rel_5/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_5/cells/rtl/verilog/InputCell.v
===================================================================
--- jtag/tags/rel_5/cells/rtl/verilog/InputCell.v (nonexistent)
+++ jtag/tags/rel_5/cells/rtl/verilog/InputCell.v (revision 22)
@@ -0,0 +1,62 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Input Cell: *
+* *
+* InputPin: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR: TAP states *
+* TCK: Test Clock *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
+input InputPin;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+
+endmodule // InputCell
\ No newline at end of file
Index: jtag/tags/rel_5/cells/rtl/verilog/ControlCell.v
===================================================================
--- jtag/tags/rel_5/cells/rtl/verilog/ControlCell.v (nonexistent)
+++ jtag/tags/rel_5/cells/rtl/verilog/ControlCell.v (revision 22)
@@ -0,0 +1,77 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* I/O Control Cell: *
+* *
+* OutputControl: Output Control from on-chip logic *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* *
+* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
+* shifting data for the exact number of time *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
+input OutputControl;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+output ToOutputEnable;
+
+reg ToNextBSCell;
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+assign ToOutputEnable = extest? ShiftedControl : OutputControl;
+
+endmodule // ControlCell
\ No newline at end of file
Index: jtag/tags/rel_5/cells/rtl/verilog/OutputCell.v
===================================================================
--- jtag/tags/rel_5/cells/rtl/verilog/OutputCell.v (nonexistent)
+++ jtag/tags/rel_5/cells/rtl/verilog/OutputCell.v (revision 22)
@@ -0,0 +1,83 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Output Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* TristatedPin: Signal from core is connected to this output pin via BS *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to TristatedPin comes from core or BS chain. *
+* Tristate control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output TristatedPin;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+endmodule // OutputCell
\ No newline at end of file
Index: jtag/tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v
===================================================================
--- jtag/tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v (nonexistent)
+++ jtag/tags/rel_5/cells/rtl/verilog/BiDirectionalCell.v (revision 22)
@@ -0,0 +1,66 @@
+/**********************************************************************************
+* *
+* BiDirectional Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* ToCore: Value that is read-in from the pin and goes to core *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* BiDirPin: Bidirectional pin connected to this BS cell *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
+* control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output BiDirPin;
+output ToCore;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+//BUF Buffer (.I(BiDirPin), .O(ToCore));
+assign ToCore = BiDirPin;
+
+
+endmodule // TristateCell
\ No newline at end of file
Index: jtag/tags/rel_4/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/rel_4/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/rel_4/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/rel_4/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_4/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/rel_4/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/rel_4/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,630 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/rel_4/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/asyst_3/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/asyst_3/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/asyst_3/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/asyst_3/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/asyst_3/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/asyst_3/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/asyst_3/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,630 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/asyst_3/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/asyst_2/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/asyst_2/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/asyst_2/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/asyst_2/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/asyst_2/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/asyst_2/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/asyst_2/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,630 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/01/18 09:27:39 simons
+// Blocking non blocking assignmenst fixed.
+//
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/asyst_2/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_3/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/rel_3/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/rel_3/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,658 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.4 2004/01/17 17:37:44 mohor
+// capture_dr_o added to ports.
+//
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* jtag_dr: JTAG Data Register *
+* *
+**********************************************************************************/
+reg [`DR_LENGTH-1:0] jtag_dr; // Data register
+reg [`DR_LENGTH-1:0] latched_jtag_dr;
+reg data_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
+ else
+ if(capture_dr)
+ jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
+ else
+ if(shift_dr)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ data_tdo <= #1 jtag_dr[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_dr *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o = instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/rel_3/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_3/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/rel_3/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/rel_3/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Length of the Data register
+`define DR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/rel_3/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_2/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/rel_2/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/rel_2/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,655 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2004/01/14 13:50:56 mohor
+// 5 consecutive TMS=1 causes reset of TAP.
+//
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+ capture_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+output capture_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+assign capture_dr_o = capture_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* jtag_dr: JTAG Data Register *
+* *
+**********************************************************************************/
+reg [`DR_LENGTH-1:0] jtag_dr; // Data register
+reg [`DR_LENGTH-1:0] latched_jtag_dr;
+reg data_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
+ else
+ if(capture_dr)
+ jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
+ else
+ if(shift_dr)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ data_tdo <= #1 jtag_dr[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_dr *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o <=#1 instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/rel_2/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_2/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/rel_2/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/rel_2/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Length of the Data register
+`define DR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/rel_2/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_2/doc/Boundary-Scan_Architecture.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: jtag/tags/rel_2/doc/Boundary-Scan_Architecture.pdf
===================================================================
--- jtag/tags/rel_2/doc/Boundary-Scan_Architecture.pdf (nonexistent)
+++ jtag/tags/rel_2/doc/Boundary-Scan_Architecture.pdf (revision 22)
jtag/tags/rel_2/doc/Boundary-Scan_Architecture.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: jtag/tags/rel_2/doc/or1k_10.bsd
===================================================================
--- jtag/tags/rel_2/doc/or1k_10.bsd (nonexistent)
+++ jtag/tags/rel_2/doc/or1k_10.bsd (revision 22)
@@ -0,0 +1,139 @@
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// or1k_10.bsd ////
+--// ////
+--// This file is part of the IEEE 1149.1 Test Access Port (TAP) ////
+--// IP core project ////
+--// http://www.opencores.org/cores/jtag/ ////
+--// ////
+--// Author(s): ////
+--// - Igor Mohor (igorM@opencores.org) ////
+--// ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// Copyright (C) 2000, 2001 Authors ////
+--// ////
+--// This source file may be used and distributed without ////
+--// restriction provided that this copyright statement is not ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer. ////
+--// ////
+--// This source file is free software; you can redistribute it ////
+--// and/or modify it under the terms of the GNU Lesser General ////
+--// Public License as published by the Free Software Foundation; ////
+--// either version 2.1 of the License, or (at your option) any ////
+--// later version. ////
+--// ////
+--// This source is distributed in the hope that it will be ////
+--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--// PURPOSE. See the GNU Lesser General Public License for more ////
+--// details. ////
+--// ////
+--// You should have received a copy of the GNU Lesser General ////
+--// Public License along with this source; if not, download it ////
+--// from http://www.opencores.org/lgpl.shtml ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2001/08/01 18:49:42 mohor
+-- Reset signal changed. Bsdl file added to the project.
+--
+--
+--
+--
+--
+
+--
+-- BSDL File created/edited by Igor Mohor (igorm@opencores.org)
+--
+--Package: ??
+entity or1k_10 is
+
+generic (PHYSICAL_PIN_MAP : string := "vq44" );
+
+port (
+ MyInput0: in bit;
+ MyInput1: in bit;
+ MyOutput0: out bit;
+ MyOutput1: out bit;
+ MyBidirectional0: inout bit;
+ MyBidirectional1: inout bit;
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit
+ );
+
+use STD_1149_1_1994.all;
+
+attribute COMPONENT_CONFORMANCE of or1k_10 : entity is "STD_1149_1_1993";
+attribute PIN_MAP of or1k_10 : entity is PHYSICAL_PIN_MAP;
+
+constant vq44: PIN_MAP_STRING:=
+ "TCK:1," &
+ "TDI:2," &
+ "TDO:3," &
+ "TMS:4," &
+ "MyInput0:5," &
+ "MyInput1:6," &
+ "MyOutput0:7," &
+ "MyOutput1:8," &
+ "MyBidirectional0:9," &
+ "MyBidirectional1:10";
+
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_MODE of TMS : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+06, BOTH); --
+attribute INSTRUCTION_LENGTH of or1k_10 : entity is 4;
+
+attribute INSTRUCTION_OPCODE of or1k_10 : entity is --
+ "EXTEST ( 0000)," &
+ "SAMPLE ( 0001)," &
+ "IDCODE ( 0010)," &
+ "BYPASS ( 1111)";
+
+attribute INSTRUCTION_CAPTURE of or1k_10: entity is "1001";
+
+attribute IDCODE_REGISTER of or1k_10: entity is --
+ "1100" & -- version
+ "0011110000111100" & -- part number
+ "00111100001" & -- manufacturer's id
+ "1"; -- required by standard
+
+--attribute USERCODE_REGISTER of or1k_10: entity is
+-- "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+
+-- attribute INSTRUCTION_DISABLE of or1k_10 : entity is "HIGHZ";
+
+attribute REGISTER_ACCESS of or1k_10 : entity is
+ "BYPASS (BYPASS)," &
+ "DEVICE_ID (IDCODE)," &
+ "BOUNDARY (SAMPLE,EXTEST)";
+
+attribute BOUNDARY_LENGTH of or1k_10 : entity is 12;
+--attribute BOUNDARY_LENGTH of or1k_10 : entity is 6;
+
+attribute BOUNDARY_REGISTER of or1k_10 : entity is
+-- num cell port function safe [ccell disval rslt]
+ "0 ( BC_1, MyInput0 ,input , X), " &
+ "1 ( BC_1, MyInput1 ,input , X), " &
+ "2 ( BC_1, MyOutput0 ,output3 , 0, 3, 0, Z), " &
+ "3 ( BC_1, * ,controlr, 1), " &
+ "4 ( BC_1, MyOutput1 ,output3 , 0, 5, 0, Z), " &
+ "5 ( BC_1, * ,controlr, 1), " &
+ "6 ( BC_1, MyBidirectional0 ,input , X), " &
+ "7 ( BC_1, MyBidirectional0 ,output3 , 0, 8, 0, Z), " &
+ "8 ( BC_1, * ,controlr, 1), " &
+ "9 ( BC_1, MyBidirectional1 ,input , X), " &
+ "10 ( BC_1, MyBidirectional1 ,output3 , 0, 11, 0, Z), " &
+ "11 ( BC_1, * ,controlr, 1) " ;
+end or1k_10;
+
+end or1k_10;
Index: jtag/tags/rel_1/tap/rtl/verilog/tap_top.v
===================================================================
--- jtag/tags/rel_1/tap/rtl/verilog/tap_top.v (nonexistent)
+++ jtag/tags/rel_1/tap/rtl/verilog/tap_top.v (revision 22)
@@ -0,0 +1,649 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2004/01/08 10:29:44 mohor
+// Control signals for tdo_pad_o mux are changed to negedge.
+//
+// Revision 1.1 2003/12/23 14:52:14 mohor
+// Directory structure changed. New version of TAP.
+//
+// Revision 1.10 2003/10/23 18:08:01 mohor
+// MBIST chain connection fixed.
+//
+// Revision 1.9 2003/10/23 16:17:02 mohor
+// CRC logic changed.
+//
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "tap_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pads
+ tms_pad_i,
+ tck_pad_i,
+ trst_pad_i,
+ tdi_pad_i,
+ tdo_pad_o,
+ tdo_padoe_o,
+
+ // TAP states
+ shift_dr_o,
+ pause_dr_o,
+ update_dr_o,
+
+ // Select signals for boundary scan or mbist
+ extest_select_o,
+ sample_preload_select_o,
+ mbist_select_o,
+ debug_select_o,
+
+ // TDO signal that is connected to TDI of sub-modules.
+ tdo_o,
+
+ // TDI signals from sub-modules
+ debug_tdi_i, // from debug module
+ bs_chain_tdi_i, // from Boundary Scan Chain
+ mbist_tdi_i // from Mbist Chain
+ );
+
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output shift_dr_o;
+output pause_dr_o;
+output update_dr_o;
+
+// Select signals for boundary scan or mbist
+output extest_select_o;
+output sample_preload_select_o;
+output mbist_select_o;
+output debug_select_o;
+
+// TDO signal that is connected to TDI of sub-modules.
+output tdo_o;
+
+// TDI signals from sub-modules
+input debug_tdi_i; // from debug module
+input bs_chain_tdi_i; // from Boundary Scan Chain
+input mbist_tdi_i; // from Mbist Chain
+
+// Registers
+reg test_logic_reset;
+reg run_test_idle;
+reg select_dr_scan;
+reg capture_dr;
+reg shift_dr;
+reg exit1_dr;
+reg pause_dr;
+reg exit2_dr;
+reg update_dr;
+reg select_ir_scan;
+reg capture_ir;
+reg shift_ir, shift_ir_neg;
+reg exit1_ir;
+reg pause_ir;
+reg exit2_ir;
+reg update_ir;
+reg extest_select;
+reg sample_preload_select;
+reg idcode_select;
+reg mbist_select;
+reg debug_select;
+reg bypass_select;
+reg tdo_pad_o;
+reg tdo_padoe_o;
+reg tms_q1, tms_q2, tms_q3, tms_q4;
+wire tms_reset;
+
+assign tdo_o = tdi_pad_i;
+assign shift_dr_o = shift_dr;
+assign pause_dr_o = pause_dr;
+assign update_dr_o = update_dr;
+
+assign extest_select_o = extest_select;
+assign sample_preload_select_o = sample_preload_select;
+assign mbist_select_o = mbist_select;
+assign debug_select_o = debug_select;
+
+
+always @ (posedge tck_pad_i)
+begin
+ tms_q1 <= #1 tms_pad_i;
+ tms_q2 <= #1 tms_q1;
+ tms_q3 <= #1 tms_q2;
+ tms_q4 <= #1 tms_q3;
+end
+
+
+assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// test_logic_reset state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ test_logic_reset<=#1 1'b1;
+ else if (tms_reset)
+ test_logic_reset<=#1 1'b1;
+ else
+ begin
+ if(tms_pad_i & (test_logic_reset | select_ir_scan))
+ test_logic_reset<=#1 1'b1;
+ else
+ test_logic_reset<=#1 1'b0;
+ end
+end
+
+// run_test_idle state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ run_test_idle<=#1 1'b0;
+ else if (tms_reset)
+ run_test_idle<=#1 1'b0;
+ else
+ if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
+ run_test_idle<=#1 1'b1;
+ else
+ run_test_idle<=#1 1'b0;
+end
+
+// select_dr_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_dr_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_dr_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & (run_test_idle | update_dr | update_ir))
+ select_dr_scan<=#1 1'b1;
+ else
+ select_dr_scan<=#1 1'b0;
+end
+
+// capture_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_dr<=#1 1'b0;
+ else if (tms_reset)
+ capture_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_dr_scan)
+ capture_dr<=#1 1'b1;
+ else
+ capture_dr<=#1 1'b0;
+end
+
+// shift_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_dr<=#1 1'b0;
+ else if (tms_reset)
+ shift_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
+ shift_dr<=#1 1'b1;
+ else
+ shift_dr<=#1 1'b0;
+end
+
+// exit1_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit1_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_dr | shift_dr))
+ exit1_dr<=#1 1'b1;
+ else
+ exit1_dr<=#1 1'b0;
+end
+
+// pause_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_dr<=#1 1'b0;
+ else if (tms_reset)
+ pause_dr<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_dr | pause_dr))
+ pause_dr<=#1 1'b1;
+ else
+ pause_dr<=#1 1'b0;
+end
+
+// exit2_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_dr<=#1 1'b0;
+ else if (tms_reset)
+ exit2_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_dr)
+ exit2_dr<=#1 1'b1;
+ else
+ exit2_dr<=#1 1'b0;
+end
+
+// update_dr state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_dr<=#1 1'b0;
+ else if (tms_reset)
+ update_dr<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_dr | exit2_dr))
+ update_dr<=#1 1'b1;
+ else
+ update_dr<=#1 1'b0;
+end
+
+// select_ir_scan state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ select_ir_scan<=#1 1'b0;
+ else if (tms_reset)
+ select_ir_scan<=#1 1'b0;
+ else
+ if(tms_pad_i & select_dr_scan)
+ select_ir_scan<=#1 1'b1;
+ else
+ select_ir_scan<=#1 1'b0;
+end
+
+// capture_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ capture_ir<=#1 1'b0;
+ else if (tms_reset)
+ capture_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & select_ir_scan)
+ capture_ir<=#1 1'b1;
+ else
+ capture_ir<=#1 1'b0;
+end
+
+// shift_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ shift_ir<=#1 1'b0;
+ else if (tms_reset)
+ shift_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
+ shift_ir<=#1 1'b1;
+ else
+ shift_ir<=#1 1'b0;
+end
+
+// exit1_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit1_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit1_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (capture_ir | shift_ir))
+ exit1_ir<=#1 1'b1;
+ else
+ exit1_ir<=#1 1'b0;
+end
+
+// pause_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ pause_ir<=#1 1'b0;
+ else if (tms_reset)
+ pause_ir<=#1 1'b0;
+ else
+ if(~tms_pad_i & (exit1_ir | pause_ir))
+ pause_ir<=#1 1'b1;
+ else
+ pause_ir<=#1 1'b0;
+end
+
+// exit2_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ exit2_ir<=#1 1'b0;
+ else if (tms_reset)
+ exit2_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & pause_ir)
+ exit2_ir<=#1 1'b1;
+ else
+ exit2_ir<=#1 1'b0;
+end
+
+// update_ir state
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ update_ir<=#1 1'b0;
+ else if (tms_reset)
+ update_ir<=#1 1'b0;
+ else
+ if(tms_pad_i & (exit1_ir | exit2_ir))
+ update_ir<=#1 1'b1;
+ else
+ update_ir<=#1 1'b0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* jtag_ir: JTAG Instruction Register *
+* *
+**********************************************************************************/
+reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
+reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
+reg instruction_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
+ else if(capture_ir)
+ jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
+ else if(shift_ir)
+ jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ instruction_tdo <= #1 jtag_ir[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_ir *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* jtag_dr: JTAG Data Register *
+* *
+**********************************************************************************/
+reg [`DR_LENGTH-1:0] jtag_dr; // Data register
+reg [`DR_LENGTH-1:0] latched_jtag_dr;
+reg data_tdo;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
+ else
+ if(capture_dr)
+ jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection
+ else
+ if(shift_dr)
+ jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
+end
+
+always @ (negedge tck_pad_i)
+begin
+ data_tdo <= #1 jtag_dr[0];
+end
+/**********************************************************************************
+* *
+* End: jtag_dr *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* idcode logic *
+* *
+**********************************************************************************/
+reg [31:0] idcode_reg;
+reg idcode_tdo;
+
+always @ (posedge tck_pad_i)
+begin
+ if(idcode_select & shift_dr)
+ idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
+ else
+ idcode_reg <= #1 `IDCODE_VALUE;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ idcode_tdo <= #1 idcode_reg;
+end
+/**********************************************************************************
+* *
+* End: idcode logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg bypassed_tdo;
+reg bypass_reg;
+
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if (trst_pad_i)
+ bypass_reg<=#1 1'b0;
+ else if(shift_dr)
+ bypass_reg<=#1 tdi_pad_i;
+end
+
+always @ (negedge tck_pad_i)
+begin
+ bypassed_tdo <=#1 bypass_reg;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+// Updating jtag_ir (Instruction Register)
+always @ (posedge tck_pad_i or posedge trst_pad_i)
+begin
+ if(trst_pad_i)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if (tms_reset)
+ latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
+ else if(update_ir)
+ latched_jtag_ir <=#1 jtag_ir;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating jtag_ir (Instruction Register)
+always @ (latched_jtag_ir)
+begin
+ extest_select = 1'b0;
+ sample_preload_select = 1'b0;
+ idcode_select = 1'b0;
+ mbist_select = 1'b0;
+ debug_select = 1'b0;
+ bypass_select = 1'b0;
+
+ case(latched_jtag_ir) /* synthesis parallel_case */
+ `EXTEST: extest_select = 1'b1; // External test
+ `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
+ `IDCODE: idcode_select = 1'b1; // ID Code
+ `MBIST: mbist_select = 1'b1; // Mbist test
+ `DEBUG: debug_select = 1'b1; // Debug
+ `BYPASS: bypass_select = 1'b1; // BYPASS
+ default: bypass_select = 1'b1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
+ debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
+ bypassed_tdo)
+begin
+ if(shift_ir_neg)
+ tdo_pad_o <=#1 instruction_tdo;
+ else
+ begin
+ case(latched_jtag_ir_neg) // synthesis parallel_case
+ `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
+ `DEBUG: tdo_pad_o = debug_tdi_i; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
+ `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
+ default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
+ endcase
+ end
+end
+
+
+// Tristate control for tdo_pad_o pin
+always @ (negedge tck_pad_i)
+begin
+ tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
+end
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+
+always @ (negedge tck_pad_i)
+begin
+ shift_ir_neg <= #1 shift_ir;
+ latched_jtag_ir_neg <= #1 latched_jtag_ir;
+end
+
+
+endmodule
jtag/tags/rel_1/tap/rtl/verilog/tap_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_1/tap/rtl/verilog/tap_defines.v
===================================================================
--- jtag/tags/rel_1/tap/rtl/verilog/tap_defines.v (nonexistent)
+++ jtag/tags/rel_1/tap/rtl/verilog/tap_defines.v (revision 22)
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_defines.v ////
+//// ////
+//// ////
+//// This file is part of the JTAG Test Access Port (TAP) ////
+//// http://www.opencores.org/projects/jtag/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Length of the Data register
+`define DR_LENGTH 4
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
jtag/tags/rel_1/tap/rtl/verilog/tap_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: jtag/tags/rel_1/doc/Boundary-Scan_Architecture.pdf
===================================================================
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Index: jtag/tags/rel_1/doc/Boundary-Scan_Architecture.pdf
===================================================================
--- jtag/tags/rel_1/doc/Boundary-Scan_Architecture.pdf (nonexistent)
+++ jtag/tags/rel_1/doc/Boundary-Scan_Architecture.pdf (revision 22)
jtag/tags/rel_1/doc/Boundary-Scan_Architecture.pdf
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+application/octet-stream
\ No newline at end of property
Index: jtag/tags/rel_1/doc/or1k_10.bsd
===================================================================
--- jtag/tags/rel_1/doc/or1k_10.bsd (nonexistent)
+++ jtag/tags/rel_1/doc/or1k_10.bsd (revision 22)
@@ -0,0 +1,139 @@
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// or1k_10.bsd ////
+--// ////
+--// This file is part of the IEEE 1149.1 Test Access Port (TAP) ////
+--// IP core project ////
+--// http://www.opencores.org/cores/jtag/ ////
+--// ////
+--// Author(s): ////
+--// - Igor Mohor (igorM@opencores.org) ////
+--// ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// Copyright (C) 2000, 2001 Authors ////
+--// ////
+--// This source file may be used and distributed without ////
+--// restriction provided that this copyright statement is not ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer. ////
+--// ////
+--// This source file is free software; you can redistribute it ////
+--// and/or modify it under the terms of the GNU Lesser General ////
+--// Public License as published by the Free Software Foundation; ////
+--// either version 2.1 of the License, or (at your option) any ////
+--// later version. ////
+--// ////
+--// This source is distributed in the hope that it will be ////
+--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--// PURPOSE. See the GNU Lesser General Public License for more ////
+--// details. ////
+--// ////
+--// You should have received a copy of the GNU Lesser General ////
+--// Public License along with this source; if not, download it ////
+--// from http://www.opencores.org/lgpl.shtml ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2001/08/01 18:49:42 mohor
+-- Reset signal changed. Bsdl file added to the project.
+--
+--
+--
+--
+--
+
+--
+-- BSDL File created/edited by Igor Mohor (igorm@opencores.org)
+--
+--Package: ??
+entity or1k_10 is
+
+generic (PHYSICAL_PIN_MAP : string := "vq44" );
+
+port (
+ MyInput0: in bit;
+ MyInput1: in bit;
+ MyOutput0: out bit;
+ MyOutput1: out bit;
+ MyBidirectional0: inout bit;
+ MyBidirectional1: inout bit;
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit
+ );
+
+use STD_1149_1_1994.all;
+
+attribute COMPONENT_CONFORMANCE of or1k_10 : entity is "STD_1149_1_1993";
+attribute PIN_MAP of or1k_10 : entity is PHYSICAL_PIN_MAP;
+
+constant vq44: PIN_MAP_STRING:=
+ "TCK:1," &
+ "TDI:2," &
+ "TDO:3," &
+ "TMS:4," &
+ "MyInput0:5," &
+ "MyInput1:6," &
+ "MyOutput0:7," &
+ "MyOutput1:8," &
+ "MyBidirectional0:9," &
+ "MyBidirectional1:10";
+
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_MODE of TMS : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+06, BOTH); --
+attribute INSTRUCTION_LENGTH of or1k_10 : entity is 4;
+
+attribute INSTRUCTION_OPCODE of or1k_10 : entity is --
+ "EXTEST ( 0000)," &
+ "SAMPLE ( 0001)," &
+ "IDCODE ( 0010)," &
+ "BYPASS ( 1111)";
+
+attribute INSTRUCTION_CAPTURE of or1k_10: entity is "1001";
+
+attribute IDCODE_REGISTER of or1k_10: entity is --
+ "1100" & -- version
+ "0011110000111100" & -- part number
+ "00111100001" & -- manufacturer's id
+ "1"; -- required by standard
+
+--attribute USERCODE_REGISTER of or1k_10: entity is
+-- "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+
+-- attribute INSTRUCTION_DISABLE of or1k_10 : entity is "HIGHZ";
+
+attribute REGISTER_ACCESS of or1k_10 : entity is
+ "BYPASS (BYPASS)," &
+ "DEVICE_ID (IDCODE)," &
+ "BOUNDARY (SAMPLE,EXTEST)";
+
+attribute BOUNDARY_LENGTH of or1k_10 : entity is 12;
+--attribute BOUNDARY_LENGTH of or1k_10 : entity is 6;
+
+attribute BOUNDARY_REGISTER of or1k_10 : entity is
+-- num cell port function safe [ccell disval rslt]
+ "0 ( BC_1, MyInput0 ,input , X), " &
+ "1 ( BC_1, MyInput1 ,input , X), " &
+ "2 ( BC_1, MyOutput0 ,output3 , 0, 3, 0, Z), " &
+ "3 ( BC_1, * ,controlr, 1), " &
+ "4 ( BC_1, MyOutput1 ,output3 , 0, 5, 0, Z), " &
+ "5 ( BC_1, * ,controlr, 1), " &
+ "6 ( BC_1, MyBidirectional0 ,input , X), " &
+ "7 ( BC_1, MyBidirectional0 ,output3 , 0, 8, 0, Z), " &
+ "8 ( BC_1, * ,controlr, 1), " &
+ "9 ( BC_1, MyBidirectional1 ,input , X), " &
+ "10 ( BC_1, MyBidirectional1 ,output3 , 0, 11, 0, Z), " &
+ "11 ( BC_1, * ,controlr, 1) " ;
+end or1k_10;
+
+end or1k_10;
Index: jtag/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf
===================================================================
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Index: jtag/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf (revision 22)
jtag/tags/arelease/ieee_1149.1_tap/Boundary-Scan_Architecture.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: jtag/tags/arelease/ieee_1149.1_tap/InputCell.v
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/InputCell.v (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/InputCell.v (revision 22)
@@ -0,0 +1,62 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Input Cell: *
+* *
+* InputPin: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR: TAP states *
+* TCK: Test Clock *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
+input InputPin;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+
+endmodule // InputCell
\ No newline at end of file
Index: jtag/tags/arelease/ieee_1149.1_tap/ControlCell.v
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/ControlCell.v (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/ControlCell.v (revision 22)
@@ -0,0 +1,77 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* I/O Control Cell: *
+* *
+* OutputControl: Output Control from on-chip logic *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* *
+* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
+* shifting data for the exact number of time *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
+input OutputControl;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+
+reg Latch;
+
+output ToNextBSCell;
+output ToOutputEnable;
+
+reg ToNextBSCell;
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+assign ToOutputEnable = extest? ShiftedControl : OutputControl;
+
+endmodule // ControlCell
\ No newline at end of file
Index: jtag/tags/arelease/ieee_1149.1_tap/OutputCell.v
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/OutputCell.v (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/OutputCell.v (revision 22)
@@ -0,0 +1,83 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Output Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* TristatedPin: Signal from core is connected to this output pin via BS *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to TristatedPin comes from core or BS chain. *
+* Tristate control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+// This is not a top module
+module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output TristatedPin;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+endmodule // OutputCell
\ No newline at end of file
Index: jtag/tags/arelease/ieee_1149.1_tap/TAP.v
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/TAP.v (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/TAP.v (revision 22)
@@ -0,0 +1,585 @@
+/**********************************************************************************
+* *
+* This verilog file is a part of the Boundary Scan Implementation and comes in *
+* a pack with several other files. It is fully IEEE 1149.1 compliant. *
+* For details check www.opencores.org (pdf files, bsdl file, etc.) *
+* *
+* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
+* *
+* This program is free software; you can redistribute it and/or modify *
+* it under the terms of the GNU General Public License as published by *
+* the Free Software Foundation; either version 2 of the License, or *
+* (at your option) any later version. *
+* *
+* See the file COPYING for the full details of the license. *
+* *
+* OPENCORES.ORG is looking for new open source IP cores and developers that *
+* would like to help in our mission. *
+* *
+**********************************************************************************/
+
+
+// Top module
+module TAP(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO,
+ TestSignal,
+ InputPin,
+ Output3Pin,
+ Output2Pin,
+ BidirectionalPin
+ );
+
+`define BSLength 14
+
+supply1 vcc;
+supply0 gnd;
+
+// Instructions specified by the IEEE-1149.1
+parameter EXTEST = 4'b0000;
+parameter SAMPLE_PRELOAD = 4'b0001;
+parameter IDCODE = 4'b0010;
+parameter BYPASS = 4'b1111;
+
+
+input P_TMS, P_TCK;
+input P_TRST, P_TDI;
+
+output P_TDO;
+
+input [1:0] InputPin; // Input pin
+output [1:0] Output3Pin; // Output pin with tristate control
+output [1:0] Output2Pin; // Output pin without tristate control
+inout [1:0] BidirectionalPin; // Input/Output pin (with tristate control)
+
+output [5:0]TestSignal; // Signals for testing purposes (can be deleted)
+
+wire TCK = P_TCK;
+wire TCKn = ~P_TCK;
+wire TMS = P_TMS;
+wire TDI = P_TDI;
+
+wire TRST = P_TRST; // TRST is active high (for easier development). Should be change to active low
+//wire TRST = ~P_TRST; // active low
+
+reg TestLogicReset;
+reg RunTestIdle;
+reg SelectDRScan;
+reg CaptureDR;
+reg ShiftDR;
+reg Exit1DR;
+reg PauseDR;
+reg Exit2DR;
+reg UpdateDR;
+
+reg SelectIRScan;
+reg CaptureIR;
+reg ShiftIR;
+reg Exit1IR;
+reg PauseIR;
+reg Exit2IR;
+reg UpdateIR;
+
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+* P_TRST must toggle at the beginning if PowerONReset signal is not present *
+* in the design. *
+* *
+* *
+* *
+**********************************************************************************/
+//wire RESET = TRST | PowerONReset; // If PowerONReset signal is used in the design
+wire RESET = TRST; // If no PowerONReset signal is used in the design
+
+// TestLogicReset state
+always @ (posedge TCK or posedge RESET)
+begin
+ if(RESET)
+ TestLogicReset<=1;
+ else
+ begin
+ if(TMS & (TestLogicReset | SelectIRScan))
+ TestLogicReset<=1;
+ else
+ TestLogicReset<=0;
+ end
+end
+
+// RunTestIdle state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ RunTestIdle<=0;
+ else
+ begin
+ if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
+ RunTestIdle<=1;
+ else
+ RunTestIdle<=0;
+ end
+end
+
+// SelectDRScan state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ SelectDRScan<=0;
+ else
+ begin
+ if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
+ SelectDRScan<=1;
+ else
+ SelectDRScan<=0;
+ end
+end
+
+// CaptureDR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ CaptureDR<=0;
+ else
+ begin
+ if(~TMS & SelectDRScan)
+ CaptureDR<=1;
+ else
+ CaptureDR<=0;
+ end
+end
+
+// ShiftDR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ ShiftDR<=0;
+ else
+ begin
+ if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
+ ShiftDR<=1;
+ else
+ ShiftDR<=0;
+ end
+end
+
+// Exit1DR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ Exit1DR<=0;
+ else
+ begin
+ if(TMS & (CaptureDR | ShiftDR))
+ Exit1DR<=1;
+ else
+ Exit1DR<=0;
+ end
+end
+
+// PauseDR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ PauseDR<=0;
+ else
+ begin
+ if(~TMS & (Exit1DR | PauseDR))
+ PauseDR<=1;
+ else
+ PauseDR<=0;
+ end
+end
+
+// Exit2DR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ Exit2DR<=0;
+ else
+ begin
+ if(TMS & PauseDR)
+ Exit2DR<=1;
+ else
+ Exit2DR<=0;
+ end
+end
+
+// UpdateDR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ UpdateDR<=0;
+ else
+ begin
+ if(TMS & (Exit1DR | Exit2DR))
+ UpdateDR<=1;
+ else
+ UpdateDR<=0;
+ end
+end
+
+// SelectIRScan state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ SelectIRScan<=0;
+ else
+ begin
+ if(TMS & SelectDRScan)
+ SelectIRScan<=1;
+ else
+ SelectIRScan<=0;
+ end
+end
+
+// CaptureIR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ CaptureIR<=0;
+ else
+ begin
+ if(~TMS & SelectIRScan)
+ CaptureIR<=1;
+ else
+ CaptureIR<=0;
+ end
+end
+
+// ShiftIR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ ShiftIR<=0;
+ else
+ begin
+ if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
+ ShiftIR<=1;
+ else
+ ShiftIR<=0;
+ end
+end
+
+// Exit1IR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ Exit1IR<=0;
+ else
+ begin
+ if(TMS & (CaptureIR | ShiftIR))
+ Exit1IR<=1;
+ else
+ Exit1IR<=0;
+ end
+end
+
+// PauseIR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ PauseIR<=0;
+ else
+ begin
+ if(~TMS & (Exit1IR | PauseIR))
+ PauseIR<=1;
+ else
+ PauseIR<=0;
+ end
+end
+
+// Exit2IR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ Exit2IR<=0;
+ else
+ begin
+ if(TMS & PauseIR)
+ Exit2IR<=1;
+ else
+ Exit2IR<=0;
+ end
+end
+
+// UpdateIR state
+always @ (posedge TCK or posedge TRST)
+begin
+ if(TRST)
+ UpdateIR<=0;
+ else
+ begin
+ if(TMS & (Exit1IR | Exit2IR))
+ UpdateIR<=1;
+ else
+ UpdateIR<=0;
+ end
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* JTAG_SIR: JTAG Shift Instruction Register: Instruction shifted in, status out *
+* JTAG_IR: JTAG Instruction Register: Updated on UpdateIR or TestLogicReset *
+* *
+* Status is shifted out. *
+* *
+**********************************************************************************/
+wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
+
+reg [3:0]JTAG_SIR; // Register used for shifting in and out
+reg [3:0]JTAG_IR; // Instruction register
+reg TDOInstruction;
+
+always @ (posedge TCK)
+begin
+ if(CaptureIR)
+ begin
+ JTAG_SIR[1:0] <= 2'b01; // This value is fixed for easier fault detection
+ JTAG_SIR[3:2] <= Status[1:0]; // Current status of chip
+ end
+ else
+ begin
+ if(ShiftIR)
+ begin
+ JTAG_SIR[3:0] <= JTAG_SIR[3:0] >> 1;
+ JTAG_SIR[3] <= TDI;
+ end
+ end
+end
+
+// Updating JTAG_IR (Instruction Register)
+always @ (posedge TCK or posedge TestLogicReset)
+begin
+ if(TestLogicReset)
+ JTAG_IR <= IDCODE;
+ else
+ begin
+ if(UpdateIR)
+ JTAG_IR <= JTAG_SIR;
+ end
+end
+
+//TDO is changing on the falling edge of TCK
+always @ (negedge TCK)
+begin
+ if(ShiftIR)
+ TDOInstruction <= JTAG_SIR[0];
+end
+
+/**********************************************************************************
+* *
+* End: JTAG_SIR *
+* End: JTAG_IR *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* JTAG_SDR: JTAG Shift Data Register: Data shifted in and out *
+* JTAG_DR: JTAG Data Register: Updated on UpdateDR *
+* *
+* Data that is shifted out can be a chip ID or a requested data (register value,*
+* memory value, etc. *
+* *
+**********************************************************************************/
+wire [32:0] IDCodeValue = 33'b011000011110000111100001111000011; // ID value (constant 0x0c3c3c3c3). IDCODE is 32-bit long, so the MSB is not used
+wire [32:0] DataValue = 33'b101001100011100001111000111001101; // This should be data from the core. For now a constant value 0x14c70f1cd is used
+wire [32:0] RequestedData = (JTAG_IR==IDCODE)? IDCodeValue : DataValue; // This is to be expanded with number of user registers
+
+reg [32:0]JTAG_SDR; // Register used for shifting in and out
+reg [32:0]JTAG_DR; // Data register
+reg TDOData;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR)
+ JTAG_SDR <= RequestedData; // DataResponse contains data requested in previous cycle
+ else
+ begin
+ if(ShiftDR)
+ begin
+ JTAG_SDR <= JTAG_SDR >> 1;
+ JTAG_SDR[32] <= TDI;
+ end
+ end
+end
+
+// Updating JTAG_DR (Data Register)
+always @ (posedge TCK)
+begin
+ if(UpdateDR)
+ JTAG_DR <= JTAG_SDR;
+end
+
+//TDO is changing on the falling edge of TCK
+always @ (negedge TCK)
+begin
+ if(ShiftDR)
+ TDOData <= JTAG_SDR[0];
+end
+
+/**********************************************************************************
+* *
+* End: JTAG_SDR *
+* End: JTAG_DR *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg BypassRegister;
+reg TDOBypassed;
+
+always @ (posedge TCK)
+begin
+ if(ShiftDR)
+ BypassRegister<=TDI;
+end
+
+always @ (negedge TCK)
+begin
+ TDOBypassed<=BypassRegister;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Boundary Scan Logic *
+* *
+**********************************************************************************/
+wire [`BSLength-1:0]ExitFromBSCell;
+
+
+wire [3:0]ToOutputEnable;
+wire [1:0]BidirectionalBuffered;
+
+wire [5:0]FromCore = 6'h0; // This are signals that core send to output (or bidirectional) pins. We have no core, so they are all zero.
+wire [3:0]ControlPIN = 4'h0; // Core control signals. Since no core is used, they are fixed to zero.
+
+// buffers
+assign BidirectionalBuffered[1:0] = BidirectionalPin[1:0]; // Inputs of bidirectional signals should be buffered (as seen below)
+//IBUF buffer0 (.I(BidirectionalPin[0]), .O(BidirectionalBuffered[0]));
+//IBUF buffer1 (.I(BidirectionalPin[1]), .O(BidirectionalBuffered[1]));
+
+wire ExtTestEnabled = (JTAG_IR==EXTEST) | (JTAG_IR==SAMPLE_PRELOAD);
+
+
+// BOUNDARY SCAN REGISTER
+// closest to TDO
+InputCell BS0 ( .InputPin(InputPin[0]), .FromPreviousBSCell(ExitFromBSCell[12]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[`BSLength-1]));
+InputCell BS1 ( .InputPin(InputPin[1]), .FromPreviousBSCell(ExitFromBSCell[11]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[12]));
+
+OutputCell BS2 ( .FromCore(FromCore[0]), .FromPreviousBSCell(ExitFromBSCell[10]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[11]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[0]), .TristatedPin(Output3Pin[0]));
+ControlCell BS3 ( .OutputControl(ControlPIN[0]), .FromPreviousBSCell(ExitFromBSCell[9]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[10]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[0]));
+
+OutputCell BS4 ( .FromCore(FromCore[1]), .FromPreviousBSCell(ExitFromBSCell[8]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[9]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[1]), .TristatedPin(Output3Pin[1]));
+ControlCell BS5 ( .OutputControl(ControlPIN[1]), .FromPreviousBSCell(ExitFromBSCell[7]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[8]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[1]));
+
+InputCell BS6 ( .InputPin(BidirectionalBuffered[0]), .FromPreviousBSCell(ExitFromBSCell[6]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[7]));
+OutputCell BS7 ( .FromCore(FromCore[2]), .FromPreviousBSCell(ExitFromBSCell[5]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[6]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[2]), .TristatedPin(BidirectionalPin[0]));
+ControlCell BS8 ( .OutputControl(ControlPIN[2]), .FromPreviousBSCell(ExitFromBSCell[4]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[5]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[2]));
+
+InputCell BS9 ( .InputPin(BidirectionalBuffered[1]), .FromPreviousBSCell(ExitFromBSCell[3]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[4]));
+OutputCell BS10 ( .FromCore(FromCore[3]), .FromPreviousBSCell(ExitFromBSCell[2]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[3]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[3]), .TristatedPin(BidirectionalPin[1]));
+ControlCell BS11 ( .OutputControl(ControlPIN[3]), .FromPreviousBSCell(ExitFromBSCell[1]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[2]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[3]));
+
+OutputCell BS12 ( .FromCore(FromCore[4]), .FromPreviousBSCell(ExitFromBSCell[0]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[1]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc), .TristatedPin(Output2Pin[0]));
+OutputCell BS13 ( .FromCore(FromCore[5]), .FromPreviousBSCell(TDI), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[0]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc), .TristatedPin(Output2Pin[1]));
+// closest to TDI
+
+
+/**********************************************************************************
+* *
+* End: Boundary Scan Logic *
+* *
+**********************************************************************************/
+
+
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO and Tristate control *
+* *
+**********************************************************************************/
+wire TDOShifted;
+assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
+
+reg TDOMuxed;
+
+
+// This multiplexing can be expanded with number of user registers
+always @ (JTAG_IR or TDOShifted or ExitFromBSCell or TDOBypassed)
+begin
+ case(JTAG_IR)
+ IDCODE: // Reading ID code
+ begin
+ TDOMuxed<=TDOShifted;
+ end
+ SAMPLE_PRELOAD: // Sampling/Preloading
+ begin
+ TDOMuxed<=ExitFromBSCell[`BSLength-1];
+ end
+ EXTEST: // External test
+ begin
+ TDOMuxed<=ExitFromBSCell[`BSLength-1];
+ end
+ default: // BYPASS instruction
+ begin
+ TDOMuxed<=TDOBypassed;
+ end
+ endcase
+end
+
+
+
+// Tristate control for P_TDO pin
+assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR)? TDOMuxed : 1'bz;
+
+
+/**********************************************************************************
+* *
+* End: Multiplexing TDO and Tristate control *
+* *
+**********************************************************************************/
+
+
+
+
+
+
+// Test Signals (can be deleted)
+
+assign TestSignal[0] = CaptureDR;
+assign TestSignal[1] = RunTestIdle;
+assign TestSignal[2] = ShiftDR;
+assign TestSignal[3] = UpdateDR;
+
+assign TestSignal[4] = JTAG_IR[0];
+assign TestSignal[5] = JTAG_IR[1];
+
+
+
+endmodule // TAP
Index: jtag/tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v
===================================================================
--- jtag/tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v (nonexistent)
+++ jtag/tags/arelease/ieee_1149.1_tap/BiDirectionalCell.v (revision 22)
@@ -0,0 +1,66 @@
+/**********************************************************************************
+* *
+* BiDirectional Cell: *
+* *
+* FromCore: Value that comes from on-chip logic and goes to pin *
+* ToCore: Value that is read-in from the pin and goes to core *
+* FromPreviousBSCell: Value from previous boundary scan cell *
+* ToNextBSCell: Value for next boundary scan cell *
+* CaptureDR, ShiftDR, UpdateDR: TAP states *
+* extest: Instruction Register Command *
+* TCK: Test Clock *
+* BiDirPin: Bidirectional pin connected to this BS cell *
+* FromOutputEnable: This pin comes from core or ControlCell *
+* *
+* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
+* control is generated in core or BS chain (ControlCell). *
+* *
+**********************************************************************************/
+
+module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
+input FromCore;
+input FromPreviousBSCell;
+input CaptureDR;
+input ShiftDR;
+input UpdateDR;
+input extest;
+input TCK;
+input FromOutputEnable;
+
+reg Latch;
+
+output ToNextBSCell;
+reg ToNextBSCell;
+
+output BiDirPin;
+output ToCore;
+
+reg ShiftedControl;
+
+wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
+
+always @ (posedge TCK)
+begin
+ if(CaptureDR | ShiftDR)
+ Latch<=SelectedInput;
+end
+
+always @ (negedge TCK)
+begin
+ ToNextBSCell<=Latch;
+end
+
+always @ (negedge TCK)
+begin
+ if(UpdateDR)
+ ShiftedControl<=ToNextBSCell;
+end
+
+wire MuxedSignal = extest? ShiftedControl : FromCore;
+assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
+
+//BUF Buffer (.I(BiDirPin), .O(ToCore));
+assign ToCore = BiDirPin;
+
+
+endmodule // TristateCell
\ No newline at end of file
Index: jtag/tags
===================================================================
--- jtag/tags (nonexistent)
+++ jtag/tags (revision 22)
jtag/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##