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Rev 21 → Rev 22

/trunk/rtl/verilog/mc_cs_rf.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_cs_rf.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
// $Id: mc_cs_rf.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-11 02:47:19 $
// $Revision: 1.5 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
/trunk/rtl/verilog/mc_mem_if.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_mem_if.v,v 1.5 2001-12-21 05:09:29 rudi Exp $
// $Id: mc_mem_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-21 05:09:29 $
// $Revision: 1.5 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
/trunk/rtl/verilog/mc_defines.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_defines.v,v 1.6 2001-12-12 06:35:15 rudi Exp $
// $Id: mc_defines.v,v 1.7 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-12 06:35:15 $
// $Revision: 1.6 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2001/12/12 06:35:15 rudi
// *** empty log message ***
//
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
111,7 → 115,6
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
//`define MC_REG_SEL (wb_addr_i[31:29] == 3'h6)
`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011)
 
// This define selects how the WISHBONE interface determines if
126,6 → 129,7
//
 
// This will be defined by the run script for my test bench ...
// Alternatively force here for synthesis ...
//`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
/trunk/rtl/verilog/mc_refresh.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_refresh.v,v 1.3 2001-12-11 02:47:19 rudi Exp $
// $Id: mc_refresh.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-11 02:47:19 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.2 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
/trunk/rtl/verilog/mc_top.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_top.v,v 1.6 2001-12-21 05:09:30 rudi Exp $
// $Id: mc_top.v,v 1.7 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-21 05:09:30 $
// $Revision: 1.6 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2001/12/21 05:09:30 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.5 2001/11/29 02:16:28 rudi
//
//
269,6 → 275,16
assign tms_s = lmr_sel ? sp_tms : tms;
assign csc_s = lmr_sel ? sp_csc : csc;
 
 
wire not_mem_cyc;
 
assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL );
 
reg mem_ack_r;
 
always @(posedge clk_i)
mem_ack_r <= #1 mem_ack;
 
////////////////////////////////////////////////////////////////////
//
// Modules
312,7 → 328,8
.csc( csc_s ),
.tms( tms_s ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_write_go( wb_write_go ),
353,7 → 370,8
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.mem_ack( mem_ack ),
.wb_ack_o( wb_ack_o ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_we_i( wb_we_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( mem_dout ),
401,6 → 419,7
.mc_br( mc_br_r ),
.mc_bg( mc_bg_d ),
.mc_ack( mc_ack_r ),
.not_mem_cyc( not_mem_cyc ),
.data_oe( data_oe ),
.oe_( oe_ ),
.we_( we_ ),
/trunk/rtl/verilog/mc_dp.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_dp.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
// $Id: mc_dp.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-11 02:47:19 $
// $Revision: 1.5 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
/trunk/rtl/verilog/mc_wb_if.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
// $Id: mc_wb_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-11 02:47:19 $
// $Revision: 1.5 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.4 2001/11/29 02:16:28 rudi
//
//
211,15 → 216,19
// WB Ack
//
 
wire wb_err_d;
 
// Ack no longer asserted when wb_err is asserted
always @(posedge clk or posedge rst)
if(rst) wb_ack_o <= #1 1'b0;
else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
 
always @(posedge clk or posedge rst)
if(rst) wb_err <= #1 1'b0;
else wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
(par_err | err | wp_err) & !wb_err;
else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
 
////////////////////////////////////////////////////////////////////
//
/trunk/rtl/verilog/mc_obct.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_obct.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
// $Id: mc_obct.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.2 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
/trunk/rtl/verilog/mc_rf.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_rf.v,v 1.7 2001-12-21 05:09:29 rudi Exp $
// $Id: mc_rf.v,v 1.8 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-21 05:09:29 $
// $Revision: 1.7 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.6 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
/trunk/rtl/verilog/mc_timing.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_timing.v,v 1.7 2001-12-21 05:09:30 rudi Exp $
// $Id: mc_timing.v,v 1.8 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-21 05:09:30 $
// $Revision: 1.7 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2001/12/21 05:09:30 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.6 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
130,6 → 136,7
cs_en, wb_cycle, wr_cycle,
mc_br, mc_bg, mc_adsc, mc_adv,
mc_c_oe, mc_ack,
not_mem_cyc,
 
// Register File Interface
csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le,
185,6 → 192,7
output mc_adv;
output mc_c_oe;
input mc_ack;
input not_mem_cyc;
 
// Register File Interface
input [31:0] csc;
577,11 → 585,11
 
always @(posedge clk or posedge rst)
if(rst) lookup_ready1 <= #1 1'b0;
else lookup_ready1 <= #1 cs_le & wb_stb_i;
else lookup_ready1 <= #1 cs_le & wb_cyc_i & wb_stb_i;
 
always @(posedge clk or posedge rst)
if(rst) lookup_ready2 <= #1 1'b0;
else lookup_ready2 <= #1 lookup_ready1 & wb_stb_i;
else lookup_ready2 <= #1 lookup_ready1 & wb_cyc_i & wb_stb_i;
 
// Keep Track if it is a SDRAM write cycle
always @(posedge clk or posedge rst)
597,7 → 605,7
else
if(wb_cycle_set) wb_cycle <= #1 1'b1;
else
if(!wb_cyc_i) wb_cycle <= #1 1'b0;
if(!wb_cyc_i | not_mem_cyc) wb_cycle <= #1 1'b0;
 
// Thses two signals are used to signal that no wishbone cycle is in
// progress. Need to register them to avoid a very long combinatorial
642,7 → 650,6
else rfr_ack_r <= #1 rfr_ack_d;
 
// Suspend Select Logic
//assign susp_sel = susp_sel_r | susp_sel_set;
assign susp_sel = susp_sel_r;
 
always @(posedge clk or posedge rst)
888,7 → 895,9
`endif
IDLE:
begin
cs_le_d = wb_stb_first | lmr_req;
//cs_le_d = wb_stb_first | lmr_req;
cs_le_d = wb_stb_first;
 
burst_cnt_ld = 1'b1;
wr_clr = 1'b1;
 
895,7 → 904,6
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
 
 
if(rfr_req)
begin
rfr_ack_d = 1'b1;
1013,10 → 1021,8
begin
if(tmr2_done & (!wb_wait | !wb_cycle) )
begin
//cs_le_d = 1'b1;
//if(cs_le_r) next_state = IDLE;
cs_le_d = wb_stb_i;
if(cs_le_r | !wb_stb_i) next_state = IDLE;
cs_le_d = wb_cycle;
if(cs_le_r | !wb_cycle) next_state = IDLE;
end
end
 
1140,6 → 1146,7
 
SRAM_RD4: // DESELECT
begin
if(wb_cycle) cs_le_d = 1'b1; // For RMW
mc_adsc = 1'b1;
next_state = IDLE;
end
/trunk/rtl/verilog/mc_incn_r.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_incn_r.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
// $Id: mc_incn_r.v,v 1.2 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-07-29 07:34:41 $
// $Revision: 1.1 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1 2001/06/12 15:18:47 rudi
//
//
/trunk/rtl/verilog/mc_rd_fifo.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_rd_fifo.v,v 1.3 2001-12-11 02:47:19 rudi Exp $
// $Id: mc_rd_fifo.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-11 02:47:19 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/12/11 02:47:19 rudi
//
// - Made some changes not to expect clock during reset ...
//
// Revision 1.2 2001/11/29 02:16:28 rudi
//
//
/trunk/rtl/verilog/mc_adr_sel.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: mc_adr_sel.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
// $Id: mc_adr_sel.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/29 02:16:28 rudi
//
//
// - More Synthesis cleanup, mostly for speed
// - Several bug fixes
// - Changed code to avoid auto-precharge and
// burst-terminate combinations (apparently illegal ?)
// Now we will do a manual precharge ...
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
/trunk/rtl/verilog/mc_obct_top.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: mc_obct_top.v,v 1.3 2001-12-21 05:09:29 rudi Exp $
// $Id: mc_obct_top.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
// $Date: 2001-12-21 05:09:29 $
// $Revision: 1.3 $
// $Date: 2002-01-21 13:08:52 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/12/21 05:09:29 rudi
//
// - Fixed combinatorial loops in synthesis
// - Fixed byte select bug
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.

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