URL
https://opencores.org/ocsvn/miniuart2/miniuart2/trunk
Subversion Repositories miniuart2
Compare Revisions
- This comparison shows the changes necessary to convert path
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- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/branches/avendor/impl/Xilinx_xc2s15/_map.rsp
0,0 → 1,6
-p xc2s15-cs144-6 |
-cm area |
-k 4 |
-c 100 |
-tx off |
uart.ngd |
/branches/avendor/impl/Xilinx_xc2s15/_par.rsp
0,0 → 1,8
-ol 2 |
-xe 0 |
-t 1 |
-c 0 |
par_temp.ncd |
-w |
uart.ncd |
uart.pcf |
/branches/avendor/impl/Xilinx_xc2s15/automake.log
0,0 → 1,19
ISE Auto-Make Log File |
----------------------- |
|
Starting: 'jhdparse @utils.jp' |
|
|
JHDPARSE - VHDL/Verilog Parser. |
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved. |
|
Scanning j:/rtl/vhdl/utils.vhd |
Scanning j:/rtl/vhdl/utils.vhd |
j:/rtl/vhdl/utils.vhd(47) library IEEE,STD; |
^ |
Warning 0008: Unable to open library std. |
Writing utils.jhd. |
|
JHDPARSE complete - 0 errors, 1 warning. |
|
Done: completed successfully. |
/branches/avendor/impl/Xilinx_xc2s15/uart.syr
0,0 → 1,372
Release 4.2i - xst E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
--> Parameter TMPDIR set to . |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> Parameter overwrite set to YES |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> Parameter xsthdpdir set to ./xst |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> ========================================================================= |
---- Source Parameters |
Input Format : VHDL |
Input File Name : uart.prj |
|
---- Target Parameters |
Target Device : xc2s15-cs144-6 |
Output File Name : uart |
Output Format : NGC |
Target Technology : spartan2 |
|
---- Source Options |
Entity Name : uart |
Automatic FSM Extraction : YES |
FSM Encoding Algorithm : Auto |
FSM Flip-Flop Type : D |
Mux Extraction : YES |
Resource Sharing : YES |
Complex Clock Enable Extraction : YES |
ROM Extraction : Yes |
RAM Extraction : Yes |
RAM Style : Auto |
Mux Style : Auto |
Decoder Extraction : YES |
Priority Encoder Extraction : YES |
Shift Register Extraction : YES |
Logical Shifter Extraction : YES |
XOR Collapsing : YES |
Automatic Register Balancing : No |
|
---- Target Options |
Add IO Buffers : YES |
Equivalent register Removal : YES |
Add Generic Clock Buffer(BUFG) : 4 |
Global Maximum Fanout : 100 |
Register Duplication : YES |
Move First FlipFlop Stage : YES |
Move Last FlipFlop Stage : YES |
Slice Packing : YES |
Pack IO Registers into IOBs : auto |
Speed Grade : 6 |
|
---- General Options |
Optimization Criterion : Speed |
Optimization Effort : 1 |
Check Attribute Syntax : YES |
Keep Hierarchy : No |
Global Optimization : AllClockNets |
Write Timing Constraints : No |
|
========================================================================= |
|
Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work. |
Entity <synchroniser> (Architecture <behaviour>) compiled. |
Entity <counter> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work. |
Entity <txunit> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work. |
Entity <rxunit> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work. |
Entity <uart> (Architecture <behaviour>) compiled. |
|
Analyzing Entity <uart> (Architecture <behaviour>). |
Entity <uart> analyzed. Unit <uart> generated. |
|
Analyzing generic Entity <counter> (Architecture <behaviour>). |
count = 130 |
Entity <counter> analyzed. Unit <counter> generated. |
|
Analyzing generic Entity <counter> (Architecture <behaviour>). |
count = 4 |
Entity <counter> analyzed. Unit <counter0> generated. |
|
Analyzing Entity <txunit> (Architecture <behaviour>). |
Entity <txunit> analyzed. Unit <txunit> generated. |
|
Analyzing Entity <rxunit> (Architecture <behaviour>). |
Entity <rxunit> analyzed. Unit <rxunit> generated. |
|
Analyzing Entity <synchroniser> (Architecture <behaviour>). |
Entity <synchroniser> analyzed. Unit <synchroniser> generated. |
|
|
Synthesizing Unit <synchroniser>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <c1a>. |
Found 1-bit register for signal <c1s>. |
Found 1-bit register for signal <r>. |
Summary: |
inferred 3 D-type flip-flop(s). |
Unit <synchroniser> synthesized. |
|
|
Synthesizing Unit <rxunit>. |
Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd. |
Found 1-bit register for signal <rxav>. |
Found 8-bit register for signal <datao>. |
Found 2-bit adder for signal <$n0002> created at line 91. |
Found 4-bit adder for signal <$n0018> created at line 85. |
Found 4-bit comparator greatequal for signal <$n0038> created at line 81. |
Found 4-bit register for signal <bitpos>. |
Found 8-bit register for signal <rreg>. |
Found 1-bit register for signal <rregl>. |
Found 2-bit register for signal <samplecnt>. |
Summary: |
inferred 24 D-type flip-flop(s). |
inferred 2 Adder/Subtracter(s). |
inferred 1 Comparator(s). |
Unit <rxunit> synthesized. |
|
|
Synthesizing Unit <txunit>. |
Related source file is J:/impl/../rtl/vhdl/Txunit.vhd. |
Found 1-bit register for signal <txd>. |
Found 4-bit adder for signal <$n0012> created at line 92. |
Found 4-bit register for signal <bitpos>. |
Found 8-bit register for signal <tbuff>. |
Found 1-bit register for signal <tbufl>. |
Found 8-bit register for signal <treg>. |
Summary: |
inferred 22 D-type flip-flop(s). |
inferred 1 Adder/Subtracter(s). |
Unit <txunit> synthesized. |
|
|
Synthesizing Unit <counter0>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <o>. |
Found 2-bit down counter for signal <cnt>. |
WARNING:Xst:647 - Input <reset> is never used. |
Summary: |
inferred 1 Counter(s). |
inferred 1 D-type flip-flop(s). |
Unit <counter0> synthesized. |
|
|
Synthesizing Unit <counter>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <o>. |
Found 8-bit down counter for signal <cnt>. |
WARNING:Xst:647 - Input <reset> is never used. |
WARNING:Xst:647 - Input <ce> is never used. |
Summary: |
inferred 1 Counter(s). |
inferred 1 D-type flip-flop(s). |
Unit <counter> synthesized. |
|
|
Synthesizing Unit <uart>. |
Related source file is J:/impl/../rtl/vhdl/miniuart.vhd. |
WARNING:Xst:646 - Signal <sig0> is assigned but never used. |
WARNING:Xst:646 - Signal <sig1> is assigned but never used. |
Found 1-bit register for signal <loada>. |
Found 1-bit register for signal <reada>. |
Found 8-bit register for signal <txdata>. |
Summary: |
inferred 10 D-type flip-flop(s). |
Unit <uart> synthesized. |
|
========================================================================= |
HDL Synthesis Report |
|
Macro Statistics |
# Registers : 26 |
4-bit register : 2 |
2-bit register : 1 |
8-bit register : 4 |
1-bit register : 19 |
# Counters : 2 |
2-bit down counter : 1 |
8-bit down counter : 1 |
# Adders/Subtractors : 3 |
2-bit adder : 1 |
4-bit adder : 2 |
# Comparators : 1 |
4-bit comparator greatequal : 1 |
|
========================================================================= |
|
|
Starting low level synthesis... |
Optimizing unit <counter> ... |
|
Optimizing unit <rxunit> ... |
|
Optimizing unit <txunit> ... |
|
Optimizing unit <uart> ... |
|
Building and optimizing final netlist ... |
|
FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute. |
========================================================================= |
Final Results |
Top Level Output File Name : uart |
Output Format : NGC |
Optimization Criterion : Speed |
Target Technology : spartan2 |
Keep Hierarchy : No |
Macro Generator : macro+ |
|
Macro Statistics |
# Registers : 35 |
4-bit register : 2 |
8-bit register : 4 |
2-bit register : 2 |
1-bit register : 27 |
# Adders/Subtractors : 3 |
4-bit adder : 2 |
8-bit subtractor : 1 |
|
Design Statistics |
# IOs : 28 |
|
Cell Usage : |
# BELS : 153 |
# GND : 1 |
# LUT1 : 13 |
# LUT1_D : 2 |
# LUT1_L : 3 |
# LUT2 : 21 |
# LUT3 : 24 |
# LUT3_L : 2 |
# LUT4 : 51 |
# LUT4_D : 2 |
# LUT4_L : 2 |
# MUXCY : 13 |
# MUXF5 : 4 |
# VCC : 1 |
# XORCY : 14 |
# FlipFlops/Latches : 72 |
# FDC : 4 |
# FDCE : 10 |
# FDE : 40 |
# FDPE : 1 |
# FDR : 11 |
# FDRE : 2 |
# FDS : 2 |
# FDSE : 2 |
# Clock Buffers : 2 |
# BUFGP : 2 |
# IO Buffers : 26 |
# IBUF : 14 |
# OBUF : 12 |
========================================================================= |
|
|
========================================================================= |
TIMING REPORT |
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT |
GENERATED AFTER PLACE-and-ROUTE. |
|
Clock Information: |
------------------ |
-----------------------------------+------------------------+-------+ |
Clock Signal | Clock buffer(FF name) | Load | |
-----------------------------------+------------------------+-------+ |
uart_rxunit_rregl:Q | NONE | 3 | |
br_clk_i | BUFGP | 59 | |
loada:Q | NONE | 1 | |
wb_clk_i | BUFGP | 10 | |
-----------------------------------+------------------------+-------+ |
|
Timing Summary: |
--------------- |
Speed Grade: -6 |
|
Minimum period: 9.318ns (Maximum Frequency: 107.319MHz) |
Minimum input arrival time before clock: 8.430ns |
Maximum output required time after clock: 10.658ns |
Maximum combinational path delay: 9.098ns |
|
Timing Detail: |
-------------- |
All values displayed in nanoseconds (ns) |
|
------------------------------------------------------------------------- |
Timing constraint: Default period analysis for Clock 'br_clk_i' |
Delay: 9.318ns (Levels of Logic = 6) |
Source: uart_rxunit_bitpos_0 |
Destination: uart_rxunit_bitpos_2 |
Source Clock: br_clk_i rising |
Destination Clock: br_clk_i rising |
|
Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDCE:C->Q 22 1.085 2.970 uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0) |
LUT1_D:I0->LO 1 0.549 0.000 uart_rxunit_Madd__n0018_inst_lut2_0 (N3009) |
MUXCY:S->O 1 0.659 0.000 uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0) |
MUXCY:CI->O 1 0.042 0.000 uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1) |
XORCY:CI->O 1 0.420 1.035 uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181) |
LUT4:I3->O 1 0.549 1.035 uart_rxunit_I_10_LUT_53 (uart_rxunit_N183) |
LUT4_L:I0->LO 1 0.549 0.000 uart_rxunit_I__n0005_2 (uart_rxunit_N201) |
FDCE:D 0.425 uart_rxunit_bitpos_2 |
---------------------------------------- |
Total 9.318ns (4.278ns logic, 5.040ns route) |
(45.9% logic, 54.1% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i' |
Offset: 8.430ns (Levels of Logic = 3) |
Source: wb_rst_i |
Destination: uart_txunit_treg_5 |
Destination Clock: br_clk_i rising |
|
Data Path: wb_rst_i to uart_txunit_treg_5 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 19 0.776 2.790 wb_rst_i_IBUF (wb_rst_i_IBUF) |
LUT4:I3->O 1 0.549 1.035 uart_txunit_I_1_LUT_11 (N2973) |
LUT4:I3->O 8 0.549 1.845 uart_txunit_I__n0009 (uart_txunit_N83) |
FDE:CE 0.886 uart_txunit_treg_5 |
---------------------------------------- |
Total 8.430ns (2.760ns logic, 5.670ns route) |
(32.7% logic, 67.3% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i' |
Offset: 10.658ns (Levels of Logic = 3) |
Source: uart_txunit_tbufl |
Destination: wb_dat_o_0 |
Source Clock: br_clk_i rising |
|
Data Path: uart_txunit_tbufl to wb_dat_o_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDCE:C->Q 5 1.085 1.566 uart_txunit_tbufl (uart_txunit_tbufl) |
LUT2:I1->O 2 0.549 1.206 uart_txunit_I_busy (N64) |
LUT4:I2->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF) |
OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0) |
---------------------------------------- |
Total 10.658ns (6.851ns logic, 3.807ns route) |
(64.3% logic, 35.7% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default path analysis |
Delay: 9.098ns (Levels of Logic = 3) |
Source: wb_adr_i_1 |
Destination: wb_dat_o_0 |
|
Data Path: wb_adr_i_1 to wb_dat_o_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 0.776 2.070 wb_adr_i_1_IBUF (wb_adr_i_1_IBUF) |
LUT4:I0->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF) |
OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0) |
---------------------------------------- |
Total 9.098ns (5.993ns logic, 3.105ns route) |
(65.9% logic, 34.1% route) |
|
========================================================================= |
CPU : 9.22 / 9.67 s | Elapsed : 10.00 / 10.00 s |
|
--> |
/branches/avendor/impl/Xilinx_xc2s15/uart.xst
0,0 → 1,40
set -tmpdir . |
set -overwrite YES |
set -xsthdpdir ./xst |
run |
-ifmt VHDL |
-ent uart |
-p xc2s15-cs144-6 |
-ifn uart.prj |
-opt_mode Speed |
-opt_level 1 |
-check_attribute_syntax YES |
-keep_hierarchy No |
-glob_opt AllClockNets |
-write_timing_constraints No |
-fsm_extract YES -fsm_encoding Auto |
-fsm_fftype D |
-mux_extract YES |
-resource_sharing YES |
-complex_clken YES |
-rom_extract Yes |
-ram_extract Yes |
-ram_style Auto |
-mux_style Auto |
-decoder_extract YES |
-priority_extract YES |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-iobuf YES |
-equivalent_register_removal YES |
-bufg 4 |
-max_fanout 100 |
-register_duplication YES |
-register_balancing No |
-move_first_stage YES |
-move_last_stage YES |
-slice_packing YES |
-iob auto |
-ofn uart |
-ofmt NGC |
/branches/avendor/impl/Xilinx_xc2s15/_prepar.rsp
--- branches/avendor/impl/Xilinx_xc2s15/miniuart.jhd (nonexistent)
+++ branches/avendor/impl/Xilinx_xc2s15/miniuart.jhd (revision 22)
@@ -0,0 +1,4 @@
+MODULE uart
+ SUBMODULE counter
+ SUBMODULE rxunit
+ SUBMODULE txunit
/branches/avendor/impl/Xilinx_xc2s15/__projnav.log
0,0 → 1,617
ISE Auto-Make Log File |
----------------------- |
|
Updating: Analyze Post-Place & Route Static Timing (Timing Analyzer) |
|
Starting: 'exewrap -tapkeep -mode pipe -tcl -command e:/ise/data/projnav/_filesAllClean.tcl _XSTClean.rsp 0' |
|
|
Creating TCL Process |
Cleaning Up Project |
Finished cleaning up project |
Done: completed successfully. |
|
Starting: 'exewrap -mode pipe -tapkeep -command e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr' |
|
|
Starting: 'e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr ' |
|
|
Release 4.2i - xst E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
--> Parameter TMPDIR set to . |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> Parameter overwrite set to YES |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> Parameter xsthdpdir set to ./xst |
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s |
|
--> ========================================================================= |
---- Source Parameters |
Input Format : VHDL |
Input File Name : uart.prj |
|
---- Target Parameters |
Target Device : xc2s15-cs144-6 |
Output File Name : uart |
Output Format : NGC |
Target Technology : spartan2 |
|
---- Source Options |
Entity Name : uart |
Automatic FSM Extraction : YES |
FSM Encoding Algorithm : Auto |
FSM Flip-Flop Type : D |
Mux Extraction : YES |
Resource Sharing : YES |
Complex Clock Enable Extraction : YES |
ROM Extraction : Yes |
RAM Extraction : Yes |
RAM Style : Auto |
Mux Style : Auto |
Decoder Extraction : YES |
Priority Encoder Extraction : YES |
Shift Register Extraction : YES |
Logical Shifter Extraction : YES |
XOR Collapsing : YES |
Automatic Register Balancing : No |
|
---- Target Options |
Add IO Buffers : YES |
Equivalent register Removal : YES |
Add Generic Clock Buffer(BUFG) : 4 |
Global Maximum Fanout : 100 |
Register Duplication : YES |
Move First FlipFlop Stage : YES |
Move Last FlipFlop Stage : YES |
Slice Packing : YES |
Pack IO Registers into IOBs : auto |
Speed Grade : 6 |
|
---- General Options |
Optimization Criterion : Speed |
Optimization Effort : 1 |
Check Attribute Syntax : YES |
Keep Hierarchy : No |
Global Optimization : AllClockNets |
Write Timing Constraints : No |
|
========================================================================= |
|
Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work. |
Entity <synchroniser> (Architecture <behaviour>) compiled. |
Entity <counter> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work. |
Entity <txunit> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work. |
Entity <rxunit> (Architecture <behaviour>) compiled. |
Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work. |
Entity <uart> (Architecture <behaviour>) compiled. |
|
Analyzing Entity <uart> (Architecture <behaviour>). |
Entity <uart> analyzed. Unit <uart> generated. |
|
Analyzing generic Entity <counter> (Architecture <behaviour>). |
count = 130 |
Entity <counter> analyzed. Unit <counter> generated. |
|
Analyzing generic Entity <counter> (Architecture <behaviour>). |
count = 4 |
Entity <counter> analyzed. Unit <counter0> generated. |
|
Analyzing Entity <txunit> (Architecture <behaviour>). |
Entity <txunit> analyzed. Unit <txunit> generated. |
|
Analyzing Entity <rxunit> (Architecture <behaviour>). |
Entity <rxunit> analyzed. Unit <rxunit> generated. |
|
Analyzing Entity <synchroniser> (Architecture <behaviour>). |
Entity <synchroniser> analyzed. Unit <synchroniser> generated. |
|
|
Synthesizing Unit <synchroniser>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <c1a>. |
Found 1-bit register for signal <c1s>. |
Found 1-bit register for signal <r>. |
Summary: |
inferred 3 D-type flip-flop(s). |
Unit <synchroniser> synthesized. |
|
|
Synthesizing Unit <rxunit>. |
Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd. |
Found 1-bit register for signal <rxav>. |
Found 8-bit register for signal <datao>. |
Found 2-bit adder for signal <$n0002> created at line 91. |
Found 4-bit adder for signal <$n0018> created at line 85. |
Found 4-bit comparator greatequal for signal <$n0038> created at line 81. |
Found 4-bit register for signal <bitpos>. |
Found 8-bit register for signal <rreg>. |
Found 1-bit register for signal <rregl>. |
Found 2-bit register for signal <samplecnt>. |
Summary: |
inferred 24 D-type flip-flop(s). |
inferred 2 Adder/Subtracter(s). |
inferred 1 Comparator(s). |
Unit <rxunit> synthesized. |
|
|
Synthesizing Unit <txunit>. |
Related source file is J:/impl/../rtl/vhdl/Txunit.vhd. |
Found 1-bit register for signal <txd>. |
Found 4-bit adder for signal <$n0012> created at line 92. |
Found 4-bit register for signal <bitpos>. |
Found 8-bit register for signal <tbuff>. |
Found 1-bit register for signal <tbufl>. |
Found 8-bit register for signal <treg>. |
Summary: |
inferred 22 D-type flip-flop(s). |
inferred 1 Adder/Subtracter(s). |
Unit <txunit> synthesized. |
|
|
Synthesizing Unit <counter0>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <o>. |
Found 2-bit down counter for signal <cnt>. |
WARNING:Xst:647 - Input <reset> is never used. |
Summary: |
inferred 1 Counter(s). |
inferred 1 D-type flip-flop(s). |
Unit <counter0> synthesized. |
|
|
Synthesizing Unit <counter>. |
Related source file is J:/impl/../rtl/vhdl/utils.vhd. |
Found 1-bit register for signal <o>. |
Found 8-bit down counter for signal <cnt>. |
WARNING:Xst:647 - Input <reset> is never used. |
WARNING:Xst:647 - Input <ce> is never used. |
Summary: |
inferred 1 Counter(s). |
inferred 1 D-type flip-flop(s). |
Unit <counter> synthesized. |
|
|
Synthesizing Unit <uart>. |
Related source file is J:/impl/../rtl/vhdl/miniuart.vhd. |
WARNING:Xst:646 - Signal <sig0> is assigned but never used. |
WARNING:Xst:646 - Signal <sig1> is assigned but never used. |
Found 1-bit register for signal <loada>. |
Found 1-bit register for signal <reada>. |
Found 8-bit register for signal <txdata>. |
Summary: |
inferred 10 D-type flip-flop(s). |
Unit <uart> synthesized. |
|
========================================================================= |
HDL Synthesis Report |
|
Macro Statistics |
# Registers : 26 |
4-bit register : 2 |
2-bit register : 1 |
8-bit register : 4 |
1-bit register : 19 |
# Counters : 2 |
2-bit down counter : 1 |
8-bit down counter : 1 |
# Adders/Subtractors : 3 |
2-bit adder : 1 |
4-bit adder : 2 |
# Comparators : 1 |
4-bit comparator greatequal : 1 |
|
========================================================================= |
|
|
Starting low level synthesis... |
Optimizing unit <counter> ... |
|
Optimizing unit <rxunit> ... |
|
Optimizing unit <txunit> ... |
|
Optimizing unit <uart> ... |
|
Building and optimizing final netlist ... |
|
FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute. |
========================================================================= |
Final Results |
Top Level Output File Name : uart |
Output Format : NGC |
Optimization Criterion : Speed |
Target Technology : spartan2 |
Keep Hierarchy : No |
Macro Generator : macro+ |
|
Macro Statistics |
# Registers : 35 |
4-bit register : 2 |
8-bit register : 4 |
2-bit register : 2 |
1-bit register : 27 |
# Adders/Subtractors : 3 |
4-bit adder : 2 |
8-bit subtractor : 1 |
|
Design Statistics |
# IOs : 28 |
|
Cell Usage : |
# BELS : 153 |
# GND : 1 |
# LUT1 : 13 |
# LUT1_D : 2 |
# LUT1_L : 3 |
# LUT2 : 21 |
# LUT3 : 24 |
# LUT3_L : 2 |
# LUT4 : 51 |
# LUT4_D : 2 |
# LUT4_L : 2 |
# MUXCY : 13 |
# MUXF5 : 4 |
# VCC : 1 |
# XORCY : 14 |
# FlipFlops/Latches : 72 |
# FDC : 4 |
# FDCE : 10 |
# FDE : 40 |
# FDPE : 1 |
# FDR : 11 |
# FDRE : 2 |
# FDS : 2 |
# FDSE : 2 |
# Clock Buffers : 2 |
# BUFGP : 2 |
# IO Buffers : 26 |
# IBUF : 14 |
# OBUF : 12 |
========================================================================= |
|
|
========================================================================= |
TIMING REPORT |
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT |
GENERATED AFTER PLACE-and-ROUTE. |
|
Clock Information: |
------------------ |
-----------------------------------+------------------------+-------+ |
Clock Signal | Clock buffer(FF name) | Load | |
-----------------------------------+------------------------+-------+ |
uart_rxunit_rregl:Q | NONE | 3 | |
br_clk_i | BUFGP | 59 | |
loada:Q | NONE | 1 | |
wb_clk_i | BUFGP | 10 | |
-----------------------------------+------------------------+-------+ |
|
Timing Summary: |
--------------- |
Speed Grade: -6 |
|
Minimum period: 9.318ns (Maximum Frequency: 107.319MHz) |
Minimum input arrival time before clock: 8.430ns |
Maximum output required time after clock: 10.658ns |
Maximum combinational path delay: 9.098ns |
|
Timing Detail: |
-------------- |
All values displayed in nanoseconds (ns) |
|
------------------------------------------------------------------------- |
Timing constraint: Default period analysis for Clock 'br_clk_i' |
Delay: 9.318ns (Levels of Logic = 6) |
Source: uart_rxunit_bitpos_0 |
Destination: uart_rxunit_bitpos_2 |
Source Clock: br_clk_i rising |
Destination Clock: br_clk_i rising |
|
Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDCE:C->Q 22 1.085 2.970 uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0) |
LUT1_D:I0->LO 1 0.549 0.000 uart_rxunit_Madd__n0018_inst_lut2_0 (N3009) |
MUXCY:S->O 1 0.659 0.000 uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0) |
MUXCY:CI->O 1 0.042 0.000 uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1) |
XORCY:CI->O 1 0.420 1.035 uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181) |
LUT4:I3->O 1 0.549 1.035 uart_rxunit_I_10_LUT_53 (uart_rxunit_N183) |
LUT4_L:I0->LO 1 0.549 0.000 uart_rxunit_I__n0005_2 (uart_rxunit_N201) |
FDCE:D 0.425 uart_rxunit_bitpos_2 |
---------------------------------------- |
Total 9.318ns (4.278ns logic, 5.040ns route) |
(45.9% logic, 54.1% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i' |
Offset: 8.430ns (Levels of Logic = 3) |
Source: wb_rst_i |
Destination: uart_txunit_treg_5 |
Destination Clock: br_clk_i rising |
|
Data Path: wb_rst_i to uart_txunit_treg_5 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 19 0.776 2.790 wb_rst_i_IBUF (wb_rst_i_IBUF) |
LUT4:I3->O 1 0.549 1.035 uart_txunit_I_1_LUT_11 (N2973) |
LUT4:I3->O 8 0.549 1.845 uart_txunit_I__n0009 (uart_txunit_N83) |
FDE:CE 0.886 uart_txunit_treg_5 |
---------------------------------------- |
Total 8.430ns (2.760ns logic, 5.670ns route) |
(32.7% logic, 67.3% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i' |
Offset: 10.658ns (Levels of Logic = 3) |
Source: uart_txunit_tbufl |
Destination: wb_dat_o_0 |
Source Clock: br_clk_i rising |
|
Data Path: uart_txunit_tbufl to wb_dat_o_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDCE:C->Q 5 1.085 1.566 uart_txunit_tbufl (uart_txunit_tbufl) |
LUT2:I1->O 2 0.549 1.206 uart_txunit_I_busy (N64) |
LUT4:I2->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF) |
OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0) |
---------------------------------------- |
Total 10.658ns (6.851ns logic, 3.807ns route) |
(64.3% logic, 35.7% route) |
|
------------------------------------------------------------------------- |
Timing constraint: Default path analysis |
Delay: 9.098ns (Levels of Logic = 3) |
Source: wb_adr_i_1 |
Destination: wb_dat_o_0 |
|
Data Path: wb_adr_i_1 to wb_dat_o_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 0.776 2.070 wb_adr_i_1_IBUF (wb_adr_i_1_IBUF) |
LUT4:I0->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF) |
OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0) |
---------------------------------------- |
Total 9.098ns (5.993ns logic, 3.105ns route) |
(65.9% logic, 34.1% route) |
|
========================================================================= |
CPU : 9.22 / 9.67 s | Elapsed : 10.00 / 10.00 s |
|
--> |
EXEWRAP detected that program 'e:/ise/bin/nt/xst.exe' completed successfully. |
|
Done: completed successfully. |
|
Starting: 'exewrap @__ednTOngd_exewrap.rsp' |
|
|
Starting: 'ngdbuild -f __ngdbuild.rsp ' |
|
|
Release 4.2i - ngdbuild E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
|
Command Line: ngdbuild -dd j:/impl/_ngo -nt timestamp -p xc2s15-cs144-6 uart.ngc |
uart.ngd |
|
Reading NGO file "J:/impl/uart.ngc" ... |
Reading component libraries for design expansion... |
|
Checking timing specifications ... |
Checking expanded design ... |
|
NGDBUILD Design Results Summary: |
Number of errors: 0 |
Number of warnings: 0 |
|
Writing NGD file "uart.ngd" ... |
|
Writing NGDBUILD log file "uart.bld"... |
|
NGDBUILD done. |
EXEWRAP detected that program 'ngdbuild' completed successfully. |
|
Done: completed successfully. |
|
Starting: 'exewrap @_ngdTOnc1_exewrap.rsp' |
|
|
Creating TCL Process |
Starting: 'map -f _map.rsp' |
|
|
Release 4.2i - Map E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
Using target part "2s15cs144-6". |
Removing unused or disabled logic... |
Running cover... |
Writing file uart.ngm... |
Running directed packing... |
Running delay-based packing... |
Running related packing... |
Writing design file "uart.ncd"... |
|
Design Summary: |
Number of errors: 0 |
Number of warnings: 0 |
Number of Slices: 83 out of 192 43% |
Number of Slices containing |
unrelated logic: 0 out of 83 0% |
Number of Slice Flip Flops: 63 out of 384 16% |
Total Number 4 input LUTs: 115 out of 384 29% |
Number used as LUTs: 110 |
Number used as a route-thru: 5 |
Number of bonded IOBs: 26 out of 86 30% |
IOB Flip Flops: 9 |
Number of GCLKs: 2 out of 4 50% |
Number of GCLKIOBs: 2 out of 4 50% |
Total equivalent gate count for design: 1,329 |
Additional JTAG gate count for IOBs: 1,344 |
|
Mapping completed. |
See MAP report file "uart.mrp" for details. |
Tcl e:/ise/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully. |
|
Done: completed successfully. |
|
Starting: 'exewrap @_nc1TOncd_exewrap.rsp' |
|
|
Creating TCL Process |
Found _prepar.rsp |
Starting: 'par -f _par.rsp' |
|
|
Release 4.2i - Par E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
|
|
WARNING:Par:69 - Option "-xe" overrides some effects of "-ol". |
|
|
Constraints file: uart.pcf |
|
Loading design for application par from file par_temp.ncd. |
"uart" is an NCD, version 2.37, device xc2s15, package cs144, speed -6 |
Loading device for application par from file '2s15.nph' in environment e:/ise. |
Device speed data version: PRELIMINARY 1.23 2001-12-19. |
|
|
Resolving physical constraints. |
Finished resolving physical constraints. |
|
Device utilization summary: |
|
Number of External GCLKIOBs 2 out of 4 50% |
Number of External IOBs 26 out of 86 30% |
Number of LOCed External IOBs 0 out of 26 0% |
|
Number of SLICEs 83 out of 192 43% |
|
Number of GCLKs 2 out of 4 50% |
|
|
|
Overall effort level (-ol): 2 (set by user) |
Placer effort level (-pl): 2 (set by user) |
Placer cost table entry (-t): 1 |
Router effort level (-rl): 2 (set by user) |
Extra effort level (-xe): 0 (set by user) |
|
Starting initial Placement phase. REAL time: 0 secs |
Finished initial Placement phase. REAL time: 0 secs |
Starting the placer. REAL time: 0 secs |
Placement pass 1 .... |
Placer score = 7875 |
Placement pass 2 ............... |
Placer score = 7375 |
Optimizing ... |
Placer score = 6385 |
Placer score = 5890 |
Placer completed in real time: 0 secs |
|
Dumping design to file uart.ncd. |
|
Total REAL time to Placer completion: 0 secs |
Total CPU time to Placer completion: 1 secs |
|
0 connection(s) routed; 522 unrouted active, 4 unrouted PWR/GND. |
Starting router resource preassignment |
Completed router resource preassignment. REAL time: 0 secs |
Starting iterative routing. |
Routing active signals. |
..... |
End of iteration 1 |
526 successful; 0 unrouted; (0) REAL time: 0 secs |
Constraints are met. |
Total REAL time: 2 secs |
Total CPU time: 1 secs |
End of route. 526 routed (100.00%); 0 unrouted. |
No errors found. |
Completely routed. |
|
This design was run without timing constraints. It is likely that much better |
circuit performance can be obtained by trying either or both of the following: |
|
- Enabling the Delay Based Cleanup router pass, if not already enabled |
- Supplying timing constraints in the input design |
|
|
Total REAL time to Router completion: 2 secs |
Total CPU time to Router completion: 1 secs |
|
Generating PAR statistics. |
Dumping design to file uart.ncd. |
|
|
All signals are completely routed. |
|
Total REAL time to PAR completion: 4 secs |
Total CPU time to PAR completion: 1 secs |
|
Placement: Completed - No errors found. |
Routing: Completed - No errors found. |
|
PAR done. |
Tcl e:/ise/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully. |
|
PAR completed successfully |
Done: completed successfully. |
|
Launching: 'exewrap -tcl -command __launchTA.tcl' |
|
|
|
ISE Auto-Make Log File |
----------------------- |
|
Starting: 'jhdparse @Rxunit.jp' |
|
|
JHDPARSE - VHDL/Verilog Parser. |
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved. |
|
Scanning j:/rtl/vhdl/Rxunit.vhd |
Scanning j:/rtl/vhdl/Rxunit.vhd |
Writing Rxunit.jhd. |
|
JHDPARSE complete - 0 errors, 0 warnings. |
|
Done: completed successfully. |
|
Starting: 'jhdparse @Txunit.jp' |
|
|
|
Starting: 'jhdparse @utils.jp' |
|
|
JHDPARSE - VHDL/Verilog Parser. |
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved. |
|
Scanning j:/rtl/vhdl/utils.vhd |
Scanning j:/rtl/vhdl/utils.vhd |
j:/rtl/vhdl/utils.vhd(47) library IEEE,STD; |
^ |
Warning 0008: Unable to open library std. |
Writing utils.jhd. |
|
JHDPARSE complete - 0 errors, 1 warning. |
|
Done: completed successfully. |
|
Starting: 'jhdparse @miniuart.jp' |
|
|
|
/branches/avendor/impl/Xilinx_xc2s15/uart.dly
0,0 → 1,1079
Release 4.2i - Par E.35 |
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. |
|
Thu Jan 09 18:11:10 2003 |
|
File: uart.dly |
|
The 20 Worst Net Delays are: |
------------------------------- |
| Max Delay (ns) | Netname | |
------------------------------- |
2.509 wb_rst_i_IBUF |
2.150 N146 |
2.092 wb_ack_o_OBUF |
2.046 uart_rxrate_O |
1.984 wb_adr_i_1_IBUF |
1.919 uart_rxunit_bitpos<0> |
1.848 uart_txrate_o |
1.843 uart_rxunit_samplecnt<1> |
1.841 uart_rxunit_samplecnt<0> |
1.798 uart_rxunit_bitpos<1> |
1.747 wb_adr_i_0_IBUF |
1.730 uart_rxunit_bitpos<2> |
1.604 uart_rxunit_N76 |
1.546 uart_txunit_bitpos<2> |
1.537 uart_rxunit_rregl |
1.525 uart_rxunit_bitpos<3> |
1.519 uart_rxunit_N181 |
1.498 uart_txunit_bitpos<1> |
1.488 uart_rxunit_N270 |
1.445 uart_txunit_tbufl |
--------------------------------- |
|
------------------------------------------------------------------------------- |
Net Delays |
------------------------------------------------------------------------------- |
|
GLOBAL_LOGIC0 |
uart_txunit_treg<5>.X |
0.365 uart_txunit_N135.G1 |
|
GLOBAL_LOGIC0_0 |
uart_rxunit_rregl.X |
0.525 uart_rxunit_N202.G1 |
|
GLOBAL_LOGIC1 |
loada.Y |
0.844 uart_txunit_N135.F1 |
|
GLOBAL_LOGIC1_0 |
uart_rxunit_rxav.Y |
0.788 uart_rxunit_N202.F1 |
|
N122 |
N122.X |
0.584 uart_txrate_cnt<0>.SR |
|
N126 |
N122.Y |
0.591 uart_txrate_o.SR |
|
N131 |
N131.X |
0.186 N131.G4 |
|
N137 |
N131.Y |
1.277 loada.SR |
|
N144 |
N144.X |
0.186 N144.G4 |
|
N146 |
N144.Y |
1.852 wb_dat_i<0>.ICE |
1.852 wb_dat_i<1>.ICE |
1.962 wb_dat_i<2>.ICE |
1.934 wb_dat_i<3>.ICE |
1.665 wb_dat_i<4>.ICE |
1.665 wb_dat_i<5>.ICE |
2.150 wb_dat_i<6>.ICE |
2.111 wb_dat_i<7>.ICE |
|
N155 |
N155.X |
0.186 N155.G4 |
|
N157 |
N155.Y |
0.743 reada.SR |
|
N2922 |
uart_txunit_N91.Y |
0.323 uart_txunit_bitpos<1>.G2 |
|
N2940 |
N2940.X |
0.365 uart_rxunit_rreg<3>.G1 |
|
N2947 |
N2964.Y |
0.346 uart_rxunit_rreg<7>.G4 |
|
N2952 |
uart_rxunit_bitpos<3>.X |
0.186 uart_rxunit_bitpos<3>.G4 |
|
N2955 |
uart_rxunit_bitpos<1>.X |
0.186 uart_rxunit_bitpos<1>.G4 |
|
N2958 |
N2958.X |
0.186 N2958.G4 |
|
N2961 |
uart_rxunit_N332.Y |
0.774 uart_rxunit_rreg<2>.F3 |
|
N2964 |
N2964.X |
0.331 uart_rxunit_rreg<7>.F3 |
|
N2973 |
N2973.X |
0.186 N2973.G4 |
|
N64 |
N64.X |
1.074 inttx_o.O |
0.634 N64.G3 |
|
br_clk_i_BUFGP |
br_clk_i_BUFGP/BUFG.OUT |
0.318 uart_rxunit_datao_1.CLK |
0.318 uart_rxunit_datao_3.CLK |
0.313 uart_rxunit_datao_5.CLK |
0.314 uart_rxunit_datao_7.CLK |
0.335 uart_txunit_treg<1>.CLK |
0.313 uart_txunit_treg<3>.CLK |
0.314 uart_txunit_treg<5>.CLK |
0.316 uart_txunit_treg<7>.CLK |
0.314 uart_txunit_bitpos<0>.CLK |
0.336 uart_txunit_bitpos<1>.CLK |
0.315 uart_rxrate_cnt_0_0.CLK |
0.315 uart_rxrate_cnt_0_2.CLK |
0.391 uart_rxrate_cnt_0_4.CLK |
0.391 uart_rxrate_cnt_0_6.CLK |
0.316 uart_rxunit_bitpos<2>.CLK |
0.316 uart_txunit_bitpos<3>.CLK |
0.412 uart_rxunit_rreg<5>.CLK |
0.391 uart_rxunit_rreg<7>.CLK |
0.333 uart_rxunit_bitpos<1>.CLK |
0.335 uart_rxunit_bitpos<3>.CLK |
0.335 uart_rxunit_rregl.CLK |
0.412 uart_rxunit_samplecnt<1>.CLK |
0.315 uart_txunit_tbufl.CLK |
0.334 uart_txunit_txd.CLK |
0.318 uart_rxunit_rreg<0>.CLK |
0.318 uart_rxunit_rreg<1>.CLK |
0.412 uart_rxunit_rreg<2>.CLK |
0.314 uart_rxunit_rreg<3>.CLK |
0.336 uart_rxunit_rreg<4>.CLK |
0.314 uart_txunit_syncload_c1s.CLK |
0.333 uart_txrate_o.CLK |
0.335 uart_txunit_bitpos<2>.CLK |
0.314 uart_rxrate_O.CLK |
0.335 uart_rxunit_bitpos<0>.CLK |
0.335 uart_txrate_cnt<0>.CLK |
0.313 uart_txunit_syncload_r.CLK |
0.335 uart_txunit_tbuff<1>.CLK |
0.314 uart_txunit_tbuff<3>.CLK |
0.335 uart_txunit_tbuff<5>.CLK |
0.316 uart_txunit_tbuff<7>.CLK |
|
br_clk_i_BUFGP/IBUFG |
br_clk_i.GCLKOUT |
0.006 br_clk_i_BUFGP/BUFG.IN |
|
loada |
loada.YQ |
0.795 uart_txunit_syncload_c1a.CLK |
|
reada |
reada.YQ |
0.697 uart_rxunit_N176.F4 |
|
rxd_pad_i_IBUF |
rxd_pad_i.I |
1.090 uart_rxunit_N282.G2 |
1.015 uart_rxunit_bitpos<2>.F4 |
1.317 uart_rxunit_I_20_LUT_8_SW0/O.G2 |
1.168 uart_rxunit_samplecnt<1>.F1 |
1.328 uart_rxunit_samplecnt<1>.G2 |
1.396 uart_rxunit_rreg<3>.F1 |
1.176 uart_rxunit_N332.F3 |
1.156 uart_rxunit_N332.G2 |
|
txdata<0> |
wb_dat_i<0>.IQ |
0.848 uart_txunit_tbuff<1>.BY |
|
txdata<1> |
wb_dat_i<1>.IQ |
0.914 uart_txunit_tbuff<1>.BX |
|
txdata<2> |
wb_dat_i<2>.IQ |
0.594 uart_txunit_tbuff<3>.BY |
|
txdata<3> |
wb_dat_i<3>.IQ |
0.545 uart_txunit_tbuff<3>.BX |
|
txdata<4> |
wb_dat_i<4>.IQ |
0.814 uart_txunit_tbuff<5>.BY |
|
txdata<5> |
wb_dat_i<5>.IQ |
0.730 uart_txunit_tbuff<5>.BX |
|
txdata<6> |
wb_dat_i<6>.IQ |
0.844 uart_txunit_tbuff<7>.BY |
|
txdata<7> |
wb_dat_i<7>.IQ |
1.071 uart_txunit_tbuff<7>.BX |
|
uart_rxrate_N26 |
uart_rxrate_N26.Y |
0.584 uart_rxrate_O.SR |
|
uart_rxrate_N37 |
uart_rxrate_N37.Y |
0.779 uart_rxrate_N47.G2 |
0.795 uart_rxrate_N26.G3 |
|
uart_rxrate_N47 |
uart_rxrate_N47.X |
0.186 uart_rxrate_N47.G4 |
0.483 uart_rxrate_N26.G2 |
|
uart_rxrate_N49 |
uart_rxrate_N47.Y |
0.726 uart_rxrate_cnt_0_0.SR |
0.681 uart_rxrate_cnt_0_2.SR |
0.609 uart_rxrate_cnt_0_4.SR |
0.591 uart_rxrate_cnt_0_6.SR |
|
uart_rxrate_O |
uart_rxrate_O.YQ |
1.786 N122.F2 |
1.998 N122.G1 |
1.944 uart_rxunit_N176.G4 |
1.168 uart_rxunit_bitpos<2>.CE |
1.731 uart_rxunit_N111.G3 |
2.046 uart_rxunit_bitpos<1>.CE |
1.344 uart_rxunit_bitpos<3>.CE |
1.842 uart_rxunit_rregl.CE |
1.189 uart_rxunit_N328.F1 |
1.344 uart_rxunit_bitpos<0>.CE |
2.016 uart_txrate_cnt<0>.CE |
|
uart_rxrate_cnt_0_0 |
uart_rxrate_cnt_0_0.XQ |
0.950 uart_rxrate_cnt_0_0.F1 |
0.933 uart_rxrate_N37.G2 |
|
uart_rxrate_cnt_0_1 |
uart_rxrate_cnt_0_0.YQ |
0.934 uart_rxrate_cnt_0_0.G1 |
0.955 uart_rxrate_N37.G1 |
|
uart_rxrate_cnt_0_2 |
uart_rxrate_cnt_0_2.XQ |
0.950 uart_rxrate_cnt_0_2.F1 |
0.788 uart_rxrate_N37.G3 |
|
uart_rxrate_cnt_0_3 |
uart_rxrate_cnt_0_2.YQ |
0.934 uart_rxrate_cnt_0_2.G1 |
0.773 uart_rxrate_N37.G4 |
|
uart_rxrate_cnt_0_4 |
uart_rxrate_cnt_0_4.XQ |
0.951 uart_rxrate_cnt_0_4.F1 |
0.880 uart_rxrate_N47.F2 |
|
uart_rxrate_cnt_0_5 |
uart_rxrate_cnt_0_4.YQ |
0.957 uart_rxrate_cnt_0_4.G1 |
0.764 uart_rxrate_N47.F3 |
|
uart_rxrate_cnt_0_6 |
uart_rxrate_cnt_0_6.XQ |
0.950 uart_rxrate_cnt_0_6.F1 |
0.982 uart_rxrate_N47.F1 |
|
uart_rxrate_cnt_0_7 |
uart_rxrate_cnt_0_6.YQ |
0.952 uart_rxrate_cnt_0_6.G1 |
0.722 uart_rxrate_N47.F4 |
|
uart_rxrate_cnt_Msub__n0000_inst_cy_5 |
uart_rxrate_cnt_0_0.COUT |
0.000 uart_rxrate_cnt_0_2.CIN |
|
uart_rxrate_cnt_Msub__n0000_inst_cy_7 |
uart_rxrate_cnt_0_2.COUT |
0.000 uart_rxrate_cnt_0_4.CIN |
|
uart_rxrate_cnt_Msub__n0000_inst_cy_9 |
uart_rxrate_cnt_0_4.COUT |
0.000 uart_rxrate_cnt_0_6.CIN |
|
uart_rxunit_I_20_LUT_8_SW0/O |
uart_rxunit_I_20_LUT_8_SW0/O.X |
0.186 uart_rxunit_I_20_LUT_8_SW0/O.G4 |
|
uart_rxunit_Madd__n0018_inst_cy_1 |
uart_rxunit_N202.COUT |
0.000 uart_rxunit_N181.CIN |
|
uart_rxunit_N102 |
uart_rxunit_rreg<3>.X |
0.963 uart_rxunit_rreg<7>.F1 |
0.810 uart_rxunit_rreg<7>.G3 |
0.624 uart_rxunit_rreg<0>.G3 |
0.810 uart_rxunit_rreg<1>.G1 |
0.186 uart_rxunit_rreg<3>.G4 |
|
uart_rxunit_N111 |
uart_rxunit_N111.X |
0.743 uart_rxunit_N195.G2 |
0.186 uart_rxunit_N111.G4 |
0.525 uart_rxunit_rregl.G1 |
|
uart_rxunit_N115 |
uart_rxunit_N111.Y |
1.011 uart_rxunit_datao_1.CE |
1.011 uart_rxunit_datao_3.CE |
1.067 uart_rxunit_datao_5.CE |
0.938 uart_rxunit_datao_7.CE |
|
uart_rxunit_N125 |
uart_rxunit_N166.Y |
0.884 uart_rxunit_bitpos<3>.G2 |
|
uart_rxunit_N130 |
uart_rxunit_N224.Y |
1.250 uart_rxunit_bitpos<3>.G3 |
|
uart_rxunit_N134 |
uart_rxunit_N181.Y |
0.525 uart_rxunit_bitpos<3>.G1 |
|
uart_rxunit_N144 |
uart_rxunit_N252.Y |
0.310 uart_rxunit_bitpos<3>.F4 |
|
uart_rxunit_N148 |
uart_rxunit_N148.X |
0.785 uart_rxunit_bitpos<3>.F3 |
|
uart_rxunit_N157 |
N2940.Y |
0.791 uart_rxunit_rreg<0>.G1 |
|
uart_rxunit_N166 |
uart_rxunit_N166.X |
1.167 uart_rxunit_rreg<5>.F4 |
1.246 uart_rxunit_rreg<0>.F1 |
0.917 uart_rxunit_rreg<1>.F4 |
1.093 uart_rxunit_rreg<4>.F3 |
|
uart_rxunit_N170 |
uart_rxunit_rreg<0>.X |
0.186 uart_rxunit_rreg<0>.G4 |
|
uart_rxunit_N176 |
uart_rxunit_N176.X |
0.809 intrx_o.SR |
0.780 uart_rxunit_rxav.SR |
|
uart_rxunit_N181 |
uart_rxunit_N181.X |
1.519 uart_rxunit_N328.G2 |
|
uart_rxunit_N183 |
uart_rxunit_N328.Y |
0.813 uart_rxunit_bitpos<2>.G1 |
|
uart_rxunit_N189 |
uart_rxunit_N148.Y |
0.323 uart_rxunit_bitpos<2>.G2 |
0.738 uart_rxunit_I_20_LUT_8_SW0/O.F2 |
|
uart_rxunit_N195 |
uart_rxunit_N195.X |
1.255 uart_rxunit_bitpos<2>.G3 |
0.186 uart_rxunit_N195.G4 |
1.195 uart_rxunit_I_20_LUT_8_SW0/O.G1 |
0.854 uart_rxunit_rregl.G2 |
1.154 uart_rxunit_samplecnt<1>.F3 |
1.293 uart_rxunit_samplecnt<1>.G1 |
0.970 uart_rxunit_N332.F4 |
|
uart_rxunit_N199 |
uart_rxunit_bitpos<2>.X |
0.186 uart_rxunit_bitpos<2>.G4 |
|
uart_rxunit_N202 |
uart_rxunit_N202.Y |
0.905 uart_rxunit_bitpos<1>.G2 |
|
uart_rxunit_N208 |
uart_rxunit_N91.Y |
0.307 uart_rxunit_bitpos<1>.F4 |
|
uart_rxunit_N212 |
uart_rxunit_bitpos<0>.Y |
1.172 uart_rxunit_bitpos<1>.F1 |
|
uart_rxunit_N219 |
uart_rxunit_N219.X |
0.795 uart_rxunit_bitpos<1>.G3 |
|
uart_rxunit_N224 |
uart_rxunit_N224.X |
0.365 uart_rxunit_bitpos<1>.G1 |
|
uart_rxunit_N234 |
uart_rxunit_N195.Y |
0.604 uart_rxunit_bitpos<0>.F3 |
|
uart_rxunit_N245 |
uart_rxunit_I_20_LUT_8_SW0/O.Y |
1.041 uart_rxunit_bitpos<0>.F4 |
|
uart_rxunit_N252 |
uart_rxunit_N252.X |
0.776 uart_rxunit_rreg<1>.G3 |
|
uart_rxunit_N260 |
uart_rxunit_rreg<1>.X |
0.186 uart_rxunit_rreg<1>.G4 |
|
uart_rxunit_N270 |
uart_rxunit_N219.Y |
1.488 uart_rxunit_rreg<3>.G2 |
|
uart_rxunit_N275 |
N2958.Y |
0.323 uart_rxunit_rreg<2>.G2 |
|
uart_rxunit_N282 |
uart_rxunit_N282.X |
1.123 uart_rxunit_rreg<5>.G2 |
1.116 uart_rxunit_rreg<4>.G2 |
|
uart_rxunit_N284 |
uart_rxunit_rreg<2>.X |
0.186 uart_rxunit_rreg<2>.G4 |
|
uart_rxunit_N309 |
uart_rxunit_rreg<4>.X |
0.186 uart_rxunit_rreg<4>.G4 |
|
uart_rxunit_N322 |
uart_rxunit_rreg<5>.X |
0.186 uart_rxunit_rreg<5>.G4 |
|
uart_rxunit_N328 |
uart_rxunit_N328.X |
0.546 uart_rxunit_N332.F1 |
|
uart_rxunit_N332 |
uart_rxunit_N332.X |
0.584 uart_rxunit_samplecnt<1>.SR |
|
uart_rxunit_N76 |
uart_rxunit_N176.Y |
1.017 uart_rxunit_rreg<5>.CE |
1.604 uart_rxunit_rreg<7>.CE |
1.186 uart_rxunit_samplecnt<1>.CE |
1.362 uart_rxunit_rreg<0>.CE |
1.362 uart_rxunit_rreg<1>.CE |
1.161 uart_rxunit_rreg<2>.CE |
1.361 uart_rxunit_rreg<3>.CE |
1.053 uart_rxunit_rreg<4>.CE |
|
uart_rxunit_N91 |
uart_rxunit_N91.X |
0.929 uart_rxunit_rreg<7>.F4 |
1.166 uart_rxunit_rreg<7>.G1 |
|
uart_rxunit_bitpos<0> |
uart_rxunit_bitpos<0>.XQ |
1.771 uart_rxunit_N148.G1 |
1.871 N2940.F1 |
1.151 N2940.G3 |
1.557 uart_rxunit_N202.F3 |
1.467 uart_rxunit_N195.F3 |
1.703 uart_rxunit_I_20_LUT_8_SW0/O.G3 |
1.855 uart_rxunit_N111.F1 |
1.710 uart_rxunit_rreg<5>.F2 |
1.151 uart_rxunit_rreg<5>.G1 |
1.919 uart_rxunit_rreg<0>.F2 |
1.646 uart_rxunit_rreg<1>.F3 |
1.637 uart_rxunit_rreg<2>.F1 |
1.128 uart_rxunit_rreg<4>.F1 |
1.135 uart_rxunit_rreg<4>.G3 |
1.163 N2958.G1 |
1.633 uart_rxunit_bitpos<0>.F1 |
0.996 uart_rxunit_bitpos<0>.G3 |
1.639 uart_rxunit_N252.F1 |
1.117 uart_rxunit_N252.G2 |
1.495 uart_rxunit_N224.F4 |
1.268 uart_rxunit_N224.G1 |
0.682 N2964.F3 |
0.709 N2964.G3 |
|
uart_rxunit_bitpos<1> |
uart_rxunit_bitpos<1>.YQ |
1.396 uart_rxunit_N219.F2 |
1.399 uart_rxunit_N148.F3 |
1.743 uart_rxunit_N148.G2 |
1.715 N2940.F2 |
1.712 N2940.G1 |
1.169 uart_rxunit_N202.G3 |
1.563 uart_rxunit_N195.F1 |
1.151 uart_rxunit_N111.F3 |
1.798 uart_rxunit_rreg<5>.G3 |
1.150 uart_rxunit_bitpos<1>.F2 |
1.634 uart_rxunit_rreg<2>.F2 |
1.666 uart_rxunit_rreg<4>.G1 |
1.589 N2958.F2 |
1.762 uart_rxunit_N166.F2 |
1.375 uart_rxunit_N252.F4 |
1.606 uart_rxunit_N252.G4 |
1.001 uart_rxunit_N224.G4 |
1.794 N2964.F1 |
1.670 N2964.G2 |
|
uart_rxunit_bitpos<2> |
uart_rxunit_bitpos<2>.YQ |
1.096 uart_rxunit_N148.G4 |
1.254 N2940.F3 |
1.324 N2940.G4 |
1.437 uart_rxunit_N282.G1 |
1.730 uart_rxunit_N181.F1 |
0.903 uart_rxunit_bitpos<2>.F3 |
1.548 uart_rxunit_N195.F4 |
1.652 uart_rxunit_N111.F2 |
1.707 uart_rxunit_rreg<5>.F1 |
1.495 uart_rxunit_rreg<0>.F3 |
1.714 uart_rxunit_rreg<1>.F1 |
1.437 uart_rxunit_rreg<4>.F4 |
0.804 N2958.G3 |
1.097 uart_rxunit_N328.G1 |
1.435 uart_rxunit_bitpos<0>.G1 |
1.160 uart_rxunit_N252.F3 |
1.420 uart_rxunit_N252.G1 |
1.310 uart_rxunit_N332.G3 |
1.567 uart_rxunit_N224.F2 |
1.448 uart_rxunit_N224.G3 |
1.293 N2964.F2 |
1.359 N2964.G1 |
|
uart_rxunit_bitpos<3> |
uart_rxunit_bitpos<3>.YQ |
1.189 uart_rxunit_N148.F4 |
1.487 uart_rxunit_N148.G3 |
1.175 N2940.F4 |
1.525 N2940.G2 |
1.200 uart_rxunit_N282.G4 |
0.728 uart_rxunit_N181.G3 |
1.204 uart_rxunit_N195.F2 |
1.353 uart_rxunit_N111.F4 |
1.115 uart_rxunit_bitpos<1>.F3 |
1.511 N2958.F1 |
1.354 uart_rxunit_N166.F3 |
1.365 uart_rxunit_N166.G1 |
1.371 uart_rxunit_N252.F2 |
1.295 uart_rxunit_N252.G3 |
1.421 uart_rxunit_N332.G4 |
1.349 uart_rxunit_N224.F1 |
1.041 N2964.F4 |
1.106 N2964.G4 |
|
uart_rxunit_datao_0 |
uart_rxunit_datao_1.YQ |
1.262 N64.G2 |
|
uart_rxunit_datao_1 |
uart_rxunit_datao_1.XQ |
0.958 wb_dat_o_1_OBUF.F1 |
|
uart_rxunit_datao_2 |
uart_rxunit_datao_3.YQ |
0.660 wb_dat_o_2_OBUF.F1 |
|
uart_rxunit_datao_3 |
uart_rxunit_datao_3.XQ |
0.448 wb_dat_o_3_OBUF.F3 |
|
uart_rxunit_datao_4 |
uart_rxunit_datao_5.YQ |
0.866 wb_dat_o_4_OBUF.G2 |
|
uart_rxunit_datao_5 |
uart_rxunit_datao_5.XQ |
0.876 wb_dat_o_3_OBUF.G2 |
|
uart_rxunit_datao_6 |
uart_rxunit_datao_7.YQ |
0.848 wb_dat_o_2_OBUF.G4 |
|
uart_rxunit_datao_7 |
uart_rxunit_datao_7.XQ |
0.739 wb_dat_o_1_OBUF.G3 |
|
uart_rxunit_rreg<0> |
uart_rxunit_rreg<0>.YQ |
0.717 uart_rxunit_datao_1.BY |
0.895 uart_rxunit_rreg<0>.G2 |
|
uart_rxunit_rreg<1> |
uart_rxunit_rreg<1>.YQ |
0.737 uart_rxunit_datao_1.BX |
0.897 uart_rxunit_rreg<1>.G2 |
|
uart_rxunit_rreg<2> |
uart_rxunit_rreg<2>.YQ |
1.281 uart_rxunit_datao_3.BY |
0.904 N2958.G2 |
|
uart_rxunit_rreg<3> |
uart_rxunit_rreg<3>.YQ |
1.045 uart_rxunit_datao_3.BX |
0.887 uart_rxunit_rreg<3>.G3 |
|
uart_rxunit_rreg<4> |
uart_rxunit_rreg<4>.YQ |
1.064 uart_rxunit_datao_5.BY |
0.919 uart_rxunit_rreg<4>.F2 |
|
uart_rxunit_rreg<5> |
uart_rxunit_rreg<5>.YQ |
1.191 uart_rxunit_datao_5.BX |
0.761 uart_rxunit_rreg<5>.F3 |
|
uart_rxunit_rreg<6> |
uart_rxunit_rreg<7>.YQ |
0.879 uart_rxunit_datao_7.BY |
0.927 uart_rxunit_rreg<7>.G2 |
|
uart_rxunit_rreg<7> |
uart_rxunit_rreg<7>.XQ |
0.753 uart_rxunit_datao_7.BX |
0.872 uart_rxunit_rreg<7>.F2 |
|
uart_rxunit_rregl |
uart_rxunit_rregl.YQ |
1.537 intrx_o.CLK |
0.780 uart_rxunit_rregl.G3 |
0.937 uart_rxunit_rxav.CLK |
|
uart_rxunit_rxav |
uart_rxunit_rxav.YQ |
1.321 wb_dat_o_1_OBUF.F3 |
|
uart_rxunit_samplecnt<0> |
uart_rxunit_samplecnt<1>.YQ |
1.311 uart_rxunit_N219.F4 |
1.315 uart_rxunit_N219.G3 |
1.330 uart_rxunit_N282.G3 |
1.452 uart_rxunit_N195.G3 |
1.163 uart_rxunit_I_20_LUT_8_SW0/O.F3 |
1.461 uart_rxunit_bitpos<3>.F1 |
1.293 uart_rxunit_samplecnt<1>.F2 |
1.189 uart_rxunit_samplecnt<1>.G3 |
1.110 uart_rxunit_rreg<2>.F4 |
1.555 uart_rxunit_rreg<3>.F2 |
1.139 N2958.F4 |
0.782 uart_rxunit_N328.F3 |
0.809 uart_rxunit_N328.G3 |
1.841 uart_rxunit_N166.F1 |
1.810 uart_rxunit_N166.G3 |
1.663 uart_rxunit_N91.F1 |
1.425 uart_rxunit_N91.G4 |
|
uart_rxunit_samplecnt<1> |
uart_rxunit_samplecnt<1>.XQ |
1.344 uart_rxunit_N219.F1 |
1.273 uart_rxunit_N219.G4 |
1.522 uart_rxunit_N282.BX |
1.579 uart_rxunit_N195.G1 |
1.057 uart_rxunit_I_20_LUT_8_SW0/O.F1 |
1.619 uart_rxunit_bitpos<3>.F2 |
1.240 uart_rxunit_samplecnt<1>.F4 |
1.385 uart_rxunit_rreg<3>.F3 |
1.022 N2958.F3 |
0.821 uart_rxunit_N328.F4 |
0.860 uart_rxunit_N328.G4 |
1.403 uart_rxunit_N166.F4 |
1.843 uart_rxunit_N166.G4 |
1.732 uart_rxunit_N91.F2 |
1.710 uart_rxunit_N91.G3 |
1.308 uart_rxunit_N332.G1 |
|
uart_txrate_cnt<0> |
uart_txrate_cnt<0>.XQ |
0.805 N122.F3 |
0.987 N122.G2 |
0.809 uart_txrate_cnt<0>.BX |
1.015 uart_txrate_cnt<0>.G1 |
|
uart_txrate_cnt<1> |
uart_txrate_cnt<0>.YQ |
0.772 N122.F4 |
0.844 N122.G3 |
0.817 uart_txrate_cnt<0>.G3 |
|
uart_txrate_o |
uart_txrate_o.YQ |
1.848 uart_txunit_bitpos<0>.CE |
1.191 uart_txunit_bitpos<1>.CE |
1.376 uart_txunit_bitpos<3>.CE |
1.426 uart_txunit_tbufl.G3 |
1.207 uart_txunit_txd.CE |
1.206 N2973.G2 |
1.453 uart_txunit_N196.G3 |
1.516 uart_txunit_bitpos<2>.CE |
|
uart_txunit_Madd__n0012_inst_cy_1 |
uart_txunit_N135.COUT |
0.000 uart_txunit_N127.CIN |
|
uart_txunit_N107 |
uart_txunit_N99.Y |
1.010 uart_txunit_txd.F2 |
|
uart_txunit_N109 |
uart_txunit_txd.X |
0.186 uart_txunit_txd.G4 |
|
uart_txunit_N124 |
uart_txunit_N124.X |
0.749 uart_txunit_txd.G2 |
|
uart_txunit_N127 |
uart_txunit_N127.X |
0.546 uart_txunit_bitpos<1>.F1 |
0.383 uart_txunit_bitpos<3>.F1 |
1.024 uart_txunit_N145.G1 |
0.812 uart_txunit_bitpos<2>.F3 |
0.872 uart_txunit_bitpos<2>.G4 |
|
uart_txunit_N135 |
uart_txunit_N135.Y |
0.729 uart_txunit_bitpos<1>.F4 |
0.606 uart_txunit_bitpos<3>.F4 |
0.958 uart_txunit_N145.G3 |
0.361 uart_txunit_bitpos<2>.G3 |
|
uart_txunit_N137 |
uart_txunit_bitpos<2>.Y |
0.610 uart_txunit_bitpos<1>.G4 |
|
uart_txunit_N143 |
uart_txunit_N127.Y |
0.508 uart_txunit_bitpos<1>.F2 |
0.304 uart_txunit_bitpos<3>.F2 |
0.881 uart_txunit_N145.G2 |
|
uart_txunit_N145 |
uart_txunit_N145.Y |
1.205 uart_txunit_bitpos<1>.G1 |
|
uart_txunit_N184 |
uart_txunit_bitpos<3>.X |
0.186 uart_txunit_bitpos<3>.G4 |
|
uart_txunit_N196 |
uart_txunit_N196.X |
0.364 uart_txunit_tbufl.G1 |
0.185 uart_txunit_N196.G4 |
|
uart_txunit_N201 |
uart_txunit_N196.Y |
0.581 uart_txunit_tbufl.CE |
|
uart_txunit_N66 |
uart_txunit_N66.Y |
0.733 uart_txunit_tbuff<1>.CE |
0.712 uart_txunit_tbuff<3>.CE |
0.616 uart_txunit_tbuff<5>.CE |
1.058 uart_txunit_tbuff<7>.CE |
|
uart_txunit_N83 |
N2973.Y |
0.749 uart_txunit_treg<1>.CE |
1.300 uart_txunit_treg<3>.CE |
0.878 uart_txunit_treg<5>.CE |
0.930 uart_txunit_treg<7>.CE |
|
uart_txunit_N91 |
uart_txunit_N91.X |
0.738 uart_txunit_txd.F3 |
|
uart_txunit_N99 |
uart_txunit_N99.X |
0.952 uart_txunit_txd.F4 |
|
uart_txunit_bitpos<0> |
uart_txunit_bitpos<0>.XQ |
0.948 uart_txunit_N99.F3 |
1.184 uart_txunit_N99.G2 |
0.911 uart_txunit_bitpos<0>.F3 |
1.271 uart_txunit_bitpos<0>.G2 |
1.392 uart_txunit_bitpos<1>.F3 |
1.281 uart_txunit_bitpos<1>.G3 |
1.420 uart_txunit_N124.BX |
0.894 uart_txunit_N135.F2 |
1.182 uart_txunit_bitpos<3>.F3 |
1.413 N2973.G3 |
0.925 uart_txunit_N196.F4 |
1.131 uart_txunit_N145.G4 |
1.338 uart_txunit_N91.F3 |
|
uart_txunit_bitpos<1> |
uart_txunit_bitpos<1>.XQ |
1.305 uart_txunit_N99.F4 |
1.498 uart_txunit_N99.G1 |
1.483 uart_txunit_bitpos<0>.G1 |
0.652 uart_txunit_N124.F4 |
0.691 uart_txunit_N124.G4 |
1.135 uart_txunit_N135.G3 |
0.870 uart_txunit_bitpos<3>.G2 |
0.888 N2973.F1 |
1.234 uart_txunit_N196.F3 |
1.135 uart_txunit_bitpos<2>.F1 |
1.255 uart_txunit_N91.F1 |
1.010 uart_txunit_N91.G3 |
|
uart_txunit_bitpos<2> |
uart_txunit_bitpos<2>.XQ |
1.055 uart_txunit_bitpos<0>.G3 |
1.192 uart_txunit_N124.F1 |
1.126 uart_txunit_N124.G3 |
1.222 uart_txunit_N127.F2 |
1.468 uart_txunit_bitpos<3>.G1 |
0.920 uart_txunit_txd.F1 |
1.048 N2973.F4 |
1.546 uart_txunit_N196.F1 |
1.161 uart_txunit_bitpos<2>.F2 |
1.042 uart_txunit_N91.G4 |
|
uart_txunit_bitpos<3> |
uart_txunit_bitpos<3>.YQ |
1.229 uart_txunit_bitpos<0>.BX |
1.216 uart_txunit_bitpos<1>.BX |
1.005 uart_txunit_N124.F3 |
1.401 uart_txunit_N124.G2 |
1.137 uart_txunit_N127.G4 |
1.063 uart_txunit_bitpos<3>.G3 |
1.327 uart_txunit_txd.G3 |
1.363 N2973.F3 |
0.748 uart_txunit_N196.F2 |
1.149 uart_txunit_bitpos<2>.F4 |
|
uart_txunit_syncload_c1a |
uart_txunit_syncload_c1a.YQ |
0.722 uart_txunit_syncload_c1s.BY |
|
uart_txunit_syncload_c1s |
uart_txunit_syncload_c1s.YQ |
1.149 uart_txunit_N196.G1 |
1.180 N64.F4 |
1.113 uart_txunit_N66.G1 |
0.797 uart_txunit_syncload_r.SR |
|
uart_txunit_syncload_r |
uart_txunit_syncload_r.YQ |
0.724 uart_txunit_syncload_c1a.SR |
0.722 uart_txunit_syncload_c1s.SR |
|
uart_txunit_tbuff<0> |
uart_txunit_tbuff<1>.YQ |
0.701 uart_txunit_treg<1>.BY |
|
uart_txunit_tbuff<1> |
uart_txunit_tbuff<1>.XQ |
0.736 uart_txunit_treg<1>.BX |
|
uart_txunit_tbuff<2> |
uart_txunit_tbuff<3>.YQ |
1.055 uart_txunit_treg<3>.BY |
|
uart_txunit_tbuff<3> |
uart_txunit_tbuff<3>.XQ |
1.067 uart_txunit_treg<3>.BX |
|
uart_txunit_tbuff<4> |
uart_txunit_tbuff<5>.YQ |
0.683 uart_txunit_treg<5>.BY |
|
uart_txunit_tbuff<5> |
uart_txunit_tbuff<5>.XQ |
0.692 uart_txunit_treg<5>.BX |
|
uart_txunit_tbuff<6> |
uart_txunit_tbuff<7>.YQ |
0.705 uart_txunit_treg<7>.BY |
|
uart_txunit_tbuff<7> |
uart_txunit_tbuff<7>.XQ |
0.693 uart_txunit_treg<7>.BX |
|
uart_txunit_tbufl |
uart_txunit_tbufl.YQ |
0.836 uart_txunit_bitpos<0>.G4 |
0.838 uart_txunit_tbufl.G4 |
1.445 N2973.G1 |
0.993 uart_txunit_N196.G2 |
1.278 N64.F3 |
|
uart_txunit_treg<0> |
uart_txunit_treg<1>.YQ |
0.857 uart_txunit_N91.F2 |
|
uart_txunit_treg<1> |
uart_txunit_treg<1>.XQ |
0.691 uart_txunit_N91.F4 |
|
uart_txunit_treg<2> |
uart_txunit_treg<3>.YQ |
0.463 uart_txunit_N99.G4 |
|
uart_txunit_treg<3> |
uart_txunit_treg<3>.XQ |
0.475 uart_txunit_N99.G3 |
|
uart_txunit_treg<4> |
uart_txunit_treg<5>.YQ |
0.581 uart_txunit_N99.F2 |
|
uart_txunit_treg<5> |
uart_txunit_treg<5>.XQ |
0.660 uart_txunit_N99.F1 |
|
uart_txunit_treg<6> |
uart_txunit_treg<7>.YQ |
1.353 uart_txunit_N124.G1 |
|
uart_txunit_treg<7> |
uart_txunit_treg<7>.XQ |
1.234 uart_txunit_N124.F2 |
|
uart_txunit_txd |
uart_txunit_txd.YQ |
0.940 txd_pad_o.O |
|
wb_ack_o_OBUF |
wb_stb_i.I |
2.092 wb_ack_o.O |
1.919 N144.G1 |
1.694 N131.F2 |
1.757 N155.F2 |
|
wb_adr_i_0_IBUF |
wb_adr_i<0>.I |
1.354 N64.G1 |
1.436 N144.F3 |
1.747 N131.G1 |
1.693 N155.G1 |
1.306 wb_dat_o_4_OBUF.G1 |
1.351 wb_dat_o_3_OBUF.F1 |
1.092 wb_dat_o_3_OBUF.G4 |
1.115 wb_dat_o_2_OBUF.F4 |
1.039 wb_dat_o_2_OBUF.G3 |
1.249 wb_dat_o_1_OBUF.F2 |
1.206 wb_dat_o_1_OBUF.G1 |
|
wb_adr_i_1_IBUF |
wb_adr_i<1>.I |
1.809 N64.G4 |
1.891 N144.F4 |
1.984 N131.G2 |
1.964 N155.G3 |
0.729 wb_dat_o_4_OBUF.G3 |
1.130 wb_dat_o_3_OBUF.F4 |
1.156 wb_dat_o_3_OBUF.G3 |
1.072 wb_dat_o_2_OBUF.F3 |
1.348 wb_dat_o_2_OBUF.G1 |
1.266 wb_dat_o_1_OBUF.F4 |
1.239 wb_dat_o_1_OBUF.G2 |
|
wb_clk_i_BUFGP |
wb_clk_i_BUFGP/BUFG.OUT |
0.391 loada.CLK |
0.411 reada.CLK |
0.365 wb_dat_i<0>.CLK |
0.365 wb_dat_i<1>.CLK |
0.344 wb_dat_i<2>.CLK |
0.344 wb_dat_i<3>.CLK |
0.365 wb_dat_i<4>.CLK |
0.365 wb_dat_i<5>.CLK |
0.344 wb_dat_i<6>.CLK |
0.344 wb_dat_i<7>.CLK |
|
wb_clk_i_BUFGP/IBUFG |
wb_clk_i.GCLKOUT |
0.006 wb_clk_i_BUFGP/BUFG.IN |
|
wb_dat_o_0_OBUF |
N64.Y |
0.771 wb_dat_o<0>.O |
|
wb_dat_o_1_OBUF |
wb_dat_o_1_OBUF.X |
0.880 wb_dat_o<1>.O |
|
wb_dat_o_2_OBUF |
wb_dat_o_2_OBUF.X |
0.354 wb_dat_o<2>.O |
|
wb_dat_o_3_OBUF |
wb_dat_o_3_OBUF.X |
0.937 wb_dat_o<3>.O |
|
wb_dat_o_4_OBUF |
wb_dat_o_4_OBUF.Y |
0.354 wb_dat_o<4>.O |
|
wb_dat_o_5_OBUF |
wb_dat_o_3_OBUF.Y |
0.713 wb_dat_o<5>.O |
|
wb_dat_o_6_OBUF |
wb_dat_o_2_OBUF.Y |
0.354 wb_dat_o<6>.O |
|
wb_dat_o_7_OBUF |
wb_dat_o_1_OBUF.Y |
0.773 wb_dat_o<7>.O |
|
wb_rst_i_IBUF |
wb_rst_i.I |
1.697 uart_rxunit_N176.F1 |
1.679 uart_rxunit_N176.G1 |
0.612 uart_txunit_bitpos<0>.SR |
1.722 uart_txunit_bitpos<1>.SR |
2.509 uart_rxunit_bitpos<2>.SR |
1.033 uart_txunit_bitpos<3>.SR |
2.016 uart_rxunit_N111.G2 |
1.976 uart_rxunit_bitpos<1>.SR |
1.950 uart_rxunit_bitpos<3>.SR |
1.808 uart_rxunit_rregl.SR |
0.619 uart_txunit_tbufl.SR |
1.146 uart_txunit_txd.SR |
1.716 N2973.F2 |
2.024 N144.G2 |
1.363 N131.F4 |
1.257 N155.F4 |
0.903 uart_txunit_bitpos<2>.SR |
1.347 uart_txunit_N66.G2 |
2.487 uart_rxunit_bitpos<0>.SR |
|
wb_we_i_IBUF |
wb_we_i.I |
0.959 N144.G3 |
0.861 N131.G3 |
1.083 N155.G2 |
|
/branches/avendor/impl/Xilinx_xc2s15/uart._prj
0,0 → 1,2
plslib |
pls ../rtl/vhdl/utils.vhd ../rtl/vhdl/Rxunit.vhd ../rtl/vhdl/Txunit.vhd ../rtl/vhdl/miniuart.vhd |
/branches/avendor/impl/Xilinx_xc2s15/utils.jhd
0,0 → 1,2
MODULE synchroniser |
MODULE counter |
/branches/avendor/impl/Xilinx_xc2s15/uart.prj
0,0 → 1,4
work ../rtl/vhdl/utils.vhd |
work ../rtl/vhdl/Rxunit.vhd |
work ../rtl/vhdl/Txunit.vhd |
work ../rtl/vhdl/miniuart.vhd |
/branches/avendor/impl/Xilinx_xc2s15/uart.mrp
0,0 → 1,121
Release 4.2i - Map E.35 |
Xilinx Mapping Report File for Design 'uart' |
|
Design Information |
------------------ |
Command Line : map -p xc2s15-cs144-6 -cm area -k 4 -c 100 -tx off uart.ngd |
Target Device : x2s15 |
Target Package : cs144 |
Target Speed : -6 |
Mapper Version : spartan2 -- $Revision: 1.1.1.1 $ |
Mapped Date : Thu Jan 09 18:11:05 2003 |
|
Design Summary |
-------------- |
Number of errors: 0 |
Number of warnings: 0 |
Number of Slices: 83 out of 192 43% |
Number of Slices containing |
unrelated logic: 0 out of 83 0% |
Number of Slice Flip Flops: 63 out of 384 16% |
Total Number 4 input LUTs: 115 out of 384 29% |
Number used as LUTs: 110 |
Number used as a route-thru: 5 |
Number of bonded IOBs: 26 out of 86 30% |
IOB Flip Flops: 9 |
Number of GCLKs: 2 out of 4 50% |
Number of GCLKIOBs: 2 out of 4 50% |
Total equivalent gate count for design: 1,329 |
Additional JTAG gate count for IOBs: 1,344 |
|
Table of Contents |
----------------- |
Section 1 - Errors |
Section 2 - Warnings |
Section 3 - Informational |
Section 4 - Removed Logic Summary |
Section 5 - Removed Logic |
Section 6 - IOB Properties |
Section 7 - RPMs |
Section 8 - Guide Report |
Section 9 - Area Group Summary |
Section 10 - Modular Design Summary |
|
Section 1 - Errors |
------------------ |
|
Section 2 - Warnings |
-------------------- |
|
Section 3 - Informational |
------------------------- |
INFO:MapLib:62 - All of the external outputs in this design are using slew rate |
limited output drivers. The delay on speed critical outputs can be |
dramatically reduced by designating them as fast outputs in the schematic. |
|
Section 4 - Removed Logic Summary |
--------------------------------- |
2 block(s) optimized away |
|
Section 5 - Removed Logic |
------------------------- |
|
Optimized Block(s): |
TYPE BLOCK |
GND GND_I |
VCC VCC_I |
|
To enable printing of redundant blocks removed and signals merged, set the |
detailed map report option and rerun map. |
|
Section 6 - IOB Properties |
-------------------------- |
|
+------------------------------------------------------------------------------------------------------------------------+ |
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | |
| | | | | Strength | Rate | | | Delay | |
+------------------------------------------------------------------------------------------------------------------------+ |
| br_clk_i | GCLKIOB | INPUT | LVTTL | | | | | | |
| wb_clk_i | GCLKIOB | INPUT | LVTTL | | | | | | |
| intrx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | | |
| inttx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| rxd_pad_i | IOB | INPUT | LVTTL | | | | | | |
| txd_pad_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_ack_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_adr_i<0> | IOB | INPUT | LVTTL | | | | | | |
| wb_adr_i<1> | IOB | INPUT | LVTTL | | | | | | |
| wb_dat_i<0> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<1> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<2> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<3> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<4> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<5> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<6> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_i<7> | IOB | INPUT | LVTTL | | | INFF | | DELAY | |
| wb_dat_o<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_dat_o<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | |
| wb_rst_i | IOB | INPUT | LVTTL | | | | | | |
| wb_stb_i | IOB | INPUT | LVTTL | | | | | | |
| wb_we_i | IOB | INPUT | LVTTL | | | | | | |
+------------------------------------------------------------------------------------------------------------------------+ |
|
Section 7 - RPMs |
---------------- |
|
Section 8 - Guide Report |
------------------------ |
Guide not run on this design. |
|
Section 9 - Area Group Summary |
------------------------------ |
No area groups were found in this design. |
|
Section 10 - Modular Design Summary |
----------------------------------- |
Modular Design not used for this design. |
/branches/avendor/impl/Xilinx_xc2s15/uart.xpi
0,0 → 1,3
PROGRAM=PAR |
STATE=ROUTED |
TIMESPECS_MET=OFF |
/branches/avendor/impl/Xilinx_xc2s15/_ngdTOnc1_exewrap.rsp
0,0 → 1,3
-tapkeep -mode pipe -tcl -command e:/ise/data/projnav/_map.tcl _map.rsp uart cmd _map.log |
/branches/avendor/impl/Xilinx_xc2s15/uart.ncd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
branches/avendor/impl/Xilinx_xc2s15/uart.ncd
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/avendor/impl/Xilinx_xc2s15/uart.pad
===================================================================
--- branches/avendor/impl/Xilinx_xc2s15/uart.pad (nonexistent)
+++ branches/avendor/impl/Xilinx_xc2s15/uart.pad (revision 22)
@@ -0,0 +1,240 @@
+Release 4.2i - Par E.35
+Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
+
+Thu Jan 09 18:11:11 2003
+
+Xilinx PAD Specification File
+*****************************
+
+Input file: par_temp.ncd
+Output file: uart.ncd
+Part type: xc2s15
+Speed grade: -6
+Package: cs144
+
+Pinout by Signal Name:
+--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+ Signal Name | Pin Name | Pin | Direction | IO Standard |IO Bank # |Drive (mA)| Slew | Pullup | IOB Delay | Voltage |Constraint |
+ | | Number | | | | | Rate | Pulldown | | | |
+--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+ br_clk_i | | M7 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | *** | | |
+ intrx_o | | N8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ inttx_o | | K6 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ rxd_pad_i | | C6 | INPUT | LVTTL | 0 | 12* | SLOW*| NONE** | NONE | | |
+ txd_pad_o | VREF | L8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ wb_ack_o | | M8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ wb_adr_i<0> | | K4 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |
+ wb_adr_i<1> | | H4 | INPUT | LVTTL | 6 | 12* | SLOW*| NONE** | NONE | | |
+ wb_clk_i | | K7 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | *** | | |
+ wb_dat_i<0> | | C8 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<1> | | D8 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<2> | | N10 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<3> | | K9 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<4> | | N9 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<5> | | K8 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<6> | | D9 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_i<7> | | C9 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ wb_dat_o<0> | VREF | L6 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<1> | | H3 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<2> | | J2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<3> | | K2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<4> | VREF | H2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<5> | VREF | K1 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<6> | | J3 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ wb_dat_o<7> | VREF | L4 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ wb_rst_i | | N11 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | NONE | | |
+ wb_stb_i | DOUT_BUSY | C11 | INPUT | LVTTL | 2 | 12* | SLOW*| NONE** | NONE | | |
+ wb_we_i | | M6 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |
+--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+
+Pinout by Pin Number:
+--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+ Pin | Signal Name | Pin Name | Direction | IO Standard |IO Bank # |Drive (mA)| Slew | Pullup | IOB Delay | Voltage |Constraint |
+ Number | | | | | | | Rate | Pulldown | | | |
+--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+ A1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ A2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ A3 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ A4 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ A5 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ A6 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ A7 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ A8 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ A9 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ A10 | | VREF | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ A11 | | TDI | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ A12 | | TDO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ A13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B1 | | TMS | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B3 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ B4 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ B5 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ B6 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ B7 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ B8 | | VREF | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ B9 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B10 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ B11 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B12 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ B13 | | CCLK | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ C1 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ C2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ C3 | | TCK | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ C4 | | VREF | | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ C5 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ C6 | rxd_pad_i | | INPUT | LVTTL | 0 | 12* | SLOW*| NONE** | NONE | | |
+ C7 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ C8 | wb_dat_i<0> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ C9 | wb_dat_i<7> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ C10 | | WRITE | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ C11 | wb_stb_i | DOUT_BUSY | INPUT | LVTTL | 2 | 12* | SLOW*| NONE** | NONE | | |
+ C12 | | DIN_D0 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ C13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ D1 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ D2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ D3 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ D4 | | VREF | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ D5 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ D6 | | VREF | | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |
+ D7 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ D8 | wb_dat_i<1> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ D9 | wb_dat_i<6> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |
+ D10 | | CS | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |
+ D11 | | VREF | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ D12 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ D13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ E1 | | VREF | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ E2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ E3 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ E4 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ E10 | | D1 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ E11 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ E12 | | D2 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ E13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ F1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ F2 | | IRDY | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ F3 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ F4 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |
+ F10 | | VREF | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ F11 | | D3 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ F12 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ F13 | | IRDY | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |
+ G1 | | TRDY | | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |
+ G2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ G3 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ G4 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |
+ G10 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ G11 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ G12 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ G13 | | TRDY | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ H1 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |
+ H2 | wb_dat_o<4> | VREF | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ H3 | wb_dat_o<1> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ H4 | wb_adr_i<1> | | INPUT | LVTTL | 6 | 12* | SLOW*| NONE** | NONE | | |
+ H10 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ H11 | | VREF | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ H12 | | D4 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ H13 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ J1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ J2 | wb_dat_o<2> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ J3 | wb_dat_o<6> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ J4 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ J10 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ J11 | | D6 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ J12 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ J13 | | D5 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ K1 | wb_dat_o<5> | VREF | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ K2 | wb_dat_o<3> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |
+ K3 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |
+ K4 | wb_adr_i<0> | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |
+ K5 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |
+ K6 | inttx_o | | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ K7 | wb_clk_i | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | *** | | |
+ K8 | wb_dat_i<5> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ K9 | wb_dat_i<3> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ K10 | | D7 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ K11 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ K12 | | VREF | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ K13 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L1 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |
+ L2 | | M1 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L3 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L4 | wb_dat_o<7> | VREF | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ L5 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L6 | wb_dat_o<0> | VREF | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |
+ L7 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L8 | txd_pad_o | VREF | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ L9 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L10 | | VREF | | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |
+ L11 | | | UNUSED | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |
+ L12 | | PROGRAM | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ L13 | | INIT | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |
+ M1 | | M0 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ M2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ M4 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ M5 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ M6 | wb_we_i | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |
+ M7 | br_clk_i | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | *** | | |
+ M8 | wb_ack_o | | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ M9 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ M10 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ M11 | | | UNUSED | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |
+ M12 | | DONE | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ M13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ N1 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ N2 | | M2 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ N4 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |
+ N5 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |
+ N6 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |
+ N7 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ N8 | intrx_o | | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |
+ N9 | wb_dat_i<4> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ N10 | wb_dat_i<2> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |
+ N11 | wb_rst_i | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | NONE | | |
+ N12 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+ N13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |
+--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen.
+*** The default IOB Delay is determined by how the IOB is used.
+
+
+#
+# To preserve the pinout above for future design iterations,
+# simply invoke PIN2UCF from the command line or issue this command in the GUI.
+# For Foundation ISE/Project Navigator - Run the process "Implement Design" -> "Place-and-Route" -> "Back-annotate Pin Locations"
+# For Design Manager - In the Design menu select "Lock Pins...
+# The location constraints above will be written into your specified UCF file. (The constraints
+# listed below are in PCF format and cannot be directly used in the UCF file).
+#
+COMP "br_clk_i" LOCATE = SITE "M7" ;
+COMP "intrx_o" LOCATE = SITE "N8" ;
+COMP "inttx_o" LOCATE = SITE "K6" ;
+COMP "rxd_pad_i" LOCATE = SITE "C6" ;
+COMP "txd_pad_o" LOCATE = SITE "L8" ;
+COMP "wb_ack_o" LOCATE = SITE "M8" ;
+COMP "wb_adr_i<0>" LOCATE = SITE "K4" ;
+COMP "wb_adr_i<1>" LOCATE = SITE "H4" ;
+COMP "wb_clk_i" LOCATE = SITE "K7" ;
+COMP "wb_dat_i<0>" LOCATE = SITE "C8" ;
+COMP "wb_dat_i<1>" LOCATE = SITE "D8" ;
+COMP "wb_dat_i<2>" LOCATE = SITE "N10" ;
+COMP "wb_dat_i<3>" LOCATE = SITE "K9" ;
+COMP "wb_dat_i<4>" LOCATE = SITE "N9" ;
+COMP "wb_dat_i<5>" LOCATE = SITE "K8" ;
+COMP "wb_dat_i<6>" LOCATE = SITE "D9" ;
+COMP "wb_dat_i<7>" LOCATE = SITE "C9" ;
+COMP "wb_dat_o<0>" LOCATE = SITE "L6" ;
+COMP "wb_dat_o<1>" LOCATE = SITE "H3" ;
+COMP "wb_dat_o<2>" LOCATE = SITE "J2" ;
+COMP "wb_dat_o<3>" LOCATE = SITE "K2" ;
+COMP "wb_dat_o<4>" LOCATE = SITE "H2" ;
+COMP "wb_dat_o<5>" LOCATE = SITE "K1" ;
+COMP "wb_dat_o<6>" LOCATE = SITE "J3" ;
+COMP "wb_dat_o<7>" LOCATE = SITE "L4" ;
+COMP "wb_rst_i" LOCATE = SITE "N11" ;
+COMP "wb_stb_i" LOCATE = SITE "C11" ;
+COMP "wb_we_i" LOCATE = SITE "M6" ;
+#
Index: branches/avendor/impl/Xilinx_xc2s15/xilinx.jid
===================================================================
--- branches/avendor/impl/Xilinx_xc2s15/xilinx.jid (nonexistent)
+++ branches/avendor/impl/Xilinx_xc2s15/xilinx.jid (revision 22)
@@ -0,0 +1 @@
+. uart ..\..\rtl\vhdl\miniuart.vhd j:\rtl\vhdl\miniuart.vhd
Index: branches/avendor/impl/Xilinx_xc2s15/uart.ngc
===================================================================
--- branches/avendor/impl/Xilinx_xc2s15/uart.ngc (nonexistent)
+++ branches/avendor/impl/Xilinx_xc2s15/uart.ngc (revision 22)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.0e
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