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/pairing/trunk/testbench/test_f36m_cubic.v
3,33 → 3,33
 
module test_f36m_cubic;
 
// Inputs
reg clk;
reg [`W6:0] a;
wire [`W6:0] c;
// Inputs
reg clk;
reg [`W6:0] a;
wire [`W6:0] c;
 
// Instantiate the Unit Under Test (UUT)
f36m_cubic uut (
.clk(clk),
.a(a),
.c(c)
);
// Instantiate the Unit Under Test (UUT)
f36m_cubic uut (
.clk(clk),
.a(a),
.c(c)
);
 
initial begin
// Initialize Inputs
clk = 0;
a = 0;
initial begin
// Initialize Inputs
clk = 0;
a = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a = {{194'h225016412804a89a862aa1865268898886919259910155856,194'h10258285148a0048861944a264aa161a048829812a1961218},{194'ha9a29a12069660862a6a651806416061940925809115510a,194'h4115a2024962a809a065428aa6088668249a2890a5518a69},{194'h12918199902558a859412a9596148a00520685401210a95a8,194'h1505090561625145816a11225085092955995885598049126}};
#100;
if(c !== {{194'ha9926611a84a4114aa562246626418486540006a4829a014,194'h8644a469852659949412582a1a262145524206028042690a},{194'h2585255021628414524615aa156881a642605a0a446018622,194'haaa8806216a0555a04194a2110464440a2964246a56a1020},{194'h14092128882119a9a050a6149146a21810891996014002449,194'h14980a940a502a4821852486460690605815894849aa20a08}})
$display("E");
$finish;
end
end
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_f3_add.v
2,50 → 2,50
 
module test_f3_add;
 
// Inputs
reg [1:0] A;
reg [1:0] B;
// Inputs
reg [1:0] A;
reg [1:0] B;
 
// Outputs
wire [1:0] C;
// Outputs
wire [1:0] C;
 
// Instantiate the Unit Under Test (UUT)
f3_add uut (
.A(A),
.B(B),
.C(C)
);
// Instantiate the Unit Under Test (UUT)
f3_add uut (
.A(A),
.B(B),
.C(C)
);
 
task check;
begin
begin
#10;
if ((A+B) % 3 != C)
begin
$display("Error"); $finish;
end
end
endtask
if ((A+B) % 3 != C)
begin
$display("Error"); $finish;
end
end
endtask
 
initial begin
// Initialize Inputs
A = 0;
B = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
endmodule
 
/pairing/trunk/testbench/test_f3_sub.v
2,50 → 2,50
 
module test_f3_sub;
 
// Inputs
reg [1:0] A;
reg [1:0] B;
// Inputs
reg [1:0] A;
reg [1:0] B;
 
// Outputs
wire [1:0] C;
// Outputs
wire [1:0] C;
 
// Instantiate the Unit Under Test (UUT)
f3_sub uut (
.A(A),
.B(B),
.C(C)
);
// Instantiate the Unit Under Test (UUT)
f3_sub uut (
.A(A),
.B(B),
.C(C)
);
 
task check;
begin
begin
#10;
if (A != (B+C) % 3)
begin
$display("Error A:%d B:%d C:%d", A, B, C); $finish;
end
end
endtask
if (A != (B+C) % 3)
begin
$display("Error A:%d B:%d C:%d", A, B, C); $finish;
end
end
endtask
 
initial begin
// Initialize Inputs
A = 0;
B = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
endmodule
 
/pairing/trunk/testbench/test_f33m_inv.v
3,34 → 3,34
 
module test_f33m_inv;
 
// Inputs
reg clk;
reg reset;
reg [`W3:0] a, w;
// Inputs
reg clk;
reg reset;
reg [`W3:0] a, w;
 
// Outputs
wire done;
wire [`W3:0] c;
// Outputs
wire done;
wire [`W3:0] c;
 
// Instantiate the Unit Under Test (UUT)
f33m_inv uut (
.clk(clk),
.reset(reset),
.a(a),
.c(c),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
f33m_inv uut (
.clk(clk),
.reset(reset),
.a(a),
.c(c),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a = {194'h210226252a484596150544098559162512219149194a91008,194'h12622041181115a64a84159a001a15a0a0609a642962068a5,194'h25429526606a8552a8622169050aa29921641120a05866014};
w = {194'h9a08022aa299850a48900010428a4aa66211109901a00a89,194'h95869a60454411009148081200aaaa121864220208592809,194'h564a6642212a164990212611055046496851a96918954695};
@ (negedge clk); reset = 1;
38,7 → 38,7
@ (posedge done); @(negedge clk);
if (c !== w) $display("E");
$finish;
end
end
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_second_part.v
3,36 → 3,36
 
module test_second_part;
 
// Inputs
reg clk;
reg reset;
reg [`W6:0] a,w;
// Inputs
reg clk;
reg reset;
reg [`W6:0] a,w;
 
// Outputs
wire done;
wire [`W6:0] c;
// Outputs
wire done;
wire [`W6:0] c;
 
// Instantiate the Unit Under Test (UUT)
second_part uut (
.clk(clk),
.reset(reset),
.a(a),
.c(c),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
second_part uut (
.clk(clk),
.reset(reset),
.a(a),
.c(c),
.done(done)
);
 
always #5 clk = ~clk;
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a = {{194'h1204a208505851241694660a526600a5458a2146924560a45,194'h205aaa952a9194aa810582958a44a26450215504612a46414},{194'h2a45a0864044919108410218084641146a6998849a4621651,194'h22a848590260089606082518041602a196a616829a2a80140},{194'h19491668519a946a6024288a5112a24a61a09955a90a1a228,194'h89204a1905581664001424a2218884a81a4018082628016a}};
w = {{194'h29a595141a15aaaaa986118869958824916644820599a9105,194'h1058412a52a604a8928a154a55625062004a8156558a25456},{194'h265269409a62958689a49a5044a024a4944252894154a5089,194'h1a00a6298165562952615a009190225988a28809955a49aaa},{194'h2285858aa2486869a809409269941a8595252895401015459,194'h124469156610a888686061a9128002611404aa18a26850589}};
@ (negedge clk); reset = 1;
41,7 → 41,7
@ (negedge clk);
if (c !== w) $display("E");
$finish;
end
end
endmodule
 
/pairing/trunk/testbench/test_f3_neg.v
2,41 → 2,41
 
module test_f3_neg;
 
// Inputs
reg [1:0] A;
// Inputs
reg [1:0] A;
 
// Outputs
wire [1:0] B;
// Outputs
wire [1:0] B;
 
// Instantiate the Unit Under Test (UUT)
f3_neg uut (
.A(A),
.B(B)
);
// Instantiate the Unit Under Test (UUT)
f3_neg uut (
.A(A),
.B(B)
);
 
task check;
begin
begin
#10;
if ((A+B) % 3 != 0)
begin
$display("Error"); $finish;
end
end
endtask
if ((A+B) % 3 != 0)
begin
$display("Error"); $finish;
end
end
endtask
 
initial begin
// Initialize Inputs
A = 0;
initial begin
// Initialize Inputs
A = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 0; check;
A = 1; check;
A = 2; check;
$finish;
end
// Add stimulus here
A = 0; check;
A = 1; check;
A = 2; check;
$finish;
end
endmodule
 
/pairing/trunk/testbench/test_f3m_inv.v
2,36 → 2,36
`define CLOCK_PERIOD 10
module test_f3m_inv;
 
// Inputs
reg [193:0] A;
reg clk;
reg reset;
// Inputs
reg [193:0] A;
reg clk;
reg reset;
 
// Outputs
wire [193:0] C;
// Outputs
wire [193:0] C;
wire done;
 
// Instantiate the Unit Under Test (UUT)
f3m_inv uut (
.A(A),
.clk(clk),
.reset(reset),
.C(C),
// Instantiate the Unit Under Test (UUT)
f3m_inv uut (
.A(A),
.clk(clk),
.reset(reset),
.C(C),
.done(done)
);
);
 
always #`CLOCK_PERIOD clk = ~clk;
 
initial begin
// Initialize Inputs
A = 0;
clk = 0;
reset = 0;
initial begin
// Initialize Inputs
A = 0;
clk = 0;
reset = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
A = 32'b10_01_01_10_01_00; // A = "x";
@(negedge clk); reset = 1;
@(negedge clk); reset = 0;
38,7 → 38,7
#(200*2*`CLOCK_PERIOD);
if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) $display("Error!");
$display("Good!"); $finish;
end
end
endmodule
 
/pairing/trunk/testbench/test_post_route.v
4,39 → 4,39
/* if you don't use Xilinx ISE, please ignore this file :) */
module test_post_route;
 
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] x1, y1, x2, y2;
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] x1, y1, x2, y2;
 
// Outputs
wire done, ok;
// Outputs
wire done, ok;
 
// Instantiate the Unit Under Test (UUT)
post_route_debug uut (
.clk(clk),
.reset(reset),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.done(done),
.ok(ok)
);
// Instantiate the Unit Under Test (UUT)
post_route_debug uut (
.clk(clk),
.reset(reset),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.done(done),
.ok(ok)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x1 = 0;
y1 = 0;
x2 = 0;
y2 = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x1 = 0;
y1 = 0;
x2 = 0;
y2 = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
x1 = 194'h6a18950064046a122a14118668466a262a91509688159890;
y1 = 194'h69112569422aa0a25224aa010888066061124a8685566825;
x2 = 194'h155945aa8924654812564110544995a28845901211454814;
47,7 → 47,7
if (ok !== 1'b1) $display("E");
$finish;
 
end
end
 
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_tate_pairing.v
3,43 → 3,43
 
module test_tate_pairing;
 
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] x1, y1, x2, y2;
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] x1, y1, x2, y2;
 
// Outputs
wire done;
wire [`W6:0] out;
// Outputs
wire done;
wire [`W6:0] out;
 
// Vars
reg [`W6:0] wish;
 
// Instantiate the Unit Under Test (UUT)
tate_pairing uut (
.clk(clk),
.reset(reset),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.done(done),
.out(out)
);
// Instantiate the Unit Under Test (UUT)
tate_pairing uut (
.clk(clk),
.reset(reset),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.done(done),
.out(out)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x1 = 0;
y1 = 0;
x2 = 0;
y2 = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x1 = 0;
y1 = 0;
x2 = 0;
y2 = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
x1 = 194'h6a18950064046a122a14118668466a262a91509688159890;
y1 = 194'h69112569422aa0a25224aa010888066061124a8685566825;
x2 = 194'h155945aa8924654812564110544995a28845901211454814;
50,7 → 50,7
@ (posedge done); @ (negedge clk);
if (out !== wish) $display("E");
$finish;
end
end
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_duursma_lee_algo.v
3,43 → 3,43
 
module test_duursma_lee_algo;
 
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] xp,yp,xr,yr;
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] xp,yp,xr,yr;
 
// Outputs
wire done;
// Outputs
wire done;
wire [`W6:0] out;
wire [`WIDTH:0] o0,o1,o2,o3,o4,o5;
 
// Instantiate the Unit Under Test (UUT)
duursma_lee_algo uut (
.clk(clk),
.reset(reset),
.xp(xp),
.yp(yp),
.xr(xr),
.yr(yr),
.done(done),
.out(out)
);
// Instantiate the Unit Under Test (UUT)
duursma_lee_algo uut (
.clk(clk),
.reset(reset),
.xp(xp),
.yp(yp),
.xr(xr),
.yr(yr),
.done(done),
.out(out)
);
assign {o5,o4,o3,o2,o1,o0} = out;
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
xp = 0;
yp = 0;
xr = 0;
yr = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
xp = 0;
yp = 0;
xr = 0;
yr = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
 
// Add stimulus here
// Add stimulus here
xp = 194'haa5a8129a02a0544a4409a500045458901280969815aa820;
yp = 194'h1414a205a21a4428968985650895464402249258428049204;
xr = 194'h614011499522506668a01a20988812468a5aa8641aa24595;
60,7 → 60,7
end
#100;
$finish;
end
end
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_f32m_mult.v
2,36 → 2,36
 
module test_f32m_mult;
 
// Inputs
reg reset;
reg clk;
reg [387:0] a,b;
// Inputs
reg reset;
reg clk;
reg [387:0] a,b;
 
// Outputs
wire [387:0] c;
wire done;
// Outputs
wire [387:0] c;
wire done;
 
// Instantiate the Unit Under Test (UUT)
f32m_mult uut (
.reset(reset),
.clk(clk),
.a(a),
.b(b),
.c(c),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
f32m_mult uut (
.reset(reset),
.clk(clk),
.a(a),
.b(b),
.c(c),
.done(done)
);
 
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
a = 0;
b = 0;
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
a = 0;
b = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a={194'h2a8aa25aa245066106a40806618aa88a2946881162a864652,194'h28258889288590a464559a0854a0a269820495a6069969aa2};
b={194'h59a0a46891951042640592a2969888012108059214504048,194'h55812555968918122622106514a25488204895614889112};
@ (negedge clk) reset = 1;
49,7 → 49,7
#100;
$finish;
end
end
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_f33m_mult.v
3,38 → 3,38
 
module test_f33m_mult;
 
// Inputs
reg clk;
reg reset;
reg [`W3:0] a,b,wish;
// Inputs
reg clk;
reg reset;
reg [`W3:0] a,b,wish;
 
// Outputs
wire done;
// Outputs
wire done;
wire [`W3:0] c;
 
// Instantiate the Unit Under Test (UUT)
f33m_mult uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.c(c),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
f33m_mult uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.c(c),
.done(done)
);
 
always #5 clk = ~clk;
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
b = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
b = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a = {194'ha05199566491a29190482a612a86561469a2a21a0598425a,194'h29a016819944661925585684aa051456a52a02442a9080568,194'h15219624104641521626a965848208a09a02a9a084499006a};
b = {194'h16458a4488a64426429a46989868049a5a94a291668056411,194'h4229659440a9689291461604a9a01a20000a191a00142951,194'h504004aaa024886a56504a8a4a58806919aa1a4549a56688};
wish = {194'ha65a56829a691285518450025a0190642544a08628a965a5,194'h22889984564568942218aa986112026a095a629a68890a859,194'h14a11844416485509289802509a000421864454612559588};
45,6 → 45,6
if (c !== wish)
$display("E");
$finish;
end
end
endmodule
 
/pairing/trunk/testbench/test_f3_mult.v
2,50 → 2,50
 
module test_f3_mult;
 
// Inputs
reg [1:0] A;
reg [1:0] B;
// Inputs
reg [1:0] A;
reg [1:0] B;
 
// Outputs
wire [1:0] C;
// Outputs
wire [1:0] C;
 
// Instantiate the Unit Under Test (UUT)
f3_mult uut (
.A(A),
.B(B),
.C(C)
);
// Instantiate the Unit Under Test (UUT)
f3_mult uut (
.A(A),
.B(B),
.C(C)
);
 
task check;
begin
begin
#10;
if ((A*B) % 3 != C)
begin
$display("Error"); $finish;
end
end
endtask
if ((A*B) % 3 != C)
begin
$display("Error"); $finish;
end
end
endtask
 
initial begin
// Initialize Inputs
A = 0;
B = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
// Add stimulus here
A = 0; B = 0; check;
A = 0; B = 1; check;
A = 0; B = 2; check;
A = 1; B = 0; check;
A = 1; B = 1; check;
A = 1; B = 2; check;
A = 2; B = 0; check;
A = 2; B = 1; check;
A = 2; B = 2; check;
$finish;
end
endmodule
 
/pairing/trunk/testbench/test_f3m_mult3.v
3,46 → 3,46
 
module test_f3m_mult3;
 
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] a0,b0,a1,b1,a2,b2,w0,w1,w2;
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] a0,b0,a1,b1,a2,b2,w0,w1,w2;
 
// Outputs
// Outputs
wire [`WIDTH:0] c0,c1,c2;
wire done;
wire done;
 
// Instantiate the Unit Under Test (UUT)
f3m_mult3 uut (
.clk(clk),
.reset(reset),
.a0(a0),
.b0(b0),
.c0(c0),
.a1(a1),
.b1(b1),
.c1(c1),
.a2(a2),
.b2(b2),
.c2(c2),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
f3m_mult3 uut (
.clk(clk),
.reset(reset),
.a0(a0),
.b0(b0),
.c0(c0),
.a1(a1),
.b1(b1),
.c1(c1),
.a2(a2),
.b2(b2),
.c2(c2),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a0 = 0;
b0 = 0;
a1 = 0;
b1 = 0;
a2 = 0;
b2 = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a0 = 0;
b0 = 0;
a1 = 0;
b1 = 0;
a2 = 0;
b2 = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a0 = 194'h2581921511a6952a4244918a069446a520480660152916412;
a1 = 194'haa59080a98122082111a110a400642169102154006590a28;
a2 = 194'h90026a06416441992252a2820a2860269a094a0a06428285;
60,7 → 60,7
if (c1 !== w1) $display("E");
if (c2 !== w2) $display("E");
$finish;
end
end
 
always #5 clk = ~clk;
endmodule
/pairing/trunk/testbench/test_f36m.v
2,36 → 2,36
 
module test_f36m;
 
// Inputs
reg clk;
reg reset;
reg [1163:0] a, b;
// Inputs
reg clk;
reg reset;
reg [1163:0] a, b;
 
// Outputs
wire done;
// Outputs
wire done;
wire [1163:0] c;
 
// Instantiate the Unit Under Test (UUT)
f36m_mult uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.c(c),
.done(done)
);
// Instantiate the Unit Under Test (UUT)
f36m_mult uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.c(c),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
b = 0;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
b = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
a = {{194'h8864990666a959a88500249a244495aaa26a2a0194082aa1,194'h2a9481526946468065456052045865262520a4a9520a5a665},{194'h185218150022515648a249a8945625895448860a18905a018,194'h269862628a1aa4489059585a002520602618299155aa0aa54},{194'h24a8112565595199615504222108089046890965559999a54,194'h989802898a9580a8264a8516568952918645268868608988}};
b = {{194'h116698585aa229805611194a6520151245204aa9114a89200,194'h8855225a25520a048a912141800501862189941946906540},{194'h292a05921518651529280825a940a22016016415906190642,194'h25a4455a419606606081860a1094a05996914048469499412},{194'h11a1415465625aa59489642111440112690a8546992a61802,194'h690a815a0a6885852602a4a5a1281458010a81184288441a}};
 
42,7 → 42,7
$display("E");
#100;
$finish;
end
end
 
always #5 clk = ~clk;
endmodule
/pairing/trunk/rtl/f3m.v
464,48 → 464,48
 
// inversion in GF(3^m). C = A^(-1)
module f3m_inv(clk, reset, A, C, done);
input [`WIDTH:0] A;
input clk;
input reset;
output reg [`WIDTH:0] C;
input [`WIDTH:0] A;
input clk;
input reset;
output reg [`WIDTH:0] C;
output reg done;
reg [`WIDTH+2:0] S, R, U, V, d;
reg [2*`M:0] i;
wire [1:0] q;
wire [`WIDTH+2:0] S1, S2,
R1,
U1, U2, U3,
V1, V2,
d1, d2;
wire don;
reg [`WIDTH+2:0] S, R, U, V, d;
reg [2*`M:0] i;
wire [1:0] q;
wire [`WIDTH+2:0] S1, S2,
R1,
U1, U2, U3,
V1, V2,
d1, d2;
wire don;
 
assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
assign don = i[0];
f3_mult
q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
func1
ins1(S, R, q, S1), // S1 = S - q*R
ins2(V, U, q, V1); // V1 = V - q*U
func2
ins3(S1, S2), // S2 = x*S1 = x*(S-q*R)
ins4(R, R1); // R1 = x*R
func3
ins5(U, U1), // U1 = x*U mod p
ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p
assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
assign don = i[0];
f3_mult
q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
func1
ins1(S, R, q, S1), // S1 = S - q*R
ins2(V, U, q, V1); // V1 = V - q*U
func2
ins3(S1, S2), // S2 = x*S1 = x*(S-q*R)
ins4(R, R1); // R1 = x*R
func3
ins5(U, U1), // U1 = x*U mod p
ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p
func4
ins7(U, R[`MOST], U2); // U2 = U/r_m
func5
ins8(U, U3); // U3 = (U/x) mod p
always @ (posedge clk)
always @ (posedge clk)
if (reset)
done <= 0;
else if (don)
else if (don)
begin
done <= 1; C <= U2[`WIDTH:0];
done <= 1; C <= U2[`WIDTH:0];
end
 
always @ (posedge clk)
/pairing/trunk/rtl/f3.v
23,14 → 23,14
 
// f3_mult: C = A*B (mod 3)
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule
 
// c == a+1 (mod 3)

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