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URL https://opencores.org/ocsvn/sc2v/sc2v/trunk

Subversion Repositories sc2v

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    /
    from Rev 21 to Rev 22
    Reverse comparison

Rev 21 → Rev 22

/trunk/ChangeLog
4,6 → 4,9
for loops with int type as index supported
Support hex numbers in switchs
Support sc_signals arrays
Corrected bug when connecting a output port to another
Solved problem in type conversions
Solved problem with enumeration list
 
25-02-2005 Version 0.4
 
/trunk/src/sc2v_step1.y
543,7 → 543,6
fprintf (regs_file, "%s", regname2);
 
regslist = InsertReg (regslist, regname, regname2);
 
free (regname);
free (regname2);
}
/trunk/src/sc2v_step2.y
113,7 → 113,7
 
ShowPortList (portlist);
printf ("\n");
RegOutputs (portlist);
RegOutputs (portlist,instanceslist);
printf ("\n");
 
ShowEnumListList (enumlistlist);
/trunk/src/sc2v_step1.l
91,10 → 91,10
"/*" if (!linecomment) multilinecomment = 1; yylval=(int)strdup(yytext); return WORD;
"*/" if (multilinecomment) multilinecomment = 0; yylval=(int)strdup(yytext); return WORD;
 
"("[ ]*"sc_uint"[ ]*"<"[ ]*[0-9+][ ]*">"[ ]*")"
"("[ ]*"sc_biguint"[ ]*"<"[ ]*[0-9+][ ]*">"[ ]*")"
"("[ ]*"sc_int"[ ]*"<"[ ]*[0-9+][ ]*">"[ ]*")"
"("[ ]*"sc_bigint"[ ]*"<"[ ]*[0-9+][ ]*">"[ ]*")"
"("[ ]*"sc_uint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_biguint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_int"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_bigint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"int"[ ]*")"
 
 
/trunk/src/sc2v_step2.l
102,6 → 102,12
"|"
"~"
 
"("[ ]*"sc_uint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_biguint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_int"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"sc_bigint"[ ]*"<"[ ]*[0-9]+[ ]*">"[ ]*")"
"("[ ]*"int"[ ]*")"
 
"//"[ ]*[tT][rR][aA][nN][sS][lL][aA][tT][eE][ ]*[oO][fF][fF] return TRANSLATEOFF; /*Translate directive*/
"//"[ ]*[tT][rR][aA][nN][sS][lL][aA][tT][eE][ ]*[oO][nN] return TRANSLATEON; /*Translate directive*/
%%
/trunk/src/sc2v_step2.c
134,7 → 134,7
}
 
void
RegOutputs (PortNode * list)
RegOutputs (PortNode * list, InstanceNode *instances)
{
 
PortNode *pll;
142,6 → 142,7
{
if (strcmp (pll->tipo, "output") == 0)
{
if(!IsWire(pll->name,instances)){
printf ("reg ");
if (pll->size != 0 && pll->size != 1)
{
148,6 → 149,7
printf ("[%d:0] ", (-1 + pll->size));}
printf ("%s;\n", pll->name);}
}
}
);
return;
}
438,16 → 440,12
EnumeratesNode *ell;
int i = 0;
SGLIB_LIST_REVERSE(EnumeratesNode, list, next);
printf ("parameter %s = 0", list->name);
if(list->next!=NULL)
if(list->next!=NULL){
list=list->next;
if(list->next!=NULL){
printf(",\n");
i=1;
printf(",\n");
i=1;
SGLIB_LIST_MAP_ON_ELEMENTS (EnumeratesNode,list, ell,next,
{
if(ell->next==NULL)
505,9 → 503,9
 
if (!(ell->istype))
{
if ((bits_i - 1) != 0)
if ((bits_i - 1) != 0)
printf ("reg [%d:0] %s;\n\n", bits_i - 1, ell->name);
else
else
printf ("reg %s;\n\n", ell->name);
}
 
/trunk/examples/dummy1.h
6,35 → 6,43
 
#include "systemc.h"
 
SC_MODULE(fsm){
SC_MODULE(dummy1){
 
sc_in<bool> clk;
sc_in<bool> rst,input1, input2;
sc_in<bool> rst;
sc_in<sc_uint<2> > input1, input2;
sc_out< sc_uint<2> > a,b,w;
 
enum state_t {S0,S1,S2};
enum state_t {A,B};
sc_signal<state_t> state,next_state;
enum {AA,BB,CC,DD,EE} estado;
enum {S0,S1,S2,S3,EE} estado;
enum {AAA} est;
 
sc_signal<sc_uint<4> > temp;
sc_signal<sc_uint<2>> b_a;
 
 
void regs();
void fsm_proc();
sc_uint<2> func1 (sc_uint<2> a, sc_uint<2> b);
moduleA *moda;
moduleA *modb;
SC_CTOR(fsm){
SC_CTOR(dummy1){
moda = new moduleA("MODA");
moda->m1_in(input1);
moda->m1_in(b_a);
moda->m1_out(w);
modb = new moduleA("MODB");
modb->m1_in(input2);
modb->m1_out(b_a);
 
 
SC_METHOD(regs);
sensitive_pos(clk);
sensitive_neg(rst);
/trunk/examples/dummy1.cpp
3,7 → 3,7
#define HOLA 1
#define CONCAT 1
 
sc_uint<2> fsm::func1(sc_uint<2> a, sc_uint<2> b){
sc_uint<2> dummy1::func1(sc_uint<2> a, sc_uint<2> b){
sc_uint<2> c;
c=a+b;
return c+5;
11,7 → 11,7
 
 
void
fsm::regs ()
dummy1::regs ()
{
if (rst.read ())
{
22,7 → 22,7
}
 
void
fsm::fsm_proc ()
dummy1::fsm_proc ()
{
/*Verilog begin
cfsm_proc={a[1:0],b[1:0]};

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