URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/xge_mac/trunk/rtl/include/defines.v
35,6 → 35,8
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// Different synthesis option for FIFOs |
// `define XIL |
|
// CPU Registers |
|
/xge_mac/trunk/rtl/verilog/generic_mem_small.v
35,6 → 35,8
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`include "defines.v" |
|
/* synthesis ramstyle = "M512" */ |
|
module generic_mem_small( |
/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
35,6 → 35,8
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`include "defines.v" |
|
/* synthesis ramstyle = "M4K" */ |
|
module generic_mem_medium( |
/xge_mac/trunk/tbench/proto_systemverilog/verification/env.sv
0,0 → 1,129
/** |
* 10 GE MAC Core verification environment file. |
* @file: env.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC (SV 1896 Systemverilog for advanced verification course) |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By: |
* $LastChangedBy$ |
*/ |
|
/** |
* Environment class to contain all test components viz. driver, monitor and scoreboard. |
* Environment instantiates driver, monitor and scoreboard, acts as a intermediatery |
* between all of them. |
* @class env |
* @par |
*/ |
|
class env; |
|
driver macCoreDriver; ///< handle for driver type object to send data to MAC Core. |
monitor macCoreMonitor; ///< handle for monitor type object to collect data from MAC Core. |
scoreboard macCoreScoreboard; |
|
mailbox driver2Scoreboard; |
mailbox monitor2Scoreboard; |
|
virtual macCoreInterface virtualMacCoreInterfaceDriver; ///< virtual interface to connect driver type object to MAC core RTL |
virtual macCoreInterface virtualMacCoreInterfaceMonitor; ///< virtual interface to connect monitor type object to MAC core RTL |
|
/** |
* Constructor for environment class. |
* Main purpose of the constructor is to connect virtual interfaces to respective objects |
* and pass down proper parameters to scoreboard for checking |
* @param driverVirtualInterface to connect interface with driver object |
* @param monitorVirtualInterface to connect interface with monitor object |
* @return: NA (returns handle and creates object of type environment class |
*/ |
function new ( virtual macCoreInterface driverVirtualInterface, |
virtual macCoreInterface monitorVirtualInterface ); |
|
this.virtualMacCoreInterfaceDriver = driverVirtualInterface; |
this.virtualMacCoreInterfaceMonitor = monitorVirtualInterface; |
|
driver2Scoreboard = new (); |
monitor2Scoreboard = new (); |
|
macCoreDriver = new (virtualMacCoreInterfaceDriver, driver2Scoreboard); |
macCoreMonitor = new (virtualMacCoreInterfaceMonitor, monitor2Scoreboard); |
|
macCoreScoreboard = new (driver2Scoreboard, monitor2Scoreboard); |
|
endfunction // new |
|
/** |
* Init task for all testcases to initialize MAC core with pre simulation configuration. |
* Main purpose of the task is to initialize all inputs of simple Tx Rx interface of MAC to 0 |
*/ |
task init (); |
virtualMacCoreInterfaceMonitor.clockingTxRx.receiveReadEnable <= 0; |
|
virtualMacCoreInterfaceDriver.clockingTxRx.transmitData <= 0; |
virtualMacCoreInterfaceDriver.clockingTxRx.transmitValid <= 0; |
virtualMacCoreInterfaceDriver.clockingTxRx.transmitStartOfPacket <= 0; |
virtualMacCoreInterfaceDriver.clockingTxRx.transmitEndOfPacket <= 0; |
virtualMacCoreInterfaceDriver.clockingTxRx.transmitPacketLengthModulus <= 0; |
|
endtask // init |
|
/** |
* Reset task for all testcases to put MAC Core through particular reset consitions |
*/ |
task reset (); |
virtualMacCoreInterfaceDriver.clockingTxRx.rstTxRxInterface_n <= 0; |
virtualMacCoreInterfaceDriver.clockingXGMIIRx.rstXGMIIInterfaceRx_n <= 0; |
virtualMacCoreInterfaceDriver.clockingXGMIITx.rstXGMIIInterfaceTx_n <= 0; |
virtualMacCoreInterfaceDriver.clockingTxRx.rstWishboneInterface <= 0; |
|
repeat (10) @(virtualMacCoreInterfaceDriver.clockingTxRx); |
virtualMacCoreInterfaceDriver.clockingTxRx.rstTxRxInterface_n <= 1; |
virtualMacCoreInterfaceDriver.clockingXGMIIRx.rstXGMIIInterfaceRx_n <= 1; |
virtualMacCoreInterfaceDriver.clockingXGMIITx.rstXGMIIInterfaceTx_n <= 1; |
virtualMacCoreInterfaceDriver.clockingTxRx.rstWishboneInterface <= 1; |
|
endtask // reset |
|
/** |
* Run task for all testcases to start simulating / executing instructions / consuming time. |
* Main purpose of the task is to instantiate send_packet and collect_packet and call scoreboard checking if available |
*/ |
task run (int noOfPackets = 10, int lengthOfFrame = 60); |
|
fork |
for (int i = 0; i < noOfPackets; i++) |
begin |
@(virtualMacCoreInterfaceDriver.clockingTxRx) |
$display ("=========Sending Packet #%0d============ at time %0t\n", i, $time); |
macCoreDriver.send_packet(lengthOfFrame); |
end |
for (int i = 0; i < noOfPackets; i++) |
begin |
wait (virtualMacCoreInterfaceMonitor.clockingTxRx.receiveAvailable == 1'b1); |
$display ("========Collecting Packet #%0d===========\n", i); |
macCoreMonitor.collect_packet(); |
end |
join |
|
endtask // run |
|
task validate (int noOfPackets = 10, int lengthOfFrame = 60); |
|
for (int i = 0; i < noOfPackets; i++) |
begin |
for (int j = 0; j < lengthOfFrame; j += 8) |
begin |
int bytesInFrame; |
|
if ( (j+8) > lengthOfFrame) bytesInFrame = lengthOfFrame % 8; |
else bytesInFrame = 0; |
macCoreScoreboard.compare (driver2Scoreboard, monitor2Scoreboard, bytesInFrame); |
end |
end |
endtask // validate |
|
endclass // env |
/xge_mac/trunk/tbench/proto_systemverilog/verification/macCoreInterface.sv
0,0 → 1,131
/** |
* Interface file for 10 GE MAC Core. |
* Takes all clocks as input and all clocks are created from single clock source in testbench |
* @file: macCoreInterface.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC extension (Systemverilog for advanced verification SV1896) course |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By |
* $LastChangedBy$ |
*/ |
|
/** |
* 10GE MAC Core interface. |
* @param clkWishboneInterface : clock for wishbone interface 30 - 156 MHz -- input to interface logic |
* @param clkTxRxInterface : clock for simple Tx-Rx interface 156.25 MHz -- input to interface logic |
* @param clkXGMIIInterfaceRx : clock for XGMII physical layer Rx interface 156.25 MHz -- input to interface logic |
* @param clkXGMIIInterfaceTx : clock for XGMII physical later Tx interface 156.25 MHz -- input to interface logic |
*/ |
|
interface macCoreInterface (input bit clkWishboneInterface, |
input bit clkTxRxInterface, |
input bit clkXGMIIInterfaceRx, |
input bit clkXGMIIInterfaceTx |
); |
|
// Reset signals used in design |
bit rstWishboneInterface; ///< Wishbone interface reset signal -- de-assertion synchronous to clkWishboneInterface |
bit rstTxRxInterface_n; ///< Simple Tx-Rx interface reset signal -- de-assertion synchronous to clkTxRxInterface ACTIVE LOW |
bit rstXGMIIInterfaceRx_n; ///< XGMII physical layer Rx interface reset signal -- de-assertion synchronous to clkXGMIIInterfaceRx ACTIVE LOW |
bit rstXGMIIInterfaceTx_n; ///< XGMII physical later Tx interface reset signal -- de-assertion synchronous to clkXGMIIInterfaceTx ACTIVE LOW |
|
// Packet receive interface signals |
bit receiveReadEnable; ///< Input to Core (outoput of test) asserted when packet is available in receive FIFO |
bit receiveAvailable; ///< Output from Core indicates packet is available for reading in receive FIFO |
bit [63:0] receivedData; ///< Output from Core represents a packet data in little endian format |
bit receiveEndOfPacket; ///< Output from Core asserted when last word of packet is read form receive FIFO |
bit receiveValid; ///< Output from Core asserted a cycle after readEnable represents a valid data on bus |
bit receiveStartOfPacket; ///< Output from Core represents first word of packet is on the bus |
bit [2:0] receivePacketLengthModulus; ///< Output from Core updated with End of packet to represent valid bytes during last word |
bit receiveError; ///< Output from Core represents current packet is bad mainly due to CRC errors |
|
// Packet transmit interface signals |
bit [63:0] transmitData; ///< Input to Core represents packet data to be transmitted in Little-Endian format |
bit transmitValid; ///< Input to Core asserted for each valid data transfer to MAC Core |
bit transmitStartOfPacket; ///< Input to Core must be asserted during first word of packet to Core |
bit transmitEndOfPacket; ///< Input to Core must be asserted during last word of packet to Core |
bit [2:0] transmitPacketLengthModulus;///< Input to Core should be valid during End Of Packet during last word and represents valid bytes |
bit transmitFIFOFull; ///< Output from Core represents transmit FIFO is about to be full |
|
// XGMII receive interface signals |
bit [7:0] xgmiiReceiveControl; ///< Input to Core - each bit corresponds to type of byte of frame; 0 - byte is data, 1 - byte is control char |
bit [63:0] xgmiiReceiveData; ///< Input to Core - represents data on XGMII interface to be received by Core (can be broken in 32 bits) |
|
// XGMII transmit interface signals |
bit [7:0] xgmiiTransmitControl; ///< Output from Core - each bit corresponds to type of byte of frame; 0 - byte is data, 1 - byte is control char |
bit [63:0] xgmiiTransmitData; ///< Output from Core - represents data on XGMII interface to be transmitted by Core (can be broken in 32 bits) |
|
// Wishbone interface signals -- won't be used for current specification requirements |
bit [7:0] wishboneInputAddress; |
bit wishboneCycle; |
bit [31:0] wishboneInputData; |
bit wishboneStrobe; |
bit wishboneWriteEnable; |
bit wishboneAck; |
bit [31:0] wishboneOutputData; |
bit wishboneInterrupt; |
|
// Put XGMII interface in loopback mode --- do it in testbench if you can just connect them to each other |
/* always_comb begin |
xgmiiReceiveControl = xgmiiTransmitControl; |
xgmiiReceiveData = xgmiiTransmitData; |
end |
*/ |
/** |
* Clocking block mainly for testcase |
* Resets are used as outputs in clocking block -- to make sure they are de-asserted on clock edges |
* may need specific testcase to test asynchronous resets |
* @param clkTxRxInterface: clock to be used for clocking block |
*/ |
clocking clockingTxRx @(posedge clkTxRxInterface); |
// Using default delays |
default output #1000; |
|
// receive interface direction |
input receiveAvailable; |
input receivedData; |
input receiveEndOfPacket; |
input receiveValid; |
input receiveStartOfPacket; |
input receivePacketLengthModulus; |
input receiveError; |
output receiveReadEnable; |
// transmit interface direction |
output transmitData; |
output transmitValid; |
output transmitStartOfPacket; |
output transmitEndOfPacket; |
output transmitPacketLengthModulus; |
input transmitFIFOFull; |
|
output rstTxRxInterface_n; |
|
output rstWishboneInterface; // not necessary but doesn't matter as we need to take care of it |
|
endclocking // clockingTxRx |
|
clocking clockingXGMIIRx @(posedge clkXGMIIInterfaceRx); |
output xgmiiReceiveControl; |
output xgmiiReceiveData; |
|
output rstXGMIIInterfaceRx_n; |
endclocking // clockingXGMIIRx |
|
clocking clockingXGMIITx @(posedge clkXGMIIInterfaceTx); |
input xgmiiTransmitControl; |
input xgmiiTransmitData; |
|
output rstXGMIIInterfaceTx_n; |
endclocking // clockingXGMIITx |
|
// Avoiding modports for 10GE MAC Core and Wishbone as functionality is not really required at this point of time |
// However for complete environment it can be extended to include all interfaces |
|
modport TESTMOD (clocking clockingTxRx, clocking clockingXGMIIRx, clocking clockingXGMIITx); |
|
|
endinterface // macCoreInterface |
/xge_mac/trunk/tbench/proto_systemverilog/verification/driver.sv
0,0 → 1,104
/** |
* 10 GE MAC Core verification environment driver file. |
* @file: driver.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC (SV 1896 Systemverilog for advanced verification course) |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By: |
* $LastChangedBy$ |
*/ |
|
/** |
* Driver class to send packet from test environment to DUT (10GE MAC Core). |
* Driver only talks with Tx interface of 10 GE MAC Core, This class will provide |
* packet data to MAC Core as represented in specification requirement. |
* @class driver |
* @par virtual macCoreInterface to connect class objects with DUT |
*/ |
|
class driver; |
|
virtual macCoreInterface virtualMacCoreInterface; ///< Virtual interface to connect class types with RTL. |
mailbox driver2Scoreboard; |
|
const bit ASSERT = 1'b1; ///< to assert sequence while transsion of packet |
const bit DEASSERT = 1'b0; ///< to deassert sequence while transmission of packet |
|
// packetFrame driverPacket; |
|
/** |
* Constructor for driver class -- main purpose is to connect design interface with class virtual interface. |
* @param virtualInterface -- virtual interface passed down from env class |
* @return: NA (creates object of type class and returns handle |
*/ |
function new (virtual macCoreInterface virtualInterface, |
input mailbox driver2Scoreboard |
); |
this.virtualMacCoreInterface = virtualInterface; |
this.driver2Scoreboard = driver2Scoreboard; |
endfunction // new |
|
/** |
* Task to send complete packet data to the input of RTL (10 GE MAC Core). |
* send_packet should follow protocol requirements specified in requirement specifications (except if it is used for error injection) |
* protocol requirement: |
* assert: packetValid |
* make sure sop, eop and mod are set to 0 at start of packet (do it at the end of each packet transmission or right here) |
* if sending 0th frame assert sop |
* if sending last fram assert eop and mod |
* put all data on packetData |
* wait for a clock edge and de-assert packetValid, eop and mod (at this point sop is still asserted ??) |
* packet class itself will take care of keeping track of number of objects created. |
*/ |
task send_packet (input int lengthOfFrame); |
packet macCore; ///< object of type packet that will be transmitted to DUT |
|
virtualMacCoreInterface.clockingTxRx.transmitValid <= ASSERT; |
|
for (int i = 0; i < lengthOfFrame; i+=8) |
begin |
macCore = new (TRANSMIT); |
assert (macCore.randomize ()); |
macCore.startOfPacket = DEASSERT; |
macCore.endOfPacket = DEASSERT; |
macCore.packetLengthModulus = 3'b0; |
|
if (i == 0) macCore.startOfPacket = ASSERT; |
//virtualMacCoreInterface.clockingTxRx.transmitStartOfPacket <= ASSERT; |
|
if (i+8 >= lengthOfFrame) begin |
macCore.endOfPacket = ASSERT; |
macCore.packetLengthModulus = lengthOfFrame % 8; |
// virtualMacCoreInterface.clockingTxRx.transmitEndOfPacket <= ASSERT; |
// virtualMacCoreInterface.clockingTxRx.transmitPacketLengthModulus <= lengthOfFrame % 8; |
end |
|
virtualMacCoreInterface.clockingTxRx.transmitStartOfPacket <= macCore.startOfPacket; |
virtualMacCoreInterface.clockingTxRx.transmitEndOfPacket <= macCore.endOfPacket; |
virtualMacCoreInterface.clockingTxRx.transmitPacketLengthModulus <= macCore.packetLengthModulus; |
|
virtualMacCoreInterface.clockingTxRx.transmitData <= { macCore.packetData [7], |
macCore.packetData [6], |
macCore.packetData [5], |
macCore.packetData [4], |
macCore.packetData [3], |
macCore.packetData [2], |
macCore.packetData [1], |
macCore.packetData [0] }; |
macCore.print (TRANSMIT); |
driver2Scoreboard.put (macCore); |
@(virtualMacCoreInterface.clockingTxRx); |
|
end // for (int i = 0; i < lengthOfFrame; i+=8) |
|
virtualMacCoreInterface.clockingTxRx.transmitValid <= DEASSERT; |
virtualMacCoreInterface.clockingTxRx.transmitEndOfPacket <= DEASSERT; |
virtualMacCoreInterface.clockingTxRx.transmitPacketLengthModulus <= 3'b0; |
|
endtask // send_packet |
|
endclass // driver |
/xge_mac/trunk/tbench/proto_systemverilog/verification/testbench.sv
0,0 → 1,123
/** |
* Testbench file for verification environment of 10GE MAC Core. |
* @file: testbench.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC (SV 1896 Systemverilog for Advanced verification course) |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By: |
* $LastChangedBy$ |
*/ |
|
/** |
* top block (module) mainly to instantiate all programs/modules and to generate clocks. |
* Clocks are generated as per specification requirements: |
* Wishbone interface clock: 30 - 156MHz |
* Simple Tx-Rx interface clock: 156.25 MHz |
* XGMII Rx interface clock: 156.25 MHz |
* XGMII Tx interface clock: 156.25 MHz |
* |
* This clock generator will create Wishbone interface clock at 78.125 MHz (cause it has |
* clock time of half of 156.25) |
* @param: clkWishboneInterface (wishbone interface clock or main clock, will be used to generate all other clocks) |
* @param: clkSimpleTxRxInterface |
* @param: clkXGMIIInterfaceRx |
* @param: clkXGMIIInterfaceTx |
*/ |
|
module top (); |
|
bit clkWishboneInterface; |
bit clkSimpleTxRxInterface; |
bit clkXGMIIInterfaceRx; |
bit clkXGMIIInterfaceTx; |
|
initial begin |
clkWishboneInterface = 0; |
clkSimpleTxRxInterface = 0; |
clkXGMIIInterfaceRx = 0; |
clkXGMIIInterfaceTx = 0; |
end |
|
initial forever #1600 clkWishboneInterface = ~clkWishboneInterface; |
|
// Creating all other clocks from wishbone clock to make it look better and easily |
// portable (arguable) However wishbone interface clock looses flexibility of having |
// any value to create 30-156MHz range |
// Following block can be modified to have each clock generated independently |
// and having more flexibility. |
always @(posedge clkWishboneInterface) begin |
// initial forever #3200 begin |
clkSimpleTxRxInterface = ~clkSimpleTxRxInterface; |
clkXGMIIInterfaceRx = ~clkXGMIIInterfaceRx; |
clkXGMIIInterfaceTx = ~clkXGMIIInterfaceTx; |
end |
|
initial begin |
$dumpfile ("toTest.dump"); |
$dumpvars (0, top); |
end |
|
// Instantiation of Interface |
macCoreInterface instInterface ( .clkWishboneInterface (clkWishboneInterface), |
.clkTxRxInterface (clkSimpleTxRxInterface), |
.clkXGMIIInterfaceRx (clkXGMIIInterfaceRx), |
.clkXGMIIInterfaceTx (clkXGMIIInterfaceTx) |
); |
|
// Instantiation of MAC DUT |
xge_mac instMAC ( // Simple Tx-Rx interface signals |
.clk_156m25 (instInterface.clkTxRxInterface), |
|
.pkt_rx_ren (instInterface.receiveReadEnable), |
.pkt_rx_avail (instInterface.receiveAvailable), |
.pkt_rx_data (instInterface.receivedData), |
.pkt_rx_eop (instInterface.receiveEndOfPacket), |
.pkt_rx_err (instInterface.receiveError), |
.pkt_rx_mod (instInterface.receivePacketLengthModulus), |
.pkt_rx_sop (instInterface.receiveStartOfPacket), |
.pkt_rx_val (instInterface.receiveValid), |
|
.pkt_tx_data (instInterface.transmitData), |
.pkt_tx_eop (instInterface.transmitEndOfPacket), |
.pkt_tx_mod (instInterface.transmitPacketLengthModulus), |
.pkt_tx_sop (instInterface.transmitStartOfPacket), |
.pkt_tx_full (instInterface.transmitFIFOFull), |
.pkt_tx_val (instInterface.transmitValid), |
|
.reset_156m25_n (instInterface.rstTxRxInterface_n), |
|
// XGMII interface signals |
.clk_xgmii_rx (instInterface.clkXGMIIInterfaceRx), |
.reset_xgmii_rx_n (instInterface.rstXGMIIInterfaceRx_n), |
.xgmii_rxc (instInterface.xgmiiTransmitControl), |
.xgmii_rxd (instInterface.xgmiiTransmitData), |
|
.clk_xgmii_tx (instInterface.clkXGMIIInterfaceTx), |
.reset_xgmii_tx_n (instInterface.rstXGMIIInterfaceTx_n), |
.xgmii_txc (instInterface.xgmiiTransmitControl), |
.xgmii_txd (instInterface.xgmiiTransmitData), |
|
// Wishbone interface signals |
.wb_clk_i (instInterface.clkWishboneInterface), |
.wb_rst_i (instInterface.rstWishboneInterface), |
.wb_adr_i (instInterface.wishboneInputAddress), |
.wb_cyc_i (instInterface.wishboneCycle), |
.wb_dat_i (instInterface.wishboneInputData), |
.wb_stb_i (instInterface.wishboneStrobe), |
.wb_we_i (instInterface.wishboneWriteEnable), |
|
.wb_ack_o (instInterface.wishboneAck), |
.wb_dat_o (instInterface.wishboneOutputData), |
.wb_int_o (instInterface.wishboneInterrupt) |
); |
|
// Testcase instatiation |
testcase instTest ( .driverTestInterface (instInterface.TESTMOD ), |
.monitorTestInterface (instInterface.TESTMOD ) |
); |
|
endmodule // top |
/xge_mac/trunk/tbench/proto_systemverilog/verification/ncvlog.log
0,0 → 1,4
ncvlog: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc. |
class packet; |
| |
ncvlog: *E,EXPMPA (packet.sv,24|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1]. |
/xge_mac/trunk/tbench/proto_systemverilog/verification/include.sv
0,0 → 1,12
typedef enum { NONE, TRANSMIT, RECEIVE } typeOfPkt; |
|
typedef struct packed { |
bit startOfPacket; |
bit [63:0] frame; |
bit endOfPacket; |
bit [2:0] packetModulus; |
} packetFrame; |
|
`define transmitData { packetData[7], packetData[6], packetData[5], packetData[4], packetData[3], packetData[2], packetData[1], packetData[0] } |
|
`define receivedData { receivedData [7], receivedData[6], receivedData[5], receivedData[4], receivedData[3], receivedData[2], receivedData[1], receivedData[0] } |
/xge_mac/trunk/tbench/proto_systemverilog/verification/scoreboard.sv
0,0 → 1,88
/** |
* Scoreboard / Checker for 10 GE MAC Core verification environment. |
* It takes packet data from driver as well as monitor class and comapre them for equality for error checking purpose |
* @file: scoreboard.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC 1896 course |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date |
* $LastChangedDate$ |
* $par Last Changed By |
* $LastChangedBy$ |
*/ |
|
/** |
* Scoreboard class for error checking of 10GE MAC Core. |
* Collects packet data from driver and monitor in the form of mailboxes and then compare them for equality. |
* If they are equal then communication was successful |
* @class scoreboard |
* @par mailbox driver2Scoreboard collects transmitted packets from driver. |
* @par mailbox monitor2Scoreboard collects received packets through monitor. |
*/ |
|
class scoreboard; |
|
mailbox driver2Scoreboard; ///< packet data passed down from driver as source or expected data |
mailbox monitor2Scoreboard; ///< packet data from monitor as source for actual data |
static bit error = 0; ///< Error flag to keep track of correctness of verification environment |
/** |
* Constructor for scoreboard class. |
* purpose is to create an object for scoreboard which will take mailboxes from respective classes |
* @param mailbox receivedFromDriver to hold mailbox received from Driver |
* @param mailbox receivedFromMonitor to hold mailbox received from Monitor |
* @return: NA (creates object of type scoreboard and returns handle) |
*/ |
function new (input mailbox receivedFromDriver, input mailbox receivedFromMonitor); |
this.driver2Scoreboard = receivedFromDriver; |
this.monitor2Scoreboard = receivedFromMonitor; |
endfunction: new |
|
/** |
* Compare task for error checking. |
* This task compares actual and expected results for correctness of design. |
* @param mailbox driver2Scoreboard expected results to be validated |
* @param mailbox monitor2Scoreboard actual results to be compared |
*/ |
task compare ( input mailbox driver2Scoreboard, |
input mailbox monitor2Scoreboard, |
int bytesInFrame); |
|
packet driverPacket; |
packet monitorPacket; |
|
driver2Scoreboard.get (driverPacket); |
monitor2Scoreboard.get (monitorPacket); |
|
`define driverData { driverPacket.packetData [7], driverPacket.packetData [6], driverPacket.packetData [5], driverPacket.packetData [4], driverPacket.packetData [3], driverPacket.packetData [2], driverPacket.packetData [1], driverPacket.packetData [0] } |
`define monitorData { monitorPacket.receivedData [7], monitorPacket.receivedData [6], monitorPacket.receivedData [5], monitorPacket.receivedData [4], monitorPacket.receivedData [3], monitorPacket.receivedData [2], monitorPacket.receivedData [1], monitorPacket.receivedData [0] } |
|
if (bytesInFrame != 0) begin |
for (int i = 0; i < bytesInFrame; i++) begin |
if (driverPacket.packetData [7-i] != monitorPacket.receivedData [7-i]) begin |
$display ("ERROR: Packet data [%0d] the data was %x and %x mismatched", i, driverPacket.packetData[7-i], monitorPacket.receivedData[7-i]); |
error = 1; |
end |
end |
end |
|
if (bytesInFrame == 0) |
if (`driverData != `monitorData) begin |
$display ("ERROR: Packet frame mismatched"); |
error = 1; |
end |
|
if (driverPacket.startOfPacket != monitorPacket.startOfPacket || driverPacket.endOfPacket != monitorPacket.endOfPacket) |
begin |
error = 1; |
$display ("ERROR: Packet control mismatched "); |
end |
|
/* if (error == 0) begin |
$display ("PASS: Packet matched properly "); |
end |
*/ |
endtask // compare |
|
endclass // scoreboard |
/xge_mac/trunk/tbench/proto_systemverilog/verification/irun.log
0,0 → 1,28
irun: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc. |
TOOL: irun 09.20-p007: Started on Sep 19, 2012 at 22:53:06 PDT |
irun |
../scenarios/compile/testcase.sv |
file: ../scenarios/compile/testcase.sv |
`include "../../verification/include.sv" |
| |
ncvlog: *E,COFILX (../scenarios/compile/testcase.sv,15|39): cannot open include file '../../verification/include.sv'. |
`include "../../verification/packet.sv" |
| |
ncvlog: *E,COFILX (../scenarios/compile/testcase.sv,16|38): cannot open include file '../../verification/packet.sv'. |
`include "../../verification/driver.sv" |
| |
ncvlog: *E,COFILX (../scenarios/compile/testcase.sv,17|38): cannot open include file '../../verification/driver.sv'. |
`include "../../verification/monitor.sv" |
| |
ncvlog: *E,COFILX (../scenarios/compile/testcase.sv,18|39): cannot open include file '../../verification/monitor.sv'. |
`include "../../verification/env.sv" |
| |
ncvlog: *E,COFILX (../scenarios/compile/testcase.sv,19|35): cannot open include file '../../verification/env.sv'. |
env envLoopBack; |
| |
ncvlog: *E,ILLPDL (../scenarios/compile/testcase.sv,34|17): Mixing of ansi & non-ansi style port declaration is not legal. |
program worklib.testcase:sv |
errors: 1, warnings: 0 |
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances. |
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 2). |
TOOL: irun 09.20-p007: Exiting on Sep 19, 2012 at 22:53:06 PDT (total: 00:00:00) |
/xge_mac/trunk/tbench/proto_systemverilog/verification/packet.sv
0,0 → 1,75
|
/** |
* packet class file for 10 GE MAC Core. |
* The file holds packet class according to specs |
* @file: packet.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: NA (UCSC systemverilog for adv. verification course) |
* |
* @version: |
* $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By: |
* $LastChangedBy$ |
* |
*/ |
|
/** |
* Packet class to represent packet for ethernet MAC core as per specs. |
* Class declaration and related methods |
* @class: packet |
*/ |
|
class packet; |
|
rand bit [7:0] packetData [8]; ///< random data variable used to send data in DUT |
bit [7:0] receivedData [8]; ///< placeholder variable for received data from DUT -- can't be same as packetData since transmission and reception can be full-duplex |
bit [2:0] packetLengthModulus; ///< modulus to report number of octates in last word of communication |
bit startOfPacket; |
bit endOfPacket; |
bit packetValid; |
|
bit transmitFIFOFull; |
bit receiveReadEnable; |
bit receiveError; |
bit receiveAvailable; |
|
static bit [15:0] transmitPktId; |
static bit [15:0] receivePktId; |
|
typeOfPkt pktClassPktType; |
|
//`define printData { packetData[7], packetData[6], packetData[5], packetData[4], packetData[3], packetData[2], packetData[1], packetData[0] } |
|
//`define printReceipt { receivedData [7], receivedData[6], receivedData[5], receivedData[4], receivedData[3], receivedData[2], receivedData[1], receivedData[0] } |
|
/** |
* Constructor for packet class. |
* It simply increments count of packet id depending on type of packet |
* @param typeOfPkt: input type to count number of packets sent / received. |
* @return : NA (creates objects and returns handle) |
*/ |
function new (input int pktClassPktType = NONE); |
if (pktClassPktType == TRANSMIT) |
transmitPktId++; |
|
if (pktClassPktType == RECEIVE) |
receivePktId++; |
endfunction // new |
|
/** |
* Print function for packet class. |
* prints relevant information for each frame transfered |
* @param: NA |
* @return: NA |
*/ |
function void print (input int pktClassPktType = NONE); |
if (pktClassPktType == TRANSMIT) |
$display (" [Time %0t ps] SOP = %b, Transmitted Data = %x, EOP = %b, Modulus = %h ", $time, startOfPacket, `transmitData, endOfPacket, packetLengthModulus); |
if (pktClassPktType == RECEIVE) |
$display (" [Time %0t ps] SOP = %b, Received Data = %x, EOP = %b, Modulus = %h ", $time, startOfPacket, `receivedData, endOfPacket, packetLengthModulus); |
endfunction: print |
|
endclass // packet |
/xge_mac/trunk/tbench/proto_systemverilog/verification/monitor.sv
0,0 → 1,92
/** |
* 10 GE MAC Core verification environment monitor file. |
* @file: monitor.sv |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC (SV 1896 Systemverilog for advanced verification course) |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By |
* $LastChangedBy$ |
*/ |
|
/** |
* Monitor class to collect packet from DUT (10 GE MAC Core) in test environment. |
* Monitor only communicate with receive interface of DUT and collects information |
* about packet, this information can be validated with expected results for error |
* checking and proper working of protocol. |
* @class monitor |
* @par virtual macCoreInterface to collect data from interface. |
*/ |
|
class monitor; |
|
virtual macCoreInterface virtualMacCoreInterface; ///< virtual interface to connect class type to RTL / module type |
mailbox monitor2Scoreboard; |
|
const bit ASSERT = 1'b1; ///< to assert sequence while receiving packet from DUT |
const bit DEASSERT = 1'b0; ///< to de-assert sequence while receiving packet from DUT |
// packetFrame monitorPacket; |
|
/** |
* Constructor for monitor class -- main purpose is to connect design interface with monitor class virtual interface. |
* @param virtualInterface -- input to constructor passed down by env class |
* @return: NA (creates an object of type monitor and returns a handle) |
*/ |
function new (virtual macCoreInterface virtualInterface, |
mailbox monitor2Scoreboard |
); |
this.virtualMacCoreInterface = virtualInterface; |
this.monitor2Scoreboard = monitor2Scoreboard; |
endfunction // new |
|
/** |
* Task to collect data from output of RTL from interface as bus. |
* collect_packet should follow protocol requirements specified in requirement specifications (unless it is used for error injection) |
* Protocol requirements: |
* Always check for receiveAvailable (need to do it in testcase or environment? but need to be running under forever) |
* if(receiveAvailable) start packet collect |
* assert receiveReadEnable |
* until receive is not complete |
* if receiveValid |
* if receiveStartOfPacket -- print/do nothing/start |
* packet.data = receiveData |
* if receiveEndOfPacket -- finish collecting packet |
* deassert receiveReadEnable |
* display some stuff |
* |
* MAY NEED TO LOOK IN OTHER FLAGS AS ERROR AND STUFF |
* creating new packet itself will take care of incrementing |
*/ |
`define receivedPacket { receiveMacCore.receivedData[7], receiveMacCore.receivedData[6], receiveMacCore.receivedData[5], receiveMacCore.receivedData[4], receiveMacCore.receivedData[3], receiveMacCore.receivedData[2], receiveMacCore.receivedData[1], receiveMacCore.receivedData[0] } |
|
task collect_packet (); |
packet receiveMacCore; ///< object of type packet that will be collected from DUT. |
|
virtualMacCoreInterface.clockingTxRx.receiveReadEnable <= ASSERT; |
|
do begin |
receiveMacCore = new (RECEIVE); |
@(virtualMacCoreInterface.clockingTxRx); |
if (virtualMacCoreInterface.clockingTxRx.receiveValid) begin |
receiveMacCore.startOfPacket = virtualMacCoreInterface.clockingTxRx.receiveStartOfPacket; |
receiveMacCore.endOfPacket = virtualMacCoreInterface.clockingTxRx.receiveEndOfPacket; |
receiveMacCore.packetLengthModulus = virtualMacCoreInterface.clockingTxRx.receivePacketLengthModulus; |
|
if (virtualMacCoreInterface.clockingTxRx.receiveStartOfPacket) begin |
$display ("Starting to receive packet \n"); |
end |
`receivedPacket = virtualMacCoreInterface.clockingTxRx.receivedData; |
receiveMacCore.print (RECEIVE); |
|
monitor2Scoreboard.put (receiveMacCore); |
end // if (virtualMacCoreInterface.clockingTxRx.receiveValid) |
end while (!virtualMacCoreInterface.clockingTxRx.receiveEndOfPacket); // UNMATCHED !! |
|
virtualMacCoreInterface.clockingTxRx.receiveReadEnable <= DEASSERT; |
|
endtask // collect_packet |
|
endclass // monitor |
/xge_mac/trunk/tbench/proto_systemverilog/scenarios/compile/testcase.sv
0,0 → 1,66
/** |
* 10 GE MAC Core loopback test scenario file. |
* @file: testcase.sv (loopback) |
* @author: Pratik Mahajan |
* @par Contact: pratik@e-pigeonpost.com |
* @par Company: UCSC (SV 1896 Systemverilog for advanced verification course) |
* |
* @version: $LastChangedRevision$ |
* @par Last Changed Date: |
* $LastChangedDate$ |
* @par Last Changed By |
* $LastChangedBy$ |
*/ |
|
`include "../../verification/include.sv" |
`include "../../verification/packet.sv" |
`include "../../verification/driver.sv" |
`include "../../verification/monitor.sv" |
`include "../../verification/scoreboard.sv" |
`include "../../verification/env.sv" |
|
/** |
* Testcase representing loopback scenario. |
* The testcase sets proper environment variable for design to work in loopback mode |
* To connect DUT in loopback mode: |
* XGMII interface Tx is connected to XGMII Rx port. |
* Data transmitted through simple Tx port collected through simple Rx port |
* and the data is compared for equality |
*/ |
|
program testcase ( macCoreInterface driverTestInterface, |
macCoreInterface monitorTestInterface |
); |
|
env envLoopBack; |
int noOfPackets; |
int lengthOfFrame; |
|
initial begin |
|
envLoopBack = new (driverTestInterface, monitorTestInterface); |
|
noOfPackets = $urandom_range (5, 8); |
lengthOfFrame = $urandom_range (58, 68); |
|
#20 envLoopBack.reset (); |
#30 envLoopBack.init (); |
envLoopBack.run (noOfPackets, lengthOfFrame); |
envLoopBack.validate (noOfPackets, lengthOfFrame); |
|
#1000000 $finish; |
|
end |
|
final begin |
$display ("\n\n"); |
$display ("\t//////////////////////////////////////////////////////////\n"); |
$display ("\t///////////// Test Finished, Results: ////////////////////\n"); |
$display ("\t//////////////////////////////////////////////////////////\n"); |
|
if (envLoopBack.macCoreScoreboard.error == 1) $display ("\t\t End Of Test ERROR: \n\t\t Error occured while checking packets\n"); |
else $display ("\t\t End Of Test PASS: \n\t\t All packets were matched properly\n"); |
end |
|
endprogram // testcase |
|
/xge_mac/trunk/sim/proto_systemverilog/irunScript
0,0 → 1,66
irun -timescale 1ps/1ps -override_timescale ../../rtl/verilog/*.v +incdir+../../rtl/include ../../testbench/verilog/tb_xge_mac.sv |
xge_mac/trunk/sim/proto_systemverilog/irunScript
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: xge_mac/trunk/sim/proto_systemverilog/irunForOOP
===================================================================
--- xge_mac/trunk/sim/proto_systemverilog/irunForOOP (nonexistent)
+++ xge_mac/trunk/sim/proto_systemverilog/irunForOOP (revision 22)
@@ -0,0 +1 @@
+irun ../../verification/macCoreInterface.sv ../../verification/testbench.sv ../../rtl/verilog/*.v testcase.sv +incdir+../../rtl/include/ +svseed=random
xge_mac/trunk/sim/proto_systemverilog/irunForOOP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: xge_mac/trunk/sim/proto_systemverilog/CLEAN
===================================================================
--- xge_mac/trunk/sim/proto_systemverilog/CLEAN (nonexistent)
+++ xge_mac/trunk/sim/proto_systemverilog/CLEAN (revision 22)
@@ -0,0 +1 @@
+\rm -rf simv* csrc *.log vcdplus.vpd *DVE* *INCA* transcript work
xge_mac/trunk/sim/proto_systemverilog/CLEAN
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: xge_mac/trunk/sim/proto_systemverilog/irun.log
===================================================================
--- xge_mac/trunk/sim/proto_systemverilog/irun.log (nonexistent)
+++ xge_mac/trunk/sim/proto_systemverilog/irun.log (revision 22)
@@ -0,0 +1,30 @@
+irun: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
+TOOL: irun 09.20-p007: Started on Oct 28, 2012 at 18:11:47 PDT
+irun
+ ../../verification/macCoreInterface.sv
+ ../../verification/testbench.sv
+ ../../rtl/verilog/fault_sm.v
+ ../../rtl/verilog/generic_fifo_ctrl.v
+ ../../rtl/verilog/generic_fifo.v
+ ../../rtl/verilog/generic_mem_medium.v
+ ../../rtl/verilog/generic_mem_small.v
+ ../../rtl/verilog/meta_sync_single.v
+ ../../rtl/verilog/meta_sync.v
+ ../../rtl/verilog/rx_data_fifo.v
+ ../../rtl/verilog/rx_dequeue.v
+ ../../rtl/verilog/rx_enqueue.v
+ ../../rtl/verilog/rx_hold_fifo.v
+ ../../rtl/verilog/sync_clk_core.v
+ ../../rtl/verilog/sync_clk_wb.v
+ ../../rtl/verilog/sync_clk_xgmii_tx.v
+ ../../rtl/verilog/tx_data_fifo.v
+ ../../rtl/verilog/tx_dequeue.v
+ ../../rtl/verilog/tx_enqueue.v
+ ../../rtl/verilog/tx_hold_fifo.v
+ ../../rtl/verilog/wishbone_if.v
+ ../../rtl/verilog/xge_mac.v
+ testcase.sv
+ +incdir+../../rtl/include/
+ +svseed=random
+irun: *E,FILEMIS: Cannot find the provided file testcase.sv.
+TOOL: irun 09.20-p007: Exiting on Oct 28, 2012 at 18:11:48 PDT (total: 00:00:01)
xge_mac/trunk/sim/proto_systemverilog/irun.log
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: xge_mac/trunk/sim/proto_systemverilog/runsim
===================================================================
--- xge_mac/trunk/sim/proto_systemverilog/runsim (nonexistent)
+++ xge_mac/trunk/sim/proto_systemverilog/runsim (revision 22)
@@ -0,0 +1,5 @@
+vcs +vcs+lic+wait -sverilog -R -l vcs.log \
+-override_timescale=1ps/1ps \
+../../rtl/verilog/*.v \
++incdir+../../rtl/include \
+../../testbench/verilog/tb_xge_mac.sv
xge_mac/trunk/sim/proto_systemverilog/runsim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property