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Rev 21 → Rev 22

/trunk/rtl-model/alu.v
74,7 → 74,9
assign pfi = iflags[2];
assign cfi = iflags[0];
 
assign flags_unchanged = (t == 4'd6 || t == 4'd2 || t == 4'd4 && func == 4'd2);
assign flags_unchanged = (t == 4'd6 || t == 4'd2
|| t == 4'd4 && func == 4'd2
|| t == 4'd5 && y[7:0] == 8'd0);
endmodule
 
module addsub(x, y, out, func, word_op, cfi, cfo, afo, ofo);
280,6 → 282,7
//
// This module implements the instructions shl/sal, sar, shr
//
 
module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
// IO ports
input [15:0] x, y;
293,7 → 296,10
wire [15:0] sal_shl, sar, shr, sar16, shr16;
wire [7:0] sar8, shr8;
wire signed [15:0] x_s;
wire ofo_shl, ofo_sar, ofo_shr, ofo_o, cfo16, cfo8;
wire signed [7:0] x_s8;
wire ofo_shl, ofo_sar, ofo_shr, ofo_o;
wire cfo_sal8, cfo_sal16, cfo_sar8, cfo_sar16, cfo_shr8, cfo_shr16;
wire cfo16, cfo8;
 
// Module instantiations
mux4_16 m0(func, sal_shl, sar, shr, 16'd0, out);
301,21 → 307,30
 
// Assignments
assign x_s = x;
assign x_s8 = x[7:0];
assign sal_shl = x << y[7:0];
assign sar16 = x_s >>> y[7:0];
assign sar16 = (y[7:0]>8'd15) ? 16'hffff : (x_s >>> y[7:0]);
assign shr16 = x >> y[7:0];
assign sar8 = x_s[7:0] >>> y[7:0];
assign sar8 = (y[7:0]>8'd15) ? 8'hff : (x_s8 >>> y[7:0]);
assign shr8 = x[7:0] >> y[7:0];
assign shr = word_op ? shr16 : {8'd0, shr8};
assign sar = word_op ? sar16 : {8'd0, sar8};
assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8};
 
assign cfo16 = (y == 16'd0) ? cfi :
( (func==2'd0) ? |(x & (16'h8000 >> (y-1))) : |(x & (16'h1 << (y-1))));
assign cfo8 = (y[7:0] == 8'd0) ? cfi :
( (func==2'd0) ? |(x[7:0] & (8'h80 >> (y-1)))
: |(x[7:0] & (8'h1 << (y-1))));
assign cfo_sal8 = |(x[7:0] & (8'h80 >> (y[7:0]-1)));
assign cfo_sal16 = |(x & (16'h8000 >> (y[7:0]-1)));
assign cfo_sar8 = (y[7:0]>8'd8) ? 1'b1 :
(1'b1 & (x_s8 >>> (y[7:0]-1)));
assign cfo_sar16 = (y[7:0]>8'd16) ? 1'b1 :
(1'b1 & (x_s >>> (y[7:0]-1)));
assign cfo_shr8 = (1'b1 & (x[7:0] >> (y[7:0]-1)));
assign cfo_shr16 = (1'b1 & (x >> (y[7:0]-1)));
 
assign cfo16 = (y[7:0] == 8'd0) ? cfi :
(func[1] ? cfo_shr16 : (func[0] ? cfo_sar16 : cfo_sal16));
assign cfo8 = (y[7:0] == 8'd0) ? cfi :
(func[1] ? cfo_shr8 : (func[0] ? cfo_sar8 : cfo_sal8));
assign cfo = word_op ? cfo16 : cfo8;
assign ofo = (y == 16'd0) ? ofi : ofo_o;
assign ofo = (y[7:0] == 16'd0) ? ofi : ofo_o;
assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
/trunk/rtl-model/fetch.v
962,6 → 962,33
dst <= 4'b0;
end
 
8'b1101_00xx: // sal/shl
begin
seq_addr <= (regm==3'b100) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `SALCRW : `SALCRB )
: (opcode[0] ? `SAL1RW : `SAL1RB ))
: (opcode[1] ? (opcode[0] ? `SALCMW : `SALCMB )
: (opcode[0] ? `SAL1MW : `SAL1MB )))
: ( (regm==3'b111) ? ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `SARCRW : `SARCRB )
: (opcode[0] ? `SAR1RW : `SAR1RB ))
: (opcode[1] ? (opcode[0] ? `SARCMW : `SARCMB )
: (opcode[0] ? `SAR1MW : `SAR1MB )))
: ((mod==2'b11) ?
(opcode[1] ? (opcode[0] ? `SHRCRW : `SHRCRB )
: (opcode[0] ? `SHR1RW : `SHR1RB ))
: (opcode[1] ? (opcode[0] ? `SHRCMW : `SHRCMB )
: (opcode[0] ? `SHR1MW : `SHR1MB ))));
 
need_modrm <= 1'b1;
need_off <= need_off_mod;
need_imm <= 1'b0;
off_size <= off_size_mod;
imm_size <= 1'b0;
src <= rm;
dst <= rm;
end
 
8'b1101_0111: // xlat
begin
seq_addr <= `XLAT;
/trunk/sim/modelsim/tb.do
3,28 → 3,33
vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
vlog -work work +incdir+.. ../memory.v ../testbench.v
vsim -novopt -t ns work.testbench
add wave /testbench/clk
add wave /testbench/rst
add wave -radix hexadecimal /testbench/cpu0/fetch0/pc
add wave -radix hexadecimal /testbench/cpu0/fetch0/state
add wave -radix hexadecimal /testbench/cpu0/fetch0/next_state
add wave -radix hexadecimal /testbench/cpu0/fetch0/opcode
add wave -radix hexadecimal /testbench/cpu0/fetch0/modrm
add wave /testbench/cpu0/fetch0/end_seq
add wave -radix hexadecimal sim:/testbench/rd_data
add wave -radix hexadecimal sim:/testbench/wr_data
add wave sim:/testbench/cpu0/fetch0/need_modrm
add wave sim:/testbench/cpu0/fetch0/need_off
add wave sim:/testbench/cpu0/fetch0/need_imm
add wave sim:/testbench/cpu0/fetch0/ir
add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/imm
add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/off
add wave -radix hexadecimal sim:/testbench/addr
add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/r\[15\]
add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/d
add wave sim:/testbench/cpu0/exec0/reg0/addr_a
add wave sim:/testbench/cpu0/exec0/reg0/addr_d
add wave sim:/testbench/cpu0/exec0/reg0/wr
add wave sim:/testbench/we
add wave sim:/testbench/ack_i
add wave sim:/testbench/cpu0/fetch_or_exec
add wave -label clk /testbench/clk
add wave -label rst /testbench/rst
add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
add wave -divider fetch
add wave -label state -radix hexadecimal /testbench/cpu0/fetch0/state
add wave -label next_state -radix hexadecimal /testbench/cpu0/fetch0/next_state
add wave -label opcode -radix hexadecimal /testbench/cpu0/fetch0/opcode
add wave -label modrm -radix hexadecimal /testbench/cpu0/fetch0/modrm
add wave -label seq_addr /testbench/cpu0/fetch0/decode0/seq_addr
add wave -label end_seq /testbench/cpu0/fetch0/end_seq
add wave -label need_modrm /testbench/cpu0/fetch0/need_modrm
add wave -label need_off /testbench/cpu0/fetch0/need_off
add wave -label need_imm /testbench/cpu0/fetch0/need_imm
add wave -label ir /testbench/cpu0/fetch0/ir
add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
add wave -divider alu
add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
add wave -label addr -radix hexadecimal /testbench/addr
add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
add wave -label wr /testbench/cpu0/exec0/reg0/wr
add wave -label we /testbench/we
add wave -label ack_i /testbench/ack_i
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
/trunk/sim/memory.v
24,5 → 24,5
if (we) if (byte_m) ram[addr] <= wr_data[7:0];
else { ram[addr1], ram[addr] } <= wr_data;
 
initial $readmemh("/home/zeus/zet/sim/10_bitwise.rtlrom", ram, 20'hf0000);
initial $readmemh("/home/zeus/zet/sim/11_shifts.rtlrom", ram, 20'hf0000);
endmodule

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