URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 210 to Rev 211
- ↔ Reverse comparison
Rev 210 → Rev 211
/trunk/rtl/vhdl/system/t8048_notri.vhd
3,7 → 3,7
-- T8048 Microcontroller System |
-- 8048 toplevel without tri-states |
-- |
-- $Id: t8048_notri.vhd,v 1.3 2004-12-02 22:08:42 arniml Exp $ |
-- $Id: t8048_notri.vhd,v 1.4 2005-11-01 21:38:48 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
54,28 → 54,29
); |
|
port ( |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
db_i : in std_logic_vector( 7 downto 0); |
db_o : out std_logic_vector( 7 downto 0); |
db_dir_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
db_i : in std_logic_vector( 7 downto 0); |
db_o : out std_logic_vector( 7 downto 0); |
db_dir_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2l_low_imp_o : out std_logic; |
p2h_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic |
); |
|
end t8048_notri; |
131,37 → 132,38
sample_t1_state_g => 4 |
) |
port map ( |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_s, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_i, |
db_o => db_o, |
db_dir_o => db_dir_o, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2_low_imp_o => p2_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => xtal3_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_s |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_s, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_i, |
db_o => db_o, |
db_dir_o => db_dir_o, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2l_low_imp_o => p2l_low_imp_o, |
p2h_low_imp_o => p2h_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => xtal3_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_s |
); |
|
|
242,6 → 244,10
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2004/12/02 22:08:42 arniml |
-- introduced generic gate_port_input_g |
-- forces masking of P1 and P2 input bus |
-- |
-- Revision 1.2 2004/12/01 23:08:08 arniml |
-- update |
-- |
/trunk/rtl/vhdl/system/t8039_notri.vhd
3,7 → 3,7
-- T8039 Microcontroller System |
-- 8039 toplevel without tri-states |
-- |
-- $Id: t8039_notri.vhd,v 1.1 2004-12-03 19:42:34 arniml Exp $ |
-- $Id: t8039_notri.vhd,v 1.2 2005-11-01 21:38:10 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
54,28 → 54,29
); |
|
port ( |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
db_i : in std_logic_vector( 7 downto 0); |
db_o : out std_logic_vector( 7 downto 0); |
db_dir_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
db_i : in std_logic_vector( 7 downto 0); |
db_o : out std_logic_vector( 7 downto 0); |
db_dir_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2l_low_imp_o : out std_logic; |
p2h_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic |
); |
|
end t8039_notri; |
129,37 → 130,38
sample_t1_state_g => 4 |
) |
port map ( |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_i, |
db_o => db_o, |
db_dir_o => db_dir_o, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2_low_imp_o => p2_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => xtal3_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => open, |
pmem_data_i => pmem_data_s |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_i, |
db_o => db_o, |
db_dir_o => db_dir_o, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2l_low_imp_o => p2l_low_imp_o, |
p2h_low_imp_o => p2h_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => xtal3_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => open, |
pmem_data_i => pmem_data_s |
); |
|
|
200,4 → 202,7
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2004/12/03 19:42:34 arniml |
-- initial check-in |
-- |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/t8050_wb.vhd
3,7 → 3,7
-- T8048 Microcontroller System |
-- 8050 toplevel with Wishbone interface |
-- |
-- $Id: t8050_wb.vhd,v 1.2 2005-06-11 10:16:05 arniml Exp $ |
-- $Id: t8050_wb.vhd,v 1.3 2005-11-01 21:39:14 arniml Exp $ |
-- |
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
-- |
55,33 → 55,34
|
port ( |
-- T48 Interface ---------------------------------------------------------- |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic; |
xtal_i : in std_logic; |
reset_n_i : in std_logic; |
t0_i : in std_logic; |
t0_o : out std_logic; |
t0_dir_o : out std_logic; |
int_n_i : in std_logic; |
ea_i : in std_logic; |
rd_n_o : out std_logic; |
psen_n_o : out std_logic; |
wr_n_o : out std_logic; |
ale_o : out std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p2l_low_imp_o : out std_logic; |
p2h_low_imp_o : out std_logic; |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p1_low_imp_o : out std_logic; |
prog_n_o : out std_logic; |
-- Wishbone Interface ----------------------------------------------------- |
wb_cyc_o : out std_logic; |
wb_stb_o : out std_logic; |
wb_we_o : out std_logic; |
wb_adr_o : out std_logic_vector(23 downto 0); |
wb_ack_i : in std_logic; |
wb_dat_i : in std_logic_vector( 7 downto 0); |
wb_dat_o : out std_logic_vector( 7 downto 0) |
wb_cyc_o : out std_logic; |
wb_stb_o : out std_logic; |
wb_we_o : out std_logic; |
wb_adr_o : out std_logic_vector(23 downto 0); |
wb_ack_i : in std_logic; |
wb_dat_i : in std_logic_vector( 7 downto 0); |
wb_dat_o : out std_logic_vector( 7 downto 0) |
|
); |
|
148,37 → 149,38
sample_t1_state_g => 4 |
) |
port map ( |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_s, |
rd_n_o => rd_n_s, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_s, |
ale_o => ale_s, |
db_i => db_bus_to_t48, |
db_o => db_bus_from_t48, |
db_dir_o => open, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2_low_imp_o => p2_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => en_clk_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_s |
xtal_i => xtal_i, |
reset_i => reset_n_i, |
t0_i => t0_i, |
t0_o => t0_o, |
t0_dir_o => t0_dir_o, |
int_n_i => int_n_i, |
ea_i => ea_s, |
rd_n_o => rd_n_s, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_s, |
ale_o => ale_s, |
db_i => db_bus_to_t48, |
db_o => db_bus_from_t48, |
db_dir_o => open, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p2l_low_imp_o => p2l_low_imp_o, |
p2h_low_imp_o => p2h_low_imp_o, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p1_low_imp_o => p1_low_imp_o, |
prog_n_o => prog_n_o, |
clk_i => xtal_i, |
en_clk_i => en_clk_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_s |
); |
|
|
291,6 → 293,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/06/11 10:16:05 arniml |
-- introduce prefix 't48_' for wb_master entity and configuration |
-- |
-- Revision 1.1 2005/05/08 10:36:59 arniml |
-- initial check-in |
-- |
/trunk/rtl/vhdl/system/t8039.vhd
2,7 → 2,7
-- |
-- T8039 Microcontroller System |
-- |
-- $Id: t8039.vhd,v 1.3 2004-12-03 19:43:12 arniml Exp $ |
-- $Id: t8039.vhd,v 1.4 2005-11-01 21:37:45 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
77,7 → 77,8
signal db_s : std_logic_vector( 7 downto 0); |
signal db_dir_s : std_logic; |
signal p2_s : std_logic_vector( 7 downto 0); |
signal p2_low_imp_s : std_logic; |
signal p2l_low_imp_s : std_logic; |
signal p2h_low_imp_s : std_logic; |
signal p1_s : std_logic_vector( 7 downto 0); |
signal p1_low_imp_s : std_logic; |
|
91,28 → 92,29
) |
|
port map ( |
xtal_i => xtal_i, |
reset_n_i => reset_n_i, |
t0_i => t0_b, |
t0_o => t0_s, |
t0_dir_o => t0_dir_s, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_b, |
db_o => db_s, |
db_dir_o => db_dir_s, |
t1_i => t1_i, |
p2_i => p2_b, |
p2_o => p2_s, |
p2_low_imp_o => p2_low_imp_s, |
p1_i => p1_b, |
p1_o => p1_s, |
p1_low_imp_o => p1_low_imp_s, |
prog_n_o => prog_n_o |
xtal_i => xtal_i, |
reset_n_i => reset_n_i, |
t0_i => t0_b, |
t0_o => t0_s, |
t0_dir_o => t0_dir_s, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_b, |
db_o => db_s, |
db_dir_o => db_dir_s, |
t1_i => t1_i, |
p2_i => p2_b, |
p2_o => p2_s, |
p2l_low_imp_o => p2l_low_imp_s, |
p2h_low_imp_o => p2h_low_imp_s, |
p1_i => p1_b, |
p1_o => p1_s, |
p1_low_imp_o => p1_low_imp_s, |
prog_n_o => prog_n_o |
); |
|
----------------------------------------------------------------------------- |
124,7 → 126,7
bidirs: process (t0_b, t0_s, t0_dir_s, |
db_b, db_s, db_dir_s, |
p1_b, p1_s, p1_low_imp_s, |
p2_b, p2_s, p2_low_imp_s) |
p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) |
|
function open_collector_f(sig : std_logic) return std_logic is |
variable sig_v : std_logic; |
184,4 → 186,7
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2004/12/03 19:43:12 arniml |
-- added hierarchy t8039_notri |
-- |
------------------------------------------------------------------------------- |
/trunk/rtl/vhdl/system/t8048.vhd
2,7 → 2,7
-- |
-- T8048 Microcontroller System |
-- |
-- $Id: t8048.vhd,v 1.7 2004-12-03 19:44:36 arniml Exp $ |
-- $Id: t8048.vhd,v 1.8 2005-11-01 21:38:31 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
80,7 → 80,8
signal db_s : std_logic_vector( 7 downto 0); |
signal db_dir_s : std_logic; |
signal p2_s : std_logic_vector( 7 downto 0); |
signal p2_low_imp_s : std_logic; |
signal p2l_low_imp_s : std_logic; |
signal p2h_low_imp_s : std_logic; |
signal p1_s : std_logic_vector( 7 downto 0); |
signal p1_low_imp_s : std_logic; |
|
94,28 → 95,29
) |
|
port map ( |
xtal_i => xtal_i, |
reset_n_i => reset_n_i, |
t0_i => t0_b, |
t0_o => t0_s, |
t0_dir_o => t0_dir_s, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_b, |
db_o => db_s, |
db_dir_o => db_dir_s, |
t1_i => t1_i, |
p2_i => p2_b, |
p2_o => p2_s, |
p2_low_imp_o => p2_low_imp_s, |
p1_i => p1_b, |
p1_o => p1_s, |
p1_low_imp_o => p1_low_imp_s, |
prog_n_o => prog_n_o |
xtal_i => xtal_i, |
reset_n_i => reset_n_i, |
t0_i => t0_b, |
t0_o => t0_s, |
t0_dir_o => t0_dir_s, |
int_n_i => int_n_i, |
ea_i => ea_i, |
rd_n_o => rd_n_o, |
psen_n_o => psen_n_o, |
wr_n_o => wr_n_o, |
ale_o => ale_o, |
db_i => db_b, |
db_o => db_s, |
db_dir_o => db_dir_s, |
t1_i => t1_i, |
p2_i => p2_b, |
p2_o => p2_s, |
p2l_low_imp_o => p2l_low_imp_s, |
p2h_low_imp_o => p2h_low_imp_s, |
p1_i => p1_b, |
p1_o => p1_s, |
p1_low_imp_o => p1_low_imp_s, |
prog_n_o => prog_n_o |
); |
|
----------------------------------------------------------------------------- |
127,7 → 129,7
bidirs: process (t0_b, t0_s, t0_dir_s, |
db_b, db_s, db_dir_s, |
p1_b, p1_s, p1_low_imp_s, |
p2_b, p2_s, p2_low_imp_s) |
p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) |
|
function open_collector_f(sig : std_logic) return std_logic is |
variable sig_v : std_logic; |
188,6 → 190,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.7 2004/12/03 19:44:36 arniml |
-- removed obsolete constant |
-- |
-- Revision 1.6 2004/12/02 22:08:42 arniml |
-- introduced generic gate_port_input_g |
-- forces masking of P1 and P2 input bus |